From 845250b651e73789f012c3ef08e39644d046f187 Mon Sep 17 00:00:00 2001
From: Per <Per Lindgren>
Date: Thu, 9 Nov 2017 15:39:34 +0100
Subject: [PATCH] memory/gdbinit

---
 .gdbinit | 18 ++++++++++++++++++
 memory.x |  5 +++++
 2 files changed, 23 insertions(+)
 create mode 100644 .gdbinit
 create mode 100644 memory.x

diff --git a/.gdbinit b/.gdbinit
new file mode 100644
index 0000000..098ff6f
--- /dev/null
+++ b/.gdbinit
@@ -0,0 +1,18 @@
+target remote :3333
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.fifo uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
+load
+step
diff --git a/memory.x b/memory.x
new file mode 100644
index 0000000..74e34b8
--- /dev/null
+++ b/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+  FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+  RAM : ORIGIN = 0x20000000, LENGTH = 20K
+}
\ No newline at end of file
-- 
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