From 2ce1b57343edf71377a9b204f7c9033c87126004 Mon Sep 17 00:00:00 2001
From: Jorge Aparicio <jorge@japaric.io>
Date: Sun, 23 Jul 2017 21:46:03 -0500
Subject: [PATCH] rustfmt, refactor a bit
---
src/adc.rs | 2 +-
src/capture.rs | 130 ++++++++++++++++++++++---------------------------
src/dma.rs | 117 ++++++++++++++++++++++----------------------
src/pwm.rs | 2 +-
src/qei.rs | 2 +-
src/serial.rs | 4 +-
src/spi.rs | 7 ++-
src/timer.rs | 2 +-
8 files changed, 125 insertions(+), 141 deletions(-)
diff --git a/src/adc.rs b/src/adc.rs
index 571c540..a4c60bc 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -7,7 +7,7 @@ use hal::prelude::*;
use static_ref::Static;
use dma::{self, CircBuffer, Dma1Channel1};
-use stm32f103xx::{ADC1, DMA1, GPIOA, RCC, TIM2};
+use stm32f103xx::{ADC1, DMA1, TIM2, GPIOA, RCC};
use {Channel, Pwm};
/// ADC Channel 1 (PA1)
diff --git a/src/capture.rs b/src/capture.rs
index ef30b36..f4f1511 100644
--- a/src/capture.rs
+++ b/src/capture.rs
@@ -39,7 +39,7 @@ use core::u16;
use cast::{u16, u32};
use hal;
use nb;
-use stm32f103xx::{AFIO, GPIOA, RCC, TIM1, TIM2, TIM3, TIM4};
+use stm32f103xx::{TIM1, TIM2, TIM3, TIM4, AFIO, GPIOA, RCC};
use timer::{Channel, TIM};
@@ -203,42 +203,34 @@ impl<'a> hal::Capture for Capture<'a, TIM1> {
let sr = tim1.sr.read();
match channel {
- Channel::_1 => {
- if sr.cc1of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc1if().bit_is_set() {
- Ok(tim1.ccr1.read().ccr1().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
- Channel::_2 => {
- if sr.cc2of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc2if().bit_is_set() {
- Ok(tim1.ccr2.read().ccr2().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
- Channel::_3 => {
- if sr.cc3of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc3if().bit_is_set() {
- Ok(tim1.ccr3.read().ccr3().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
- Channel::_4 => {
- if sr.cc4of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc4if().bit_is_set() {
- Ok(tim1.ccr4.read().ccr4().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
+ Channel::_1 => if sr.cc1of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc1if().bit_is_set() {
+ Ok(tim1.ccr1.read().ccr1().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
+ Channel::_2 => if sr.cc2of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc2if().bit_is_set() {
+ Ok(tim1.ccr2.read().ccr2().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
+ Channel::_3 => if sr.cc3of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc3if().bit_is_set() {
+ Ok(tim1.ccr3.read().ccr3().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
+ Channel::_4 => if sr.cc4of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc4if().bit_is_set() {
+ Ok(tim1.ccr4.read().ccr4().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
}
}
@@ -498,42 +490,34 @@ where
let sr = tim1.sr.read();
match channel {
- Channel::_1 => {
- if sr.cc1of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc1if().bit_is_set() {
- Ok(tim1.ccr1.read().ccr1().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
- Channel::_2 => {
- if sr.cc2of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc2if().bit_is_set() {
- Ok(tim1.ccr2.read().ccr2().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
- Channel::_3 => {
- if sr.cc3of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc3if().bit_is_set() {
- Ok(tim1.ccr3.read().ccr3().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
- Channel::_4 => {
- if sr.cc4of().bit_is_set() {
- Err(nb::Error::Other(Error::Overcapture))
- } else if sr.cc4if().bit_is_set() {
- Ok(tim1.ccr4.read().ccr4().bits())
- } else {
- Err(nb::Error::WouldBlock)
- }
- }
+ Channel::_1 => if sr.cc1of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc1if().bit_is_set() {
+ Ok(tim1.ccr1.read().ccr1().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
+ Channel::_2 => if sr.cc2of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc2if().bit_is_set() {
+ Ok(tim1.ccr2.read().ccr2().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
+ Channel::_3 => if sr.cc3of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc3if().bit_is_set() {
+ Ok(tim1.ccr3.read().ccr3().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
+ Channel::_4 => if sr.cc4of().bit_is_set() {
+ Err(nb::Error::Other(Error::Overcapture))
+ } else if sr.cc4if().bit_is_set() {
+ Ok(tim1.ccr4.read().ccr4().bits())
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
}
}
diff --git a/src/dma.rs b/src/dma.rs
index 2aa1edc..0019657 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -40,18 +40,23 @@ pub struct Dma1Channel5 {
}
/// Buffer to be used with a certain DMA `CHANNEL`
+// NOTE(packed) workaround for rust-lang/rust#41315
+#[repr(packed)]
pub struct Buffer<T, CHANNEL> {
_marker: PhantomData<CHANNEL>,
data: UnsafeCell<T>,
flag: Cell<BorrowFlag>,
- status: Cell<Status>,
+ state: Cell<State>,
}
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-enum Status {
+enum State {
+ // A new `Buffer` starts in this state. We set it to zero to place this
+ // buffer in the .bss section
+ Unlocked = 0,
+
Locked,
MutLocked,
- Unlocked,
}
type BorrowFlag = usize;
@@ -118,7 +123,7 @@ impl<T, CHANNEL> Buffer<T, CHANNEL> {
_marker: PhantomData,
data: UnsafeCell::new(data),
flag: Cell::new(0),
- status: Cell::new(Status::Unlocked),
+ state: Cell::new(State::Unlocked),
}
}
@@ -161,33 +166,33 @@ impl<T, CHANNEL> Buffer<T, CHANNEL> {
}
pub(crate) fn lock(&self) -> &T {
- assert_eq!(self.status.get(), Status::Unlocked);
+ assert_eq!(self.state.get(), State::Unlocked);
assert_ne!(self.flag.get(), WRITING);
self.flag.set(self.flag.get() + 1);
- self.status.set(Status::Locked);
+ self.state.set(State::Locked);
unsafe { &*self.data.get() }
}
pub(crate) fn lock_mut(&self) -> &mut T {
- assert_eq!(self.status.get(), Status::Unlocked);
+ assert_eq!(self.state.get(), State::Unlocked);
assert_eq!(self.flag.get(), UNUSED);
self.flag.set(WRITING);
- self.status.set(Status::MutLocked);
+ self.state.set(State::MutLocked);
unsafe { &mut *self.data.get() }
}
- unsafe fn unlock(&self, status: Status) {
- match status {
- Status::Locked => self.flag.set(self.flag.get() - 1),
- Status::MutLocked => self.flag.set(UNUSED),
+ unsafe fn unlock(&self, state: State) {
+ match state {
+ State::Locked => self.flag.set(self.flag.get() - 1),
+ State::MutLocked => self.flag.set(UNUSED),
_ => { /* unreachable!() */ }
}
- self.status.set(Status::Unlocked);
+ self.state.set(State::Unlocked);
}
}
@@ -195,16 +200,16 @@ impl<T, CHANNEL> Buffer<T, CHANNEL> {
impl<T> Buffer<T, Dma1Channel2> {
/// Waits until the DMA releases this buffer
pub fn release(&self, dma1: &DMA1) -> nb::Result<(), Error> {
- let status = self.status.get();
+ let state = self.state.get();
- if status == Status::Unlocked {
+ if state == State::Unlocked {
return Ok(());
}
if dma1.isr.read().teif2().bit_is_set() {
Err(nb::Error::Other(Error::Transfer))
} else if dma1.isr.read().tcif2().bit_is_set() {
- unsafe { self.unlock(status) }
+ unsafe { self.unlock(state) }
dma1.ifcr.write(|w| w.ctcif2().set_bit());
dma1.ccr2.modify(|_, w| w.en().clear_bit());
Ok(())
@@ -217,16 +222,16 @@ impl<T> Buffer<T, Dma1Channel2> {
impl<T> Buffer<T, Dma1Channel4> {
/// Waits until the DMA releases this buffer
pub fn release(&self, dma1: &DMA1) -> nb::Result<(), Error> {
- let status = self.status.get();
+ let state = self.state.get();
- if status == Status::Unlocked {
+ if state == State::Unlocked {
return Ok(());
}
if dma1.isr.read().teif4().bit_is_set() {
Err(nb::Error::Other(Error::Transfer))
} else if dma1.isr.read().tcif4().bit_is_set() {
- unsafe { self.unlock(status) }
+ unsafe { self.unlock(state) }
dma1.ifcr.write(|w| w.ctcif4().set_bit());
dma1.ccr4.modify(|_, w| w.en().clear_bit());
Ok(())
@@ -239,16 +244,16 @@ impl<T> Buffer<T, Dma1Channel4> {
impl<T> Buffer<T, Dma1Channel5> {
/// Waits until the DMA releases this buffer
pub fn release(&self, dma1: &DMA1) -> nb::Result<(), Error> {
- let status = self.status.get();
+ let state = self.state.get();
- if status == Status::Unlocked {
+ if state == State::Unlocked {
return Ok(());
}
if dma1.isr.read().teif5().bit_is_set() {
Err(nb::Error::Other(Error::Transfer))
} else if dma1.isr.read().tcif5().bit_is_set() {
- unsafe { self.unlock(status) }
+ unsafe { self.unlock(state) }
dma1.ifcr.write(|w| w.ctcif5().set_bit());
dma1.ccr5.modify(|_, w| w.en().clear_bit());
Ok(())
@@ -262,21 +267,21 @@ impl<T> Buffer<T, Dma1Channel5> {
pub struct CircBuffer<B, CHANNEL> {
_marker: PhantomData<CHANNEL>,
buffer: UnsafeCell<[B; 2]>,
- status: Cell<CircStatus>,
+ state: Cell<CircState>,
}
impl<B, CHANNEL> CircBuffer<B, CHANNEL> {
pub(crate) fn lock(&self) -> &[B; 2] {
- assert_eq!(self.status.get(), CircStatus::Free);
+ assert_eq!(self.state.get(), CircState::Free);
- self.status.set(CircStatus::MutatingFirstHalf);
+ self.state.set(CircState::MutatingFirstHalf);
unsafe { &*self.buffer.get() }
}
}
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-enum CircStatus {
+enum CircState {
/// Not in use by the DMA
Free,
/// The DMA is mutating the first half of the buffer
@@ -291,7 +296,7 @@ impl<B> CircBuffer<B, Dma1Channel1> {
CircBuffer {
_marker: PhantomData,
buffer: UnsafeCell::new(buffer),
- status: Cell::new(CircStatus::Free),
+ state: Cell::new(CircState::Free),
}
}
@@ -301,54 +306,50 @@ impl<B> CircBuffer<B, Dma1Channel1> {
where
F: FnOnce(&B) -> R,
{
- let status = self.status.get();
+ let state = self.state.get();
- assert_ne!(status, CircStatus::Free);
+ assert_ne!(state, CircState::Free);
let isr = dma1.isr.read();
if isr.teif1().bit_is_set() {
Err(nb::Error::Other(Error::Transfer))
} else {
- match status {
- CircStatus::MutatingFirstHalf => {
- if isr.tcif1().bit_is_set() {
- Err(nb::Error::Other(Error::Overrun))
- } else if isr.htif1().bit_is_set() {
- dma1.ifcr.write(|w| w.chtif1().set_bit());
+ match state {
+ CircState::MutatingFirstHalf => if isr.tcif1().bit_is_set() {
+ Err(nb::Error::Other(Error::Overrun))
+ } else if isr.htif1().bit_is_set() {
+ dma1.ifcr.write(|w| w.chtif1().set_bit());
- self.status.set(CircStatus::MutatingSecondHalf);
+ self.state.set(CircState::MutatingSecondHalf);
- let ret = f(unsafe { &(*self.buffer.get())[0] });
+ let ret = f(unsafe { &(*self.buffer.get())[0] });
- if isr.tcif1().bit_is_set() {
- Err(nb::Error::Other(Error::Overrun))
- } else {
- Ok(ret)
- }
+ if isr.tcif1().bit_is_set() {
+ Err(nb::Error::Other(Error::Overrun))
} else {
- Err(nb::Error::WouldBlock)
+ Ok(ret)
}
- }
- CircStatus::MutatingSecondHalf => {
- if isr.htif1().bit_is_set() {
- Err(nb::Error::Other(Error::Overrun))
- } else if isr.tcif1().bit_is_set() {
- dma1.ifcr.write(|w| w.ctcif1().set_bit());
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
+ CircState::MutatingSecondHalf => if isr.htif1().bit_is_set() {
+ Err(nb::Error::Other(Error::Overrun))
+ } else if isr.tcif1().bit_is_set() {
+ dma1.ifcr.write(|w| w.ctcif1().set_bit());
- self.status.set(CircStatus::MutatingFirstHalf);
+ self.state.set(CircState::MutatingFirstHalf);
- let ret = f(unsafe { &(*self.buffer.get())[1] });
+ let ret = f(unsafe { &(*self.buffer.get())[1] });
- if isr.htif1().bit_is_set() {
- Err(nb::Error::Other(Error::Overrun))
- } else {
- Ok(ret)
- }
+ if isr.htif1().bit_is_set() {
+ Err(nb::Error::Other(Error::Overrun))
} else {
- Err(nb::Error::WouldBlock)
+ Ok(ret)
}
- }
+ } else {
+ Err(nb::Error::WouldBlock)
+ },
_ => unreachable!(),
}
}
diff --git a/src/pwm.rs b/src/pwm.rs
index 54d87ee..05c0145 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -36,7 +36,7 @@ use core::marker::Unsize;
use cast::{u16, u32};
use hal;
use static_ref::Static;
-use stm32f103xx::{AFIO, DMA1, GPIOA, RCC, TIM1, TIM2, TIM3, TIM4};
+use stm32f103xx::{DMA1, TIM1, TIM2, TIM3, TIM4, AFIO, GPIOA, RCC};
use dma::{self, Buffer, Dma1Channel2};
use timer::{Channel, TIM};
diff --git a/src/qei.rs b/src/qei.rs
index 6281bbc..13ff176 100644
--- a/src/qei.rs
+++ b/src/qei.rs
@@ -24,7 +24,7 @@ use core::any::{Any, TypeId};
use core::u16;
use hal;
-use stm32f103xx::{AFIO, GPIOA, RCC, TIM1, TIM2, TIM3, TIM4};
+use stm32f103xx::{TIM1, TIM2, TIM3, TIM4, AFIO, GPIOA, RCC};
use timer::TIM;
diff --git a/src/serial.rs b/src/serial.rs
index baffdf6..8d9ceaa 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -29,8 +29,8 @@ use cast::u16;
use hal;
use nb;
use static_ref::Static;
-use stm32f103xx::{AFIO, DMA1, GPIOA, GPIOB, RCC, USART1, USART2, USART3,
- gpioa, usart1};
+use stm32f103xx::{gpioa, DMA1, USART1, USART2, USART3, usart1, AFIO, GPIOA,
+ GPIOB, RCC};
use dma::{self, Buffer, Dma1Channel4, Dma1Channel5};
diff --git a/src/spi.rs b/src/spi.rs
index d0ecfc9..ddf407a 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -22,7 +22,7 @@ use core::ptr;
use hal;
use nb;
-use stm32f103xx::{AFIO, GPIOA, GPIOB, RCC, SPI1, SPI2, gpioa, spi1};
+use stm32f103xx::{gpioa, SPI1, SPI2, spi1, AFIO, GPIOA, GPIOB, RCC};
/// SPI instance that can be used with the `Spi` abstraction
pub unsafe trait SPI: Deref<Target = spi1::RegisterBlock> {
@@ -101,9 +101,8 @@ where
} else if spi.get_type_id() == TypeId::of::<SPI2>() {
// enable AFIO, SPI1, GPIOA
rcc.apb1enr.modify(|_, w| w.spi2en().enabled());
- rcc.apb2enr.modify(
- |_, w| w.afioen().enabled().iopben().enabled(),
- );
+ rcc.apb2enr
+ .modify(|_, w| w.afioen().enabled().iopben().enabled());
// NSS = PB12 = Alternate function push pull
// SCK = PB13 = Alternate function push pull
diff --git a/src/timer.rs b/src/timer.rs
index f1acddd..a60aaac 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -6,7 +6,7 @@ use core::ops::Deref;
use cast::{u16, u32};
use hal;
use nb::{self, Error};
-use stm32f103xx::{GPIOA, GPIOB, RCC, TIM1, TIM2, TIM3, TIM4, gpioa, tim2};
+use stm32f103xx::{gpioa, TIM1, TIM2, TIM3, TIM4, tim2, GPIOA, GPIOB, RCC};
/// Channel associated to a timer
#[derive(Clone, Copy, Debug)]
--
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