diff --git a/examples/zero-tasks.rs b/examples/zero-tasks.rs index 9e81802197822cb7ebfdf71de65dfc43a28b023a..2ef6bd0b0b747161e060a58bf7dd9b518cf588dc 100644 --- a/examples/zero-tasks.rs +++ b/examples/zero-tasks.rs @@ -33,51 +33,21 @@ fn pll0_feed_sequence(syscon: &lpc176x5x::SYSCON) { .write(|w| unsafe { w.pll0feed().bits(0x55) }); } -// The initialization phase. -// -// This runs first and within a *global* critical section. Nothing can preempt -// this function. -fn init(p: init::Peripherals) { - // use lpc176x5x::syscon::clksrcsel::*; - // use lpc176x5x::syscon::scs::*; - // use lpc176x5x::syscon::clkoutcfg::*; - - // This function has access to all the peripherals of the device - let itm = p.ITM; - iprintln!(&itm.stim[0], "1769 init"); - // let r = p.SYSCON.clksrcsel.read().clksrc(); - // match r { - // CLKSRCR::SELECTS_THE_INTERNAL => rtfm::bkpt(), - // _ => rtfm::bkpt(), - // } - +// sets the main clock to 100Mhz, buses to 25Mhz +fn clk_init(p: &init::Peripherals) { // setup clock output to p1.27 p.SYSCON .clkoutcfg .write(|w| w.clkoutsel().selects_the_cpu_cloc().clkout_en().set_bit()); - iprintln!( - &itm.stim[0], - "CLKSRSEL {:?}", - p.SYSCON.clksrcsel.read().clksrc() - ); - iprintln!( - &itm.stim[0], - "CLKOUTDIV {:?}", - p.SYSCON.clkoutcfg.read().clkoutdiv().bits() - ); - // connect (rout) cklout to p1.27 p.PINCONNECT.pinsel3.write(|w| w.p1_27().clkout()); // set the pin direction to output p.GPIO.dir1.write(|w| w.pindir27().set_bit()); // enable external oscillator, and spinwait until ready - let mut x = 0; p.SYSCON.scs.write(|w| w.oscen().enabled()); - while p.SYSCON.scs.read().oscstat().is_not_ready() { - x += 1; - } + while p.SYSCON.scs.read().oscstat().is_not_ready() {} p.SYSCON.cclkcfg.write(|w| unsafe { w.cclksel().bits(3) }); // PLL0 / 4 @@ -108,10 +78,8 @@ fn init(p: init::Peripherals) { pll0_feed_sequence(&p.SYSCON); // wait until PLL0 locked - x = 0; - while p.SYSCON.pll0stat.read().plock0().bit_is_clear() { - x += 1; - } + while p.SYSCON.pll0stat.read().plock0().bit_is_clear() {} + // enable and connect PLL0 p.SYSCON .pll0con @@ -120,19 +88,33 @@ fn init(p: init::Peripherals) { pll0_feed_sequence(&p.SYSCON); // wait until PLL0 both connected and enabled - x = 0; while p.SYSCON.pll0stat.read().plle0_stat().bit_is_clear() || p.SYSCON.pll0stat.read().pllc0_stat().bit_is_clear() - { - x += 1; - } + {} + + // we are not using USB so PLL1 is left disabled +} - iprintln!(&itm.stim[0], "-- here -- {}", x); +// The initialization phase. +// +// This runs first and within a *global* critical section. Nothing can preempt +// this function. +fn init(p: init::Peripherals) { + clk_init(&p); + let itm = p.ITM; + iprintln!(&itm.stim[0], "-- Running at 100Mhz -- "); rtfm::bkpt(); + // use lpc176x5x::syscon::clksrcsel::*; + // use lpc176x5x::syscon::scs::*; + // use lpc176x5x::syscon::clkoutcfg::*; + + // This function has access to all the peripherals of the device + // setup ethernet mac } + // The idle loop. // // This runs after `init` and has a priority of 0. All tasks can preempt this