diff --git a/.cargo/config b/.cargo/config
index 1ab52827c2bfa858bc120a5e4f7a33137de3649c..b16330a6d51ad26678784eb880f48632ce8bb32b 100644
--- a/.cargo/config
+++ b/.cargo/config
@@ -31,4 +31,4 @@ rustflags = [
]
[build]
-target = "thumbv7em-none-eabihf"
\ No newline at end of file
+target = "thumbv7m-none-eabi"
\ No newline at end of file
diff --git a/.gdbinit b/.gdbinit
index 7c72d4fb1f4064ffbe5275f665caa65846bf90da..ac666ae84f5cb33fb0025cc60d41a050d29a4ca9 100644
--- a/.gdbinit
+++ b/.gdbinit
@@ -1,6 +1,8 @@
-target remote :3333
-monitor arm semihosting enable
+monitor reset init
+monitor adapter_khz 1000
+monitor arm semihosting enable
+monitor reset init
load
-step
+monitor reset init
\ No newline at end of file
diff --git a/.gdbinit_org b/.gdbinit_org
new file mode 100644
index 0000000000000000000000000000000000000000..2ad46f6b179569dc714300e36c8cf9e36440c196
--- /dev/null
+++ b/.gdbinit_org
@@ -0,0 +1,9 @@
+target remote :3333
+monitor reset init
+monitor adapter_khz 4000
+monitor arm semihosting enable
+
+load
+monitor reset init
+step
+
diff --git a/.vscode/launch.json b/.vscode/launch.json
index 9b0e94793b69884354de1ba53e5cf96bcc9994d6..d97d76836e1a496ec47a54adac4b71e44d73d67d 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -111,15 +111,16 @@
"request": "attach",
"name": "Debug zero-tasks",
"gdbpath": "/usr/bin/arm-none-eabi-gdb",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/zero-tasks",
+ "executable": "./target/thumbv7m-none-eabi/debug/examples/zero-tasks",
"target": ":3333",
"remote": true,
"autorun": [
"monitor reset init",
+ "monitor adapter_khz 5000",
"monitor arm semihosting enable",
- "monitor tpiu config internal /tmp/itm.log uart off 16000000",
- "monitor itm port 0 on",
- "load"
+ "monitor reset init",
+ "load",
+ "monitor reset init"
],
"cwd": "${workspaceRoot}"
}
diff --git a/Readme.md b/Readme.md
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/doc.md b/doc.md
new file mode 100644
index 0000000000000000000000000000000000000000..4dad768399765e84699a69ae0580df47a6d940f0
--- /dev/null
+++ b/doc.md
@@ -0,0 +1,38 @@
+lpcexpesso lpc1769
+board description "LPCXpressoLPC1769revB.pdf"
+
+* SWD/JTAG Interface, lpc
+Jumper j4, (desoldered)
+
+
+ 2 VIO_3V3X
+ 4 JTAG_TMS_SWDIOX
+ 6 JTAG_TCLK_SWCLKX
+ 8 JTAG_TDO_SWOX
+ 10 JTAG_TDIX
+ 12 JTAG_RESETX
+ 14 EXT_POWX
+ 16 GNDX
+
+* SWD/JTAG Interface, nucleo, UM1724, Table 5
+1 VDD_TARGET
+2 SWCLK
+3 GND
+4 SWDIO
+5 NRST
+6 SWO
+
+
+nucleo lpc
+1 VDD_TARGET - White - 2 VIO_3V3X (not used)
+2 SWCLK - Pink - 6 TCLK_SWCLKX
+3 GND - Black - 16 GNDX
+4 SWDIO - Grey - 4 TMS_SWDIOX
+5 NRST - Blue - 12 RESETX
+
+on the lpc, j4, power is provided from the usb, pin 1-2 bridged
+NRST, should it be connected?
+
+openocd -f interface/stlink-v2-1.cfg -f target/lpc17xx.cfg -c "init; reset halt"
+
+
diff --git a/examples/simple.rs b/examples/simple.rs
new file mode 100644
index 0000000000000000000000000000000000000000..a54d1ef2f2df0445888a58e30b59cca497f3a185
--- /dev/null
+++ b/examples/simple.rs
@@ -0,0 +1,28 @@
+//! Nesting claims and how the preemption threshold works
+//!
+//! If you run this program you'll hit the breakpoints as indicated by the
+//! letters in the comments: A, then B, then C, etc.
+#![deny(unsafe_code)]
+#![feature(proc_macro)]
+#![no_std]
+
+extern crate cortex_m_rtfm as rtfm;
+extern crate stm32f40x;
+
+use stm32f40x::Interrupt;
+use rtfm::{app, Resource, Threshold};
+
+app! {
+ device: stm32f40x,
+}
+
+fn init(_p: init::Peripherals, _r: init::Resources) {
+ rtfm::bkpt();
+}
+
+#[inline(never)]
+fn idle() -> ! {
+ rtfm::bkpt();
+
+ loop {}
+}
diff --git a/examples/zero-tasks.rs b/examples/zero-tasks.rs
index 91ff10334ebf92aea3da04e23b5f414bfdfbdf14..9b2dd270f62d90044331b2c9e9e583066f763d28 100644
--- a/examples/zero-tasks.rs
+++ b/examples/zero-tasks.rs
@@ -37,8 +37,13 @@ fn init(p: init::Peripherals) {
// function. This function can never return so it must contain some sort of
// endless loop.
fn idle() -> ! {
+ let mut x = 0;
+ for i in 0..10 {
+ x += 1;
+ }
+ rtfm::bkpt();
loop {
// This puts the processor to sleep until there's a task to service
- rtfm::wfi();
+ // rtfm::wfi();
}
}
diff --git a/lpc17xx.cfg b/lpc17xx.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f6f9ce8d78f10d42942ab7d641864f64f73c247c
--- /dev/null
+++ b/lpc17xx.cfg
@@ -0,0 +1,14 @@
+# NXP LPC17xx Cortex-M3 with at least 8kB SRAM
+set CHIPNAME lpc17xx
+set CHIPSERIES lpc1700
+if { ![info exists WORKAREASIZE] } {
+ set WORKAREASIZE 0x2000
+}
+$CHIPNAME configure -event gdb-attach {
+ halt
+}
+ $CHIPNAME configure -event gdb-attach {
+ reset init
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/lpc1xxx.cfg b/lpc1xxx.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..9c10e9f933a3bc1633e22e611d7dfa08a86131ca
--- /dev/null
+++ b/lpc1xxx.cfg
@@ -0,0 +1,159 @@
+# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
+#
+# !!!!!!
+#
+# This file should not be included directly, rather by the lpc11xx.cfg,
+# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
+# appropriate values.
+#
+# !!!!!!
+
+# LPC8xx chips support only SWD transport.
+# LPC11xx chips support only SWD transport.
+# LPC12xx chips support only SWD transport.
+# LPC11Uxx chips support only SWD transports.
+# LPC13xx chips support only SWD transports.
+# LPC17xx chips support both JTAG and SWD transports.
+# LPC40xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+if { [info exists CHIPSERIES] } {
+ # Validate chip series is supported
+ if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } {
+ error "Unsupported LPC1xxx chip series specified."
+ }
+ set _CHIPSERIES $CHIPSERIES
+} else {
+ error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+# After reset, the chip is clocked by an internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+ # Allow user override
+ set _CCLK $CCLK
+} else {
+ # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
+ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+ set _CCLK 12000
+ } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+ set _CCLK 4000
+ }
+}
+
+if { [info exists CPUTAPID] } {
+ # Allow user override
+ set _CPUTAPID $CPUTAPID
+} else {
+ # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
+ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
+ set _CPUTAPID 0x0bb11477
+ } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+ if { [using_jtag] } {
+ set _CPUTAPID 0x4ba00477
+ } {
+ set _CPUTAPID 0x2ba01477
+ }
+ }
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+
+# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
+
+# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
+# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
+# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
+# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
+# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
+# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
+#
+# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
+# (same cmd51 destination boundary alignment, and all three support 256 byte
+# transfers).
+#
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
+ auto $_CCLK calc_checksum
+
+if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+ # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
+ # "User Flash Mode" where interrupt vectors are _not_ remapped,
+ # and reside in flash instead).
+ #
+ # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+ # Bit Symbol Value Description
+ # 1:0 MAP System memory remap
+ # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
+ # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
+ # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
+ # 31:2 - - Reserved.
+ $_TARGETNAME configure -event reset-init {
+ mww 0x40048000 0x02
+ }
+} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+ # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+ # "User Flash Mode" where interrupt vectors are _not_ remapped,
+ # and reside in flash instead).
+ #
+ # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+ # Bit Symbol Value Description Reset
+ # value
+ # 0 MAP Memory map control. 0
+ # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+ # 1 User mode. The on-chip Flash memory is mapped to address 0.
+ # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+ #
+ # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+ $_TARGETNAME configure -event reset-init {
+ mww 0x400FC040 0x01
+ }
+}
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter_khz 10
+
+# delays on reset lines
+adapter_nsrst_delay 200
+if {[using_jtag]} {
+ jtag_ntrst_delay 200
+}
+
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
diff --git a/memory.x b/memory.x
index 534d4786655e3734779bc36863f96c07c9c03a24..006c5e8cc15da0e5f324eac530e395faa27df91a 100644
--- a/memory.x
+++ b/memory.x
@@ -1,6 +1,6 @@
-/* STM32F103C8V6 */
+/* lpc176[8, 9] */
MEMORY
{
- FLASH : ORIGIN = 0x08000000, LENGTH = 64K
- RAM : ORIGIN = 0x20000000, LENGTH = 20K
+ FLASH : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM : ORIGIN = 0x10000000, LENGTH = 32K
}
diff --git a/openocd.cfg b/openocd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..9abc6bbb64bd4acb30785e2c53665d344dde1bde
--- /dev/null
+++ b/openocd.cfg
@@ -0,0 +1,19 @@
+set _CHIPNAME lpc1769
+
+source [find interface/stlink-v2.cfg]
+#transport select hla_swd
+
+hla newtap $_CHIPNAME cpu -expected-id 0x2ba01477
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME stm32_stlink -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 4000 calc_checksum
+
+$_TARGETNAME configure -event reset-init {
+ # remap flash to 0x0
+ mww 0x400FC040 0x01
+}
\ No newline at end of file
diff --git a/stlink-v2-1.cfg b/stlink-v2-1.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..093e80177078667dbc03e166ac5d7e997086b4f2
--- /dev/null
+++ b/stlink-v2-1.cfg
@@ -0,0 +1,16 @@
+#
+# STMicroelectronics ST-LINK/V2-1 in-circuit debugger/programmer
+#
+
+interface hla
+hla_layout stlink
+hla_device_desc "ST-LINK/V2-1"
+hla_vid_pid 0x0483 0x374b
+
+# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
+# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
+# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
+# number reset issues.
+# eg.
+#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
+
diff --git a/stlink-v2.cfg b/stlink-v2.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..ae545a1187762bbdbb80e24913dbe746421310f5
--- /dev/null
+++ b/stlink-v2.cfg
@@ -0,0 +1,16 @@
+#
+# STMicroelectronics ST-LINK/V2 in-circuit debugger/programmer
+#
+
+interface hla
+hla_layout stlink
+hla_device_desc "ST-LINK/V2"
+hla_vid_pid 0x0483 0x3748
+
+# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
+# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
+# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
+# number reset issues.
+# eg.
+#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
+