Commit 65f29a01 authored by Per's avatar Per

swd disable

parent 9474be3d
......@@ -22,11 +22,7 @@ use cortex_m::peripheral::Peripherals;
// debugging is possible even if sleeping
fn dbg_enable() {
let dbg = unsafe { &*stm32f103xx::DBG::ptr() };
let afio = unsafe { &*stm32f103xx::AFIO::ptr() };
// #[allow(non_snake_case)]
// let GPIOA = unsafe { &*stm32f40x::GPIOA::ptr() };
// #[allow(non_snake_case)]
// let GPIOB = unsafe { &*stm32f40x::GPIOB::ptr() };
dbg.cr.modify(|_, w| {
w.dbg_sleep()
.set_bit()
......@@ -37,41 +33,19 @@ fn dbg_enable() {
.trace_ioen()
.set_bit()
});
// 31.4.2, table 220
// afio.mapr.modify(|_, w| unsafe { w.swj_cfg().bits(0b000) }); // all debugging
// GPIOA.moder.reset();
// GPIOA.pupdr.reset();
// GPIOB.moder.reset();
// GPIOB.pupdr.reset();
}
// set the MCU in true sleepdeep mode on WFI/WFE
// debugging is disabled (until re-enabled)
fn dbg_disable() {
#[allow(non_snake_case)]
let DBG = unsafe { &*stm32f103xx::DBG::ptr() };
let afio = unsafe { &*stm32f103xx::AFIO::ptr() };
fn gpio_low_power() {
#[allow(non_snake_case)]
let GPIOA = unsafe { &*stm32f103xx::GPIOA::ptr() };
#[allow(non_snake_case)]
let GPIOB = unsafe { &*stm32f103xx::GPIOB::ptr() };
#[allow(non_snake_case)]
let GPIOC = unsafe { &*stm32f103xx::GPIOC::ptr() };
// set all gpio to analog input
let _a_crl_ = GPIOA.crl.read().bits();
let _a_crh_ = GPIOA.crh.read().bits();
// let _b_moder_ = GPIOB.crl.read().bits();
// let _a_pupdr_ = GPIOA.pupdr.read().bits();
// let _b_pupdr_ = GPIOB.pupdr.read().bits();
// 0.142 mA without manipulating GPIO/GPIOB
let v = GPIOA.crl.read().bits();
#[allow(non_snake_case)]
let GPIOD = unsafe { &*stm32f103xx::GPIOD::ptr() };
// GPIOA.crl.write(|w| unsafe { w.bits(0x0) }); // PA l, analog
// GPIOA.crl.modify(|_, w| w.cnf1().bits(0b10)); // PA1 input pull up/down
// set all gpio to analog input, besides PA1 (used for wakeup)
// set PA0, PA2-7, to analog mode
GPIOA.crl.modify(|_, w| {
......@@ -111,6 +85,7 @@ fn dbg_disable() {
.bits(0b00)
});
// set PB0-7 to analog mode
GPIOB.crl.modify(|_, w| {
w.cnf0()
.bits(0b00)
......@@ -130,7 +105,7 @@ fn dbg_disable() {
.bits(0b00)
});
// set PA8-15, to analog mode
// set PB8-15, to analog mode
GPIOB.crh.modify(|_, w| {
w.cnf8()
.bits(0b00)
......@@ -150,6 +125,7 @@ fn dbg_disable() {
.bits(0b00)
});
// set PC0-7 to analog mode
GPIOC.crl.modify(|_, w| {
w.cnf0()
.bits(0b00)
......@@ -169,7 +145,7 @@ fn dbg_disable() {
.bits(0b00)
});
// set PA8-15, to analog mode
// set PC8-15, to analog mode
GPIOC.crh.modify(|_, w| {
w.cnf8()
.bits(0b00)
......@@ -189,19 +165,45 @@ fn dbg_disable() {
.bits(0b00)
});
let vl = GPIOA.crl.read().bits();
let vh = GPIOA.crh.read().bits();
// GPIOA.crh.write(|w| unsafe { w.bits(0x0) }); // PA h, analog
// GPIOA.moder.modify(|_, w| w.moder1().input_mode()); // PA1, input_mode
// GPIOB.pupdr.write(|w| unsafe { w.bits(0) }); // PA, floating
// GPIOA.pupdr.modify(|_, w| w.pupdr1().pull_up()); // PA1, pull up
let _a_crl = GPIOA.crl.read().bits();
let _a_crh = GPIOA.crh.read().bits();
asm::nop();
// set PD0-7 to analog mode
GPIOD.crl.modify(|_, w| {
w.cnf0()
.bits(0b00)
.cnf1()
.bits(0b00)
.cnf2()
.bits(0b00)
.cnf3()
.bits(0b00)
.cnf4()
.bits(0b00)
.cnf5()
.bits(0b00)
.cnf6()
.bits(0b00)
.cnf7()
.bits(0b00)
});
// let swj = afio.mapr.read().bits();
// set PD8-15, to analog mode
GPIOD.crh.modify(|_, w| {
w.cnf8()
.bits(0b00)
.cnf9()
.bits(0b00)
.cnf10()
.bits(0b00)
.cnf11()
.bits(0b00)
.cnf12()
.bits(0b00)
.cnf13()
.bits(0b00)
.cnf14()
.bits(0b00)
.cnf15()
.bits(0b00)
});
// DBG.cr.modify(|_, w| {
// w.dbg_sleep()
......@@ -213,12 +215,24 @@ fn dbg_disable() {
// .trace_ioen()
// .clear_bit()
// });
}
// treat SWD pins PA 13, 14, 15 as general purose IO
fn swd_disable() {
#[allow(non_snake_case)]
let AFIO = unsafe { &*stm32f103xx::AFIO::ptr() };
// 31.4.2, table 220
// afio.mapr.modify(|_, w| unsafe { w.swj_cfg().bits(0b100) }); // no debugging
AFIO.mapr.modify(|_, w| unsafe { w.swj_cfg().bits(0b100) }); // no debugging
}
// treat SWD pins PA13, 14 15, as SWD
fn swd_enable() {
#[allow(non_snake_case)]
let AFIO = unsafe { &*stm32f103xx::AFIO::ptr() };
// GPIOB.moder.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); // PB, analog
// GPIOB.pupdr.write(|w| unsafe { w.bits(0) }); // PB, floating
// 31.4.2, table 220
AFIO.mapr.modify(|_, w| unsafe { w.swj_cfg().bits(0b000) }); // all debugging
}
// the program entry point is ...
......@@ -245,14 +259,14 @@ interrupt!(EXTI1, exti1);
// the exti1 interrupt implementation
fn exti1() {
// dbg_enable();
swd_enable();
led(10);
asm::bkpt();
// led(10);
swd_disable();
// clear pending state
let exti = unsafe { &*stm32f103xx::EXTI::ptr() };
exti.pr.write(|w| w.pr1().set_bit());
// dbg_disable();
}
fn led(i: u8) {
......@@ -295,8 +309,8 @@ fn main() -> ! {
r.AFIO.exticr1.modify(|_, w| unsafe { w.exti1().bits(0) });
// input by default
// r.GPIOA.crl.modify(|_, w| w.cnf1().bits(0b10)); // PA1 input pull up/down
// r.GPIOA.odr.modify(|_, w| w.odr1().set_bit()); // PA1 input pull up
r.GPIOA.crl.modify(|_, w| w.cnf1().bits(0b10)); // PA1 input pull up/down
r.GPIOA.odr.modify(|_, w| w.odr1().set_bit()); // PA1 input pull up
r.EXTI.ftsr.modify(|_, w| w.tr1().set_bit()); // EXTI1 trigger on falling, enable tr1
r.EXTI.imr.modify(|_, w| w.mr1().set_bit()); // EXTI1 interrupt mask register, enable mr1
......@@ -305,7 +319,7 @@ fn main() -> ! {
// test raising a software interrupt
// r.EXTI.swier.write(|w| w.swier1().set_bit()); // trigger sw interrupt
let pr = r.EXTI.pr.read().bits();
let _pr = r.EXTI.pr.read().bits();
// r.EXTI.pr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); // clear all pending interrups/events, a bit ugly
......@@ -322,14 +336,14 @@ fn main() -> ! {
// regulator in run mode (on)
// r.PWR.cr.modify(|_, w| w.pdds().clear_bit());
let pwr = r.PWR.cr.read().bits();
let _pwr = r.PWR.cr.read().bits();
asm::nop();
dbg_disable();
gpio_low_power();
r.EXTI.pr.write(|w| w.pr1().set_bit());
swd_disable();
loop {
asm::wfi();
//led(10);
}
}
......
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