examples/rtic_bare5.rs

+//! rtic_bare5.rs
+//!
+//! C Like Peripheral API
+//!
+//! What it covers:
+//! - abstractions in Rust
+//! - structs and implementations
+
+#![no_std]
+#![no_main]
+
+extern crate cortex_m;
+extern crate panic_semihosting;
+
+// C like API...
+mod stm32f40x {
+    #[allow(dead_code)]
+    use core::{cell, ptr};
+
+    #[rustfmt::skip]
+    mod address {
+        pub const PERIPH_BASE: u32      = 0x40000000;
+        pub const AHB1PERIPH_BASE: u32  = PERIPH_BASE + 0x00020000;
+        pub const RCC_BASE: u32         = AHB1PERIPH_BASE + 0x3800;
+        pub const GPIOA_BASE: u32       = AHB1PERIPH_BASE + 0x0000;
+    }
+    use address::*;
+
+    pub struct VolatileCell<T> {
+        pub value: cell::UnsafeCell<T>,
+    }
+
+    impl<T> VolatileCell<T> {
+        #[inline(always)]
+        pub fn read(&self) -> T
+        where
+            T: Copy,
+        {
+            unsafe { ptr::read_volatile(self.value.get()) }
+        }
+
+        #[inline(always)]
+        pub fn write(&self, value: T)
+        where
+            T: Copy,
+        {
+            unsafe { ptr::write_volatile(self.value.get(), value) }
+        }
+    }
+
+    // modify (reads, modifies a field, and writes the volatile cell)
+    //
+    // parameters:
+    // offset (field offset)
+    // width  (field width)
+    // value  (new value that the field should take)
+    //
+    impl VolatileCell<u32> {
+        #[inline(always)]
+        pub fn modify(&self, offset: u8, width: u8, value: u32) {
+            // your code here
+        }
+    }
+
+    #[repr(C)]
+    #[allow(non_snake_case)]
+    #[rustfmt::skip]
+    pub struct RCC {
+        pub CR:         VolatileCell<u32>,      // < RCC clock control register,                                    Address offset: 0x00 
+        pub PLLCFGR:    VolatileCell<u32>,      // < RCC PLL configuration register,                                Address offset: 0x04 
+        pub CFGR:       VolatileCell<u32>,      // < RCC clock configuration register,                              Address offset: 0x08 
+        pub CIR:        VolatileCell<u32>,      // < RCC clock interrupt register,                                  Address offset: 0x0C 
+        pub AHB1RSTR:   VolatileCell<u32>,      // < RCC AHB1 peripheral reset register,                            Address offset: 0x10 
+        pub AHB2RSTR:   VolatileCell<u32>,      // < RCC AHB2 peripheral reset register,                            Address offset: 0x14 
+        pub AHB3RSTR:   VolatileCell<u32>,      // < RCC AHB3 peripheral reset register,                            Address offset: 0x18 
+        pub RESERVED0:  VolatileCell<u32>,      // < Reserved, 0x1C                                                                      
+        pub APB1RSTR:   VolatileCell<u32>,      // < RCC APB1 peripheral reset register,                            Address offset: 0x20 
+        pub APB2RSTR:   VolatileCell<u32>,      // < RCC APB2 peripheral reset register,                            Address offset: 0x24 
+        pub RESERVED1:  [VolatileCell<u32>; 2], // < Reserved, 0x28-0x2C                                                                 
+        pub AHB1ENR:    VolatileCell<u32>,      // < RCC AHB1 peripheral clock register,                            Address offset: 0x30 
+        pub AHB2ENR:    VolatileCell<u32>,      // < RCC AHB2 peripheral clock register,                            Address offset: 0x34 
+        pub AHB3ENR:    VolatileCell<u32>,      // < RCC AHB3 peripheral clock register,                            Address offset: 0x38 
+        pub RESERVED2:  VolatileCell<u32>,      // < Reserved, 0x3C                                                                      
+        pub APB1ENR:    VolatileCell<u32>,      // < RCC APB1 peripheral clock enable register,                     Address offset: 0x40 
+        pub APB2ENR:    VolatileCell<u32>,      // < RCC APB2 peripheral clock enable register,                     Address offset: 0x44 
+        pub RESERVED3:  [VolatileCell<u32>; 2], // < Reserved, 0x48-0x4C                                                                 
+        pub AHB1LPENR:  VolatileCell<u32>,      // < RCC AHB1 peripheral clock enable in low power mode register,   Address offset: 0x50 
+        pub AHB2LPENR:  VolatileCell<u32>,      // < RCC AHB2 peripheral clock enable in low power mode register,   Address offset: 0x54 
+        pub AHB3LPENR:  VolatileCell<u32>,      // < RCC AHB3 peripheral clock enable in low power mode register,   Address offset: 0x58 
+        pub RESERVED4:  VolatileCell<u32>,      // < Reserved, 0x5C                                                                      
+        pub APB1LPENR:  VolatileCell<u32>,      // < RCC APB1 peripheral clock enable in low power mode register,   Address offset: 0x60 
+        pub APB2LPENR:  VolatileCell<u32>,      // < RCC APB2 peripheral clock enable in low power mode register,   Address offset: 0x64 
+        pub RESERVED5:  [VolatileCell<u32>; 2], // < Reserved, 0x68-0x6C                                                                 
+        pub BDCR:       VolatileCell<u32>,      // < RCC Backup domain control register,                            Address offset: 0x70 
+        pub CSR:        VolatileCell<u32>,      // < RCC clock control & status register,                           Address offset: 0x74 
+        pub RESERVED6:  [VolatileCell<u32>; 2], // < Reserved, 0x78-0x7C                                                                 
+        pub SSCGR:      VolatileCell<u32>,      // < RCC spread spectrum clock generation register,                 Address offset: 0x80 
+        pub PLLI2SCFGR: VolatileCell<u32>,      // < RCC PLLI2S configuration register,                             Address offset: 0x84 
+    }
+
+    impl RCC {
+        pub fn get() -> *mut RCC {
+            address::RCC_BASE as *mut RCC
+        }
+    }
+
+    #[repr(C)]
+    #[allow(non_snake_case)]
+    #[rustfmt::skip]
+    pub struct GPIOA {
+        pub MODER:      VolatileCell<u32>,      // < GPIO port mode register,                                       Address offset: 0x00     
+        pub OTYPER:     VolatileCell<u32>,      // < GPIO port output type register,                                Address offset: 0x04     
+        pub OSPEEDR:    VolatileCell<u32>,      // < GPIO port output speed register,                               Address offset: 0x08     
+        pub PUPDR:      VolatileCell<u32>,      // < GPIO port pull-up/pull-down register,                          Address offset: 0x0C     
+        pub IDR:        VolatileCell<u32>,      // < GPIO port input data register,                                 Address offset: 0x10     
+        pub ODR:        VolatileCell<u32>,      // < GPIO port output data register,                                Address offset: 0x14     
+        pub BSRRL:      VolatileCell<u16>,      // < GPIO port bit set/reset low register,                          Address offset: 0x18     
+        pub BSRRH:      VolatileCell<u16>,      // < GPIO port bit set/reset high register,                         Address offset: 0x1A     
+        pub LCKR:       VolatileCell<u32>,      // < GPIO port configuration lock register,                         Address offset: 0x1C     
+        pub AFR:        [VolatileCell<u32>;2],  // < GPIO alternate function registers,                             Address offset: 0x20-0x24
+    }
+
+    impl GPIOA {
+        pub fn get() -> *mut GPIOA {
+            GPIOA_BASE as *mut GPIOA
+        }
+    }
+}
+use stm32f40x::*;
+
+// see the Reference Manual RM0368 (www.st.com/resource/en/reference_manual/dm00096844.pdf)
+// rcc,     chapter 6
+// gpio,    chapter 8
+
+fn wait(i: u32) {
+    for _ in 0..i {
+        cortex_m::asm::nop(); // no operation (cannot be optimized out)
+    }
+}
+
+// simple test of Your `modify`
+//
+fn test_modify() {
+    let t: VolatileCell<u32> = VolatileCell {
+        value: core::cell::UnsafeCell::new(0),
+    };
+    t.write(0);
+    assert!(t.read() == 0);
+    t.modify(3, 3, 0b10101);
+    //     10101
+    //    ..0111000
+    //    ---------
+    //    000101000
+    assert!(t.read() == 0b101 << 3);
+    t.modify(4, 3, 0b10001);
+    //    000101000
+    //      111
+    //      001
+    //    000011000
+    assert!(t.read() == 0b011 << 3);
+    //
+    // add more tests here if you like
+}
+
+#[rtic::app(device = stm32f4)]
+const APP: () = {
+    #[init]
+    fn init(_cx: init::Context) {
+        let rcc = unsafe { &mut *RCC::get() }; // get the reference to RCC in memory
+        let gpioa = unsafe { &mut *GPIOA::get() }; // get the reference to GPIOA in memory
+
+        // power on GPIOA
+        let r = rcc.AHB1ENR.read(); // read
+        rcc.AHB1ENR.write(r | 1 << (0)); // set enable
+
+        // configure PA5 as output
+        let r = gpioa.MODER.read() & !(0b11 << (5 * 2)); // read and mask
+        gpioa.MODER.write(r | 0b01 << (5 * 2)); // set output mode
+
+        // test_modify();
+
+        loop {
+            // set PA5 high
+            gpioa.BSRRH.write(1 << 5); // set bit, output hight (turn on led)
+
+            // alternatively to set the bit high we can
+            // read the value, or with PA5 (bit 5) and write back
+            // gpioa.ODR.write(gpioa.ODR.read() | (1 << 5));
+
+            wait(10_000);
+
+            // set PA5 low
+            gpioa.BSRRL.write(1 << 5); // clear bit, output low (turn off led)
+
+            // alternatively to clear the bit we can
+            // read the value, mask out PA5 (bit 5) and write back
+            // gpioa.ODR.write(gpioa.ODR.read() & !(1 << 5));
+            wait(10_000);
+        }
+    }
+};
+
+// 1. C like API.
+//    Using C the .h files are used for defining interfaces, like function signatures (prototypes),
+//    structs and macros (but usually not the functions themselves).
+//
+//    Here is a peripheral abstraction quite similar to what you would find in the .h files
+//    provided by ST (and other companies). Actually, the file presented here is mostly a
+//    cut/paste/replace of the stm32f40x.h, just Rustified.
+//
+//    In the loop we access PA5 through bit set/clear operations.
+//    Comment out those operations and uncomment the ODR based accesses.
+//    (They should have the same behavior, but is a bit less efficient.)
+//
+//    Run and see that the program behaves the same.
+//
+//    Commit your answers (bare5_1)
+//
+// 2. Extend the read/write API with a `modify` for u32, taking the
+//    - address (&mut u32),
+//    - field offset (in bits, u8),
+//    - field width (in bits, u8),
+//    - and value (u32).
+//
+//    Implement and check that running `test` gives you expected behavior.
+//
+//    Change the code into using your new `modify` API.
+//
+//    Run and see that the program behaves the same.
+//
+//    Discussion:
+//    As with arithmetic operations, default semantics differ in between
+//    debug/dev and release builds.
+//    In debug << rhs is checked, rhs must be less than 32 (for 32 bit datatypes).
+//
+//    Notice, over-shifting (where bits are spilled) is always considered legal,
+//    its just the shift amount that is checked.
+//    There are explicit unchecked versions available if so wanted.
+//
+//    We are now approaching a more "safe" to use API.
+//    What if we could automatically generate that from Vendors specifications (SVD files)?
+//    Wouldn't that be great?
+//
+//    ** your answer here **
+//
+//    Commit your answers (bare5_2)

examples/rtic_bare6.rs

+//! rtic_bare6.rs
+//!
+//! Clocking
+//!
+//! What it covers:
+//! - using svd2rust generated API
+//! - using the stm32f4xx-hal to set clocks
+//! - routing the clock to a PIN for monitoring by an oscilloscope
+
+#![no_main]
+#![no_std]
+
+use panic_rtt_target as _;
+use rtic::cyccnt::{Instant, U32Ext as _};
+use rtt_target::{rprintln, rtt_init_print};
+use stm32f4xx_hal::{
+    prelude::*,
+    stm32::{self, GPIOC, RCC},
+};
+
+const OFFSET: u32 = 8_000_000;
+
+#[rtic::app(device = stm32f4xx_hal::stm32, monotonic = rtic::cyccnt::CYCCNT, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        // late resources
+        GPIOA: stm32::GPIOA,
+    }
+    #[init(schedule = [toggle])]
+    fn init(cx: init::Context) -> init::LateResources {
+        rtt_init_print!();
+        rprintln!("init");
+
+        let mut core = cx.core;
+        let device = cx.device;
+
+        // Initialize (enable) the monotonic timer (CYCCNT)
+        core.DCB.enable_trace();
+        core.DWT.enable_cycle_counter();
+
+        // semantically, the monotonic timer is frozen at time "zero" during `init`
+        // NOTE do *not* call `Instant::now` in this context; it will return a nonsense value
+        let now = cx.start; // the start time of the system
+
+        // Schedule `toggle` to run 8e6 cycles (clock cycles) in the future
+        cx.schedule.toggle(now + OFFSET.cycles()).unwrap();
+
+        // setup LED
+        // power on GPIOA, RM0368 6.3.11
+        device.RCC.ahb1enr.modify(|_, w| w.gpioaen().set_bit());
+        // configure PA5 as output, RM0368 8.4.1
+        device.GPIOA.moder.modify(|_, w| w.moder5().bits(1));
+
+        clock_out(&device.RCC, &device.GPIOC);
+
+        let rcc = device.RCC.constrain();
+
+        let _clocks = rcc.cfgr.freeze();
+
+        // Set up the system clock. 48 MHz?
+        // let _clocks = rcc
+        //     .cfgr
+        //     .sysclk(48.mhz())
+        //     .pclk1(24.mhz())
+        //     .freeze();
+
+        // let _clocks = rcc
+        //     .cfgr
+        //     .sysclk(64.mhz())
+        //     .pclk1(64.mhz())
+        //     .pclk2(64.mhz())
+        //     .freeze();
+        //
+        // let _clocks = rcc
+        //     .cfgr
+        //     .sysclk(84.mhz())
+        //     .pclk1(42.mhz())
+        //     .pclk2(64.mhz())
+        //     .freeze();
+
+        // pass on late resources
+        init::LateResources {
+            GPIOA: device.GPIOA,
+        }
+    }
+
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        rprintln!("idle");
+        loop {
+            continue;
+        }
+    }
+
+    #[task(resources = [GPIOA], schedule = [toggle])]
+    fn toggle(cx: toggle::Context) {
+        static mut TOGGLE: bool = false;
+        rprintln!("toggle  @ {:?}", Instant::now());
+
+        if *TOGGLE {
+            cx.resources.GPIOA.bsrr.write(|w| w.bs5().set_bit());
+        } else {
+            cx.resources.GPIOA.bsrr.write(|w| w.br5().set_bit());
+        }
+
+        *TOGGLE = !*TOGGLE;
+        cx.schedule.toggle(cx.scheduled + OFFSET.cycles()).unwrap();
+    }
+
+    extern "C" {
+        fn EXTI0();
+    }
+};
+
+// see the Reference Manual RM0368 (www.st.com/resource/en/reference_manual/dm00096844.pdf)
+// rcc,     chapter 6
+// gpio,    chapter 8
+
+fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
+    // output MCO2 to pin PC9
+
+    // mco2 	: SYSCLK = 0b00
+    // mcopre 	: divide by 4 = 0b110
+    rcc.cfgr
+        .modify(|_, w| unsafe { w.mco2().bits(0b00).mco2pre().bits(0b110) });
+
+    // power on GPIOC, RM0368 6.3.11
+    rcc.ahb1enr.modify(|_, w| w.gpiocen().set_bit());
+
+    // MCO_2 alternate function AF0, STM32F401xD STM32F401xE data sheet
+    // table 9
+    // AF0, gpioc reset value = AF0
+
+    // configure PC9 as alternate function 0b10, RM0368 6.2.10
+    gpioc.moder.modify(|_, w| w.moder9().bits(0b10));
+
+    // otyper reset state push/pull, in reset state (don't need to change)
+
+    // ospeedr 0b11 = very high speed
+    gpioc.ospeedr.modify(|_, w| w.ospeedr9().bits(0b11));
+}
+
+// 0. Background reading:
+//
+//    Clock trees:
+//    STM32F401xD STM32F401xE, section 3.11
+//    We have two AMBA High-performance Buses (APBs)
+//    APB1 low speed bus (max freq 42 MHz)
+//    APB2 high speed bus (max freq 84 MHz)
+//
+//    RM0368 Section 6.2
+//    Some important/useful clock acronyms and their use:
+//
+//    SYSCLK - the clock that drives the `core`
+//    HCLK   - the clock that drives the AMBA bus(es), memory, DMA, trace unit, etc.
+//
+//    Typically we set HCLK = SYSCLK / 1 (no pre-scale) for our applications
+//
+//    FCLK   - Free running clock running at HCLK
+//
+//    CST    - CoreSystemTimer drives the SysTick counter, HCLK/(1 or 8)
+//    PCLK1  - The clock driving the APB1 (<= 42 MHz)
+//             Timers on the APB1 bus will be triggered at PCLK1 * 2
+//    PCLK2  - The clock driving the APB2 (<= 84 MHz)
+//             Timers on the APB2 bus will be triggered at PCLK2
+//
+//    Configuration:
+//
+//    The `Cargo.toml` file defines your dependencies.
+//
+//    [dependencies.stm32f4]
+//    version = "0.13.0"
+//    features = ["stm32f411", "rt"]
+//
+//    [dependencies.stm32f4xx-hal]
+//    version = "0.8.3"
+//    features = ["rt", "stm32f411", "usb_fs"]
+//
+//    The stm32f411 and f401 is essentially the same chip, the f411 is guaranteed
+//    up to 100MHz, but we can "overclock" the f401 to 100MHz if needed.
+//
+//    The `features = ["stm32f411", "rt"]` selects the target MCU, and
+//    "rt" enables functionality for exception handling etc.
+//
+//    The HAL provides a generic abstraction over the whole stm32f4 family.
+//
+//    In our configuration we enable "stm32f411" with the "rt" feature
+//    and the "usb_fs" (for USB OnTheGo support).
+//
+//    The HAL re-exports the selected "stm32f411" under the `stm32` path.
+//
+//    Initialization:
+//
+//    In the code, we first setup the DWT/CYCCNT for the Monotonic timer,
+//    and schedule a task to be run after `OFFSET` number of clock cycles.
+//
+//    The `device.RCC.constrain()`, gives a default setting for the MCU RCC
+//    (Reset and Clock Control) peripheral.
+//    `rcc.cfgr.x.freeze()`, freezes the current (default) config.
+//
+//    What is wrong with the following configurations?
+//
+//    `rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze()`;
+//
+//    ** your answer here **
+//
+//    `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
+//
+//    ** your answer here **
+//
+//    Start `stm32cubemx` and select or create a project targeting stm32f401.
+//    Go to the graphical clock configuration view.
+//
+//    Try to setup the clock according to:
+//
+//    `rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze()`;
+//
+//    What happens?
+//
+//    ** your answer here **
+//
+//    Try to setup the clock according to:
+//
+//    What happens?
+//
+//    `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
+//
+//    ** your answer here **
+//
+//    Commit your answers (bare6_0)
+//
+// 1. In this example you will use RTT.
+//
+//    > cargo run --example rtic_bare6
+//
+//    Confirm that your RTT traces the init, idle and led on/off.
+//
+//    What is the (default) MCU (SYSCLK) frequency?
+//
+//    ** your answer here **
+//
+//    What is the (default) DWT CYCCNT frequency?
+//
+//    ** your answer here **
+//
+//    What is the frequency of blinking?
+//
+//    ** your answer here **
+//
+//    Commit your answers (bare6_1)
+//
+// 2. Now connect an oscilloscope to PC9, which is set to
+//    output the MCO2.
+//
+//    Compute the value of SYSCLK based on the oscilloscope reading
+//
+//    ** your answer here **
+//
+//    What is the peak to peak (voltage) reading of the signal?
+//
+//    ** your answer here **
+//
+//    Make a folder called "pictures" in your git project.
+//    Make a screen dump or photo of the oscilloscope output.
+//    Save the the picture as "bare_6_16mhz_high_speed".
+//
+//    Commit your answers (bare6_2)
+//
+// 3. Now run the example in 48Mz, by commenting out line 56, and un-commenting
+//    lines 58-63.
+//`
+//    What is the frequency of blinking?
+//
+//    ** your answer here **
+//
+//    Now change the constant `OFFSET` so you get the same blinking frequency as in 1.
+//    Test and validate that you got the desired behavior.
+//
+//    Commit your answers (bare6_3)
+//
+// 4. Repeat experiment 2
+//
+//    What is the frequency of MCO2 read by the oscilloscope?
+//
+//    ** your answer here **
+//
+//    Compute the value of SYSCLK based on the oscilloscope reading.
+//
+//    ** your answer here **
+//
+//    What is the peak to peak reading of the signal?
+//
+//    ** your answer here **
+//
+//    Make a screen dump or photo of the oscilloscope output.
+//    Save the the picture as "bare_6_48mhz_high_speed".
+//
+//    Commit your answers (bare6_4)
+//
+// 5. In the `clock_out` function, the setup of registers is done through
+//    setting bit-pattens manually, e.g.
+//     rcc.cfgr
+//        .modify(|_, w| unsafe { w.mco2().bits(0b00).mco2pre().bits(0b110) });
+//
+//    However based on the vendor SVD file the svd2rust API provides
+//    a better abstraction, based on pattern enums and functions.
+//
+//    To view the API you can generate documentation for your crate:
+//
+//    > cargo doc --open
+//
+//    By searching for `mco2` you find the enumerations and functions.
+//    So here
+//       `w.mco2().bits{0b00}` is equivalent to
+//       `w.mco2().sysclk()` and improves readability.
+//
+//    Replace all bit-patterns used in `clock_out` by the function name equivalents.
+//    (alternatively, use the enum values.)
+//
+//    Test that the application still runs as before.
+//
+//    Commit your code (bare6_5)
+//
+// 6. Now reprogram the PC9 to be "Low Speed", and re-run at 48Mz.
+//
+//    Did the frequency change in comparison to assignment 5?
+//
+//    ** your answer here **
+//
+//    What is the peak to peak reading of the signal (and why did it change)?
+//
+//    ** your answer here **
+//
+//    Make a screen dump or photo of the oscilloscope output.
+//    Save the the picture as "bare_6_48mhz_low_speed".
+//
+//    Commit your answers (bare6_6)
+//
+// 7. Try setting the clocks according to:
+//
+//    `rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze()`;
+//
+//    Does the code compile?
+//
+//    ** your answer here **
+//
+//    What happens at run-time?
+//
+//    ** your answer here **
+//
+//    Try setting the clocks according to:
+//
+//    `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
+//
+//    Does the code compile?
+//
+//    ** your answer here **
+//
+//    What happens at run-time?
+//
+//    ** your answer here **
+//
+//    Is that a correct?
+//
+//    Optional: If you find it incorrect, file an issue to `stm32f4xx-hal` describing the problem.
+//    (Remember always check already open issues, and add to existing if related.)
+//
+// 7. Discussion
+//
+//    In this exercise, you have learned to use the stm32f4xx-hal
+//    to set the clock speed of your MCU.
+//
+//    You have also learned how you can monitor/validate MCU clock(s) on pin(s)
+//    connected to an oscilloscope.
+//
+//    You have also learned how you can improve readability of your code
+//    by leveraging the abstractions provided by the PAC.
+//
+//    As mentioned before the PACs are machine generated by `svd2rust`
+//    from vendor provided System View Descriptions (SVDs).
+//
+//    The PACs provide low level peripheral access abstractions, while
+//    the HALs provide higher level abstractions and functionality.

examples/rtic_bare7.rs

+//! rtic_bare7.rs
+//!
+//! HAL OutputPin abstractions
+//!
+//! What it covers:
+//! - using embedded hal, and the OutputPin abstraction
+
+#![no_main]
+#![no_std]
+
+use panic_rtt_target as _;
+use rtic::cyccnt::{Instant, U32Ext as _};
+use rtt_target::{rprintln, rtt_init_print};
+use stm32f4xx_hal::stm32;
+
+use stm32f4xx_hal::{
+    gpio::{gpioa::PA5, Output, PushPull},
+    prelude::*,
+};
+
+use embedded_hal::digital::v2::{OutputPin, ToggleableOutputPin};
+
+const OFFSET: u32 = 8_000_000;
+
+#[rtic::app(device = stm32f4xx_hal::stm32, monotonic = rtic::cyccnt::CYCCNT, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        // late resources
+        GPIOA: stm32::GPIOA,
+        // led: PA5<Output<PushPull>>,
+    }
+    #[init(schedule = [toggle])]
+    fn init(cx: init::Context) -> init::LateResources {
+        rtt_init_print!();
+        rprintln!("init");
+
+        let mut core = cx.core;
+        let device = cx.device;
+
+        // Initialize (enable) the monotonic timer (CYCCNT)
+        core.DCB.enable_trace();
+        core.DWT.enable_cycle_counter();
+
+        // semantically, the monotonic timer is frozen at time "zero" during `init`
+        // NOTE do *not* call `Instant::now` in this context; it will return a nonsense value
+        let now = cx.start; // the start time of the system
+
+        // Schedule `toggle` to run 8e6 cycles (clock cycles) in the future
+        cx.schedule.toggle(now + OFFSET.cycles()).unwrap();
+
+        // power on GPIOA, RM0368 6.3.11
+        device.RCC.ahb1enr.modify(|_, w| w.gpioaen().set_bit());
+        // configure PA5 as output, RM0368 8.4.1
+        device.GPIOA.moder.modify(|_, w| w.moder5().bits(1));
+
+        // pass on late resources
+        init::LateResources {
+            GPIOA: device.GPIOA,
+        }
+    }
+
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        rprintln!("idle");
+        loop {
+            continue;
+        }
+    }
+
+    #[task(resources = [GPIOA], schedule = [toggle])]
+    fn toggle(cx: toggle::Context) {
+        static mut TOGGLE: bool = false;
+        rprintln!("toggle  @ {:?}", Instant::now());
+
+        if *TOGGLE {
+            cx.resources.GPIOA.bsrr.write(|w| w.bs5().set_bit());
+        } else {
+            cx.resources.GPIOA.bsrr.write(|w| w.br5().set_bit());
+        }
+
+        *TOGGLE = !*TOGGLE;
+        cx.schedule.toggle(cx.scheduled + OFFSET.cycles()).unwrap();
+    }
+
+    extern "C" {
+        fn EXTI0();
+    }
+};
+
+fn _toggle_generic<E>(led: &mut dyn OutputPin<Error = E>, toggle: &mut bool) {
+    if *toggle {
+        led.set_high().ok();
+    } else {
+        led.set_low().ok();
+    }
+
+    *toggle = !*toggle;
+}
+
+fn _toggleable_generic<E>(led: &mut dyn ToggleableOutputPin<Error = E>) {
+    led.toggle().ok();
+}
+
+// 1. In this example you will use RTT.
+//
+//    > cargo run --example rtic_bare7
+//
+//    Look in the generated documentation for `set_high`/`set_low`.
+//    (You created documentation for your dependencies in previous exercise
+//    so you can just search (press `S`) for `OutputPin`).
+//    You will find that these methods are implemented for `Output` pins.
+//
+//    Now change your code to use these functions instead of the low-level GPIO API.
+//
+//    HINTS:
+//    - A GPIOx peripheral can be `split` into individual PINs Px0..Px15).
+//    - A Pxy, can be turned into an `Output` by `into_push_pull_output`.
+//    - You may optionally set other pin properties as well (such as `speed`).
+//    - An `Output` pin provides `set_low`/`set_high`
+//    - Instead of passing `GPIO` resource to the `toggle` task pass the
+//      `led: PA5<Output<PushPull>>` resource instead.
+//
+//    Comment your code to explain the steps taken.
+//
+//    Confirm that your implementation correctly toggles the LED as in
+//    previous exercise.
+//
+//    Commit your code (bare7_1)
+//
+// 2. Further generalizations:
+//
+//    Now look at the documentation for `embedded_hal::digital::v2::OutputPin`.
+//
+//    You see that the OutputPin trait defines `set_low`/`set_high` functions.
+//    Your task is to alter the code to use the `set_low`/`set_high` API.
+//
+//    The function `_toggle_generic` is generic to any object that
+//    implements the `OutputPin<Error = E>` trait.
+//
+//    Digging deeper we find the type parameter `E`, which in this case
+//    is left generic (unbound).
+//
+//    It will be instantiated with a concrete type argument when called.
+//
+//    Our `PA5<Output<PushPull>>` implements `OutputPin` trait, thus
+//    we can pass the `led` resource to `_toggle_generic`.
+//
+//    The error type is given by the stm32f4xx-hal implementation:
+//    where `core::convert::Infallible` is used to indicate
+//    there are no errors to be expected (hence infallible).
+//
+//    Additionally, `_toggle_generic` takes a mutable reference
+//    `toggle: &mut bool`, so you need to pass your `TOGGLE` variable.
+//
+//    As you see, `TOGGLE` holds the "state", switching between
+//    `true` and `false` (to make your led blink).
+//
+//    Change your code into using the `_toggle_generic` function.
+//    (You may rename it to `toggle_generic` if wished.)
+//
+//    Confirm that your implementation correctly toggles the LED as in
+//    previous exercise.
+//
+//    Commit your code (bare7_2)
+//
+// 3. What about the state?
+//
+//    In your code `TOGGLE` holds the "state". However, the underlying
+//    hardware ALSO holds the state (if the corresponding bit is set/cleared).
+//
+//    What if we can leverage that, and guess what we can!!!!
+//
+//    Look at the documentation for `embedded_hal::digital::v2::ToggleableOutputPin`,
+//    and the implementation of:
+//
+//    fn _toggleable_generic(led: &mut dyn ToggleableOutputPin<Error = Infallible>) {
+//      led.toggle().ok();
+//    }
+//
+//    The latter does not take any state variable, instead it directly `toggle()`
+//    the `ToggleableOutputPin`.
+//
+//    Now alter your code to leverage on the `_toggleable_generic` function.
+//    (You should be able to remove the `TOGGLE` state variable altogether.)
+//
+//    Confirm that your implementation correctly toggles the LED as in
+//    previous exercise.
+//
+//    Commit your code (bare7_3)
+//
+// 4. Discussion:
+//
+//    In this exercise you have gone from a very hardware specific implementation,
+//    to leveraging abstractions (batteries included).
+//
+//    Your final code amounts to "configuration" rather than "coding".
+//
+//    This reduces the risk of errors (as you let the libraries do the heavy lifting).
+//
+//    This also improves code-re use. E.g., if you were to do something less
+//    trivial then merely toggling you can do that in a generic manner,
+//    breaking out functionality into "components" re-usable in other applications.
+//
+//    Of course the example is trivial, you don't gain much here, but the principle
+//    is the same behind drivers for USART communication, USB, PMW3389 etc.
+//
+// 5. More details:
+//
+//    Looking closer at the implementation:
+//    `led: &mut dyn OutputPin<Error = E>`
+//
+//    You may ask what kind of mumbo jumbo is at play here.
+//
+//    This is the way to express that we expect a mutable reference to a trait object
+//    that implements the `OutputPin`. Since we will change the underlying object
+//    (in this case an GPIOA pin 5) the reference needs to be mutable.
+//
+//    Trait objects are further explained in the Rust book.
+//    The `dyn` keyword indicates dynamic dispatch (through a VTABLE).
+//    https://doc.rust-lang.org/std/keyword.dyn.html
+//
+//    Notice: the Rust compiler (rustc + LLVM) is really smart. In many cases
+//    it can analyse the call chain, and conclude the exact trait object type at hand.
+//    In such cases the dynamic dispatch is turned into a static dispatch
+//    and the VTABLE is gone, and we have a zero-cost abstraction.
+//
+//    If the trait object is stored for e.g., in an array along with other
+//    trait objects (of different concrete type), there is usually no telling
+//    the concrete type of each element, and we will have dynamic dispatch.
+//    Arguably, this is also a zero-cost abstraction, as there is no (obvious)
+//    way to implement it more efficiently. Remember, zero-cost is not without cost
+//    just that it is as good as it possibly gets (you can't make it better by hand).
+//
+//    You can also force the compiler to deduce the type at compile time, by using
+//    `impl` instead of `dyn`, if you are sure you don't want the compiler to
+//    "fallback" to dynamic dispatch.
+//
+//    You might find Rust to have long compile times. Yes you are right,
+//    and this type of deep analysis done in release mode is part of the story.
+//    On the other hand, the aggressive optimization allows us to code
+//    in a generic high level fashion and still have excellent performing binaries.

examples/rtic_bare8.rs

+//! bare8.rs
+//!
+//! Serial
+//!
+//! What it covers:
+//! - serial communication
+//! - bad design
+
+#![no_main]
+#![no_std]
+
+use panic_rtt_target as _;
+
+use nb::block;
+
+use stm32f4xx_hal::{
+    gpio::{gpioa::PA, Output, PushPull},
+    prelude::*,
+    serial::{config::Config, Rx, Serial, Tx},
+    stm32::USART2,
+};
+
+use rtic::app;
+use rtt_target::{rprintln, rtt_init_print};
+
+#[app(device = stm32f4xx_hal::stm32, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        // Late resources
+        TX: Tx<USART2>,
+        RX: Rx<USART2>,
+    }
+
+    // init runs in an interrupt free section
+    #[init]
+    fn init(cx: init::Context) -> init::LateResources {
+        rtt_init_print!();
+        rprintln!("init");
+
+        let device = cx.device;
+
+        let rcc = device.RCC.constrain();
+
+        // 16 MHz (default, all clocks)
+        let clocks = rcc.cfgr.freeze();
+
+        let gpioa = device.GPIOA.split();
+
+        let tx = gpioa.pa2.into_alternate_af7();
+        let rx = gpioa.pa3.into_alternate_af7();
+
+        let serial = Serial::usart2(
+            device.USART2,
+            (tx, rx),
+            Config::default().baudrate(115_200.bps()),
+            clocks,
+        )
+        .unwrap();
+
+        // Separate out the sender and receiver of the serial port
+        let (tx, rx) = serial.split();
+
+        // Late resources
+        init::LateResources { TX: tx, RX: rx }
+    }
+
+    // idle may be interrupted by other interrupts/tasks in the system
+    #[idle(resources = [RX, TX])]
+    fn idle(cx: idle::Context) -> ! {
+        let rx = cx.resources.RX;
+        let tx = cx.resources.TX;
+
+        loop {
+            match block!(rx.read()) {
+                Ok(byte) => {
+                    rprintln!("Ok {:?}", byte);
+                    tx.write(byte).unwrap();
+                }
+                Err(err) => {
+                    rprintln!("Error {:?}", err);
+                }
+            }
+        }
+    }
+};
+
+// 0. Background
+//
+//    The Nucleo st-link programmer provides a Virtual Com Port (VCP).
+//    It is connected to the PA2(TX)/PA3(RX) pins of the stm32f401/411.
+//    On the host, the VCP is presented under `/dev/ttyACMx`, where
+//    `x` is an enumerated number (ff 0 is busy it will pick 1, etc.)
+//
+// 1. In this example we use RTT.
+//
+//    > cargo run --example rtic_bare8
+//
+//    Start a terminal program, e.g., `moserial`.
+//    Connect to the port
+//
+//    Device       /dev/ttyACM0
+//    Baude Rate   115200
+//    Data Bits    8
+//    Stop Bits    1
+//    Parity       None
+//
+//    This setting is typically abbreviated as 115200 8N1.
+//
+//    Send a single character (byte), (set the option `No end` in `moserial`).
+//    Verify that sent bytes are echoed back, and that RTT tracing is working.
+//
+//    Try sending "a", don't send the quotation marks, just a.
+//
+//    What do you receive in `moserial`?
+//
+//    ** your answer here **
+//
+//    What do you receive in the RTT terminal?
+//
+//    ** your answer here **
+//
+//    Try sending: "abcd" as a single sequence, don't send the quotation marks, just abcd.
+//
+//    What did you receive in `moserial`?
+//
+//    ** your answer here **
+//
+//    What do you receive in the RTT terminal?
+//
+//    ** your answer here **
+//
+//    What do you believe to be the problem?
+//
+//    Hint: Look at the code in `idle` what does it do?
+//
+//    ** your answer here **
+//
+//    Experiment a bit, what is the max length sequence you can receive without errors?
+//
+//    ** your answer here **
+//
+//    Commit your answers (bare8_1)
+//
+// 2. Add a local variable `received` that counts the number of bytes received.
+//    Add a local variable `errors` that counts the number of errors.
+//
+//    Adjust the RTT trace to print the added information inside the loop.
+//
+//    Compile/run reconnect, and verify that it works as intended.
+//
+//    Commit your development (bare8_2)
+//
+// 3. Experiment a bit, what is the max length sequence you can receive without errors?
+//
+//    ** your answer here **
+//
+//    How did the added tracing/instrumentation affect the behavior?
+//
+//    ** your answer here **
+//
+//    Commit your answer (bare8_3)
+//
+// 4. Now try compile and run the same experiment 3 but in --release mode.
+//
+//    > cargo run --example rtic_bare8 --release
+//
+//    Reconnect your `moserial` terminal.
+//
+//    Experiment a bit, what is the max length sequence you can receive without errors?
+//
+//    ** your answer here **
+//
+//    Commit your answer (bare8_4)
+//
+// 5. Discussion
+//
+//    (If you ever used Arduino, you might feel at home with the `loop` and poll design.)
+//
+//    Typically, this is what you can expect from a polling approach, if you
+//    are not very careful what you are doing. This exemplifies a bad design.
+//
+//    Loss of data might be Ok for some applications but this typically NOT what we want.
+//
+//    (With that said, Arduino gets away with some simple examples as their drivers do
+//    internal magic - buffering data etc.)

examples/rtic_bare9.rs

+//! bare8.rs
+//!
+//! Serial
+//!
+//! What it covers:
+
+#![no_main]
+#![no_std]
+
+use panic_rtt_target as _;
+
+use stm32f4xx_hal::{
+    prelude::*,
+    serial::{config::Config, Event, Rx, Serial, Tx},
+    stm32::USART2,
+};
+
+use rtic::app;
+use rtt_target::{rprintln, rtt_init_print};
+
+#[app(device = stm32f4xx_hal::stm32, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        // Late resources
+        TX: Tx<USART2>,
+        RX: Rx<USART2>,
+    }
+
+    // init runs in an interrupt free section
+    #[init]
+    fn init(cx: init::Context) -> init::LateResources {
+        rtt_init_print!();
+        rprintln!("init");
+
+        let device = cx.device;
+
+        let rcc = device.RCC.constrain();
+
+        // 16 MHz (default, all clocks)
+        let clocks = rcc.cfgr.freeze();
+
+        let gpioa = device.GPIOA.split();
+
+        let tx = gpioa.pa2.into_alternate_af7();
+        let rx = gpioa.pa3.into_alternate_af7();
+
+        let mut serial = Serial::usart2(
+            device.USART2,
+            (tx, rx),
+            Config::default().baudrate(115_200.bps()),
+            clocks,
+        )
+        .unwrap();
+
+        // generate interrupt on Rxne
+        serial.listen(Event::Rxne);
+
+        // Separate out the sender and receiver of the serial port
+        let (tx, rx) = serial.split();
+
+        // Late resources
+        init::LateResources { TX: tx, RX: rx }
+    }
+
+    // idle may be interrupted by other interrupts/tasks in the system
+    #[idle()]
+    fn idle(_cx: idle::Context) -> ! {
+        loop {
+            continue;
+        }
+    }
+
+    // capacity sets the size of the input buffer (# outstanding messages)
+    #[task(resources = [TX], priority = 1, capacity = 128)]
+    fn rx(cx: rx::Context, data: u8) {
+        let tx = cx.resources.TX;
+        tx.write(data).unwrap();
+        rprintln!("data {}", data);
+    }
+
+    // Task bound to the USART2 interrupt.
+    #[task(binds = USART2,  priority = 2, resources = [RX], spawn = [rx])]
+    fn usart2(cx: usart2::Context) {
+        let rx = cx.resources.RX;
+        let data = rx.read().unwrap();
+        cx.spawn.rx(data).unwrap();
+    }
+
+    extern "C" {
+        fn EXTI0();
+    }
+};
+
+// 0. Background
+//
+//    As seen in the prior example, you may loose data unless polling frequently enough.
+//    Let's try an interrupt driven approach instead.
+//
+//    In init we just add:
+//
+//    // generate interrupt on Rxne
+//    serial.listen(Event::Rxne);
+//
+//    This causes the USART hardware to generate an interrupt when data is available.
+//
+//    // Task bound to the USART2 interrupt.
+//    #[task(binds = USART2,  priority = 2, resources = [RX], spawn = [rx])]
+//    fn usart2(cx: usart2::Context) {
+//      let rx = cx.resources.RX;
+//      let data = rx.read().unwrap();
+//      cx.spawn.rx(data).unwrap();
+//    }
+//
+//    The `usart2` task will be triggered, and we read one byte from the internal
+//    buffer in the USART2 hardware. (panic if something goes bad)
+//
+//    We send the read byte to the `rx` task (by `cx.spawn.rx(data).unwrap();`)
+//    (We panic if the capacity of the message queue is reached)
+//
+//    // capacity sets the size of the input buffer (# outstanding messages)
+//    #[task(resources = [TX], priority = 1, capacity = 128)]
+//    fn rx(cx: rx::Context, data: u8) {
+//        let tx = cx.resources.TX;
+//        tx.write(data).unwrap();
+//        rprintln!("data {}", data);
+//    }
+//
+//    Here we echo the data back, `tx.write(data).unwrap();` (panic if usart is busy)
+//    We then trace the received data `rprintln!("data {}", data);`
+//
+//    The `priority = 2` gives the `usart2` task the highest priority
+//    (to ensure that we don't miss data).
+//
+//    The `priority = 1` gives the `rx` task a lower priority.
+//    Here we can take our time and process the data.
+//
+//    `idle` runs at priority 0, lowest priority in the system.
+//    Here we can do some background job, when nothing urgent is happening.
+//
+//    This is an example of a good design!
+//
+// 1. In this example we use RTT.
+//
+//    > cargo run --example rtic_bare9
+//
+//    Try breaking it!!!!
+//    Throw any data at it, and see if you could make it panic!
+//
+//    Were you able to crash it?
+//
+//    ** your answer here **
+//
+//    Notice, the input tracing in `moserial` seems broken, and may loose data.
+//    So don't be alarmed if data is missing, its a GUI tool after all.
+//
+//    If you want to sniff the `ttyACM0`, install e.g., `interceptty` and run
+//    > interceptty /dev/ttyACM0
+//
+//    In another terminal, you can do:
+//    > cat examples/rtic_bare9.rs > /dev/ttyACM0
+//
+//    Incoming data will be intercepted/displayed by `interceptty`.
+//    (In the RTT trace you will see that data is indeed arriving to the target.)
+//
+//    Commit your answer (bare9_1)
+//
+// 2. Now, re-implement the received and error counters from previous exercise.
+//
+//    Good design:
+//    - Defer any tracing to lower priority task/tasks
+//      (you may introduce an error task at low priority).
+//
+//    - State variables can be introduced either locally (static mut), or
+//      by using a resource.
+//
+//      If a resource is shared among tasks of different priorities:
+//      The highest priority task will have direct access to the data,
+//      the lower priority task(s) will need to lock the resource first.
+//
+//    Check the RTIC book, https://rtic.rs/0.5/book/en/by-example
+//    regarding resources, software tasks, error handling etc.
+//
+//    Test that your implementation works and traces number of
+//    bytes received and errors encountered.
+//
+//    If implemented correctly, it should be very hard (or impossible)
+//    to get an error.
+//
+//    You can force an error by doing some "stupid delay" (faking workload),
+//    e.g., burning clock cycles using `cortex_m::asm::delay` in the
+//    `rx` task. Still you need to saturate the capacity (128 bytes).
+//
+//    To make errors easier to produce, reduce the capacity.
+//
+//    Once finished, comment your code.
+//
+//    Commit your code (bare9_2)
+//
+// 3. Discussion
+//
+//    Here you have used RTIC to implement a highly efficient and good design.
+//
+//    Tasks in RTIC are run-to-end, with non-blocking access to resources.
+//    (Even `lock` is non-blocking, isn't that sweet?)
+//
+//    Tasks in RTIC are scheduled according to priorities.
+//    (A higher priority task `H` always preempts lower priority task `L` running,
+//    unless `L` holds a resource with higher or equal ceiling as `H`.)
+//
+//    Tasks in RTIC can spawn other tasks.
+//    (`capacity` sets the message queue size.)
+//
+//    By design RTIC guarantees race- and deadlock-free execution.
+//
+//    It also comes with theoretical underpinning for static analysis.
+//    - task response time
+//    - overall schedulability
+//    - stack memory analysis
+//    - etc.
+//
+//    RTIC leverages on the zero-cost abstractions in Rust,
+//    and the implementation offers best in class performance.

examples/rtic_blinky.rs

+// run with gdb, either from terminal or in vscode
+//
+// from terminal:
+// start openocd in separate terminal
+// > openocd -f openocd.cfg
+//
+// start gdb
+// > arm-none-eabi-gdb target/thumbv7em-none-eabihf/debug/examples/rtic_blinky -x openocd.gdb
+
 #![deny(unsafe_code)]
 #![deny(warnings)]
 #![no_main]
@@ -5,7 +14,7 @@
 
 use cortex_m::peripheral::DWT;
 use cortex_m_semihosting::hprintln;
-use panic_rtt_target as _;
+use panic_semihosting as _;
 use rtic::cyccnt::{Instant, U32Ext as _};
 use stm32f4xx_hal::stm32;
 

examples/rtic_crash.rs

+#![no_main]
+#![no_std]
+
+use core::ptr;
+use panic_halt as _;
+use stm32f4;
+
+#[rtic::app(device = stm32f4)]
+const APP: () = {
+    #[init]
+    fn init(_cx: init::Context) {
+        unsafe {
+            // read an address outside of the RAM region; this causes a HardFault exception
+            ptr::read_volatile(0x2FFF_FFFF as *const u32);
+        }
+    }
+};
+
+// Here you can inspect the call stack (found to the left in vscode).
+//
+// The default implementation for `HardFault` exception is just an infinite loop.
+// Press the pause symbol to halt the processor:
+//
+// The upmost item in CALL STACK, is the current frame:
+// (the infinite loop loop)
+//
+// The bottom most item is the start of the program (the generated main).
+//
+// In between, you can see the calls made
+// main->init->read_volatile->HardFault->compiler_fence
+//
+// Click on init, and you will see that line 14 in this application caused the
+// erroneous read operation.

examples/rtic_hello.rs

+#![no_main]
+#![no_std]
+
+use cortex_m_semihosting::hprintln;
+use panic_halt as _;
+use stm32f4;
+
+#[rtic::app(device = stm32f4)]
+const APP: () = {
+    #[init]
+    fn init(_cx: init::Context) {
+        for a in 0..11 {
+            hprintln!("RTIC Says Hello, to all students!! {}", a).unwrap();
+        }
+    }
+};

examples/panic.rs → examples/rtic_panic.rs

-//! Changing the panicking behavior
-//!
-//! The easiest way to change the panicking behavior is to use a different [panic handler crate][0].
-//!
-//! [0]: https://crates.io/keywords/panic-impl
-
 #![no_main]
 #![no_std]
 
+use cortex_m_semihosting::hprintln;
+
 // Pick one of these panic handlers:
 
 // `panic!` halts execution; the panic message is ignored
 // use panic_halt as _;
 
 // Reports panic messages to the host stderr using semihosting
-// NOTE to use this you need to uncomment the `panic-semihosting` dependency in Cargo.toml
-// use panic_semihosting as _;
+use panic_semihosting as _;
 
 // Logs panic messages using the ITM (Instrumentation Trace Macrocell)
-// NOTE to use this you need to uncomment the `panic-itm` dependency in Cargo.toml
-use panic_itm as _;
+// use panic_itm as _;
 
-use cortex_m_rt::entry;
-use stm32f4 as _;
+use stm32f4;
 
-#[entry]
-fn main() -> ! {
-    panic!("Oops")
+#[rtic::app(device = stm32f4)]
+const APP: () = {
+    #[init]
+    fn init(_cx: init::Context) {
+        for i in 0..10 {
+            hprintln!("RTIC Says Hello, world {}!!", 100 / (5 - i)).ok();
+        }
     }
+};

examples/rtt-pmw3389-sine.rs

+//! examples/rtt-pwm-sine.rs
+//! cargo run --examples rtt-pwm-sine --release
+
+// #![deny(unsafe_code)]
+// #![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use cortex_m::{asm, peripheral::DWT};
+
+use panic_rtt_target as _;
+use rtic::cyccnt::{Instant, U32Ext as _};
+use rtt_target::{rprint, rprintln, rtt_init_print};
+
+use core::f32::consts::PI;
+use micromath::F32Ext;
+
+use stm32f4xx_hal::{
+    bb,
+    dwt::Dwt,
+    gpio::Speed,
+    gpio::{
+        gpiob::{PB10, PB4},
+        gpioc::{PC2, PC3},
+        Alternate, Output, PushPull,
+    },
+    prelude::*,
+    pwm,
+    rcc::Clocks,
+    spi::Spi,
+    stm32,
+};
+
+use embedded_hal::spi::MODE_3;
+use panic_rtt_target as _;
+
+use app::{
+    pmw3389::{self, Register},
+    DwtDelay,
+};
+
+type PMW3389T = pmw3389::Pmw3389<
+    Spi<
+        stm32f4xx_hal::stm32::SPI2,
+        (
+            PB10<Alternate<stm32f4xx_hal::gpio::AF5>>,
+            PC2<Alternate<stm32f4xx_hal::gpio::AF5>>,
+            PC3<Alternate<stm32f4xx_hal::gpio::AF5>>,
+        ),
+    >,
+    PB4<Output<PushPull>>,
+>;
+
+include!(concat!(env!("OUT_DIR"), "/sin_abs_const.rs"));
+
+#[rtic::app(device = stm32f4xx_hal::stm32,  monotonic = rtic::cyccnt::CYCCNT, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        // late resources
+        TIM1: stm32::TIM1,
+        pmw3389: PMW3389T,
+    }
+    #[init(schedule = [pwm_out, poll])]
+    fn init(mut cx: init::Context) -> init::LateResources {
+        rtt_init_print!();
+        rprintln!("init");
+
+        let device = cx.device;
+        let mut core = cx.core;
+
+        // Initialize (enable) the monotonic timer (CYCCNT)
+        core.DCB.enable_trace();
+        core.DWT.enable_cycle_counter();
+
+        let rcc = device.RCC.constrain();
+        // Set up the system clock. 96 MHz?
+        let clocks = rcc.cfgr.sysclk(96.mhz()).pclk1(24.mhz()).freeze();
+
+        // Configure SPI
+        // spi2
+        // sck    - pb10, (yellow)
+        // miso   - pc2, (red)
+        // mosi   - pc3, (orange)
+        // ncs    - pb4, (long yellow)
+        // motion - (brown)
+        //
+        // +5, (white)
+        // gnd, (black)
+
+        cortex_m::asm::dsb(); // chip errata
+        let gpiob = device.GPIOB.split();
+        cortex_m::asm::dsb(); // chip errata
+        let gpioc = device.GPIOC.split();
+        cortex_m::asm::dsb(); // chip errata
+
+        let sck = gpiob.pb10.into_alternate_af5().set_speed(Speed::VeryHigh);
+        let miso = gpioc.pc2.into_alternate_af5().set_speed(Speed::High);
+        let mosi = gpioc.pc3.into_alternate_af5().set_speed(Speed::High);
+        let cs = gpiob.pb4.into_push_pull_output().set_speed(Speed::High);
+
+        let spi = Spi::spi2(
+            device.SPI2,
+            (sck, miso, mosi),
+            MODE_3,
+            stm32f4xx_hal::time::KiloHertz(2000).into(),
+            clocks,
+        );
+
+        let delay = DwtDelay::new(&mut core.DWT, clocks);
+        let mut pmw3389 = pmw3389::Pmw3389::new(spi, cs, delay).unwrap();
+
+        // // set in burst mode
+        // pmw3389.write_register(Register::MotionBurst, 0x00).unwrap();
+
+        // setup TIM1 as PWM (for implementing an 8 bit DA)
+        let gpioa = device.GPIOA.split();
+        cortex_m::asm::dsb(); // chip errata
+
+        // we set the pins to VeryHigh to get the sharpest waveform possible
+        // (rise and fall times should have similar characteristics)
+        let _channels = (
+            gpioa.pa8.into_alternate_af1().set_speed(Speed::VeryHigh),
+            gpioa.pa9.into_alternate_af1().set_speed(Speed::VeryHigh),
+        );
+
+        // Setup PWM RAW
+        let tim1 = device.TIM1;
+        // Here we need unsafe as we are "stealing" the RCC peripheral
+        // At this point it has been contrained into SysConf and used to set clocks
+        let rcc = unsafe { &(*stm32::RCC::ptr()) };
+
+        rcc.apb2enr.modify(|_, w| w.tim1en().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().clear_bit());
+
+        // Setup chanel 1 and 2 as pwm_mode1
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc1pe().set_bit().oc1m().pwm_mode1());
+
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc2pe().set_bit().oc2m().pwm_mode1());
+
+        // The reference manual is a bit ambiguous about when enabling this bit is really
+        // necessary, but since we MUST enable the pre-load for the output channels then we
+        // might as well enable for the auto-reload too
+        tim1.cr1.modify(|_, w| w.arpe().set_bit());
+
+        let clk = clocks.pclk2().0 * if clocks.ppre2() == 1 { 1 } else { 2 };
+        // check the actual clock setup
+        rprintln!("clk {}", clk);
+
+        // we want maximum performance, thus we set the prescaler to 0
+        let pre = 0;
+        rprintln!("pre {}", pre);
+        tim1.psc.write(|w| w.psc().bits(pre));
+
+        // we want 8 bits of resolution
+        // so our ARR = 2^8 - 1 = 256 - 1 = 255
+        let arr = 255;
+        rprintln!("arr {}", arr);
+        tim1.arr.write(|w| unsafe { w.bits(arr) });
+
+        //  Trigger update event to load the registers
+        tim1.cr1.modify(|_, w| w.urs().set_bit());
+        tim1.egr.write(|w| w.ug().set_bit());
+        tim1.cr1.modify(|_, w| w.urs().clear_bit());
+
+        // Set main output enable of all Output Compare (OC) registers
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
+        // Set output enable for channels 1 and 2
+        tim1.ccer.write(|w| w.cc1e().set_bit().cc2e().set_bit());
+
+        // Setup the timer
+        tim1.cr1.write(|w| {
+            w.cms()
+                .bits(0b00) // edge aligned mode
+                .dir() // counter used as up-counter
+                .clear_bit()
+                .opm() // one pulse mode
+                .clear_bit()
+                .cen() // enable counter
+                .set_bit()
+        });
+
+        // Set main output enable of all Output Compare (OC) registers
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
+        // Set duty cycle of Channels
+        tim1.ccr1.write(|w| unsafe { w.ccr().bits(128) });
+        tim1.ccr2.write(|w| unsafe { w.ccr().bits(128) });
+
+        // Set preload for the CCx
+        tim1.cr2.write(|w| w.ccpc().set_bit());
+
+        // Enable update events
+        tim1.dier.write(|w| w.uie().enabled());
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        // just to check that we actually get update events
+        while tim1.sr.read().uif().is_clear() {
+            rprint!("-");
+        }
+        rprintln!("here");
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        cx.schedule.pwm_out(cx.start + PWM_CYCLES.cycles()).ok();
+        cx.schedule.poll(cx.start + POLL_CYCLES.cycles()).ok();
+        // pass on late resources
+        init::LateResources {
+            TIM1: tim1,
+            pmw3389,
+        }
+    }
+
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        rprintln!("idle");
+        // panic!("panic");
+        loop {
+            asm::nop()
+        }
+    }
+
+    #[task(priority = 1)]
+    fn trace(_cx: trace::Context, pos_x: i64, pos_y: i64) {
+        static mut OLD_POS_X: i64 = 0;
+        static mut OLD_POS_Y: i64 = 0;
+        rprintln!(
+            "@{:?}, pos_x {:010}, diff {:010}, pos_y {:010}, diff {:010} ",
+            Instant::now(),
+            pos_x,
+            pos_x.wrapping_sub(*OLD_POS_X),
+            pos_y,
+            pos_y.wrapping_sub(*OLD_POS_Y),
+        );
+        *OLD_POS_X = pos_x;
+        *OLD_POS_Y = pos_y;
+    }
+
+    #[task(priority = 2, resources = [pmw3389], schedule = [poll], spawn = [trace])]
+    fn poll(cx: poll::Context) {
+        static mut COUNTER: u32 = 0;
+        static mut POS_X: i64 = 0;
+        static mut POS_Y: i64 = 0;
+
+        // run each ms
+        *COUNTER += 1;
+        if *COUNTER == 1000 {
+            // run each s
+            cx.spawn.trace(*POS_X, *POS_Y).unwrap();
+            *COUNTER = 0;
+        }
+
+        let pmw3389 = cx.resources.pmw3389;
+
+        //write 0x01 to Motion register and read from it to freeze the motion values and make them available
+        pmw3389.write_register(Register::Motion, 0x01).unwrap();
+        let _ = pmw3389.read_register(Register::Motion).unwrap();
+
+        let xl: u8 = pmw3389.read_register(Register::DeltaXL).unwrap();
+        let xh: u8 = pmw3389.read_register(Register::DeltaXH).unwrap();
+        let yl = pmw3389.read_register(Register::DeltaYL).unwrap();
+        let yh = pmw3389.read_register(Register::DeltaYH).unwrap();
+
+        // let (x, _y) = cx.resources.pmw3389.read_status().unwrap();
+        *POS_X += (((xl as u16) | ((xh as u16) << 8)) as i16) as i64;
+        *POS_Y += (((yl as u16) | ((yh as u16) << 8)) as i16) as i64;
+
+        // task should run each second N ms (96_000 cycles at 96MHz)
+        cx.schedule
+            .poll(cx.scheduled + POLL_CYCLES.cycles())
+            .unwrap();
+    }
+
+    #[task(priority = 3, resources = [TIM1], schedule = [pwm_out])]
+    fn pwm_out(cx: pwm_out::Context) {
+        static mut INDEX: u16 = 0;
+        static mut LEFT: u16 = 0;
+        static mut RIGHT: u16 = 0;
+        // static mut FLOAT: u16 = 0;
+
+        let tim1 = cx.resources.TIM1;
+
+        tim1.ccr1.write(|w| unsafe { w.ccr().bits(*LEFT) });
+        tim1.ccr2.write(|w| unsafe { w.ccr().bits(*RIGHT) });
+        // tim1.ccr2.write(|w| unsafe { w.ccr().bits(*FLOAT) });
+
+        cx.schedule
+            .pwm_out(cx.scheduled + PWM_CYCLES.cycles())
+            .unwrap();
+
+        *INDEX = (*INDEX).wrapping_add(1_000);
+        // let f: f32 = (*INDEX as f32 * 2.0 * PI) / 65536.0;
+        // *FLOAT = (128.0 + f.sin() * 128.0) as u16;
+
+        *LEFT = SINE_BUF[*INDEX as usize] as u16;
+        *RIGHT = SINE_BUF[*INDEX as usize] as u16;
+
+        // if cx.scheduled.elapsed() > 1500.cycles() {
+        //     panic!("task overrun");
+        // }
+    }
+
+    extern "C" {
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI2();
+    }
+};
+
+// We aim for a sampling rate of 48kHz, assuming that the input filter of the
+// sound card used to sample the generated signal has an appropriate input filter
+const PWM_CYCLES: u32 = 2000; // 96_000_000 / 2_000 = 48_000 Hz
+const POLL_CYCLES: u32 = 96_000; // 96_000_000 / 96_000 = 1_000 Hz

examples/rtt-pwm-dma.rs

+//! examples/rtt-pwm-dma.rs
+//! cargo run --examples rtt-pwm-dma
+
+// #![deny(unsafe_code)]
+// #![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use cortex_m::{asm, peripheral::DWT};
+use panic_halt as _;
+use rtt_target::{rprint, rprintln, rtt_init_print};
+use stm32f4xx_hal::{bb, dma, gpio::Speed, prelude::*, pwm, stm32};
+
+#[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true)]
+const APP: () = {
+    #[init]
+    fn init(mut cx: init::Context) {
+        rtt_init_print!();
+        rprintln!("init");
+        let dp = cx.device;
+
+        // Initialize (enable) the monotonic timer (CYCCNT)
+        cx.core.DCB.enable_trace();
+        cx.core.DWT.enable_cycle_counter();
+
+        let rcc = dp.RCC.constrain();
+        // Set up the system clock. 48 MHz?
+        let clocks = rcc
+            .cfgr
+            // .use_hse(8.mhz())
+            .sysclk(48.mhz())
+            .pclk1(24.mhz())
+            .freeze();
+
+        let gpioa = dp.GPIOA.split();
+        // we set the pins to VeryHigh to get the sharpest waveform possible
+        // (rise and fall times should have similar characteristics)
+        let channels = (
+            gpioa.pa8.into_alternate_af1().set_speed(Speed::VeryHigh),
+            gpioa.pa9.into_alternate_af1().set_speed(Speed::VeryHigh),
+        );
+
+        // Setup PWM RAW
+        let tim1 = dp.TIM1;
+        // Here we need unsafe as we are "stealing" the RCC peripheral
+        // At this point it has been contrained into SysConf and used to set clocks
+        let rcc = unsafe { &(*stm32::RCC::ptr()) };
+
+        rcc.apb2enr.modify(|_, w| w.tim1en().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().clear_bit());
+
+        // Setup chanel 1 and 2 as pwm_mode1
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc1pe().set_bit().oc1m().pwm_mode1());
+
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc2pe().set_bit().oc2m().pwm_mode1());
+
+        // The reference manual is a bit ambiguous about when enabling this bit is really
+        // necessary, but since we MUST enable the preload for the output channels then we
+        // might as well enable for the auto-reload too
+        tim1.cr1.modify(|_, w| w.arpe().set_bit());
+
+        let clk = clocks.pclk2().0 * if clocks.ppre2() == 1 { 1 } else { 2 };
+        // check that its actually 48_000_000
+        rprintln!("clk {}", clk);
+
+        // we want maximum performance, thus we set the prescaler to 0
+        let pre = 0;
+        rprintln!("pre {}", pre);
+        tim1.psc.write(|w| w.psc().bits(pre));
+
+        // we want 8 bits of resolution
+        // so our ARR = 2^8 - 1 = 256 - 1 = 255
+        let arr = 255;
+        rprintln!("arr {}", arr);
+        tim1.arr.write(|w| unsafe { w.bits(arr) });
+
+        //  Trigger update event to load the registers
+        tim1.cr1.modify(|_, w| w.urs().set_bit());
+        tim1.egr.write(|w| w.ug().set_bit());
+        tim1.cr1.modify(|_, w| w.urs().clear_bit());
+
+        // Set main output enable of all Output Compare (OC) registers
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
+        // Set output enable for channels 1 and 2
+        // Channel 1 (bit  0)
+        unsafe { bb::set(&tim1.ccer, 0) }
+        // Channel 4 (bit  0)
+        unsafe { bb::set(&tim1.ccer, 4) }
+
+        // Setup the timer
+        tim1.cr1.write(|w| {
+            w.cms()
+                .bits(0b00) // edge aligned mode
+                .dir() // counter used as upcounter
+                .clear_bit()
+                .opm() // one pulse mode
+                .clear_bit()
+                .cen() // enable counter
+                .set_bit()
+        });
+
+        // Setup TIMER2
+        let tim2 = dp.TIM2;
+        // Here we need unsafe as we are "stealing" the RCC peripheral
+        // At this point it has been contrained into SysConf and used to set clocks
+        let rcc = unsafe { &(*stm32::RCC::ptr()) };
+
+        rcc.apb1enr.modify(|_, w| w.tim2en().set_bit());
+        rcc.apb1rstr.modify(|_, w| w.tim2rst().set_bit());
+        rcc.apb1rstr.modify(|_, w| w.tim2rst().clear_bit());
+
+        // auto-reload, preload
+        tim1.cr1.modify(|_, w| w.arpe().set_bit());
+
+        let clk = clocks.pclk2().0 * if clocks.ppre2() == 1 { 1 } else { 2 };
+        // check that its actually 48_000_000
+        rprintln!("clk {}", clk);
+
+        // assume we have a sine at
+        let pre = 0;
+        rprintln!("pre {}", pre);
+        tim2.psc.write(|w| w.psc().bits(pre));
+
+        // we want 8 bits of resolution
+        // so our ARR = 2^8 - 1 = 256 - 1 = 255
+        let arr = 255;
+        rprintln!("arr {}", arr);
+        tim1.arr.write(|w| unsafe { w.bits(arr) });
+
+        //  Trigger update event to load the registers
+        tim1.cr1.modify(|_, w| w.urs().set_bit());
+        tim1.egr.write(|w| w.ug().set_bit());
+        tim1.cr1.modify(|_, w| w.urs().clear_bit());
+
+        // Set main output enable of all Output Compare (OC) registers
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
+        // Set output enable for channels 1 and 2
+        // Channel 1 (bit  0)
+        unsafe { bb::set(&tim1.ccer, 0) }
+        // Channel 4 (bit  0)
+        unsafe { bb::set(&tim1.ccer, 4) }
+
+        // Setup the timer
+        tim1.cr1.write(|w| {
+            w.cms()
+                .bits(0b00) // edge aligned mode
+                .dir() // counter used as upcounter
+                .clear_bit()
+                .opm() // one pulse mode
+                .clear_bit()
+                .cen() // enable counter
+                .set_bit()
+        });
+
+        // Set duty cycle of Channels
+        tim1.ccr1.write(|w| unsafe { w.ccr().bits(128) });
+        tim1.ccr2.write(|w| unsafe { w.ccr().bits(128) });
+
+        // Set preload for the CCx
+        tim1.cr2.write(|w| w.ccpc().set_bit());
+
+        tim1.dier.write(|w| w.uie().enabled());
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        while tim1.sr.read().uif().is_clear() {
+            rprint!("-");
+        }
+        rprintln!("here");
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        let mut dma_buff = [0u8; 256];
+        for i in 0..256 {
+            dma_buff[i] = i as u8;
+        }
+
+        loop {
+            for i in 0..256 {
+                // wait until next update event
+                while tim1.sr.read().uif().is_clear() {}
+                tim1.sr.modify(|_, w| w.uif().clear());
+
+                tim1.ccr1
+                    .write(|w| unsafe { w.ccr().bits(dma_buff[i] as u16) });
+                tim1.ccr2
+                    .write(|w| unsafe { w.ccr().bits(dma_buff[i] as u16) });
+            }
+        }
+    }
+
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        rprintln!("idle");
+        loop {
+            continue;
+        }
+    }
+};

examples/rtt-pwm-saw.rs

+//! examples/rtt-pwm-saw.rs
+//! cargo run --examples rtt-pwm-saw
+
+// #![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+// use cortex_m::{asm, peripheral::DWT};
+use panic_halt as _;
+use rtt_target::{rprint, rprintln, rtt_init_print};
+use stm32f4xx_hal::{bb, gpio::Speed, prelude::*, stm32};
+
+#[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true)]
+const APP: () = {
+    #[init]
+    fn init(mut cx: init::Context) {
+        rtt_init_print!();
+        rprintln!("init");
+        let dp = cx.device;
+
+        // Initialize (enable) the monotonic timer (CYCCNT)
+        cx.core.DCB.enable_trace();
+        cx.core.DWT.enable_cycle_counter();
+
+        let rcc = dp.RCC.constrain();
+        // Set up the system clock. 48 MHz?
+        let clocks = rcc
+            .cfgr
+            // .use_hse(8.mhz())
+            .sysclk(48.mhz())
+            .pclk1(24.mhz())
+            .freeze();
+
+        let gpioa = dp.GPIOA.split();
+        // we set the pins to VeryHigh to get the sharpest waveform possible
+        // (rise and fall times should have similar characteristics)
+        let _channels = (
+            gpioa.pa8.into_alternate_af1().set_speed(Speed::VeryHigh),
+            gpioa.pa9.into_alternate_af1().set_speed(Speed::VeryHigh),
+        );
+
+        // Setup PWM RAW
+        let tim1 = dp.TIM1;
+        // Here we need unsafe as we are "stealing" the RCC peripheral
+        // (At this point it has been constrained into SysConf and used to set clocks.)
+        let rcc = unsafe { &(*stm32::RCC::ptr()) };
+
+        // unsafe {
+        //     bb::set(&rcc.apb2enr, 0u8);
+        //     bb::set(&rcc.apb2rstr, 0u8);
+        //     bb::clear(&rcc.apb2rstr, 0u8);
+        // }
+        //
+        // For some reason bb:: hangs target in release mode,
+        // so I implemented it using modify instead
+        rcc.apb2enr.modify(|_, w| w.tim1en().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().clear_bit());
+
+        // Setup chanel 1 and 2 as pwm_mode1
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc1pe().set_bit().oc1m().pwm_mode1());
+
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc2pe().set_bit().oc2m().pwm_mode1());
+
+        // The reference manual is a bit ambiguous about when enabling this bit is really
+        // necessary, but since we MUST enable the preload for the output channels then we
+        // might as well enable for the auto-reload too
+        tim1.cr1.modify(|_, w| w.arpe().set_bit());
+
+        let clk = clocks.pclk2().0 * if clocks.ppre2() == 1 { 1 } else { 2 };
+        // check that its actually 48_000_000
+        rprintln!("clk {}", clk);
+
+        // we want maximum performance, thus we set the prescaler to 0
+        let pre = 0;
+        rprintln!("pre {}", pre);
+        tim1.psc.write(|w| w.psc().bits(pre));
+
+        // we want 8 bits of resolution
+        // so our ARR = 2^8 - 1 = 256 - 1 = 255
+        let arr = 255;
+        rprintln!("arr {}", arr);
+        tim1.arr.write(|w| unsafe { w.bits(arr) });
+
+        //  Trigger update event to load the registers
+        tim1.cr1.modify(|_, w| w.urs().set_bit());
+        tim1.egr.write(|w| w.ug().set_bit());
+        tim1.cr1.modify(|_, w| w.urs().clear_bit());
+
+        // Set main output enable of all Output Compare (OC) registers
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
+        // Set output enable for channels 1 and 2
+        // Channel 1 (bit  0)
+        unsafe { bb::set(&tim1.ccer, 0) }
+        // Channel 4 (bit  0)
+        unsafe { bb::set(&tim1.ccer, 4) }
+
+        // Setup the timer
+        tim1.cr1.write(|w| {
+            w.cms()
+                .bits(0b00) // edge aligned mode
+                .dir() // counter used as upcounter
+                .clear_bit()
+                .opm() // one pulse mode
+                .clear_bit()
+                .cen() // enable counter
+                .set_bit()
+        });
+
+        // Set duty cycle of Channels
+        tim1.ccr1.write(|w| unsafe { w.ccr().bits(128) });
+        tim1.ccr2.write(|w| unsafe { w.ccr().bits(128) });
+
+        // Set preload for the CCx
+        tim1.cr2.write(|w| w.ccpc().set_bit());
+
+        tim1.dier.write(|w| w.uie().enabled());
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        while tim1.sr.read().uif().is_clear() {
+            rprint!("-");
+        }
+        rprintln!("here");
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        loop {
+            for i in 0..256 {
+                // wait until next update event
+                while tim1.sr.read().uif().is_clear() {}
+                tim1.sr.modify(|_, w| w.uif().clear());
+
+                tim1.ccr1.write(|w| unsafe { w.ccr().bits(i) });
+                tim1.ccr2.write(|w| unsafe { w.ccr().bits(i) });
+            }
+        }
+    }
+
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        rprintln!("idle");
+        loop {
+            continue;
+        }
+    }
+};

examples/rtt-pwm-sine-task.rs

+//! examples/rtt-pwm-sine.rs
+//! cargo run --examples rtt-pwm-sine --release
+
+// #![deny(unsafe_code)]
+// #![deny(warnings)]
+#![no_main]
+#![no_std]
+
+// use core::f32::consts::PI;
+use cortex_m::{asm, peripheral::DWT};
+// use panic_halt as _;
+use panic_rtt_target as _;
+use rtic::cyccnt::{Instant, U32Ext as _};
+use rtt_target::{rprint, rprintln, rtt_init_print};
+
+use core::f32::consts::PI;
+use micromath::F32Ext;
+
+use stm32f4xx_hal::{bb, gpio::Speed, prelude::*, pwm, stm32};
+
+include!(concat!(env!("OUT_DIR"), "/sin_abs_const.rs"));
+
+#[rtic::app(device = stm32f4xx_hal::stm32,  monotonic = rtic::cyccnt::CYCCNT, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        // late resources
+        TIM1: stm32::TIM1,
+    }
+    #[init(schedule = [pwm_out])]
+    fn init(mut cx: init::Context) -> init::LateResources {
+        rtt_init_print!();
+        rprintln!("init");
+        let dp = cx.device;
+
+        // Initialize (enable) the monotonic timer (CYCCNT)
+        cx.core.DCB.enable_trace();
+        cx.core.DWT.enable_cycle_counter();
+
+        let rcc = dp.RCC.constrain();
+        // Set up the system clock. 48 MHz?
+        let clocks = rcc
+            .cfgr
+            // .use_hse(8.mhz())
+            // .sysclk(48.mhz())
+            .sysclk(96.mhz())
+            .pclk1(24.mhz())
+            .freeze();
+
+        let gpioa = dp.GPIOA.split();
+        // we set the pins to VeryHigh to get the sharpest waveform possible
+        // (rise and fall times should have similar characteristics)
+        let _channels = (
+            gpioa.pa8.into_alternate_af1().set_speed(Speed::VeryHigh),
+            gpioa.pa9.into_alternate_af1().set_speed(Speed::VeryHigh),
+        );
+
+        // Setup PWM RAW
+        let tim1 = dp.TIM1;
+        // Here we need unsafe as we are "stealing" the RCC peripheral
+        // At this point it has been contrained into SysConf and used to set clocks
+        let rcc = unsafe { &(*stm32::RCC::ptr()) };
+
+        rcc.apb2enr.modify(|_, w| w.tim1en().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().set_bit());
+        rcc.apb2rstr.modify(|_, w| w.tim1rst().clear_bit());
+
+        // Setup chanel 1 and 2 as pwm_mode1
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc1pe().set_bit().oc1m().pwm_mode1());
+
+        tim1.ccmr1_output()
+            .modify(|_, w| w.oc2pe().set_bit().oc2m().pwm_mode1());
+
+        // The reference manual is a bit ambiguous about when enabling this bit is really
+        // necessary, but since we MUST enable the pre-load for the output channels then we
+        // might as well enable for the auto-reload too
+        tim1.cr1.modify(|_, w| w.arpe().set_bit());
+
+        let clk = clocks.pclk2().0 * if clocks.ppre2() == 1 { 1 } else { 2 };
+        // check that its actually 48_000_000
+        rprintln!("clk {}", clk);
+
+        // we want maximum performance, thus we set the prescaler to 0
+        let pre = 0;
+        rprintln!("pre {}", pre);
+        tim1.psc.write(|w| w.psc().bits(pre));
+
+        // we want 8 bits of resolution
+        // so our ARR = 2^8 - 1 = 256 - 1 = 255
+        let arr = 255;
+        rprintln!("arr {}", arr);
+        tim1.arr.write(|w| unsafe { w.bits(arr) });
+
+        //  Trigger update event to load the registers
+        tim1.cr1.modify(|_, w| w.urs().set_bit());
+        tim1.egr.write(|w| w.ug().set_bit());
+        tim1.cr1.modify(|_, w| w.urs().clear_bit());
+
+        // Set main output enable of all Output Compare (OC) registers
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
+        // Set output enable for channels 1 and 2
+        tim1.ccer.write(|w| w.cc1e().set_bit().cc2e().set_bit());
+
+        // Setup the timer
+        tim1.cr1.write(|w| {
+            w.cms()
+                .bits(0b00) // edge aligned mode
+                .dir() // counter used as up-counter
+                .clear_bit()
+                .opm() // one pulse mode
+                .clear_bit()
+                .cen() // enable counter
+                .set_bit()
+        });
+
+        // Set main output enable of all Output Compare (OC) registers
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
+        // Set duty cycle of Channels
+        tim1.ccr1.write(|w| unsafe { w.ccr().bits(128) });
+        tim1.ccr2.write(|w| unsafe { w.ccr().bits(128) });
+
+        // Set preload for the CCx
+        tim1.cr2.write(|w| w.ccpc().set_bit());
+
+        // Enable update events
+        tim1.dier.write(|w| w.uie().enabled());
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        // Set divider to 4, (48_000_000/256)/4
+        // tim1.rcr.modify(|_, w| unsafe { w.rep().bits(4) });
+
+        while tim1.sr.read().uif().is_clear() {
+            rprint!("-");
+        }
+        rprintln!("here");
+        tim1.sr.modify(|_, w| w.uif().clear());
+
+        // pass on late resources
+        cx.schedule.pwm_out(cx.start + PERIOD.cycles()).ok();
+        init::LateResources { TIM1: tim1 }
+    }
+
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        rprintln!("idle");
+        // panic!("panic");
+        loop {
+            continue;
+        }
+    }
+
+    #[task(resources = [TIM1], schedule = [pwm_out])]
+    fn pwm_out(cx: pwm_out::Context) {
+        static mut INDEX: u16 = 0;
+        static mut LEFT: u16 = 0;
+        static mut RIGHT: u16 = 0;
+        static mut FLOAT: u16 = 0;
+
+        let tim1 = cx.resources.TIM1;
+
+        tim1.ccr1.write(|w| unsafe { w.ccr().bits(*LEFT) });
+        // tim1.ccr2.write(|w| unsafe { w.ccr().bits(*RIGHT) });
+        tim1.ccr2.write(|w| unsafe { w.ccr().bits(*FLOAT) });
+
+        *INDEX = (*INDEX).wrapping_add(10_000);
+        let f: f32 = (*INDEX as f32 * 2.0 * PI) / 65536.0;
+        *FLOAT = (128.0 + f.sin() * 128.0) as u16;
+        cx.schedule.pwm_out(cx.scheduled + PERIOD.cycles()).ok();
+
+        *LEFT = SINE_BUF[*INDEX as usize] as u16;
+        *RIGHT = SINE_BUF[*INDEX as usize] as u16;
+
+        if cx.scheduled.elapsed() > 500.cycles() {
+            panic!("task overrun");
+        }
+    }
+
+    extern "C" {
+        fn EXTI0();
+    }
+};
+
+// We aim for a sampling rate of 48kHz, assuming that the input filter of the
+// sound card used to sample the generated signal has an appropriate input filter
+const PERIOD: u32 = 2000; // 96_000_000 / 48_000;

examples/rtt-pwm.rs

-//! examples/rtt_timing.rs
 //! cargo run --examples rtt-pwm
 
 #![deny(unsafe_code)]
-// #![deny(warnings)]
+#![deny(warnings)]
 #![no_main]
 #![no_std]
 
-use cortex_m::{asm, peripheral::DWT};
 use panic_halt as _;
 use rtt_target::{rprintln, rtt_init_print};
-use stm32f4xx_hal::{dma, gpio::Speed, prelude::*, pwm, stm32};
+use stm32f4xx_hal::{gpio::Speed, prelude::*, pwm};
 
 #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true)]
 const APP: () = {
     #[init]
-    fn init(mut cx: init::Context) {
+    fn init(cx: init::Context) {
         rtt_init_print!();
         rprintln!("init");
         let dp = cx.device;
 
-        // Initialize (enable) the monotonic timer (CYCCNT)
-        cx.core.DCB.enable_trace();
-        cx.core.DWT.enable_cycle_counter();
-
         // Set up the system clock. 16 MHz?
         let rcc = dp.RCC.constrain();
         let clocks = rcc.cfgr.freeze();
 
         let gpioa = dp.GPIOA.split();
         let channels = (
-            gpioa.pa8.into_alternate_af1().set_speed(Speed::Low),
-            gpioa.pa9.into_alternate_af1(),
+            gpioa.pa8.into_alternate_af1().set_speed(Speed::High),
+            gpioa.pa9.into_alternate_af1().set_speed(Speed::High),
         );
 
         let pwm = pwm::tim1(dp.TIM1, channels, clocks, 1u32.khz());
@@ -39,7 +33,7 @@ const APP: () = {
         rprintln!("max_duty {}", max_duty);
         ch1.set_duty(max_duty / 2);
         ch1.enable();
-        ch2.set_duty((max_duty * 1) / 2);
+        ch2.set_duty((max_duty * 1) / 3);
         ch2.enable();
     }
 

examples/rtt-timing.rs

 //! examples/rtt_timing.rs
 //! cargo run --examples rtt-timing
 
-#![deny(unsafe_code)]
 #![deny(warnings)]
 #![no_main]
 #![no_std]

examples/rtt_rtic_hello.rs

+// cargo run --example rtt_rtic_hello
+
+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+use rtt_target::{rprintln, rtt_init_print};
+use stm32f4;
+
+#[rtic::app(device = stm32f4)]
+const APP: () = {
+    #[init]
+    fn init(_cx: init::Context) {
+        rtt_init_print!();
+        for i in 0..11 {
+            rprintln!("RTIC Says Hello, world {}!!", i);
+        }
+    }
+
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        rprintln!("lets get lazy");
+        loop {
+            continue;
+        }
+    }
+};