From 4cd62a9f75b2ca122dc7d26bacbcd38770cb3db1 Mon Sep 17 00:00:00 2001
From: Jorge Aparicio <jorge@japaric.io>
Date: Sat, 23 Dec 2017 21:27:05 +0100
Subject: [PATCH] add a Cargo feature, cm7-r0p1, to fix a Cortex-M7 BASEPRI
erratum
---
Cargo.toml | 5 ++++-
ci/script.sh | 4 ++++
src/register/basepri.rs | 15 +++++++++++++--
src/register/basepri_max.rs | 15 +++++++++++++--
4 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/Cargo.toml b/Cargo.toml
index 9db89d6..8a6c0e2 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -12,4 +12,7 @@ version = "0.3.1"
[dependencies]
aligned = "0.1.1"
bare-metal = "0.1.0"
-volatile-register = "0.2.0"
\ No newline at end of file
+volatile-register = "0.2.0"
+
+[features]
+cm7-r0p1 = []
\ No newline at end of file
diff --git a/ci/script.sh b/ci/script.sh
index 9b60f0c..d5d1c69 100644
--- a/ci/script.sh
+++ b/ci/script.sh
@@ -2,6 +2,10 @@ set -euxo pipefail
main() {
case $TARGET in
+ thumbv7em-none-eabi*)
+ xargo check --target $TARGET --features cm7-r0p1
+ xargo check --target $TARGET
+ ;;
thumbv*-none-eabi*)
xargo check --target $TARGET
;;
diff --git a/src/register/basepri.rs b/src/register/basepri.rs
index a024d74..c9be9d3 100644
--- a/src/register/basepri.rs
+++ b/src/register/basepri.rs
@@ -18,11 +18,22 @@ pub fn read() -> u8 {
}
/// Writes to the CPU register
+///
+/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
+/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
+#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
#[inline]
-pub unsafe fn write(_basepri: u8) {
+pub unsafe fn write(basepri: u8) {
match () {
#[cfg(target_arch = "arm")]
- () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
+ () => match () {
+ #[cfg(not(feature = "cm7-r0p1"))]
+ () => asm!("msr BASEPRI, $0" :: "r"(basepri) : "memory" : "volatile"),
+ #[cfg(feature = "cm7-r0p1")]
+ () => asm!("cpsid i
+ msr BASEPRI, $0
+ cpsie i" :: "r"(basepri) : "memory" : "volatile"),
+ },
#[cfg(not(target_arch = "arm"))]
() => unimplemented!(),
}
diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs
index 0833aa7..c386e86 100644
--- a/src/register/basepri_max.rs
+++ b/src/register/basepri_max.rs
@@ -4,12 +4,23 @@
///
/// - `basepri != 0` AND `basepri::read() == 0`, OR
/// - `basepri != 0` AND `basepri < basepri::read()`
+///
+/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
+/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
+#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
#[inline]
-pub fn write(_basepri: u8) {
+pub fn write(basepri: u8) {
match () {
#[cfg(target_arch = "arm")]
() => unsafe {
- asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile");
+ match () {
+ #[cfg(not(feature = "cm7-r0p1"))]
+ () => asm!("msr BASEPRI_MAX, $0" :: "r"(basepri) : "memory" : "volatile"),
+ #[cfg(feature = "cm7-r0p1")]
+ () => asm!("cpsid i
+ msr BASEPRI_MAX, $0
+ cpsie i" :: "r"(basepri) : "memory" : "volatile"),
+ }
},
#[cfg(not(target_arch = "arm"))]
() => unimplemented!(),
--
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