diff --git a/.vscode/launch.json b/.vscode/launch.json
index f2dcf0aeb80d781780856129376b542678cf5b70..bc6f39cb24b822c4851fbaa3b82af61b6fcb635f 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -8,20 +8,37 @@
"type": "cortex-debug",
"request": "launch",
"servertype": "openocd",
- "name": "itm 64Mhz (debug)",
- "preLaunchTask": "cargo build --example itm",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
+ "name": "hello 16Mhz (debug)",
+ "preLaunchTask": "cargo build --example hello",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/hello",
"configFiles": [
"interface/stlink.cfg",
"target/stm32f4x.cfg"
],
"postLaunchCommands": [
- // sets the MCU to 64Mhz
+ "monitor arm semihosting enable"
+ ],
+ "cwd": "${workspaceRoot}"
+ },
+ {
+ "type": "cortex-debug",
+ "request": "launch",
+ "servertype": "openocd",
+ "name": "itm 16Mhz (debug)",
+ "preLaunchTask": "cargo build --example itm",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
+ // uses local config files
+ "configFiles": [
+ "./stlink.cfg",
+ "./stm32f4x.cfg"
+ ],
+ "postLaunchCommands": [
+ // here the MCU remains in 16MHz, since we use our local .cfg files
"monitor reset init"
],
"swoConfig": {
"enabled": true,
- "cpuFrequency": 64000000,
+ "cpuFrequency": 16000000,
"swoFrequency": 2000000,
"source": "probe",
"decoders": [
@@ -38,16 +55,30 @@
"type": "cortex-debug",
"request": "launch",
"servertype": "openocd",
- "name": "hello 16Mhz (debug)",
- "preLaunchTask": "cargo build --example hello",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/hello",
+ "name": "itm 64Mhz (debug)",
+ "preLaunchTask": "cargo build --example itm",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
"configFiles": [
"interface/stlink.cfg",
"target/stm32f4x.cfg"
],
"postLaunchCommands": [
- "monitor arm semihosting enable"
+ // sets the MCU to 64Mhz
+ "monitor reset init"
],
+ "swoConfig": {
+ "enabled": true,
+ "cpuFrequency": 64000000,
+ "swoFrequency": 2000000,
+ "source": "probe",
+ "decoders": [
+ {
+ "type": "console",
+ "label": "ITM",
+ "port": 0
+ }
+ ]
+ },
"cwd": "${workspaceRoot}"
},
{
@@ -67,36 +98,6 @@
],
"cwd": "${workspaceRoot}"
},
- {
- "type": "cortex-debug",
- "request": "launch",
- "servertype": "openocd",
- "name": "itm 16Mhz (debug)",
- "preLaunchTask": "cargo build --example itm",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
- // uses local config files
- "configFiles": [
- "./stlink.cfg",
- "./stm32f4x.cfg"
- ],
- "postLaunchCommands": [
- "monitor reset init"
- ],
- "swoConfig": {
- "enabled": true,
- "cpuFrequency": 16000000,
- "swoFrequency": 2000000,
- "source": "probe",
- "decoders": [
- {
- "type": "console",
- "label": "ITM",
- "port": 0
- }
- ]
- },
- "cwd": "${workspaceRoot}"
- },
// launch configuration for using an external itm viewer
// $ tail -f /tmp/itm.log
// or, prior to launching the bebug session
@@ -129,7 +130,7 @@
"request": "launch",
"servertype": "openocd",
"name": "device (debug)",
- "preLaunchTask": "cargo build --example device --features stm32f4",
+ "preLaunchTask": "cargo build --example device",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/device",
// uses local config files
"configFiles": [
@@ -160,16 +161,13 @@
"request": "launch",
"servertype": "openocd",
"name": "serial (debug)",
- "preLaunchTask": "cargo build --example serial --features stm32f4",
+ "preLaunchTask": "cargo build --example serial",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/serial",
// uses local config files
"configFiles": [
"./stlink.cfg",
"./stm32f4x.cfg"
],
- "postLaunchCommands": [
- "monitor arm semihosting enable"
- ],
"swoConfig": {
"enabled": true,
"cpuFrequency": 16000000,
@@ -384,7 +382,7 @@
"request": "launch",
"servertype": "openocd",
"name": "bare6 (debug) 16Mhz",
- "preLaunchTask": "cargo build --example bare6 --features stm32f4",
+ "preLaunchTask": "cargo build --example bare6",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/bare6",
"configFiles": [
"interface/stlink.cfg",
@@ -412,52 +410,21 @@
"type": "cortex-debug",
"request": "launch",
"servertype": "openocd",
- "name": "bare7 (debug)",
- "preLaunchTask": "cargo build --example bare7 --features stm32f4",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare7",
- // uses local config files
- "configFiles": [
- "./stlink.cfg",
- "./stm32f4x.cfg"
- ],
- "postLaunchCommands": [
- "monitor arm semihosting enable"
- ],
- "swoConfig": {
- "enabled": true,
- "cpuFrequency": 16000000,
- "swoFrequency": 2000000,
- "source": "probe",
- "decoders": [
- {
- "type": "console",
- "label": "ITM",
- "port": 0
- }
- ]
- },
- "svdFile": "STM32F413.svd",
- "cwd": "${workspaceRoot}"
- },
- {
- "type": "cortex-debug",
- "request": "launch",
- "servertype": "openocd",
- "name": "bare7 (debug) 64MHz",
- "preLaunchTask": "cargo build --example bare7 --features stm32f4",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare7",
- // uses local config files
+ "name": "bare6 (debug) 64Mhz",
+ "preLaunchTask": "cargo build --example bare6",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare6",
"configFiles": [
"interface/stlink.cfg",
"target/stm32f4x.cfg"
],
"postLaunchCommands": [
- "monitor reset halt"
+ // put the MCU in 64MHz
+ "monitor reset init"
],
"swoConfig": {
"enabled": true,
"cpuFrequency": 64000000,
- "swoFrequency": 2000000,
+ "swoFrequency": 2000000, // you may try 1000000 if not working
"source": "probe",
"decoders": [
{
@@ -467,27 +434,26 @@
}
]
},
- "svdFile": "STM32F413.svd",
"cwd": "${workspaceRoot}"
},
{
"type": "cortex-debug",
"request": "launch",
"servertype": "openocd",
- "name": "bare7 (debug) 84MHz",
- "preLaunchTask": "cargo build --example bare7 --features stm32f4",
+ "name": "bare7 (debug) 16MHz",
+ "preLaunchTask": "cargo build --example bare7",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/bare7",
// uses local config files
"configFiles": [
- "interface/stlink.cfg",
- "target/stm32f4x.cfg"
+ "./stlink.cfg",
+ "./stm32f4x.cfg"
],
"postLaunchCommands": [
- "monitor reset halt"
+ "monitor arm semihosting enable"
],
"swoConfig": {
"enabled": true,
- "cpuFrequency": 84000000,
+ "cpuFrequency": 16000000,
"swoFrequency": 2000000,
"source": "probe",
"decoders": [
@@ -505,20 +471,20 @@
"type": "cortex-debug",
"request": "launch",
"servertype": "openocd",
- "name": "bare6 (debug) 64Mhz",
- "preLaunchTask": "cargo build --example bare6 --features stm32f4",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare6",
+ "name": "bare7 (debug) 64MHz",
+ "preLaunchTask": "cargo build --example bare7",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare7",
"configFiles": [
"interface/stlink.cfg",
"target/stm32f4x.cfg"
],
"postLaunchCommands": [
- "monitor reset init"
+ "monitor reset halt"
],
"swoConfig": {
"enabled": true,
"cpuFrequency": 64000000,
- "swoFrequency": 2000000, // you may try 1000000 if not working
+ "swoFrequency": 2000000,
"source": "probe",
"decoders": [
{
@@ -528,26 +494,28 @@
}
]
},
+ "svdFile": "STM32F413.svd",
"cwd": "${workspaceRoot}"
},
{
"type": "cortex-debug",
"request": "launch",
"servertype": "openocd",
- "name": "bare6 (debug) 84Mhz",
- "preLaunchTask": "cargo build --example bare6 --features stm32f4",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare6",
+ "name": "bare7 (debug) 84MHz",
+ "preLaunchTask": "cargo build --example bare7",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare7",
+ // uses local config files
"configFiles": [
"interface/stlink.cfg",
"target/stm32f4x.cfg"
],
"postLaunchCommands": [
- "monitor reset init"
+ "monitor reset halt"
],
"swoConfig": {
"enabled": true,
"cpuFrequency": 84000000,
- "swoFrequency": 2000000, // you may try 1000000 if not working
+ "swoFrequency": 2000000,
"source": "probe",
"decoders": [
{
@@ -557,56 +525,7 @@
}
]
},
- "cwd": "${workspaceRoot}"
- },
- {
- "type": "cortex-debug",
- "request": "launch",
- "servertype": "openocd",
- "name": "bare7 (debug) 16Mhz",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare7",
- "configFiles": [
- "interface/stlink.cfg",
- "target/stm32f4x.cfg"
- ],
- "swoConfig": {
- "enabled": true,
- "cpuFrequency": 16000000,
- "swoFrequency": 2000000, // you may try 1000000 if not working
- "source": "probe",
- "decoders": [
- {
- "type": "console",
- "label": "Name",
- "port": 0
- }
- ]
- },
- "cwd": "${workspaceRoot}"
- },
- {
- "type": "cortex-debug",
- "request": "launch",
- "servertype": "openocd",
- "name": "c bare7 16Mhz",
- "executable": "./target/thumbv7em-none-eabihf/debug/examples/bare7",
- "configFiles": [
- "interface/stlink.cfg",
- "target/stm32f4x.cfg"
- ],
- "swoConfig": {
- "enabled": true,
- "cpuFrequency": 16000000,
- "swoFrequency": 2000000, // you may try 1000000 if not working
- "source": "probe",
- "decoders": [
- {
- "type": "console",
- "label": "Name",
- "port": 0
- }
- ]
- },
+ "svdFile": "STM32F413.svd",
"cwd": "${workspaceRoot}"
},
{
@@ -614,7 +533,7 @@
"request": "launch",
"servertype": "openocd",
"name": "bare8 (debug)",
- "preLaunchTask": "cargo build --example bare8 --features stm32f4",
+ "preLaunchTask": "cargo build --example bare8",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/bare8",
"configFiles": [
"interface/stlink.cfg",
@@ -641,7 +560,7 @@
"request": "launch",
"servertype": "openocd",
"name": "bare9 (debug)",
- "preLaunchTask": "cargo build --example bare9 --features stm32f4",
+ "preLaunchTask": "cargo build --example bare9",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/bare9",
"configFiles": [
"interface/stlink.cfg",
diff --git a/.vscode/tasks.json b/.vscode/tasks.json
index 9822b8f2eafd705e98ff4ebbf71719a5759c7ec2..fab7e524b93af3b9b2bf2a45228a49b3145858d9 100644
--- a/.vscode/tasks.json
+++ b/.vscode/tasks.json
@@ -75,6 +75,18 @@
"isDefault": true
}
},
+ {
+ "type": "shell",
+ "label": "cargo build --example serial",
+ "command": "cargo build --example serial --features \"hal\"",
+ "problemMatcher": [
+ "$rustc"
+ ],
+ "group": {
+ "kind": "build",
+ "isDefault": true
+ }
+ },
{
"type": "shell",
"label": "cargo build --example rtfm_interrupt --features \"pac rtfm\"",
@@ -197,20 +209,8 @@
},
{
"type": "shell",
- "label": "cargo build --example bare6 --features stm32f4",
- "command": "cargo build --example bare6 --features stm32f4",
- "problemMatcher": [
- "$rustc"
- ],
- "group": {
- "kind": "build",
- "isDefault": true
- }
- },
- {
- "type": "shell",
- "label": "cargo build --example serial --features stm32f4",
- "command": "cargo build --example serial --features stm32f4",
+ "label": "cargo build --example bare6",
+ "command": "cargo build --example bare6 --features \"hal\"",
"problemMatcher": [
"$rustc"
],
@@ -221,8 +221,8 @@
},
{
"type": "shell",
- "label": "cargo build --example bare7 --features stm32f4",
- "command": "cargo build --example bare7 --features \"hal pac\"",
+ "label": "cargo build --example bare7",
+ "command": "cargo build --example bare7 --features \"hal\"",
"problemMatcher": [
"$rustc"
],
@@ -233,7 +233,7 @@
},
{
"type": "shell",
- "label": "cargo build --example bare8 --features stm32f4",
+ "label": "cargo build --example bare8",
"command": "cargo build --example bare8 --features \"hal rtfm\"",
"problemMatcher": [
"$rustc"
@@ -245,7 +245,7 @@
},
{
"type": "shell",
- "label": "cargo build --example bare9 --features stm32f4",
+ "label": "cargo build --example bare9",
"command": "cargo build --example bare9 --features \"hal rtfm\"",
"problemMatcher": [
"$rustc"
diff --git a/examples/bare0.rs b/examples/bare0.rs
index cfd6f9061e843acff464435a6fdbcc410dbae27e..17e1a50fca5e01617c06eb87c524a4d0b161ad12 100644
--- a/examples/bare0.rs
+++ b/examples/bare0.rs
@@ -7,7 +7,7 @@
//! - checked vs. wrapping arithmetics
//! - safe and unsafe code
//! - making a safe API
-//!
+
// build without the Rust standard library
#![no_std]
// no standard main, we declare main using [entry]
diff --git a/examples/bare1.rs b/examples/bare1.rs
index 4a8fbc20d34572309f9d2815c76b1068252c62bc..b11eb3a004884c3ee0a1043611683a3e365c0dc9 100644
--- a/examples/bare1.rs
+++ b/examples/bare1.rs
@@ -6,7 +6,6 @@
//! - tracing over semihosting and ITM
//! - assembly calls and inline assembly
//! - more on arithmetics
-//!
#![no_main]
#![no_std]
diff --git a/examples/bare2.rs b/examples/bare2.rs
index 3986dccc7ab777b6533dcc6d53fb5f1678777652..e6b3c3d3b077acff1ff180fa460932ad8dd9a25b 100644
--- a/examples/bare2.rs
+++ b/examples/bare2.rs
@@ -58,7 +58,7 @@ fn main() -> ! {
// 0. Setup
// > cargo doc --open
// This will document your crate, and open the docs in your browser.
-// If it does not auto-open, the copy paste the path in your browser.
+// If it does not auto-open, then copy paste the path in your browser.
//
// In the docs, seach (`S`) for DWT, and click `cortex_m::peripheral::DWT`.
// Read the API docs.
diff --git a/examples/bare3.rs b/examples/bare3.rs
index f1ce59b3f153f24c519440dbb53f34bed7da3804..c5974cb2064e9cb0816bb1834fd7644d0304069c 100644
--- a/examples/bare3.rs
+++ b/examples/bare3.rs
@@ -5,7 +5,6 @@
//! What it covers:
//! - types, str, arrays ([u8;uszie]), slices (&[u8])
//! - iteration, copy
-//!
#![no_main]
#![no_std]
diff --git a/examples/bare6.rs b/examples/bare6.rs
index c9ad65b4b47db2eaaacdef5aad922ede044e5a71..c71aadf40755f51488593739b4d7943262ca6dda 100644
--- a/examples/bare6.rs
+++ b/examples/bare6.rs
@@ -6,8 +6,6 @@
//! - using svd2rust generated API
//! - setting the clock via script (again)
//! - routing the clock to a PIN for monitoring by an oscilloscope
-//! - changing the clock using Rust code
-//!
#![no_main]
#![no_std]
@@ -25,7 +23,7 @@ fn main() -> ! {
let mut c = stm32f413::CorePeripherals::take().unwrap();
let stim = &mut c.ITM.stim[0];
- iprintln!(stim, "Hello, bare6!");
+ iprintln!(stim, "bare6!");
c.DWT.enable_cycle_counter();
unsafe {
@@ -35,7 +33,6 @@ fn main() -> ! {
iprintln!(stim, "{}", t);
clock_out(&p.RCC, &p.GPIOC);
- // clock::set_84_mhz(rcc, flash);
idle(stim, p.RCC, p.GPIOA);
loop {}
diff --git a/examples/bare7.rs b/examples/bare7.rs
index 89ada1fb4ddec34245811518503f46ddf4c7a7c8..f438100739af6f3c10377dc666d33f8ba6a1f37c 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -1,11 +1,8 @@
//! Serial echo
//!
-//! Connect using e.g., `moserial` to `/dev/ttyACM0`
-//! 115200 8N1
-//!
-//! The MCU will echo incoming data and send a trace over ITM.
-//! Notice, as the hardware has a single byte buffer only, the input
-//! buffer may overflow.
+//! What it covers:
+//! - changing the clock using Rust code
+//! - working with the svd2rust API
#![deny(unsafe_code)]
#![feature(uniform_paths)]
@@ -146,6 +143,7 @@ fn main() -> ! {
// commit your answers (bare7_3)
//
// 4. Revisit the `README.md` regarding serial communication.
+// Setup `minicom` or similar to `/dev/ttyACM0`, 115200 8N1.
//
// Run the example, make sure your ITM is set to 84MHz.
//
@@ -182,7 +180,7 @@ fn main() -> ! {
//
// Your crate can be autmatically documentedthread:
//
-// $ cargo doc --open --features stm32f4
+// $ cargo doc --open --features "hal"
//
// This will document both your crate and its dependencies besides the `core` library.
//
diff --git a/examples/bare8.rs b/examples/bare8.rs
index 8d5f15609cee35b8b7d0437469fa7f292e5d1b46..c1a4ae894cf315c5de6d68a93865e99b1f865113 100644
--- a/examples/bare8.rs
+++ b/examples/bare8.rs
@@ -1,5 +1,11 @@
-// #![deny(unsafe_code)]
-// #![deny(warnings)]
+//! The RTFM framework
+//!
+//! What it covers:
+//! - utilisizing the RTFM framework for serial communicaton
+//! - singletons (enteties with a singe instance)
+//! - owned resources
+//! - peripheral access in RTFM
+
#![no_main]
#![no_std]
@@ -13,13 +19,9 @@ use crate::hal::prelude::*;
use crate::hal::serial::{config::Config, Rx, Serial, Tx};
use hal::stm32::{ITM, USART2};
-// use crate::hal::stm32::Interrupt::EXTI0;
use rtfm::app;
-// use hal::stm32::Interrupt::EXTI0;
#[app(device = hal::stm32)]
-// #[app(device = stm32f4xx_hal::stm32)]
-
const APP: () = {
// Late resources
static mut TX: Tx<USART2> = ();
@@ -30,7 +32,7 @@ const APP: () = {
#[init]
fn init() {
let stim = &mut core.ITM.stim[0];
- iprintln!(stim, "start");
+ iprintln!(stim, "bare8");
let rcc = device.RCC.constrain();
@@ -80,208 +82,12 @@ const APP: () = {
}
};
-// extern crate cortex_m_rtfm as rtfm;
-// extern crate f4;
-// extern crate heapless;
-
-// #[macro_use]
-// extern crate cortex_m_debug;
-
-// use f4::prelude::*;
-// use f4::Serial;
-// use f4::time::Hertz;
-// use heapless::Vec;
-// use rtfm::{app, Resource, Threshold};
-
-// // CONFIGURATION
-// const BAUD_RATE: Hertz = Hertz(115_200);
-
-// // RTFM FRAMEWORK
-// app! {
-// device: f4::stm32f40x,
-
-// resources: {
-// static VECTOR: Vec<u8, [u8; 4]> = Vec::new();
-// },
-
-// tasks: {
-// USART2: {
-// path: rx,
-// priority: 2,
-// resources: [VECTOR, USART2],
-// },
-// EXTI1: {
-// path: trace,
-// priority: 1,
-// resources: [VECTOR],
-// }
-// },
-// }
-
-// // `rx` task trigger on arrival of a USART2 interrupt
-// fn rx(t: &mut Threshold, r: USART2::Resources) {
-// let serial = Serial(&**r.USART2);
-
-// // we don't need to block waiting for data to arrive
-// // (as we were triggered) by the data arrival (or error)
-// match serial.read() {
-// Ok(byte) => {
-// // received byte correct
-// r.VECTOR.claim_mut(t, |vector, _| {
-// // critical section for the shared vector
-// let _ = vector.push(byte);
-// // here you could put your error handling for vector full
-// });
-// let _ = serial.write(byte);
-// }
-// Err(err) => {
-// // some transmission error
-// ipln!("Error {:?}", err);
-// r.USART2.dr.read(); // clear the error by reading the data register
-// }
-// }
-
-// // trigger the `trace` task
-// rtfm::set_pending(f4::stm32f40x::Interrupt::EXTI1);
-// }
-
-// // `trace` task triggered by the hight priority `rx` task
-// // a low priority task for the background processing (like tracing)
-// fn trace(t: &mut Threshold, r: EXTI1::Resources) {
-// let mut b = [0; 4]; // local buffer
-// let mut l = 0; // length of the received vector
-
-// r.VECTOR.claim(t, |vector, _| {
-// // critical section for the shared vector
-// // here the task `rx` will be blocked from executing
-// l = vector.len();
-// b[..l].copy_from_slice(&***vector); // efficent copy vector to the local buffer
-// });
-// // since we do the actual tracing (relatively slow)
-// // OUTSIDE the claim (critical section), there will be no
-// // additional blocking of `rx`
-// ipln!("Vec {:?}", &b[..l]);
-// }
-
-// // Here we see the typical use of init INITIALIZING the system
-// fn init(p: init::Peripherals, _r: init::Resources) {
-// ipln!("init");
-// let serial = Serial(p.USART2);
-
-// serial.init(BAUD_RATE.invert(), None, p.GPIOA, p.RCC);
-// // in effect telling the USART2 to trigger the `rx` task/interrupt
-// serial.listen(f4::serial::Event::Rxne);
-// }
-
-// // We will spend all time sleeping (unless we have work to do)
-// // reactive programming in RTFM ftw!!!
-// fn idle() -> ! {
-// // Sleep
-// loop {
-// rtfm::wfi();
-// }
-// }
-
-// // 1. compile and run the project at 16MHz
-// // make sure its running (not paused)
-// // start a terminal program, e.g., `moserial`
-// // connect to the port
-// //
-// // Device /dev/ttyACM0
-// // Baude Rate 115200
-// // Data Bits 8
-// // Stop Bits 1
-// // Parity None
-// // Handshake None
-// //
-// // (this is also known in short as 15200 8N1)
-// //
-// // you should now be able to send data and recive an echo from the MCU
-// //
-// // try sending: "abcd" as a single sequence (set the option No end in moserial)
-// // (don't send the quation marks, just abcd)
-// //
-// // what did you receive, and what was the output of the ITM trace
-// // ** your answer here **
-// //
-// // did you experience any over-run errors?
-// // ** your answer here **
-// //
-// // what is the key problem and its solution (try to follow the commented code)
-// // ** your answer here **
-// //
-// // commit your answers (bare8_1)
-// //
-// // 2. now catch the case when we are trying to write to a full vector/buffer
-// // and write a suiteble error message
-// //
-// // commit your answers (bare8_2)
-// //
-// // as a side note....
-// //
-// // The concurrency model behind RTFM offers
-// // 1. Race-free resource access
-// //
-// // 2. Deadlock-free exection
-// //
-// // 3. Shared execution stack (no pre-allocated stack regions)
-// //
-// // 4. Bound priority inversion
-// //
-// // 5. Theoretical underpinning ->
-// // + proofs of soundness
-// // + schedulability analysis
-// // + response time analysis
-// // + stack memory analysis
-// // + ... leverages on 25 years of reseach in the real-time community
-// // based on the seminal work of Baker in the early 1990s
-// // (known as the Stack Resource Policy, SRP)
-// //
-// // Our implementation in Rust offers
-// // 1. compile check and analysis of tasks and resources
-// // + the API implementation together with the Rust compiler will ensure that
-// // both RTFM (SRP) soundness and the Rust memory model invariants
-// // are upheld (under all circumpstances).
-// //
-// // 2. arguably the worlds fastest real time scheduler *
-// // + task invocation 0-cycle OH on top of HW interrupt handling
-// // + 2 cycle OH for locking a shared resource (on claim entry)
-// // + 1 cycle OH for releasineg a shared resoure (on claim exit)
-// //
-// // 3. arguably the worlds most memory efficient scheduler *
-// // + 1 byte stack memory OH for each (nested) claim
-// // (no additional book-keeping during run-time)
-// //
-// // * applies to static task/resource models with single core
-// // pre-emptive, static priority scheduling
-// //
-// // in comparison "real-time" schedulers for threaded models like FreeRTOS
-// // - CPU and memory OH magnitudes larger (100s of cycles/kilobytes of memory)
-// // - ... and what's worse OH is typically unbound (no proofs of worst case)
-// // - potential race conditions (up to the user to verify)
-// // - potential dead-locks (up to the implementation)
-// // - potential unbound priority inversion (up to the implementation)
-// //
-// // Rust RTFM (currently) target ONLY STATIC SYSTEMS, there is no notion
-// // of dynamically creating new executions contexts/threads
-// // so a direct comparison is not completely fair.
-// //
-// // On the other hand, embedded applications are typically static by nature
-// // so a STATIC model is to that end better suitable.
-// //
-// // RTFM is reactive by nature, a task execute to end, triggered
-// // by an internal or external event, (where an interrupt is an external event
-// // from the environment, like a HW peripheral such as the USART2).
-// //
-// // Threads on the other hand are concurrent and infinte by nature and
-// // actively blocking/yeilding awaiting stimuli. Hence reactivity needs to be CODED.
-// // This leads to an anomaly, the underlying HW is reactive (interrupts),
-// // requiring an interrupt handler, that creates a signal to the scheduler.
-// //
-// // The scheduler then needs to keep track of all threads and at some point choose
-// // to dispatch the awaiting thread. So reactivity is bottlenecked to the point
-// // of scheduling by que management, context switching and other additional
-// // book keeping.
-// //
-// // In essence, the thread scheduler tries to re-establish the reactivity that
-// // were there (interrupts), a battle that cannot be won...
+// 1. Compile and run the example.
+// Verify that it has the same behavior as bare7.
+//
+// 2. Add a local variable `received` that counts the number of bytes received.
+// Add a local variable `errors` that counts the number of errors.
+//
+// Adjust the ITM trace to include the additional information.
+//
+// commit your development (bare8_2)
diff --git a/examples/bare9.rs b/examples/bare9.rs
index 47176124e28a9c837ef0ef3803ecde56f24a899a..ef8f240a216a3f5e3c6df5bb6736bd4514c6254c 100644
--- a/examples/bare9.rs
+++ b/examples/bare9.rs
@@ -13,11 +13,8 @@ use crate::hal::prelude::*;
use crate::hal::serial::{config::Config, Event, Rx, Serial, Tx};
use hal::stm32::ITM;
-// use crate::hal::stm32::Interrupt::EXTI0;
use rtfm::app;
-// use hal::stm32::Interrupt::EXTI0;
-// #[app(device = stm32f4xx_hal::stm32)]
#[app(device = hal::stm32)]
const APP: () = {
diff --git a/examples/device.rs b/examples/device.rs
index f78e4823a176471f46f361dd82ad632f2a11a12e..351b9236d40d78465d81a1aa22160fdd93ecd955 100644
--- a/examples/device.rs
+++ b/examples/device.rs
@@ -23,7 +23,7 @@ extern crate panic_halt;
use cortex_m::{iprint, peripheral::syst::SystClkSource};
use cortex_m_rt::entry;
use cortex_m_semihosting::hprintln;
-use stm32f4::stm32f411::{interrupt, Interrupt, ITM, NVIC};
+use stm32f4::stm32f413::{interrupt, Interrupt, ITM, NVIC};
#[entry]
fn main() -> ! {
diff --git a/examples/serial.rs b/examples/serial.rs
index ccf0d218860d58edcfebae083ca0ab46b246757e..32c66c9b5805337c7331f86263f1d24e86a5d2f0 100644
--- a/examples/serial.rs
+++ b/examples/serial.rs
@@ -40,10 +40,8 @@ fn main() -> ! {
// let _clocks = rcc.cfgr.freeze();
let tx = gpioa.pa2.into_alternate_af7();
-
let rx = gpioa.pa3.into_alternate_af7(); // try comment out
-
- // let rx = gpioa.pa3.into_alternate_af0(); // try uncomment
+ // let rx = gpioa.pa3.into_alternate_af0(); // try uncomment
let serial = Serial::usart2(
p.USART2,