diff --git a/.vscode/launch.json b/.vscode/launch.json
index 18e491737252166c37fc793e05b78b0fe0237eea..802eb42bb0d82df9f86707d58ab6d24b1184d992 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -16,6 +16,7 @@
"target/stm32f4x.cfg"
],
"postLaunchCommands": [
+ // sets the MCU to 64Mhz
"monitor reset init"
],
"swoConfig": {
@@ -95,6 +96,37 @@
},
"cwd": "${workspaceRoot}"
},
+ {
+ "type": "cortex-debug",
+ "request": "launch",
+ "servertype": "openocd",
+ "name": "device (debug)",
+ "preLaunchTask": "cargo build --example device --features stm32f4",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/device",
+ // uses local config files
+ "configFiles": [
+ "./stlink.cfg",
+ "./stm32f4x.cfg"
+ ],
+ "postLaunchCommands": [
+ "monitor arm semihosting enable"
+ ],
+ "swoConfig": {
+ "enabled": true,
+ "cpuFrequency": 16000000,
+ "swoFrequency": 2000000,
+ "source": "probe",
+ "decoders": [
+ {
+ "type": "console",
+ "label": "ITM",
+ "port": 0
+ }
+ ]
+ },
+ "svdFile": "STM32F413.svd",
+ "cwd": "${workspaceRoot}"
+ },
{
"type": "cortex-debug",
"request": "launch",
diff --git a/.vscode/tasks.json b/.vscode/tasks.json
index 649f1aacb794503e5e07ca2741cbd87333a72b6e..b535eecf7e8abb1c6e23621e8a0f2dcdedc2553a 100644
--- a/.vscode/tasks.json
+++ b/.vscode/tasks.json
@@ -63,5 +63,17 @@
"isDefault": true
}
},
+ {
+ "type": "shell",
+ "label": "cargo build --example device --features stm32f4",
+ "command": "cargo build --example device --features stm32f4",
+ "problemMatcher": [
+ "$rustc"
+ ],
+ "group": {
+ "kind": "build",
+ "isDefault": true
+ }
+ },
]
}
\ No newline at end of file
diff --git a/Cargo.toml b/Cargo.toml
index cc13cce1e280c56dc5e0ca4af013628478ac63f1..1b4547c369086ab9b7e449825deb89b947cbd769 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -7,12 +7,11 @@ version = "0.1.0"
[dependencies]
cortex-m = "0.5.8"
-cortex-m-rt = "0.6.5"
+cortex-m-rt = "0.6.7"
cortex-m-semihosting = "0.3.2"
panic-halt = "0.2.0"
-# panic-abort = "0.3.1"
+# panic-abort = "0.3.1" # requires nightly toolchain
-# Uncomment for the panic example.
panic-semihosting = "0.5.1"
panic-itm = "0.4.0"
bare-metal = "0.2.4"
@@ -20,10 +19,14 @@ bare-metal = "0.2.4"
# Uncomment for the allocator example.
# alloc-cortex-m = "0.3.5"
-# Uncomment for the device example.
-# [dependencies.stm32f30x]
-# features = ["rt"]
-# version = "0.7.1"
+[dependencies.stm32f4]
+version = "0.5.0"
+features = ["stm32f411", "rt"]
+optional = true
+
+[[example]]
+name = "device"
+required-features = ["stm32f4"]
# this lets you use `cargo fix`!
[[bin]]
@@ -35,7 +38,8 @@ bench = false
panic = "abort"
[profile.release]
-codegen-units = 1 # better optimizations
-debug = true # symbols are nice and they don't increase the size on Flash
-lto = true # better optimizations
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations
panic = "abort"
+
diff --git a/README.md b/README.md
index ad2d2e1a7ca519292639736e833d00463b5f4dec..851f1e245e1f5f4c09a6a10ca9eb4255fafb1bbd 100644
--- a/README.md
+++ b/README.md
@@ -198,8 +198,79 @@ they gain access to the `ITM` periphereal. In the first case we *steal* the whol
In case the execution of an intstruction fails, a `HardFault` exception is raised by the hardware, and the `HardFault` handler is executed. We can define our own handler as in example `crash.rs`. In `main` we attempt to read an illegal address, causing a `HardFault`, and we hit a breakpoint (`openocd.gdb` script sets a breakbpoint at the `HardFualt` handler). From there you can print the exception frame, reflecting the state of the MCU when the error occured. You can use `gdb` to give a `back trace` of the call-stack leading up to the error. See the example for detailed information.
+---
+
+### Device Crates and System View Descriptions (SVDs)
+
+Besides the ARM provided *core* peripherals the STM32F401re/STM32F411re MCUs has numerous vendor specific peripherals (GPIOs, Timers, USARTs etc.). The vendor provides a System View Description (SVD) specifying the register block layouts (fields, enumerated values, etc.). Using the `svd2rust` tool we can derive a `Device Crate` providing an API that allow us to access each register according to the vendors specification. The `device.rs` example showcase how a `Device Crate` for the STM32F401re/STM32F411re MCUs can be added. (These MCUs have the same set of peripherals, only the the maximum clock rating differs.)
+
+The example output a `.` each second over `semihosting` and `ITM`.
+
+Looking at the `Corgo.toml` file we find:
+
+``` toml
+[package]
+authors = ["Per Lindgren <per.lindgren@ltu.se>"]
+edition = "2018"
+readme = "README.md"
+name = "app"
+version = "0.1.0"
+
+[dependencies]
+cortex-m = "0.5.8"
+cortex-m-rt = "0.6.7"
+cortex-m-semihosting = "0.3.2"
+panic-halt = "0.2.0"
+# panic-abort = "0.3.1" # requires nightly toolchain
+
+panic-semihosting = "0.5.1"
+panic-itm = "0.4.0"
+bare-metal = "0.2.4"
+
+# Uncomment for the allocator example.
+# alloc-cortex-m = "0.3.5"
+
+[dependencies.stm32f4]
+version = "0.5.0"
+features = ["stm32f411", "rt"]
+optional = true
+
+[[example]]
+name = "device"
+required-features = ["stm32f4"]
+# this lets you use `cargo fix`!
+[[bin]]
+name = "app"
+test = false
+bench = false
+
+[profile.dev]
+panic = "abort"
+
+[profile.release]
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations
+panic = "abort"
+```
+
+Of particular interest here is the *optional* dependency to [dependencies.stm32f4], where `"stm32f4"` is a `required-feature` for the example `"device"`. In effect, you need to compile `device` as:
+
+``` console
+cargo build --example device --features stm32f4
+```
+
+In turn:
+
+``` toml
+[dependencies.stm32f4]
+version = "0.5.0"
+features = ["stm32f411", "rt"]
+optional = true
+```
+Compiles `stm32f4` (a generic library for all STMF4 MCUs) with `features = features = ["stm32f411", "rt"]`, which indicates the specific MCU with `rt` (run-time support) enabled. By having the `Device Crate` as an optional dependency, we did not need to compile it (unless we need it, and as you might have experienced already compiling the `Device Crate` takes a bit of time initially). (An SVD file is typically > 50k lines, amounting to the same (or more) lines of Rust code.)
---
diff --git a/STM32F413.svd b/STM32F413.svd
new file mode 100644
index 0000000000000000000000000000000000000000..7c3cd803a77ea7500c49eb43759e13e90f85cf2b
--- /dev/null
+++ b/STM32F413.svd
@@ -0,0 +1,49411 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<device schemaVersion="1.1"
+xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
+xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+ <name>STM32F413</name>
+ <version>1.0</version>
+ <description>STM32F413_v1r0</description>
+ <cpu>
+ <name>CM4</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>true</mpuPresent>
+ <fpuPresent>true</fpuPresent>
+ <nvicPrioBits>4</nvicPrioBits>
+ <vendorSystickConfig>0</vendorSystickConfig>
+ </cpu>
+
+ <!--Bus Interface Properties-->
+ <!--Cortex-M4 is byte addressable-->
+ <addressUnitBits>8</addressUnitBits>
+ <!--the maximum data bit width accessible within a single transfer-->
+ <width>32</width>
+ <!--Register Default Properties-->
+ <size>0x20</size>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <peripherals>
+ <peripheral>
+ <name>ADC1</name>
+ <description>Analog-to-digital converter</description>
+ <groupName>ADC</groupName>
+ <baseAddress>0x40012000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>ADC</name>
+ <description>ADC1 global interrupt</description>
+ <value>18</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OVR</name>
+ <description>Overrun</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STRT</name>
+ <description>Regular channel start flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSTRT</name>
+ <description>Injected channel start
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOC</name>
+ <description>Injected channel end of
+ conversion</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EOC</name>
+ <description>Regular channel end of
+ conversion</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWD</name>
+ <description>Analog watchdog flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OVRIE</name>
+ <description>Overrun interrupt enable</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RES</name>
+ <description>Resolution</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWDEN</name>
+ <description>Analog watchdog enable on regular
+ channels</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JAWDEN</name>
+ <description>Analog watchdog enable on injected
+ channels</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DISCNUM</name>
+ <description>Discontinuous mode channel
+ count</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>JDISCEN</name>
+ <description>Discontinuous mode on injected
+ channels</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DISCEN</name>
+ <description>Discontinuous mode on regular
+ channels</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JAUTO</name>
+ <description>Automatic injected group
+ conversion</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDSGL</name>
+ <description>Enable the watchdog on a single channel
+ in scan mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCAN</name>
+ <description>Scan mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCIE</name>
+ <description>Interrupt enable for injected
+ channels</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDIE</name>
+ <description>Analog watchdog interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EOCIE</name>
+ <description>Interrupt enable for EOC</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDCH</name>
+ <description>Analog watchdog channel select
+ bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SWSTART</name>
+ <description>Start conversion of regular
+ channels</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTEN</name>
+ <description>External trigger enable for regular
+ channels</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>EXTSEL</name>
+ <description>External event select for regular
+ group</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>JSWSTART</name>
+ <description>Start conversion of injected
+ channels</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEXTEN</name>
+ <description>External trigger enable for injected
+ channels</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>JEXTSEL</name>
+ <description>External event select for injected
+ group</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ALIGN</name>
+ <description>Data alignment</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EOCS</name>
+ <description>End of conversion
+ selection</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DDS</name>
+ <description>DMA disable selection (for single ADC
+ mode)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMA</name>
+ <description>Direct memory access mode (for single
+ ADC mode)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CONT</name>
+ <description>Continuous conversion</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADON</name>
+ <description>A/D Converter ON / OFF</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMPR1</name>
+ <displayName>SMPR1</displayName>
+ <description>sample time register 1</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SMPx_x</name>
+ <description>Sample time bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMPR2</name>
+ <displayName>SMPR2</displayName>
+ <description>sample time register 2</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SMPx_x</name>
+ <description>Sample time bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JOFR1</name>
+ <displayName>JOFR1</displayName>
+ <description>injected channel data offset register
+ x</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JOFFSET1</name>
+ <description>Data offset for injected channel
+ x</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JOFR2</name>
+ <displayName>JOFR2</displayName>
+ <description>injected channel data offset register
+ x</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JOFFSET2</name>
+ <description>Data offset for injected channel
+ x</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JOFR3</name>
+ <displayName>JOFR3</displayName>
+ <description>injected channel data offset register
+ x</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JOFFSET3</name>
+ <description>Data offset for injected channel
+ x</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JOFR4</name>
+ <displayName>JOFR4</displayName>
+ <description>injected channel data offset register
+ x</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JOFFSET4</name>
+ <description>Data offset for injected channel
+ x</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HTR</name>
+ <displayName>HTR</displayName>
+ <description>watchdog higher threshold
+ register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000FFF</resetValue>
+ <fields>
+ <field>
+ <name>HT</name>
+ <description>Analog watchdog higher
+ threshold</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LTR</name>
+ <displayName>LTR</displayName>
+ <description>watchdog lower threshold
+ register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LT</name>
+ <description>Analog watchdog lower
+ threshold</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SQR1</name>
+ <displayName>SQR1</displayName>
+ <description>regular sequence register 1</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>L</name>
+ <description>Regular channel sequence
+ length</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SQ16</name>
+ <description>16th conversion in regular
+ sequence</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ15</name>
+ <description>15th conversion in regular
+ sequence</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ14</name>
+ <description>14th conversion in regular
+ sequence</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ13</name>
+ <description>13th conversion in regular
+ sequence</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SQR2</name>
+ <displayName>SQR2</displayName>
+ <description>regular sequence register 2</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SQ12</name>
+ <description>12th conversion in regular
+ sequence</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ11</name>
+ <description>11th conversion in regular
+ sequence</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ10</name>
+ <description>10th conversion in regular
+ sequence</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ9</name>
+ <description>9th conversion in regular
+ sequence</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ8</name>
+ <description>8th conversion in regular
+ sequence</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ7</name>
+ <description>7th conversion in regular
+ sequence</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SQR3</name>
+ <displayName>SQR3</displayName>
+ <description>regular sequence register 3</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SQ6</name>
+ <description>6th conversion in regular
+ sequence</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ5</name>
+ <description>5th conversion in regular
+ sequence</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ4</name>
+ <description>4th conversion in regular
+ sequence</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ3</name>
+ <description>3rd conversion in regular
+ sequence</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ2</name>
+ <description>2nd conversion in regular
+ sequence</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SQ1</name>
+ <description>1st conversion in regular
+ sequence</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JSQR</name>
+ <displayName>JSQR</displayName>
+ <description>injected sequence register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JL</name>
+ <description>Injected sequence length</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>JSQ4</name>
+ <description>4th conversion in injected
+ sequence</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>JSQ3</name>
+ <description>3rd conversion in injected
+ sequence</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>JSQ2</name>
+ <description>2nd conversion in injected
+ sequence</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>JSQ1</name>
+ <description>1st conversion in injected
+ sequence</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JDR1</name>
+ <displayName>JDR1</displayName>
+ <description>injected data register x</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JDR2</name>
+ <displayName>JDR2</displayName>
+ <description>injected data register x</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JDR3</name>
+ <displayName>JDR3</displayName>
+ <description>injected data register x</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>JDR4</name>
+ <displayName>JDR4</displayName>
+ <description>injected data register x</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>regular data register</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA</name>
+ <description>Regular data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CSR</name>
+ <displayName>CSR</displayName>
+ <description>Common status register</description>
+ <addressOffset>0x300</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWD1</name>
+ <description>Analog watchdog flag of
+ ADC1</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EOC1</name>
+ <description>End of conversion of ADC1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOC1</name>
+ <description>Injected channel end of conversion of
+ ADC1</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSTRT1</name>
+ <description>Injected channel Start flag of
+ ADC1</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STRT1</name>
+ <description>Regular channel Start flag of
+ ADC1</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVR1</name>
+ <description>Overrun flag of ADC1</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR</name>
+ <displayName>CCR</displayName>
+ <description>common control register</description>
+ <addressOffset>0x304</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ADCPRE</name>
+ <description>ADC prescaler</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>VBATE</name>
+ <description>VBAT enable</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TSVREFE</name>
+ <description>Temperature sensor and VREFINT
+ enable</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>CRC</name>
+ <description>Cryptographic processor</description>
+ <groupName>CRC</groupName>
+ <baseAddress>0x40023000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>Data register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>DR</name>
+ <description>Data Register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IDR</name>
+ <displayName>IDR</displayName>
+ <description>Independent Data register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IDR</name>
+ <description>Independent Data register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>Control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CR</name>
+ <description>Control regidter</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>DBG</name>
+ <description>Debug support</description>
+ <groupName>DBG</groupName>
+ <baseAddress>0xE0042000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>DBGMCU_IDCODE</name>
+ <displayName>DBGMCU_IDCODE</displayName>
+ <description>IDCODE</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x10006411</resetValue>
+ <fields>
+ <field>
+ <name>DEV_ID</name>
+ <description>DEV_ID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>REV_ID</name>
+ <description>REV_ID</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DBGMCU_CR</name>
+ <displayName>DBGMCU_CR</displayName>
+ <description>Control Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DBG_SLEEP</name>
+ <description>DBG_SLEEP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_STOP</name>
+ <description>DBG_STOP</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_STANDBY</name>
+ <description>DBG_STANDBY</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TRACE_IOEN</name>
+ <description>TRACE_IOEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TRACE_MODE</name>
+ <description>TRACE_MODE</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DBGMCU_APB1_FZ</name>
+ <displayName>DBGMCU_APB1_FZ</displayName>
+ <description>Debug MCU APB1 Freeze registe</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DBG_TIM2_STOP</name>
+ <description>DBG_TIM2_STOP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_TIM3_STOP</name>
+ <description>DBG_TIM3 _STOP</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_TIM4_STOP</name>
+ <description>DBG_TIM4_STOP</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_TIM5_STOP</name>
+ <description>DBG_TIM5_STOP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_RTC_Stop</name>
+ <description>RTC stopped when Core is
+ halted</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_WWDG_STOP</name>
+ <description>DBG_WWDG_STOP</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_IWDEG_STOP</name>
+ <description>DBG_IWDEG_STOP</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_I2C1_SMBUS_TIMEOUT</name>
+ <description>DBG_J2C1_SMBUS_TIMEOUT</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_I2C2_SMBUS_TIMEOUT</name>
+ <description>DBG_J2C2_SMBUS_TIMEOUT</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_I2C3SMBUS_TIMEOUT</name>
+ <description>DBG_J2C3SMBUS_TIMEOUT</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DBGMCU_APB2_FZ</name>
+ <displayName>DBGMCU_APB2_FZ</displayName>
+ <description>Debug MCU APB2 Freeze registe</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DBG_TIM1_STOP</name>
+ <description>TIM1 counter stopped when core is
+ halted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_TIM9_STOP</name>
+ <description>TIM9 counter stopped when core is
+ halted</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_TIM10_STOP</name>
+ <description>TIM10 counter stopped when core is
+ halted</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBG_TIM11_STOP</name>
+ <description>TIM11 counter stopped when core is
+ halted</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>EXTI</name>
+ <description>External interrupt/event
+ controller</description>
+ <groupName>EXTI</groupName>
+ <baseAddress>0x40013C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TAMP_STAMP</name>
+ <description>Tamper and TimeStamp interrupts through the
+ EXTI line</description>
+ <value>2</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI0</name>
+ <description>EXTI Line0 interrupt</description>
+ <value>6</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI1</name>
+ <description>EXTI Line1 interrupt</description>
+ <value>7</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI2</name>
+ <description>EXTI Line2 interrupt</description>
+ <value>8</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI3</name>
+ <description>EXTI Line3 interrupt</description>
+ <value>9</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI4</name>
+ <description>EXTI Line4 interrupt</description>
+ <value>10</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI9_5</name>
+ <description>EXTI Line[9:5] interrupts</description>
+ <value>23</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI15_10</name>
+ <description>EXTI Line[15:10] interrupts</description>
+ <value>40</value>
+ </interrupt>
+ <interrupt>
+ <name>lptim1_OR_it_eit_23</name>
+ <description>LP Timer global interrupt or EXT1 interrupt
+ line 23</description>
+ <value>97</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>IMR</name>
+ <displayName>IMR</displayName>
+ <description>Interrupt mask register
+ (EXTI_IMR)</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MR0</name>
+ <description>Interrupt Mask on line 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR1</name>
+ <description>Interrupt Mask on line 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR2</name>
+ <description>Interrupt Mask on line 2</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR3</name>
+ <description>Interrupt Mask on line 3</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR4</name>
+ <description>Interrupt Mask on line 4</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR5</name>
+ <description>Interrupt Mask on line 5</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR6</name>
+ <description>Interrupt Mask on line 6</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR7</name>
+ <description>Interrupt Mask on line 7</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR8</name>
+ <description>Interrupt Mask on line 8</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR9</name>
+ <description>Interrupt Mask on line 9</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR10</name>
+ <description>Interrupt Mask on line 10</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR11</name>
+ <description>Interrupt Mask on line 11</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR12</name>
+ <description>Interrupt Mask on line 12</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR13</name>
+ <description>Interrupt Mask on line 13</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR14</name>
+ <description>Interrupt Mask on line 14</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR15</name>
+ <description>Interrupt Mask on line 15</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR16</name>
+ <description>Interrupt Mask on line 16</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR17</name>
+ <description>Interrupt Mask on line 17</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR18</name>
+ <description>Interrupt Mask on line 18</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR19</name>
+ <description>Interrupt Mask on line 19</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR20</name>
+ <description>Interrupt Mask on line 20</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR21</name>
+ <description>Interrupt Mask on line 21</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR22</name>
+ <description>Interrupt Mask on line 22</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EMR</name>
+ <displayName>EMR</displayName>
+ <description>Event mask register (EXTI_EMR)</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MR0</name>
+ <description>Event Mask on line 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR1</name>
+ <description>Event Mask on line 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR2</name>
+ <description>Event Mask on line 2</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR3</name>
+ <description>Event Mask on line 3</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR4</name>
+ <description>Event Mask on line 4</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR5</name>
+ <description>Event Mask on line 5</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR6</name>
+ <description>Event Mask on line 6</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR7</name>
+ <description>Event Mask on line 7</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR8</name>
+ <description>Event Mask on line 8</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR9</name>
+ <description>Event Mask on line 9</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR10</name>
+ <description>Event Mask on line 10</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR11</name>
+ <description>Event Mask on line 11</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR12</name>
+ <description>Event Mask on line 12</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR13</name>
+ <description>Event Mask on line 13</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR14</name>
+ <description>Event Mask on line 14</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR15</name>
+ <description>Event Mask on line 15</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR16</name>
+ <description>Event Mask on line 16</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR17</name>
+ <description>Event Mask on line 17</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR18</name>
+ <description>Event Mask on line 18</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR19</name>
+ <description>Event Mask on line 19</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR20</name>
+ <description>Event Mask on line 20</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR21</name>
+ <description>Event Mask on line 21</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MR22</name>
+ <description>Event Mask on line 22</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RTSR</name>
+ <displayName>RTSR</displayName>
+ <description>Rising Trigger selection register
+ (EXTI_RTSR)</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TR0</name>
+ <description>Rising trigger event configuration of
+ line 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR1</name>
+ <description>Rising trigger event configuration of
+ line 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR2</name>
+ <description>Rising trigger event configuration of
+ line 2</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR3</name>
+ <description>Rising trigger event configuration of
+ line 3</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR4</name>
+ <description>Rising trigger event configuration of
+ line 4</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR5</name>
+ <description>Rising trigger event configuration of
+ line 5</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR6</name>
+ <description>Rising trigger event configuration of
+ line 6</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR7</name>
+ <description>Rising trigger event configuration of
+ line 7</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR8</name>
+ <description>Rising trigger event configuration of
+ line 8</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR9</name>
+ <description>Rising trigger event configuration of
+ line 9</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR10</name>
+ <description>Rising trigger event configuration of
+ line 10</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR11</name>
+ <description>Rising trigger event configuration of
+ line 11</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR12</name>
+ <description>Rising trigger event configuration of
+ line 12</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR13</name>
+ <description>Rising trigger event configuration of
+ line 13</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR14</name>
+ <description>Rising trigger event configuration of
+ line 14</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR15</name>
+ <description>Rising trigger event configuration of
+ line 15</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR16</name>
+ <description>Rising trigger event configuration of
+ line 16</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR17</name>
+ <description>Rising trigger event configuration of
+ line 17</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR18</name>
+ <description>Rising trigger event configuration of
+ line 18</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR19</name>
+ <description>Rising trigger event configuration of
+ line 19</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR20</name>
+ <description>Rising trigger event configuration of
+ line 20</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR21</name>
+ <description>Rising trigger event configuration of
+ line 21</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR22</name>
+ <description>Rising trigger event configuration of
+ line 22</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FTSR</name>
+ <displayName>FTSR</displayName>
+ <description>Falling Trigger selection register
+ (EXTI_FTSR)</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TR0</name>
+ <description>Falling trigger event configuration of
+ line 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR1</name>
+ <description>Falling trigger event configuration of
+ line 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR2</name>
+ <description>Falling trigger event configuration of
+ line 2</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR3</name>
+ <description>Falling trigger event configuration of
+ line 3</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR4</name>
+ <description>Falling trigger event configuration of
+ line 4</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR5</name>
+ <description>Falling trigger event configuration of
+ line 5</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR6</name>
+ <description>Falling trigger event configuration of
+ line 6</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR7</name>
+ <description>Falling trigger event configuration of
+ line 7</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR8</name>
+ <description>Falling trigger event configuration of
+ line 8</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR9</name>
+ <description>Falling trigger event configuration of
+ line 9</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR10</name>
+ <description>Falling trigger event configuration of
+ line 10</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR11</name>
+ <description>Falling trigger event configuration of
+ line 11</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR12</name>
+ <description>Falling trigger event configuration of
+ line 12</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR13</name>
+ <description>Falling trigger event configuration of
+ line 13</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR14</name>
+ <description>Falling trigger event configuration of
+ line 14</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR15</name>
+ <description>Falling trigger event configuration of
+ line 15</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR16</name>
+ <description>Falling trigger event configuration of
+ line 16</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR17</name>
+ <description>Falling trigger event configuration of
+ line 17</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR18</name>
+ <description>Falling trigger event configuration of
+ line 18</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR19</name>
+ <description>Falling trigger event configuration of
+ line 19</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR20</name>
+ <description>Falling trigger event configuration of
+ line 20</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR21</name>
+ <description>Falling trigger event configuration of
+ line 21</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TR22</name>
+ <description>Falling trigger event configuration of
+ line 22</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SWIER</name>
+ <displayName>SWIER</displayName>
+ <description>Software interrupt event register
+ (EXTI_SWIER)</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SWIER0</name>
+ <description>Software Interrupt on line
+ 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER1</name>
+ <description>Software Interrupt on line
+ 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER2</name>
+ <description>Software Interrupt on line
+ 2</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER3</name>
+ <description>Software Interrupt on line
+ 3</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER4</name>
+ <description>Software Interrupt on line
+ 4</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER5</name>
+ <description>Software Interrupt on line
+ 5</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER6</name>
+ <description>Software Interrupt on line
+ 6</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER7</name>
+ <description>Software Interrupt on line
+ 7</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER8</name>
+ <description>Software Interrupt on line
+ 8</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER9</name>
+ <description>Software Interrupt on line
+ 9</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER10</name>
+ <description>Software Interrupt on line
+ 10</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER11</name>
+ <description>Software Interrupt on line
+ 11</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER12</name>
+ <description>Software Interrupt on line
+ 12</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER13</name>
+ <description>Software Interrupt on line
+ 13</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER14</name>
+ <description>Software Interrupt on line
+ 14</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER15</name>
+ <description>Software Interrupt on line
+ 15</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER16</name>
+ <description>Software Interrupt on line
+ 16</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER17</name>
+ <description>Software Interrupt on line
+ 17</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER18</name>
+ <description>Software Interrupt on line
+ 18</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER19</name>
+ <description>Software Interrupt on line
+ 19</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER20</name>
+ <description>Software Interrupt on line
+ 20</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER21</name>
+ <description>Software Interrupt on line
+ 21</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWIER22</name>
+ <description>Software Interrupt on line
+ 22</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PR</name>
+ <displayName>PR</displayName>
+ <description>Pending register (EXTI_PR)</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PR0</name>
+ <description>Pending bit 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR1</name>
+ <description>Pending bit 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR2</name>
+ <description>Pending bit 2</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR3</name>
+ <description>Pending bit 3</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR4</name>
+ <description>Pending bit 4</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR5</name>
+ <description>Pending bit 5</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR6</name>
+ <description>Pending bit 6</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR7</name>
+ <description>Pending bit 7</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR8</name>
+ <description>Pending bit 8</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR9</name>
+ <description>Pending bit 9</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR10</name>
+ <description>Pending bit 10</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR11</name>
+ <description>Pending bit 11</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR12</name>
+ <description>Pending bit 12</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR13</name>
+ <description>Pending bit 13</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR14</name>
+ <description>Pending bit 14</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR15</name>
+ <description>Pending bit 15</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR16</name>
+ <description>Pending bit 16</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR17</name>
+ <description>Pending bit 17</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR18</name>
+ <description>Pending bit 18</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR19</name>
+ <description>Pending bit 19</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR20</name>
+ <description>Pending bit 20</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR21</name>
+ <description>Pending bit 21</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PR22</name>
+ <description>Pending bit 22</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>FLASH</name>
+ <description>FLASH</description>
+ <groupName>FLASH</groupName>
+ <baseAddress>0x40023C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>FLASH</name>
+ <description>FLASH global interrupt</description>
+ <value>4</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>ACR</name>
+ <displayName>ACR</displayName>
+ <description>Flash access control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LATENCY</name>
+ <description>Latency</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PRFTEN</name>
+ <description>Prefetch enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ICEN</name>
+ <description>Instruction cache enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DCEN</name>
+ <description>Data cache enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ICRST</name>
+ <description>Instruction cache reset</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>DCRST</name>
+ <description>Data cache reset</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>KEYR</name>
+ <displayName>KEYR</displayName>
+ <description>Flash key register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>KEY</name>
+ <description>FPEC key</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OPTKEYR</name>
+ <displayName>OPTKEYR</displayName>
+ <description>Flash option key register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OPTKEY</name>
+ <description>Option byte key</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>Status register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EOP</name>
+ <description>End of operation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>OPERR</name>
+ <description>Operation error</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>WRPERR</name>
+ <description>Write protection error</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PGAERR</name>
+ <description>Programming alignment
+ error</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PGPERR</name>
+ <description>Programming parallelism
+ error</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PGSERR</name>
+ <description>Programming sequence error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BSY</name>
+ <description>Busy</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>Control register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x80000000</resetValue>
+ <fields>
+ <field>
+ <name>PG</name>
+ <description>Programming</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SER</name>
+ <description>Sector Erase</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MER</name>
+ <description>Mass Erase</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SNB</name>
+ <description>Sector number</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Program size</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>STRT</name>
+ <description>Start</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EOPIE</name>
+ <description>End of operation interrupt
+ enable</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRIE</name>
+ <description>Error interrupt enable</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OPTCR</name>
+ <displayName>OPTCR</displayName>
+ <description>Flash option control register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000014</resetValue>
+ <fields>
+ <field>
+ <name>OPTLOCK</name>
+ <description>Option lock</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPTSTRT</name>
+ <description>Option start</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BOR_LEV</name>
+ <description>BOR reset Level</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>WDG_SW</name>
+ <description>WDG_SW User option bytes</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>nRST_STOP</name>
+ <description>nRST_STOP User option
+ bytes</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>nRST_STDBY</name>
+ <description>nRST_STDBY User option
+ bytes</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RDP</name>
+ <description>Read protect</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>nWRP</name>
+ <description>Not write protect</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>IWDG</name>
+ <description>Independent watchdog</description>
+ <groupName>IWDG</groupName>
+ <baseAddress>0x40003000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>KR</name>
+ <displayName>KR</displayName>
+ <description>Key register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>KEY</name>
+ <description>Key value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PR</name>
+ <displayName>PR</displayName>
+ <description>Prescaler register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PR</name>
+ <description>Prescaler divider</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RLR</name>
+ <displayName>RLR</displayName>
+ <description>Reload register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000FFF</resetValue>
+ <fields>
+ <field>
+ <name>RL</name>
+ <description>Watchdog counter reload
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>Status register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RVU</name>
+ <description>Watchdog counter reload value
+ update</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PVU</name>
+ <description>Watchdog prescaler value
+ update</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>PWR</name>
+ <description>Power control</description>
+ <groupName>PWR</groupName>
+ <baseAddress>0x40007000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>PVD</name>
+ <description>PVD through EXTI line detection
+ interrupt</description>
+ <value>1</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>power control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>VOS</name>
+ <description>Regulator voltage scaling output
+ selection</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ADCDC1</name>
+ <description>ADCDC1</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FPDS</name>
+ <description>Flash power down in Stop
+ mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBP</name>
+ <description>Disable backup domain write
+ protection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLS</name>
+ <description>PVD level selection</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>PVDE</name>
+ <description>Power voltage detector
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CSBF</name>
+ <description>Clear standby flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CWUF</name>
+ <description>Clear wakeup flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PDDS</name>
+ <description>Power down deepsleep</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LPDS</name>
+ <description>Low-power deep sleep</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CSR</name>
+ <displayName>CSR</displayName>
+ <description>power control/status register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>WUF</name>
+ <description>Wakeup flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SBF</name>
+ <description>Standby flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PVDO</name>
+ <description>PVD output</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BRR</name>
+ <description>Backup regulator ready</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EWUP</name>
+ <description>Enable WKUP pin</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BRE</name>
+ <description>Backup regulator enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>VOSRDY</name>
+ <description>Regulator voltage scaling output
+ selection ready bit</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>RCC</name>
+ <description>Reset and clock control</description>
+ <groupName>RCC</groupName>
+ <baseAddress>0x40023800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>RCC</name>
+ <description>RCC global interrupt</description>
+ <value>5</value>
+ </interrupt>
+ <interrupt>
+ <name>FPU</name>
+ <description>FPU global interrupt</description>
+ <value>81</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>clock control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000083</resetValue>
+ <fields>
+ <field>
+ <name>HSION</name>
+ <description>Internal high-speed clock
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HSIRDY</name>
+ <description>Internal high-speed clock ready
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HSITRIM</name>
+ <description>Internal high-speed clock
+ trimming</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>HSICAL</name>
+ <description>Internal high-speed clock
+ calibration</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>HSEON</name>
+ <description>HSE clock enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HSERDY</name>
+ <description>HSE clock ready flag</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HSEBYP</name>
+ <description>HSE clock bypass</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CSSON</name>
+ <description>Clock security system
+ enable</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLON</name>
+ <description>Main PLL (PLL) enable</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLRDY</name>
+ <description>Main PLL (PLL) clock ready
+ flag</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLI2SON</name>
+ <description>PLLI2S enable</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLI2SRDY</name>
+ <description>PLLI2S clock ready flag</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLLCFGR</name>
+ <displayName>PLLCFGR</displayName>
+ <description>PLL configuration register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x24003010</resetValue>
+ <fields>
+ <field>
+ <name>PLLQ3</name>
+ <description>Main PLL (PLL) division factor for USB
+ OTG FS, SDIO and random number generator
+ clocks</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLQ2</name>
+ <description>Main PLL (PLL) division factor for USB
+ OTG FS, SDIO and random number generator
+ clocks</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLQ1</name>
+ <description>Main PLL (PLL) division factor for USB
+ OTG FS, SDIO and random number generator
+ clocks</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLQ0</name>
+ <description>Main PLL (PLL) division factor for USB
+ OTG FS, SDIO and random number generator
+ clocks</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLSRC</name>
+ <description>Main PLL(PLL) and audio PLL (PLLI2S)
+ entry clock source</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLP1</name>
+ <description>Main PLL (PLL) division factor for main
+ system clock</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLP0</name>
+ <description>Main PLL (PLL) division factor for main
+ system clock</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN8</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN7</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN6</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN5</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN4</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN3</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN2</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN1</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLN0</name>
+ <description>Main PLL (PLL) multiplication factor for
+ VCO</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLM5</name>
+ <description>Division factor for the main PLL (PLL)
+ and audio PLL (PLLI2S) input clock</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLM4</name>
+ <description>Division factor for the main PLL (PLL)
+ and audio PLL (PLLI2S) input clock</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLM3</name>
+ <description>Division factor for the main PLL (PLL)
+ and audio PLL (PLLI2S) input clock</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLM2</name>
+ <description>Division factor for the main PLL (PLL)
+ and audio PLL (PLLI2S) input clock</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLM1</name>
+ <description>Division factor for the main PLL (PLL)
+ and audio PLL (PLLI2S) input clock</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLM0</name>
+ <description>Division factor for the main PLL (PLL)
+ and audio PLL (PLLI2S) input clock</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLR</name>
+ <description>Main PLL (PLL) division factor for I2S,
+ DFSDM clocks</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CFGR</name>
+ <displayName>CFGR</displayName>
+ <description>clock configuration register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MCO2</name>
+ <description>Microcontroller clock output
+ 2</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MCO2PRE</name>
+ <description>MCO2 prescaler</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MCO1PRE</name>
+ <description>MCO1 prescaler</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MCO1</name>
+ <description>Microcontroller clock output
+ 1</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RTCPRE</name>
+ <description>HSE division factor for RTC
+ clock</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PPRE2</name>
+ <description>APB high-speed prescaler
+ (APB2)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PPRE1</name>
+ <description>APB Low speed prescaler
+ (APB1)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HPRE</name>
+ <description>AHB prescaler</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SWS1</name>
+ <description>System clock switch status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SWS0</name>
+ <description>System clock switch status</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SW1</name>
+ <description>System clock switch</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SW0</name>
+ <description>System clock switch</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CIR</name>
+ <displayName>CIR</displayName>
+ <description>clock interrupt register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CSSC</name>
+ <description>Clock security system interrupt
+ clear</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>PLLI2SRDYC</name>
+ <description>PLLI2S ready interrupt
+ clear</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>PLLRDYC</name>
+ <description>Main PLL(PLL) ready interrupt
+ clear</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>HSERDYC</name>
+ <description>HSE ready interrupt clear</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>HSIRDYC</name>
+ <description>HSI ready interrupt clear</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>LSERDYC</name>
+ <description>LSE ready interrupt clear</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>LSIRDYC</name>
+ <description>LSI ready interrupt clear</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>PLLI2SRDYIE</name>
+ <description>PLLI2S ready interrupt
+ enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PLLRDYIE</name>
+ <description>Main PLL (PLL) ready interrupt
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HSERDYIE</name>
+ <description>HSE ready interrupt enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HSIRDYIE</name>
+ <description>HSI ready interrupt enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LSERDYIE</name>
+ <description>LSE ready interrupt enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LSIRDYIE</name>
+ <description>LSI ready interrupt enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CSSF</name>
+ <description>Clock security system interrupt
+ flag</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PLLI2SRDYF</name>
+ <description>PLLI2S ready interrupt
+ flag</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PLLRDYF</name>
+ <description>Main PLL (PLL) ready interrupt
+ flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>HSERDYF</name>
+ <description>HSE ready interrupt flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>HSIRDYF</name>
+ <description>HSI ready interrupt flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>LSERDYF</name>
+ <description>LSE ready interrupt flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>LSIRDYF</name>
+ <description>LSI ready interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB1RSTR</name>
+ <displayName>AHB1RSTR</displayName>
+ <description>AHB1 peripheral reset register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>GPIOARST</name>
+ <description>IO port A reset</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOBRST</name>
+ <description>IO port B reset</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOCRST</name>
+ <description>IO port C reset</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIODRST</name>
+ <description>IO port D reset</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOERST</name>
+ <description>IO port E reset</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOFRST</name>
+ <description>IO port F reset</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOGRST</name>
+ <description>IO port G reset</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOHRST</name>
+ <description>IO port H reset</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CRCRST</name>
+ <description>CRC reset</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMA1RST</name>
+ <description>DMA2 reset</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMA2RST</name>
+ <description>DMA2 reset</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB2RSTR</name>
+ <displayName>AHB2RSTR</displayName>
+ <description>AHB2 peripheral reset register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OTGFSRST</name>
+ <description>USB OTG FS module reset</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RNGRST</name>
+ <description>RNGRST</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CRYPRST</name>
+ <description>CRYP module reset</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>APB1RSTR</name>
+ <displayName>APB1RSTR</displayName>
+ <description>APB1 peripheral reset register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIM2RST</name>
+ <description>TIM2 reset</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM3RST</name>
+ <description>TIM3 reset</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM4RST</name>
+ <description>TIM4 reset</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM5RST</name>
+ <description>TIM5 reset</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM6RST</name>
+ <description>TIM6RST</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM7RST</name>
+ <description>TIM7RST</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM12RST</name>
+ <description>TIM12RST</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM13RST</name>
+ <description>TIM13RST</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM14RST</name>
+ <description>TIM14RST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WWDGRST</name>
+ <description>Window watchdog reset</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI2RST</name>
+ <description>SPI 2 reset</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI3RST</name>
+ <description>SPI 3 reset</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART2RST</name>
+ <description>USART 2 reset</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART3RST</name>
+ <description>USART3RST</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C1RST</name>
+ <description>I2C 1 reset</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C2RST</name>
+ <description>I2C 2 reset</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C3RST</name>
+ <description>I2C3 reset</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C4RST</name>
+ <description>I2C4RST</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN1RST</name>
+ <description>CAN1RST</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN2RST</name>
+ <description>CAN2RST</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWRRST</name>
+ <description>Power interface reset</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LPTIMER1RST</name>
+ <description>LPTimer1 reset</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART4RST</name>
+ <description>USART4 reset</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART5RST</name>
+ <description>USART5 reset</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN3RST</name>
+ <description>CAN 3 reset</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DACRST</name>
+ <description>DAC reset</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART7RST</name>
+ <description>UART 7 reset</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART8RST</name>
+ <description>UART 8 reset</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>APB2RSTR</name>
+ <displayName>APB2RSTR</displayName>
+ <description>APB2 peripheral reset register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIM1RST</name>
+ <description>TIM1 reset</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM8RST</name>
+ <description>TIM8RST</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART1RST</name>
+ <description>USART1 reset</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART6RST</name>
+ <description>USART6 reset</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADCRST</name>
+ <description>ADC interface reset (common to all
+ ADCs)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDIORST</name>
+ <description>SDIO reset</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI1RST</name>
+ <description>SPI 1 reset</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYSCFGRST</name>
+ <description>System configuration controller
+ reset</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM9RST</name>
+ <description>TIM9 reset</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM10RST</name>
+ <description>TIM10 reset</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM11RST</name>
+ <description>TIM11 reset</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFSDMRST</name>
+ <description>DFSDMRST</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART9RST</name>
+ <description>USART9 reset</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SART10RST</name>
+ <description>USART10 reset</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI4RST</name>
+ <description>SPI4 reset</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI5RST</name>
+ <description>SPI5RST</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SAI1RST</name>
+ <description>SAI1 reset</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFSDM2RST</name>
+ <description>DFSDM2 reset</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB1ENR</name>
+ <displayName>AHB1ENR</displayName>
+ <description>AHB1 peripheral clock register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00100000</resetValue>
+ <fields>
+ <field>
+ <name>GPIOAEN</name>
+ <description>IO port A clock enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOBEN</name>
+ <description>IO port B clock enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOCEN</name>
+ <description>IO port C clock enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIODEN</name>
+ <description>IO port D clock enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOEEN</name>
+ <description>IO port E clock enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOFEN</name>
+ <description>IO port F clock enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOGEN</name>
+ <description>IO port G clock enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOHEN</name>
+ <description>IO port H clock enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CRCEN</name>
+ <description>CRC clock enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMA1EN</name>
+ <description>DMA1 clock enable</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMA2EN</name>
+ <description>DMA2 clock enable</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB2ENR</name>
+ <displayName>AHB2ENR</displayName>
+ <description>AHB2 peripheral clock enable
+ register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OTGFSEN</name>
+ <description>USB OTG FS clock enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RNGEN</name>
+ <description>RNGEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CRYPEN</name>
+ <description>CRYP clock enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>APB1ENR</name>
+ <displayName>APB1ENR</displayName>
+ <description>APB1 peripheral clock enable
+ register</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIM2EN</name>
+ <description>TIM2 clock enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM3EN</name>
+ <description>TIM3 clock enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM4EN</name>
+ <description>TIM4 clock enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM5EN</name>
+ <description>TIM5 clock enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM6EN</name>
+ <description>TIM6EN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM7EN</name>
+ <description>TIM7EN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM12EN</name>
+ <description>TIM12EN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM13EN</name>
+ <description>TIM13EN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM14EN</name>
+ <description>TIM14EN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WWDGEN</name>
+ <description>Window watchdog clock
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI2EN</name>
+ <description>SPI2 clock enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI3EN</name>
+ <description>SPI3 clock enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART2EN</name>
+ <description>USART 2 clock enable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART3EN</name>
+ <description>USART3EN</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C1EN</name>
+ <description>I2C1 clock enable</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C2EN</name>
+ <description>I2C2 clock enable</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C3EN</name>
+ <description>I2C3 clock enable</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C4EN</name>
+ <description>I2C4EN</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN1EN</name>
+ <description>CAN1EN</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN2EN</name>
+ <description>CAN2EN</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWREN</name>
+ <description>Power interface clock
+ enable</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LPTIMER1EN</name>
+ <description>LPTimer 1 clock enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTCAPB</name>
+ <description>clock enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART4EN</name>
+ <description>UART 4 clock enable</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART5EN</name>
+ <description>UART 5 clock enable</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN3EN</name>
+ <description>CAN 3 clock enable</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DACEN</name>
+ <description>DAC clock enable</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART7EN</name>
+ <description>UART7 clock enable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART8EN</name>
+ <description>UART8 clock enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>APB2ENR</name>
+ <displayName>APB2ENR</displayName>
+ <description>APB2 peripheral clock enable
+ register</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIM1EN</name>
+ <description>TIM1 clock enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM8EN</name>
+ <description>TIM8EN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART1EN</name>
+ <description>USART1 clock enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART6EN</name>
+ <description>USART6 clock enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADC1EN</name>
+ <description>ADC1 clock enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDIOEN</name>
+ <description>SDIO clock enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI1EN</name>
+ <description>SPI1 clock enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI4EN</name>
+ <description>SPI4 clock enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYSCFGEN</name>
+ <description>System configuration controller clock
+ enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM9EN</name>
+ <description>TIM9 clock enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM10EN</name>
+ <description>TIM10 clock enable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM11EN</name>
+ <description>TIM11 clock enable</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFSDMEN</name>
+ <description>DFSDMEN</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI5EN</name>
+ <description>SPI5 clock enable</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SAI1EN</name>
+ <description>SAI 1 clock enable</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFSDM2EN</name>
+ <description>DFSDM2 clock enable</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB1LPENR</name>
+ <displayName>AHB1LPENR</displayName>
+ <description>AHB1 peripheral clock enable in low power
+ mode register</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x7E6791FF</resetValue>
+ <fields>
+ <field>
+ <name>GPIOALPEN</name>
+ <description>IO port A clock enable during sleep
+ mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOBLPEN</name>
+ <description>IO port B clock enable during Sleep
+ mode</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOCLPEN</name>
+ <description>IO port C clock enable during Sleep
+ mode</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIODLPEN</name>
+ <description>IO port D clock enable during Sleep
+ mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOELPEN</name>
+ <description>IO port E clock enable during Sleep
+ mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOFLPEN</name>
+ <description>IO port F clock enable during sleep
+ mode</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOGLPEN</name>
+ <description>IO port G clock enable during sleep
+ mode</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPIOHLPEN</name>
+ <description>IO port H clock enable during Sleep
+ mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CRCLPEN</name>
+ <description>CRC clock enable during Sleep
+ mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FLITFLPEN</name>
+ <description>Flash interface clock enable during
+ Sleep mode</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SRAM1LPEN</name>
+ <description>SRAM 1interface clock enable during
+ Sleep mode</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMA1LPEN</name>
+ <description>DMA1 clock enable during Sleep
+ mode</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMA2LPEN</name>
+ <description>DMA2 clock enable during Sleep
+ mode</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SRAM2LPEN</name>
+ <description>SRAM2interface clock enable during Sleep
+ mode</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB2LPENR</name>
+ <displayName>AHB2LPENR</displayName>
+ <description>AHB2 peripheral clock enable in low power
+ mode register</description>
+ <addressOffset>0x54</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000000F1</resetValue>
+ <fields>
+ <field>
+ <name>OTGFSLPEN</name>
+ <description>USB OTG FS clock enable during Sleep
+ mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RNGLPEN</name>
+ <description>RNGLPEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSMCLPEN</name>
+ <description>Flexible memory controller module clock
+ enable during Sleep mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>QSPILPEN</name>
+ <description>QUADSPI memory controller module clock
+ enable during Sleep mode</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>APB1LPENR</name>
+ <displayName>APB1LPENR</displayName>
+ <description>APB1 peripheral clock enable in low power
+ mode register</description>
+ <addressOffset>0x60</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x36FEC9FF</resetValue>
+ <fields>
+ <field>
+ <name>TIM2LPEN</name>
+ <description>TIM2 clock enable during Sleep
+ mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM3LPEN</name>
+ <description>TIM3 clock enable during Sleep
+ mode</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM4LPEN</name>
+ <description>TIM4 clock enable during Sleep
+ mode</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM5LPEN</name>
+ <description>TIM5 clock enable during Sleep
+ mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM6LPEN</name>
+ <description>TIM6LPEN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM7LPEN</name>
+ <description>TIM7LPEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM12LPEN</name>
+ <description>TIM12LPEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM13LPEN</name>
+ <description>TIM13LPEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM14LPEN</name>
+ <description>TIM14LPEN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WWDGLPEN</name>
+ <description>Window watchdog clock enable during
+ Sleep mode</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI2LPEN</name>
+ <description>SPI2 clock enable during Sleep
+ mode</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI3LPEN</name>
+ <description>SPI3 clock enable during Sleep
+ mode</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART2LPEN</name>
+ <description>USART2 clock enable during Sleep
+ mode</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART3LPEN</name>
+ <description>USART3LPEN</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C1LPEN</name>
+ <description>I2C1 clock enable during Sleep
+ mode</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C2LPEN</name>
+ <description>I2C2 clock enable during Sleep
+ mode</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C3LPEN</name>
+ <description>I2C3 clock enable during Sleep
+ mode</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C4LPEN</name>
+ <description>I2C4LPEN</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN1LPEN</name>
+ <description>CAN1LPEN</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN2LPEN</name>
+ <description>CAN2LPEN</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWRLPEN</name>
+ <description>Power interface clock enable during
+ Sleep mode</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LPTIMER1LPEN</name>
+ <description>TIM14 clock enable during Sleep
+ mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTCAPBEN</name>
+ <description>RTC APB clock enable during Sleep
+ mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART4LPEN</name>
+ <description>USART4 clock enable during Sleep
+ mode</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART5LPEN</name>
+ <description>USART5 clock enable during Sleep
+ mode</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAN3LPEN</name>
+ <description>CAN3 clock enable during Sleep
+ mode</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DACLPEN</name>
+ <description>DAC clock enable during Sleep
+ mode</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART7LPEN</name>
+ <description>UART7 clock enable during Sleep
+ mode</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UART8LPEN</name>
+ <description>UART8 clock enable during Sleep
+ mode</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>APB2LPENR</name>
+ <displayName>APB2LPENR</displayName>
+ <description>APB2 peripheral clock enabled in low power
+ mode register</description>
+ <addressOffset>0x64</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00075F33</resetValue>
+ <fields>
+ <field>
+ <name>TIM1LPEN</name>
+ <description>TIM1 clock enable during Sleep
+ mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM8LPEN</name>
+ <description>TIM8LPEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART1LPEN</name>
+ <description>USART1 clock enable during Sleep
+ mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART6LPEN</name>
+ <description>USART6 clock enable during Sleep
+ mode</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADC1LPEN</name>
+ <description>ADC1 clock enable during Sleep
+ mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDIOLPEN</name>
+ <description>SDIO clock enable during Sleep
+ mode</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI1LPEN</name>
+ <description>SPI 1 clock enable during Sleep
+ mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI4LPEN</name>
+ <description>SPI4 clock enable during Sleep
+ mode</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYSCFGLPEN</name>
+ <description>System configuration controller clock
+ enable during Sleep mode</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM9LPEN</name>
+ <description>TIM9 clock enable during sleep
+ mode</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM10LPEN</name>
+ <description>TIM10 clock enable during Sleep
+ mode</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIM11LPEN</name>
+ <description>TIM11 clock enable during Sleep
+ mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFSDMLPEN</name>
+ <description>DFSDMLPEN</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART9LPEN</name>
+ <description>USART9 clock enable during Sleep
+ mode</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>USART10LPEN</name>
+ <description>USART10 clock enable during Sleep
+ mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTITEN</name>
+ <description>EXTIT APB and SYSCTRL PFREE clock enable
+ during Sleep mode</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPI5LPEN</name>
+ <description>SPI5 clock enable during Sleep
+ mode</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SAI1LPEN</name>
+ <description>SAI1 clock enable during Sleep
+ mode</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFSDM2LPEN</name>
+ <description>DFSDM2 clock enable during Sleep
+ mode</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDCR</name>
+ <displayName>BDCR</displayName>
+ <description>Backup domain control register</description>
+ <addressOffset>0x70</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BDRST</name>
+ <description>Backup domain software
+ reset</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RTCEN</name>
+ <description>RTC clock enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RTCSEL1</name>
+ <description>RTC clock source selection</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RTCSEL0</name>
+ <description>RTC clock source selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LSEBYP</name>
+ <description>External low-speed oscillator
+ bypass</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LSERDY</name>
+ <description>External low-speed oscillator
+ ready</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>LSEON</name>
+ <description>External low-speed oscillator
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LSEMOD</name>
+ <description>External low-speed oscillator
+ bypass</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CSR</name>
+ <displayName>CSR</displayName>
+ <description>clock control & status
+ register</description>
+ <addressOffset>0x74</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x0E000000</resetValue>
+ <fields>
+ <field>
+ <name>LPWRRSTF</name>
+ <description>Low-power reset flag</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>WWDGRSTF</name>
+ <description>Window watchdog reset flag</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>WDGRSTF</name>
+ <description>Independent watchdog reset
+ flag</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SFTRSTF</name>
+ <description>Software reset flag</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PORRSTF</name>
+ <description>POR/PDR reset flag</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PADRSTF</name>
+ <description>PIN reset flag</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BORRSTF</name>
+ <description>BOR reset flag</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RMVF</name>
+ <description>Remove reset flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LSIRDY</name>
+ <description>Internal low-speed oscillator
+ ready</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>LSION</name>
+ <description>Internal low-speed oscillator
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SSCGR</name>
+ <displayName>SSCGR</displayName>
+ <description>spread spectrum clock generation
+ register</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SSCGEN</name>
+ <description>Spread spectrum modulation
+ enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPREADSEL</name>
+ <description>Spread Select</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>INCSTEP</name>
+ <description>Incrementation step</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>15</bitWidth>
+ </field>
+ <field>
+ <name>MODPER</name>
+ <description>Modulation period</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>13</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLLI2SCFGR</name>
+ <displayName>PLLI2SCFGR</displayName>
+ <description>PLLI2S configuration register</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x20003000</resetValue>
+ <fields>
+ <field>
+ <name>PLLI2SR</name>
+ <description>PLLI2S division factor for I2S
+ clocks</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>PLLI2SN</name>
+ <description>PLLI2S multiplication factor for
+ VCO</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>9</bitWidth>
+ </field>
+ <field>
+ <name>PLLI2SM</name>
+ <description>Division factor for the main PLL (PLL)
+ and audio PLL (PLLI2S) input clock</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ <field>
+ <name>PLLI2SSRC</name>
+ <description>PLLI2S entry clock source</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PLLI2SQ</name>
+ <description>PLLI2S division factor for USB OTG
+ FS/SDIO/RNG clock</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB3RSTR</name>
+ <displayName>AHB3RSTR</displayName>
+ <description>peripheral reset register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FSMCRST</name>
+ <description>Flexible memory controller module
+ reset</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>QSPIRST</name>
+ <description>QUADSPI module reset</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB3ENR</name>
+ <displayName>AHB3ENR</displayName>
+ <description>AHB3 peripheral clock enable
+ register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FSMCEN</name>
+ <description>Flexible memory controller module clock
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>QSPIEN</name>
+ <description>QUADSPI memory controller module clock
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHB3LPENR</name>
+ <displayName>AHB3LPENR</displayName>
+ <description>AHB3 peripheral clock enable in low power
+ mode register</description>
+ <addressOffset>0x58</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000003</resetValue>
+ <fields>
+ <field>
+ <name>FSMCLPEN</name>
+ <description>Flexible memory controller module clock
+ enable during Sleep mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>QSPILPEN</name>
+ <description>QUADSPI memory controller module clock
+ enable during Sleep mode</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCKCFGR</name>
+ <displayName>DCKCFGR</displayName>
+ <description>Dedicated Clocks Configuration
+ Register</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CKDFSDM1ASEL</name>
+ <description>DFSDM1 audio clock
+ selection.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMPRE</name>
+ <description>Timers clocks prescalers
+ selection</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2S1SRC</name>
+ <description>I2S APB1 clocks source selection
+ (I2S2/3)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>I2S2SRC</name>
+ <description>I2S APB2 clocks source selection
+ (I2S1/4/5)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>LPTIMER1SEL</name>
+ <description>LPTIMER1 kernel clock
+ selection.</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CKGATENR</name>
+ <displayName>CKGATENR</displayName>
+ <description>RCC clocks gated enable
+ register</description>
+ <addressOffset>0x90</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AHB2APB1_CKEN</name>
+ <description>AHB to APB1 Bridge clock
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AHB2APB2_CKEN</name>
+ <description>AHB to APB2 Bridge clock
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CM4DBG_CKEN</name>
+ <description>Cortex M4 ETM clock enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPARE_CKEN</name>
+ <description>Spare clock enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SRAM_CKEN</name>
+ <description>SRQAM controller clock
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FLITF_CKEN</name>
+ <description>Flash Interface clock
+ enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCC_CKEN</name>
+ <description>RCC clock enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EVTCL_CKEN</name>
+ <description>EVTCL_CKEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCKCFGR2</name>
+ <displayName>DCKCFGR2</displayName>
+ <description>Dedicated Clocks Configuration
+ Register</description>
+ <addressOffset>0x94</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CKSDIOSEL</name>
+ <description>SDIO clock selection.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CK48MSEL</name>
+ <description>SDIO/USBFS clock
+ selection.</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2CFMP1SEL</name>
+ <description>I2CFMP1 kernel clock source
+ selection</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>RTC</name>
+ <description>Real-time clock</description>
+ <groupName>RTC</groupName>
+ <baseAddress>0x40002800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>RTC_WKUP</name>
+ <description>RTC Wakeup interrupt through the EXTI
+ line</description>
+ <value>3</value>
+ </interrupt>
+ <interrupt>
+ <name>EXTI17_RTC_Alarm</name>
+ <description>RTC Alarms (A and B) through EXTI line
+ interrupt</description>
+ <value>41</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>TR</name>
+ <displayName>TR</displayName>
+ <description>time register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PM</name>
+ <description>AM/PM notation</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HT</name>
+ <description>Hour tens in BCD format</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>HU</name>
+ <description>Hour units in BCD format</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MNT</name>
+ <description>Minute tens in BCD format</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MNU</name>
+ <description>Minute units in BCD format</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ST</name>
+ <description>Second tens in BCD format</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SU</name>
+ <description>Second units in BCD format</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>date register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00002101</resetValue>
+ <fields>
+ <field>
+ <name>YT</name>
+ <description>Year tens in BCD format</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>YU</name>
+ <description>Year units in BCD format</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>WDU</name>
+ <description>Week day units</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MT</name>
+ <description>Month tens in BCD format</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MU</name>
+ <description>Month units in BCD format</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DT</name>
+ <description>Date tens in BCD format</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DU</name>
+ <description>Date units in BCD format</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>COE</name>
+ <description>Calibration output enable</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OSEL</name>
+ <description>Output selection</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>POL</name>
+ <description>Output polarity</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>COSEL</name>
+ <description>Calibration Output
+ selection</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BKP</name>
+ <description>Backup</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SUB1H</name>
+ <description>Subtract 1 hour (winter time
+ change)</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADD1H</name>
+ <description>Add 1 hour (summer time
+ change)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TSIE</name>
+ <description>Time-stamp interrupt
+ enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WUTIE</name>
+ <description>Wakeup timer interrupt
+ enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALRBIE</name>
+ <description>Alarm B interrupt enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALRAIE</name>
+ <description>Alarm A interrupt enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TSE</name>
+ <description>Time stamp enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WUTE</name>
+ <description>Wakeup timer enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALRBE</name>
+ <description>Alarm B enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALRAE</name>
+ <description>Alarm A enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DCE</name>
+ <description>Coarse digital calibration
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FMT</name>
+ <description>Hour format</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BYPSHAD</name>
+ <description>Bypass the shadow
+ registers</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REFCKON</name>
+ <description>Reference clock detection enable (50 or
+ 60 Hz)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TSEDGE</name>
+ <description>Time-stamp event active
+ edge</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WCKSEL</name>
+ <description>Wakeup clock selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISR</name>
+ <displayName>ISR</displayName>
+ <description>initialization and status
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000007</resetValue>
+ <fields>
+ <field>
+ <name>ALRAWF</name>
+ <description>Alarm A write flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ALRBWF</name>
+ <description>Alarm B write flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>WUTWF</name>
+ <description>Wakeup timer write flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SHPF</name>
+ <description>Shift operation pending</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>INITS</name>
+ <description>Initialization status flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>RSF</name>
+ <description>Registers synchronization
+ flag</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>INITF</name>
+ <description>Initialization flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>INIT</name>
+ <description>Initialization mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ALRAF</name>
+ <description>Alarm A flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ALRBF</name>
+ <description>Alarm B flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>WUTF</name>
+ <description>Wakeup timer flag</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TSF</name>
+ <description>Time-stamp flag</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TSOVF</name>
+ <description>Time-stamp overflow flag</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TAMP1F</name>
+ <description>Tamper detection flag</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TAMP2F</name>
+ <description>TAMPER2 detection flag</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RECALPF</name>
+ <description>Recalibration pending Flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRER</name>
+ <displayName>PRER</displayName>
+ <description>prescaler register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x007F00FF</resetValue>
+ <fields>
+ <field>
+ <name>PREDIV_A</name>
+ <description>Asynchronous prescaler
+ factor</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>PREDIV_S</name>
+ <description>Synchronous prescaler
+ factor</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>15</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>WUTR</name>
+ <displayName>WUTR</displayName>
+ <description>wakeup timer register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000FFFF</resetValue>
+ <fields>
+ <field>
+ <name>WUT</name>
+ <description>Wakeup auto-reload value
+ bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIBR</name>
+ <displayName>CALIBR</displayName>
+ <description>calibration register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DCS</name>
+ <description>Digital calibration sign</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DC</name>
+ <description>Digital calibration</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ALRMAR</name>
+ <displayName>ALRMAR</displayName>
+ <description>alarm A register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MSK4</name>
+ <description>Alarm A date mask</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WDSEL</name>
+ <description>Week day selection</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DT</name>
+ <description>Date tens in BCD format</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DU</name>
+ <description>Date units or day in BCD
+ format</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSK3</name>
+ <description>Alarm A hours mask</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PM</name>
+ <description>AM/PM notation</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HT</name>
+ <description>Hour tens in BCD format</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>HU</name>
+ <description>Hour units in BCD format</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSK2</name>
+ <description>Alarm A minutes mask</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MNT</name>
+ <description>Minute tens in BCD format</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MNU</name>
+ <description>Minute units in BCD format</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSK1</name>
+ <description>Alarm A seconds mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ST</name>
+ <description>Second tens in BCD format</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SU</name>
+ <description>Second units in BCD format</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ALRMBR</name>
+ <displayName>ALRMBR</displayName>
+ <description>alarm B register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MSK4</name>
+ <description>Alarm B date mask</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WDSEL</name>
+ <description>Week day selection</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DT</name>
+ <description>Date tens in BCD format</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DU</name>
+ <description>Date units or day in BCD
+ format</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSK3</name>
+ <description>Alarm B hours mask</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PM</name>
+ <description>AM/PM notation</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HT</name>
+ <description>Hour tens in BCD format</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>HU</name>
+ <description>Hour units in BCD format</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSK2</name>
+ <description>Alarm B minutes mask</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MNT</name>
+ <description>Minute tens in BCD format</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MNU</name>
+ <description>Minute units in BCD format</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSK1</name>
+ <description>Alarm B seconds mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ST</name>
+ <description>Second tens in BCD format</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SU</name>
+ <description>Second units in BCD format</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>WPR</name>
+ <displayName>WPR</displayName>
+ <description>write protection register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>KEY</name>
+ <description>Write protection key</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SSR</name>
+ <displayName>SSR</displayName>
+ <description>sub second register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SS</name>
+ <description>Sub second value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SHIFTR</name>
+ <displayName>SHIFTR</displayName>
+ <description>shift control register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ADD1S</name>
+ <description>Add one second</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SUBFS</name>
+ <description>Subtract a fraction of a
+ second</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>15</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TSTR</name>
+ <displayName>TSTR</displayName>
+ <description>time stamp time register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PM</name>
+ <description>AM/PM notation</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HT</name>
+ <description>Hour tens in BCD format</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>HU</name>
+ <description>Hour units in BCD format</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MNT</name>
+ <description>Minute tens in BCD format</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MNU</name>
+ <description>Minute units in BCD format</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ST</name>
+ <description>Second tens in BCD format</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SU</name>
+ <description>Second units in BCD format</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TSDR</name>
+ <displayName>TSDR</displayName>
+ <description>time stamp date register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>WDU</name>
+ <description>Week day units</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MT</name>
+ <description>Month tens in BCD format</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MU</name>
+ <description>Month units in BCD format</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DT</name>
+ <description>Date tens in BCD format</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DU</name>
+ <description>Date units in BCD format</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TSSSR</name>
+ <displayName>TSSSR</displayName>
+ <description>timestamp sub second register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SS</name>
+ <description>Sub second value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALR</name>
+ <displayName>CALR</displayName>
+ <description>calibration register</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CALP</name>
+ <description>Increase frequency of RTC by 488.5
+ ppm</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CALW8</name>
+ <description>Use an 8-second calibration cycle
+ period</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CALW16</name>
+ <description>Use a 16-second calibration cycle
+ period</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CALM</name>
+ <description>Calibration minus</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>9</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TAFCR</name>
+ <displayName>TAFCR</displayName>
+ <description>tamper and alternate function configuration
+ register</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ALARMOUTTYPE</name>
+ <description>AFO_ALARM output type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TSINSEL</name>
+ <description>TIMESTAMP mapping</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMP1INSEL</name>
+ <description>TAMPER1 mapping</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMPPUDIS</name>
+ <description>TAMPER pull-up disable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMPPRCH</name>
+ <description>Tamper precharge duration</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>TAMPFLT</name>
+ <description>Tamper filter count</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>TAMPFREQ</name>
+ <description>Tamper sampling frequency</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TAMPTS</name>
+ <description>Activate timestamp on tamper detection
+ event</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMP2TRG</name>
+ <description>Active level for tamper 2</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMP2E</name>
+ <description>Tamper 2 detection enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMPIE</name>
+ <description>Tamper interrupt enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMP1TRG</name>
+ <description>Active level for tamper 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TAMP1E</name>
+ <description>Tamper 1 detection enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ALRMASSR</name>
+ <displayName>ALRMASSR</displayName>
+ <description>alarm A sub second register</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MASKSS</name>
+ <description>Mask the most-significant bits starting
+ at this bit</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SS</name>
+ <description>Sub seconds value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>15</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ALRMBSSR</name>
+ <displayName>ALRMBSSR</displayName>
+ <description>alarm B sub second register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MASKSS</name>
+ <description>Mask the most-significant bits starting
+ at this bit</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SS</name>
+ <description>Sub seconds value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>15</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP0R</name>
+ <displayName>BKP0R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP1R</name>
+ <displayName>BKP1R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x54</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP2R</name>
+ <displayName>BKP2R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x58</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP3R</name>
+ <displayName>BKP3R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x5C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP4R</name>
+ <displayName>BKP4R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x60</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP5R</name>
+ <displayName>BKP5R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x64</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP6R</name>
+ <displayName>BKP6R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x68</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP7R</name>
+ <displayName>BKP7R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x6C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP8R</name>
+ <displayName>BKP8R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x70</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP9R</name>
+ <displayName>BKP9R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x74</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP10R</name>
+ <displayName>BKP10R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x78</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP11R</name>
+ <displayName>BKP11R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x7C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP12R</name>
+ <displayName>BKP12R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP13R</name>
+ <displayName>BKP13R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP14R</name>
+ <displayName>BKP14R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x88</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP15R</name>
+ <displayName>BKP15R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP16R</name>
+ <displayName>BKP16R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x90</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP17R</name>
+ <displayName>BKP17R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x94</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP18R</name>
+ <displayName>BKP18R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x98</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BKP19R</name>
+ <displayName>BKP19R</displayName>
+ <description>backup register</description>
+ <addressOffset>0x9C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BKP</name>
+ <description>BKP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SDIO</name>
+ <description>Secure digital input/output
+ interface</description>
+ <groupName>SDIO</groupName>
+ <baseAddress>0x40012C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>SDIO</name>
+ <description>SDIO global interrupt</description>
+ <value>49</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>POWER</name>
+ <displayName>POWER</displayName>
+ <description>power control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PWRCTRL</name>
+ <description>PWRCTRL</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CLKCR</name>
+ <displayName>CLKCR</displayName>
+ <description>SDI clock control register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>HWFC_EN</name>
+ <description>HW Flow Control enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NEGEDGE</name>
+ <description>SDIO_CK dephasing selection
+ bit</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WIDBUS</name>
+ <description>Wide bus mode enable bit</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>BYPASS</name>
+ <description>Clock divider bypass enable
+ bit</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWRSAV</name>
+ <description>Power saving configuration
+ bit</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CLKEN</name>
+ <description>Clock enable bit</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>Clock divide factor</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARG</name>
+ <displayName>ARG</displayName>
+ <description>argument register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CMDARG</name>
+ <description>Command argument</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMD</name>
+ <displayName>CMD</displayName>
+ <description>command register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CE_ATACMD</name>
+ <description>CE-ATA command</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>nIEN</name>
+ <description>not Interrupt Enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ENCMDcompl</name>
+ <description>Enable CMD completion</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDIOSuspend</name>
+ <description>SD I/O suspend command</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPSMEN</name>
+ <description>Command path state machine (CPSM) Enable
+ bit</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPEND</name>
+ <description>CPSM Waits for ends of data transfer
+ (CmdPend internal signal).</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITINT</name>
+ <description>CPSM waits for interrupt
+ request</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITRESP</name>
+ <description>Wait for response bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CMDINDEX</name>
+ <description>Command index</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RESPCMD</name>
+ <displayName>RESPCMD</displayName>
+ <description>command response register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RESPCMD</name>
+ <description>Response command index</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RESP1</name>
+ <displayName>RESP1</displayName>
+ <description>response 1..4 register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CARDSTATUS1</name>
+ <description>Card Status</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RESP2</name>
+ <displayName>RESP2</displayName>
+ <description>response 1..4 register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CARDSTATUS2</name>
+ <description>Card Status</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RESP3</name>
+ <displayName>RESP3</displayName>
+ <description>response 1..4 register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CARDSTATUS3</name>
+ <description>Card Status</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RESP4</name>
+ <displayName>RESP4</displayName>
+ <description>response 1..4 register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CARDSTATUS4</name>
+ <description>Card Status</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DTIMER</name>
+ <displayName>DTIMER</displayName>
+ <description>data timer register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATATIME</name>
+ <description>Data timeout period</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DLEN</name>
+ <displayName>DLEN</displayName>
+ <description>data length register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATALENGTH</name>
+ <description>Data length value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>25</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCTRL</name>
+ <displayName>DCTRL</displayName>
+ <description>data control register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SDIOEN</name>
+ <description>SD I/O enable functions</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RWMOD</name>
+ <description>Read wait mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RWSTOP</name>
+ <description>Read wait stop</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RWSTART</name>
+ <description>Read wait start</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBLOCKSIZE</name>
+ <description>Data block size</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN</name>
+ <description>DMA enable bit</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTMODE</name>
+ <description>Data transfer mode selection 1: Stream
+ or SDIO multibyte data transfer.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTDIR</name>
+ <description>Data transfer direction
+ selection</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTEN</name>
+ <description>DTEN</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCOUNT</name>
+ <displayName>DCOUNT</displayName>
+ <description>data counter register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATACOUNT</name>
+ <description>Data count value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>25</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STA</name>
+ <displayName>STA</displayName>
+ <description>status register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CEATAEND</name>
+ <description>CE-ATA command completion signal
+ received for CMD61</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDIOIT</name>
+ <description>SDIO interrupt received</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXDAVL</name>
+ <description>Data available in receive
+ FIFO</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXDAVL</name>
+ <description>Data available in transmit
+ FIFO</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXFIFOE</name>
+ <description>Receive FIFO empty</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFIFOE</name>
+ <description>Transmit FIFO empty</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXFIFOF</name>
+ <description>Receive FIFO full</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFIFOF</name>
+ <description>Transmit FIFO full</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXFIFOHF</name>
+ <description>Receive FIFO half full: there are at
+ least 8 words in the FIFO</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFIFOHE</name>
+ <description>Transmit FIFO half empty: at least 8
+ words can be written into the FIFO</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXACT</name>
+ <description>Data receive in progress</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXACT</name>
+ <description>Data transmit in progress</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDACT</name>
+ <description>Command transfer in
+ progress</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBCKEND</name>
+ <description>Data block sent/received (CRC check
+ passed)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STBITERR</name>
+ <description>Start bit not detected on all data
+ signals in wide bus mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DATAEND</name>
+ <description>Data end (data counter, SDIDCOUNT, is
+ zero)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDSENT</name>
+ <description>Command sent (no response
+ required)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDREND</name>
+ <description>Command response received (CRC check
+ passed)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXOVERR</name>
+ <description>Received FIFO overrun
+ error</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXUNDERR</name>
+ <description>Transmit FIFO underrun
+ error</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTIMEOUT</name>
+ <description>Data timeout</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTIMEOUT</name>
+ <description>Command response timeout</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DCRCFAIL</name>
+ <description>Data block sent/received (CRC check
+ failed)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCRCFAIL</name>
+ <description>Command response received (CRC check
+ failed)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICR</name>
+ <displayName>ICR</displayName>
+ <description>interrupt clear register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CEATAENDC</name>
+ <description>CEATAEND flag clear bit</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDIOITC</name>
+ <description>SDIOIT flag clear bit</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBCKENDC</name>
+ <description>DBCKEND flag clear bit</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STBITERRC</name>
+ <description>STBITERR flag clear bit</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DATAENDC</name>
+ <description>DATAEND flag clear bit</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDSENTC</name>
+ <description>CMDSENT flag clear bit</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDRENDC</name>
+ <description>CMDREND flag clear bit</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXOVERRC</name>
+ <description>RXOVERR flag clear bit</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXUNDERRC</name>
+ <description>TXUNDERR flag clear bit</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTIMEOUTC</name>
+ <description>DTIMEOUT flag clear bit</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTIMEOUTC</name>
+ <description>CTIMEOUT flag clear bit</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DCRCFAILC</name>
+ <description>DCRCFAIL flag clear bit</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCRCFAILC</name>
+ <description>CCRCFAIL flag clear bit</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MASK</name>
+ <displayName>MASK</displayName>
+ <description>mask register</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CEATAENDIE</name>
+ <description>CE-ATA command completion signal
+ received interrupt enable</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDIOITIE</name>
+ <description>SDIO mode interrupt received interrupt
+ enable</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXDAVLIE</name>
+ <description>Data available in Rx FIFO interrupt
+ enable</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXDAVLIE</name>
+ <description>Data available in Tx FIFO interrupt
+ enable</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXFIFOEIE</name>
+ <description>Rx FIFO empty interrupt
+ enable</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFIFOEIE</name>
+ <description>Tx FIFO empty interrupt
+ enable</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXFIFOFIE</name>
+ <description>Rx FIFO full interrupt
+ enable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFIFOFIE</name>
+ <description>Tx FIFO full interrupt
+ enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXFIFOHFIE</name>
+ <description>Rx FIFO half full interrupt
+ enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFIFOHEIE</name>
+ <description>Tx FIFO half empty interrupt
+ enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXACTIE</name>
+ <description>Data receive acting interrupt
+ enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXACTIE</name>
+ <description>Data transmit acting interrupt
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDACTIE</name>
+ <description>Command acting interrupt
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBCKENDIE</name>
+ <description>Data block end interrupt
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STBITERRIE</name>
+ <description>Start bit error interrupt
+ enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DATAENDIE</name>
+ <description>Data end interrupt enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDSENTIE</name>
+ <description>Command sent interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMDRENDIE</name>
+ <description>Command response received interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXOVERRIE</name>
+ <description>Rx FIFO overrun error interrupt
+ enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXUNDERRIE</name>
+ <description>Tx FIFO underrun error interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTIMEOUTIE</name>
+ <description>Data timeout interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTIMEOUTIE</name>
+ <description>Command timeout interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DCRCFAILIE</name>
+ <description>Data CRC fail interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCRCFAILIE</name>
+ <description>Command CRC fail interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FIFOCNT</name>
+ <displayName>FIFOCNT</displayName>
+ <description>FIFO counter register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FIFOCOUNT</name>
+ <description>Remaining number of words to be written
+ to or read from the FIFO.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FIFO</name>
+ <displayName>FIFO</displayName>
+ <description>data FIFO register</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FIFOData</name>
+ <description>Receive and transmit FIFO
+ data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SYSCFG</name>
+ <description>System configuration controller</description>
+ <groupName>SYSCFG</groupName>
+ <baseAddress>0x40013800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>MEMRM</name>
+ <displayName>MEMRM</displayName>
+ <description>memory remap register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MEM_MODE</name>
+ <description>MEM_MODE</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PMC</name>
+ <displayName>PMC</displayName>
+ <description>peripheral mode configuration
+ register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ADC1DC2</name>
+ <description>ADC1DC2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EXTICR1</name>
+ <displayName>EXTICR1</displayName>
+ <description>external interrupt configuration register
+ 1</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>EXTI3</name>
+ <description>EXTI x configuration (x = 0 to
+ 3)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI2</name>
+ <description>EXTI x configuration (x = 0 to
+ 3)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI1</name>
+ <description>EXTI x configuration (x = 0 to
+ 3)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI0</name>
+ <description>EXTI x configuration (x = 0 to
+ 3)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EXTICR2</name>
+ <displayName>EXTICR2</displayName>
+ <description>external interrupt configuration register
+ 2</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>EXTI7</name>
+ <description>EXTI x configuration (x = 4 to
+ 7)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI6</name>
+ <description>EXTI x configuration (x = 4 to
+ 7)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI5</name>
+ <description>EXTI x configuration (x = 4 to
+ 7)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI4</name>
+ <description>EXTI x configuration (x = 4 to
+ 7)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EXTICR3</name>
+ <displayName>EXTICR3</displayName>
+ <description>external interrupt configuration register
+ 3</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>EXTI11</name>
+ <description>EXTI x configuration (x = 8 to
+ 11)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI10</name>
+ <description>EXTI10</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI9</name>
+ <description>EXTI x configuration (x = 8 to
+ 11)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI8</name>
+ <description>EXTI x configuration (x = 8 to
+ 11)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EXTICR4</name>
+ <displayName>EXTICR4</displayName>
+ <description>external interrupt configuration register
+ 4</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>EXTI15</name>
+ <description>EXTI x configuration (x = 12 to
+ 15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI14</name>
+ <description>EXTI x configuration (x = 12 to
+ 15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI13</name>
+ <description>EXTI x configuration (x = 12 to
+ 15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EXTI12</name>
+ <description>EXTI x configuration (x = 12 to
+ 15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMPCR</name>
+ <displayName>CMPCR</displayName>
+ <description>Compensation cell control
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>READY</name>
+ <description>READY</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMP_PD</name>
+ <description>Compensation cell
+ power-down</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_BUFOUT</name>
+ <displayName>I2C_BUFOUT</displayName>
+ <description>I2C_BUFOUT</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>I2C4SCL</name>
+ <description>I2C4SCL</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2C4SDA</name>
+ <description>I2C4SDA</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>TIM1</name>
+ <description>Advanced-timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40010000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM1_CC</name>
+ <description>TIM1 Capture Compare interrupt</description>
+ <value>27</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMS</name>
+ <description>Center-aligned mode
+ selection</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Direction</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPM</name>
+ <description>One-pulse mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>OIS4</name>
+ <description>Output Idle state 4</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OIS3N</name>
+ <description>Output Idle state 3</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OIS3</name>
+ <description>Output Idle state 3</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OIS2N</name>
+ <description>Output Idle state 2</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OIS2</name>
+ <description>Output Idle state 2</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OIS1N</name>
+ <description>Output Idle state 1</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OIS1</name>
+ <description>Output Idle state 1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TI1S</name>
+ <description>TI1 selection</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MMS</name>
+ <description>Master mode selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CCDS</name>
+ <description>Capture/compare DMA
+ selection</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCUS</name>
+ <description>Capture/compare control update
+ selection</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCPC</name>
+ <description>Capture/compare preloaded
+ control</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMCR</name>
+ <displayName>SMCR</displayName>
+ <description>slave mode control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ETP</name>
+ <description>External trigger polarity</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ECE</name>
+ <description>External clock enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ETPS</name>
+ <description>External trigger prescaler</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ETF</name>
+ <description>External trigger filter</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSM</name>
+ <description>Master/Slave mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TS</name>
+ <description>Trigger selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SMS</name>
+ <description>Slave mode selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TDE</name>
+ <description>Trigger DMA request enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>COMDE</name>
+ <description>COM DMA request enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4DE</name>
+ <description>Capture/Compare 4 DMA request
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3DE</name>
+ <description>Capture/Compare 3 DMA request
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2DE</name>
+ <description>Capture/Compare 2 DMA request
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1DE</name>
+ <description>Capture/Compare 1 DMA request
+ enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDE</name>
+ <description>Update DMA request enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BIE</name>
+ <description>Break interrupt enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIE</name>
+ <description>Trigger interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>COMIE</name>
+ <description>COM interrupt enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IE</name>
+ <description>Capture/Compare 4 interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IE</name>
+ <description>Capture/Compare 3 interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IE</name>
+ <description>Capture/Compare 2 interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4OF</name>
+ <description>Capture/Compare 4 overcapture
+ flag</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3OF</name>
+ <description>Capture/Compare 3 overcapture
+ flag</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2OF</name>
+ <description>Capture/compare 2 overcapture
+ flag</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BIF</name>
+ <description>Break interrupt flag</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIF</name>
+ <description>Trigger interrupt flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>COMIF</name>
+ <description>COM interrupt flag</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IF</name>
+ <description>Capture/Compare 4 interrupt
+ flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IF</name>
+ <description>Capture/Compare 3 interrupt
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IF</name>
+ <description>Capture/Compare 2 interrupt
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>BG</name>
+ <description>Break generation</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TG</name>
+ <description>Trigger generation</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>COMG</name>
+ <description>Capture/Compare control update
+ generation</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4G</name>
+ <description>Capture/compare 4
+ generation</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3G</name>
+ <description>Capture/compare 3
+ generation</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2G</name>
+ <description>Capture/compare 2
+ generation</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register 1 (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC2CE</name>
+ <description>Output Compare 2 clear
+ enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2M</name>
+ <description>Output Compare 2 mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC2PE</name>
+ <description>Output Compare 2 preload
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2FE</name>
+ <description>Output Compare 2 fast
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC1CE</name>
+ <description>Output Compare 1 clear
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1M</name>
+ <description>Output Compare 1 mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>Output Compare 1 preload
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>Output Compare 1 fast
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC2F</name>
+ <description>Input capture 2 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC2PCS</name>
+ <description>Input capture 2 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ICPCS</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Output</name>
+ <displayName>CCMR2_Output</displayName>
+ <description>capture/compare mode register 2 (output
+ mode)</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC4CE</name>
+ <description>Output compare 4 clear
+ enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4M</name>
+ <description>Output compare 4 mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC4PE</name>
+ <description>Output compare 4 preload
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4FE</name>
+ <description>Output compare 4 fast
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>Capture/Compare 4
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC3CE</name>
+ <description>Output compare 3 clear
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3M</name>
+ <description>Output compare 3 mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC3PE</name>
+ <description>Output compare 3 preload
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3FE</name>
+ <description>Output compare 3 fast
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>Capture/Compare 3
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Input</name>
+ <displayName>CCMR2_Input</displayName>
+ <description>capture/compare mode register 2 (input
+ mode)</description>
+ <alternateRegister>CCMR2_Output</alternateRegister>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC4F</name>
+ <description>Input capture 4 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC4PSC</name>
+ <description>Input capture 4 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>Capture/Compare 4
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC3F</name>
+ <description>Input capture 3 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC3PSC</name>
+ <description>Input capture 3 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>Capture/compare 3
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4E</name>
+ <description>Capture/Compare 4 output
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3NP</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3NE</name>
+ <description>Capture/Compare 3 complementary output
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3E</name>
+ <description>Capture/Compare 3 output
+ enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2NP</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2NE</name>
+ <description>Capture/Compare 2 complementary output
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2P</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2E</name>
+ <description>Capture/Compare 2 output
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1NE</name>
+ <description>Capture/Compare 1 complementary output
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1</name>
+ <description>Capture/Compare 1 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR2</name>
+ <displayName>CCR2</displayName>
+ <description>capture/compare register 2</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR2</name>
+ <description>Capture/Compare 2 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR3</name>
+ <displayName>CCR3</displayName>
+ <description>capture/compare register 3</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR3</name>
+ <description>Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR4</name>
+ <displayName>CCR4</displayName>
+ <description>capture/compare register 4</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR4</name>
+ <description>Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCR</name>
+ <displayName>DCR</displayName>
+ <description>DMA control register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DBL</name>
+ <description>DMA burst length</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>DBA</name>
+ <description>DMA base address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAR</name>
+ <displayName>DMAR</displayName>
+ <description>DMA address for full transfer</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DMAB</name>
+ <description>DMA register for burst
+ accesses</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RCR</name>
+ <displayName>RCR</displayName>
+ <description>repetition counter register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>REP</name>
+ <description>Repetition counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDTR</name>
+ <displayName>BDTR</displayName>
+ <description>break and dead-time register</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>MOE</name>
+ <description>Main output enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AOE</name>
+ <description>Automatic output enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BKP</name>
+ <description>Break polarity</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BKE</name>
+ <description>Break enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OSSR</name>
+ <description>Off-state selection for Run
+ mode</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OSSI</name>
+ <description>Off-state selection for Idle
+ mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock configuration</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DTG</name>
+ <description>Dead-time generator setup</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="TIM1">
+ <name>TIM8</name>
+ <baseAddress>0x40010400</baseAddress>
+ <interrupt>
+ <name>TIM8_CC</name>
+ <description>TIM8 Cap/Com interrupt</description>
+ <value>46</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>TIM10</name>
+ <description>General-purpose-timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40014400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM1_UP_TIM10</name>
+ <description>TIM1 Update interrupt and TIM10 global
+ interrupt</description>
+ <value>25</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register 1 (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC1M</name>
+ <description>Output Compare 1 mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>Output Compare 1 preload
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>Output Compare 1 fast
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ICPCS</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1</name>
+ <description>Capture/Compare 1 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>TIM11</name>
+ <description>General-purpose-timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40014800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM1_TRG_COM_TIM11</name>
+ <description>TIM1 Trigger and Commutation interrupts and
+ TIM11 global interrupt</description>
+ <value>26</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register 1 (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC1M</name>
+ <description>Output Compare 1 mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>Output Compare 1 preload
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>Output Compare 1 fast
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ICPCS</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1</name>
+ <description>Capture/Compare 1 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OR</name>
+ <displayName>OR</displayName>
+ <description>option register</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RMP</name>
+ <description>Input 1 remapping
+ capability</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>TIM2</name>
+ <description>General purpose timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM2</name>
+ <description>TIM2 global interrupt</description>
+ <value>28</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMS</name>
+ <description>Center-aligned mode
+ selection</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Direction</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPM</name>
+ <description>One-pulse mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TI1S</name>
+ <description>TI1 selection</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MMS</name>
+ <description>Master mode selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CCDS</name>
+ <description>Capture/compare DMA
+ selection</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMCR</name>
+ <displayName>SMCR</displayName>
+ <description>slave mode control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ETP</name>
+ <description>External trigger polarity</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ECE</name>
+ <description>External clock enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ETPS</name>
+ <description>External trigger prescaler</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ETF</name>
+ <description>External trigger filter</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSM</name>
+ <description>Master/Slave mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TS</name>
+ <description>Trigger selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SMS</name>
+ <description>Slave mode selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TDE</name>
+ <description>Trigger DMA request enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4DE</name>
+ <description>Capture/Compare 4 DMA request
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3DE</name>
+ <description>Capture/Compare 3 DMA request
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2DE</name>
+ <description>Capture/Compare 2 DMA request
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1DE</name>
+ <description>Capture/Compare 1 DMA request
+ enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDE</name>
+ <description>Update DMA request enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIE</name>
+ <description>Trigger interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IE</name>
+ <description>Capture/Compare 4 interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IE</name>
+ <description>Capture/Compare 3 interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IE</name>
+ <description>Capture/Compare 2 interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4OF</name>
+ <description>Capture/Compare 4 overcapture
+ flag</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3OF</name>
+ <description>Capture/Compare 3 overcapture
+ flag</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2OF</name>
+ <description>Capture/compare 2 overcapture
+ flag</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIF</name>
+ <description>Trigger interrupt flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IF</name>
+ <description>Capture/Compare 4 interrupt
+ flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IF</name>
+ <description>Capture/Compare 3 interrupt
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IF</name>
+ <description>Capture/Compare 2 interrupt
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TG</name>
+ <description>Trigger generation</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4G</name>
+ <description>Capture/compare 4
+ generation</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3G</name>
+ <description>Capture/compare 3
+ generation</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2G</name>
+ <description>Capture/compare 2
+ generation</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register 1 (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC2CE</name>
+ <description>OC2CE</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2M</name>
+ <description>OC2M</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC2PE</name>
+ <description>OC2PE</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2FE</name>
+ <description>OC2FE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>CC2S</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC1CE</name>
+ <description>OC1CE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1M</name>
+ <description>OC1M</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>OC1PE</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>OC1FE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>CC1S</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC2F</name>
+ <description>Input capture 2 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC2PCS</name>
+ <description>Input capture 2 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ICPCS</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Output</name>
+ <displayName>CCMR2_Output</displayName>
+ <description>capture/compare mode register 2 (output
+ mode)</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>O24CE</name>
+ <description>O24CE</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4M</name>
+ <description>OC4M</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC4PE</name>
+ <description>OC4PE</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4FE</name>
+ <description>OC4FE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>CC4S</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC3CE</name>
+ <description>OC3CE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3M</name>
+ <description>OC3M</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC3PE</name>
+ <description>OC3PE</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3FE</name>
+ <description>OC3FE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>CC3S</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Input</name>
+ <displayName>CCMR2_Input</displayName>
+ <description>capture/compare mode register 2 (input
+ mode)</description>
+ <alternateRegister>CCMR2_Output</alternateRegister>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC4F</name>
+ <description>Input capture 4 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC4PSC</name>
+ <description>Input capture 4 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>Capture/Compare 4
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC3F</name>
+ <description>Input capture 3 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC3PSC</name>
+ <description>Input capture 3 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>Capture/compare 3
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4NP</name>
+ <description>Capture/Compare 4 output
+ Polarity</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4E</name>
+ <description>Capture/Compare 4 output
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3NP</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3E</name>
+ <description>Capture/Compare 3 output
+ enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2NP</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2P</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2E</name>
+ <description>Capture/Compare 2 output
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT_H</name>
+ <description>High counter value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CNT_L</name>
+ <description>Low counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR_H</name>
+ <description>High Auto-reload value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>ARR_L</name>
+ <description>Low Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1_H</name>
+ <description>High Capture/Compare 1
+ value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR1_L</name>
+ <description>Low Capture/Compare 1
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR2</name>
+ <displayName>CCR2</displayName>
+ <description>capture/compare register 2</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR2_H</name>
+ <description>High Capture/Compare 2
+ value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR2_L</name>
+ <description>Low Capture/Compare 2
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR3</name>
+ <displayName>CCR3</displayName>
+ <description>capture/compare register 3</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR3_H</name>
+ <description>High Capture/Compare value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR3_L</name>
+ <description>Low Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR4</name>
+ <displayName>CCR4</displayName>
+ <description>capture/compare register 4</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR4_H</name>
+ <description>High Capture/Compare value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR4_L</name>
+ <description>Low Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCR</name>
+ <displayName>DCR</displayName>
+ <description>DMA control register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DBL</name>
+ <description>DMA burst length</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>DBA</name>
+ <description>DMA base address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAR</name>
+ <displayName>DMAR</displayName>
+ <description>DMA address for full transfer</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DMAB</name>
+ <description>DMA register for burst
+ accesses</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OR</name>
+ <displayName>OR</displayName>
+ <description>TIM5 option register</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ITR1_RMP</name>
+ <description>Timer Input 4 remap</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>TIM3</name>
+ <description>General purpose timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40000400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM3</name>
+ <description>TIM3 global interrupt</description>
+ <value>29</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMS</name>
+ <description>Center-aligned mode
+ selection</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Direction</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPM</name>
+ <description>One-pulse mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TI1S</name>
+ <description>TI1 selection</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MMS</name>
+ <description>Master mode selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CCDS</name>
+ <description>Capture/compare DMA
+ selection</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMCR</name>
+ <displayName>SMCR</displayName>
+ <description>slave mode control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ETP</name>
+ <description>External trigger polarity</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ECE</name>
+ <description>External clock enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ETPS</name>
+ <description>External trigger prescaler</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ETF</name>
+ <description>External trigger filter</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSM</name>
+ <description>Master/Slave mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TS</name>
+ <description>Trigger selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SMS</name>
+ <description>Slave mode selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TDE</name>
+ <description>Trigger DMA request enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4DE</name>
+ <description>Capture/Compare 4 DMA request
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3DE</name>
+ <description>Capture/Compare 3 DMA request
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2DE</name>
+ <description>Capture/Compare 2 DMA request
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1DE</name>
+ <description>Capture/Compare 1 DMA request
+ enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDE</name>
+ <description>Update DMA request enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIE</name>
+ <description>Trigger interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IE</name>
+ <description>Capture/Compare 4 interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IE</name>
+ <description>Capture/Compare 3 interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IE</name>
+ <description>Capture/Compare 2 interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4OF</name>
+ <description>Capture/Compare 4 overcapture
+ flag</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3OF</name>
+ <description>Capture/Compare 3 overcapture
+ flag</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2OF</name>
+ <description>Capture/compare 2 overcapture
+ flag</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIF</name>
+ <description>Trigger interrupt flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IF</name>
+ <description>Capture/Compare 4 interrupt
+ flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IF</name>
+ <description>Capture/Compare 3 interrupt
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IF</name>
+ <description>Capture/Compare 2 interrupt
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TG</name>
+ <description>Trigger generation</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4G</name>
+ <description>Capture/compare 4
+ generation</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3G</name>
+ <description>Capture/compare 3
+ generation</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2G</name>
+ <description>Capture/compare 2
+ generation</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register 1 (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC2CE</name>
+ <description>OC2CE</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2M</name>
+ <description>OC2M</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC2PE</name>
+ <description>OC2PE</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2FE</name>
+ <description>OC2FE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>CC2S</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC1CE</name>
+ <description>OC1CE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1M</name>
+ <description>OC1M</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>OC1PE</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>OC1FE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>CC1S</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC2F</name>
+ <description>Input capture 2 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC2PCS</name>
+ <description>Input capture 2 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ICPCS</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Output</name>
+ <displayName>CCMR2_Output</displayName>
+ <description>capture/compare mode register 2 (output
+ mode)</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>O24CE</name>
+ <description>O24CE</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4M</name>
+ <description>OC4M</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC4PE</name>
+ <description>OC4PE</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4FE</name>
+ <description>OC4FE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>CC4S</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC3CE</name>
+ <description>OC3CE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3M</name>
+ <description>OC3M</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC3PE</name>
+ <description>OC3PE</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3FE</name>
+ <description>OC3FE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>CC3S</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Input</name>
+ <displayName>CCMR2_Input</displayName>
+ <description>capture/compare mode register 2 (input
+ mode)</description>
+ <alternateRegister>CCMR2_Output</alternateRegister>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC4F</name>
+ <description>Input capture 4 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC4PSC</name>
+ <description>Input capture 4 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>Capture/Compare 4
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC3F</name>
+ <description>Input capture 3 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC3PSC</name>
+ <description>Input capture 3 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>Capture/compare 3
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4NP</name>
+ <description>Capture/Compare 4 output
+ Polarity</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4E</name>
+ <description>Capture/Compare 4 output
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3NP</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3E</name>
+ <description>Capture/Compare 3 output
+ enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2NP</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2P</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2E</name>
+ <description>Capture/Compare 2 output
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT_H</name>
+ <description>High counter value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CNT_L</name>
+ <description>Low counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR_H</name>
+ <description>High Auto-reload value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>ARR_L</name>
+ <description>Low Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1_H</name>
+ <description>High Capture/Compare 1
+ value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR1_L</name>
+ <description>Low Capture/Compare 1
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR2</name>
+ <displayName>CCR2</displayName>
+ <description>capture/compare register 2</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR2_H</name>
+ <description>High Capture/Compare 2
+ value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR2_L</name>
+ <description>Low Capture/Compare 2
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR3</name>
+ <displayName>CCR3</displayName>
+ <description>capture/compare register 3</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR3_H</name>
+ <description>High Capture/Compare value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR3_L</name>
+ <description>Low Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR4</name>
+ <displayName>CCR4</displayName>
+ <description>capture/compare register 4</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR4_H</name>
+ <description>High Capture/Compare value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR4_L</name>
+ <description>Low Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCR</name>
+ <displayName>DCR</displayName>
+ <description>DMA control register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DBL</name>
+ <description>DMA burst length</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>DBA</name>
+ <description>DMA base address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAR</name>
+ <displayName>DMAR</displayName>
+ <description>DMA address for full transfer</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DMAB</name>
+ <description>DMA register for burst
+ accesses</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="TIM3">
+ <name>TIM4</name>
+ <baseAddress>0x40000800</baseAddress>
+ <interrupt>
+ <name>TIM4</name>
+ <description>TIM4 global interrupt</description>
+ <value>30</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>TIM5</name>
+ <description>General-purpose-timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40000C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM5</name>
+ <description>TIM5 global interrupt</description>
+ <value>50</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMS</name>
+ <description>Center-aligned mode
+ selection</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Direction</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPM</name>
+ <description>One-pulse mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TI1S</name>
+ <description>TI1 selection</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MMS</name>
+ <description>Master mode selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CCDS</name>
+ <description>Capture/compare DMA
+ selection</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMCR</name>
+ <displayName>SMCR</displayName>
+ <description>slave mode control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ETP</name>
+ <description>External trigger polarity</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ECE</name>
+ <description>External clock enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ETPS</name>
+ <description>External trigger prescaler</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ETF</name>
+ <description>External trigger filter</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MSM</name>
+ <description>Master/Slave mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TS</name>
+ <description>Trigger selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SMS</name>
+ <description>Slave mode selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TDE</name>
+ <description>Trigger DMA request enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4DE</name>
+ <description>Capture/Compare 4 DMA request
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3DE</name>
+ <description>Capture/Compare 3 DMA request
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2DE</name>
+ <description>Capture/Compare 2 DMA request
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1DE</name>
+ <description>Capture/Compare 1 DMA request
+ enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDE</name>
+ <description>Update DMA request enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIE</name>
+ <description>Trigger interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IE</name>
+ <description>Capture/Compare 4 interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IE</name>
+ <description>Capture/Compare 3 interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IE</name>
+ <description>Capture/Compare 2 interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4OF</name>
+ <description>Capture/Compare 4 overcapture
+ flag</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3OF</name>
+ <description>Capture/Compare 3 overcapture
+ flag</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2OF</name>
+ <description>Capture/compare 2 overcapture
+ flag</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIF</name>
+ <description>Trigger interrupt flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4IF</name>
+ <description>Capture/Compare 4 interrupt
+ flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3IF</name>
+ <description>Capture/Compare 3 interrupt
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IF</name>
+ <description>Capture/Compare 2 interrupt
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TG</name>
+ <description>Trigger generation</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4G</name>
+ <description>Capture/compare 4
+ generation</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3G</name>
+ <description>Capture/compare 3
+ generation</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2G</name>
+ <description>Capture/compare 2
+ generation</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register 1 (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC2CE</name>
+ <description>OC2CE</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2M</name>
+ <description>OC2M</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC2PE</name>
+ <description>OC2PE</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2FE</name>
+ <description>OC2FE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>CC2S</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC1CE</name>
+ <description>OC1CE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1M</name>
+ <description>OC1M</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>OC1PE</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>OC1FE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>CC1S</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC2F</name>
+ <description>Input capture 2 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC2PCS</name>
+ <description>Input capture 2 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ICPCS</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Output</name>
+ <displayName>CCMR2_Output</displayName>
+ <description>capture/compare mode register 2 (output
+ mode)</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>O24CE</name>
+ <description>O24CE</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4M</name>
+ <description>OC4M</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC4PE</name>
+ <description>OC4PE</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC4FE</name>
+ <description>OC4FE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>CC4S</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC3CE</name>
+ <description>OC3CE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3M</name>
+ <description>OC3M</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC3PE</name>
+ <description>OC3PE</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC3FE</name>
+ <description>OC3FE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>CC3S</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR2_Input</name>
+ <displayName>CCMR2_Input</displayName>
+ <description>capture/compare mode register 2 (input
+ mode)</description>
+ <alternateRegister>CCMR2_Output</alternateRegister>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC4F</name>
+ <description>Input capture 4 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC4PSC</name>
+ <description>Input capture 4 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC4S</name>
+ <description>Capture/Compare 4
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC3F</name>
+ <description>Input capture 3 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC3PSC</name>
+ <description>Input capture 3 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC3S</name>
+ <description>Capture/compare 3
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC4NP</name>
+ <description>Capture/Compare 4 output
+ Polarity</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC4E</name>
+ <description>Capture/Compare 4 output
+ enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3NP</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3P</name>
+ <description>Capture/Compare 3 output
+ Polarity</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC3E</name>
+ <description>Capture/Compare 3 output
+ enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2NP</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2P</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2E</name>
+ <description>Capture/Compare 2 output
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT_H</name>
+ <description>High counter value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CNT_L</name>
+ <description>Low counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR_H</name>
+ <description>High Auto-reload value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>ARR_L</name>
+ <description>Low Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1_H</name>
+ <description>High Capture/Compare 1
+ value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR1_L</name>
+ <description>Low Capture/Compare 1
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR2</name>
+ <displayName>CCR2</displayName>
+ <description>capture/compare register 2</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR2_H</name>
+ <description>High Capture/Compare 2
+ value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR2_L</name>
+ <description>Low Capture/Compare 2
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR3</name>
+ <displayName>CCR3</displayName>
+ <description>capture/compare register 3</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR3_H</name>
+ <description>High Capture/Compare value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR3_L</name>
+ <description>Low Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR4</name>
+ <displayName>CCR4</displayName>
+ <description>capture/compare register 4</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR4_H</name>
+ <description>High Capture/Compare value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>CCR4_L</name>
+ <description>Low Capture/Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCR</name>
+ <displayName>DCR</displayName>
+ <description>DMA control register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DBL</name>
+ <description>DMA burst length</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>DBA</name>
+ <description>DMA base address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAR</name>
+ <displayName>DMAR</displayName>
+ <description>DMA address for full transfer</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DMAB</name>
+ <description>DMA register for burst
+ accesses</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OR</name>
+ <displayName>OR</displayName>
+ <description>TIM5 option register</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>IT4_RMP</name>
+ <description>Timer Input 4 remap</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>TIM9</name>
+ <description>General purpose timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40014000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM1_BRK_TIM9</name>
+ <description>TIM1 Break interrupt and TIM9 global
+ interrupt</description>
+ <value>24</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPM</name>
+ <description>One-pulse mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>MMS</name>
+ <description>Master mode selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMCR</name>
+ <displayName>SMCR</displayName>
+ <description>slave mode control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>MSM</name>
+ <description>Master/Slave mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TS</name>
+ <description>Trigger selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SMS</name>
+ <description>Slave mode selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TIE</name>
+ <description>Trigger interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IE</name>
+ <description>Capture/Compare 2 interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC2OF</name>
+ <description>Capture/compare 2 overcapture
+ flag</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIF</name>
+ <description>Trigger interrupt flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IF</name>
+ <description>Capture/Compare 2 interrupt
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TG</name>
+ <description>Trigger generation</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2G</name>
+ <description>Capture/compare 2
+ generation</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register 1 (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC2M</name>
+ <description>Output Compare 2 mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC2PE</name>
+ <description>Output Compare 2 preload
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2FE</name>
+ <description>Output Compare 2 fast
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC1M</name>
+ <description>Output Compare 1 mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>Output Compare 1 preload
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>Output Compare 1 fast
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC2F</name>
+ <description>Input capture 2 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>IC2PCS</name>
+ <description>Input capture 2 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>ICPCS</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC2NP</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2P</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2E</name>
+ <description>Capture/Compare 2 output
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1</name>
+ <description>Capture/Compare 1 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR2</name>
+ <displayName>CCR2</displayName>
+ <description>capture/compare register 2</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR2</name>
+ <description>Capture/Compare 2 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>USART1</name>
+ <description>Universal synchronous asynchronous receiver
+ transmitter</description>
+ <groupName>USART</groupName>
+ <baseAddress>0x40011000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>USART1</name>
+ <description>USART1 global interrupt</description>
+ <value>37</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>Status register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00C00000</resetValue>
+ <fields>
+ <field>
+ <name>CTS</name>
+ <description>CTS flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LBD</name>
+ <description>LIN break detection flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXE</name>
+ <description>Transmit data register
+ empty</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TC</name>
+ <description>Transmission complete</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RXNE</name>
+ <description>Read data register not
+ empty</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IDLE</name>
+ <description>IDLE line detected</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ORE</name>
+ <description>Overrun error</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>NF</name>
+ <description>Noise detected flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>FE</name>
+ <description>Framing error</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PE</name>
+ <description>Parity error</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>Data register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DR</name>
+ <description>Data value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>9</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BRR</name>
+ <displayName>BRR</displayName>
+ <description>Baud rate register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DIV_Mantissa</name>
+ <description>mantissa of USARTDIV</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>DIV_Fraction</name>
+ <description>fraction of USARTDIV</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>Control register 1</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>OVER8</name>
+ <description>Oversampling mode</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UE</name>
+ <description>USART enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>M</name>
+ <description>Word length</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAKE</name>
+ <description>Wakeup method</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PCE</name>
+ <description>Parity control enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PS</name>
+ <description>Parity selection</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PEIE</name>
+ <description>PE interrupt enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXEIE</name>
+ <description>TXE interrupt enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transmission complete interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXNEIE</name>
+ <description>RXNE interrupt enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDLEIE</name>
+ <description>IDLE interrupt enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TE</name>
+ <description>Transmitter enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RE</name>
+ <description>Receiver enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RWU</name>
+ <description>Receiver wakeup</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SBK</name>
+ <description>Send break</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>Control register 2</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>LINEN</name>
+ <description>LIN mode enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOP</name>
+ <description>STOP bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CLKEN</name>
+ <description>Clock enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPOL</name>
+ <description>Clock polarity</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPHA</name>
+ <description>Clock phase</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LBCL</name>
+ <description>Last bit clock pulse</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LBDIE</name>
+ <description>LIN break detection interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LBDL</name>
+ <description>lin break detection length</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADD</name>
+ <description>Address of the USART node</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR3</name>
+ <displayName>CR3</displayName>
+ <description>Control register 3</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ONEBIT</name>
+ <description>One sample bit method
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTSIE</name>
+ <description>CTS interrupt enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTSE</name>
+ <description>CTS enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTSE</name>
+ <description>RTS enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAT</name>
+ <description>DMA enable transmitter</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAR</name>
+ <description>DMA enable receiver</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCEN</name>
+ <description>Smartcard mode enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NACK</name>
+ <description>Smartcard NACK enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HDSEL</name>
+ <description>Half-duplex selection</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IRLP</name>
+ <description>IrDA low-power</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IREN</name>
+ <description>IrDA mode enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EIE</name>
+ <description>Error interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GTPR</name>
+ <displayName>GTPR</displayName>
+ <description>Guard time and prescaler
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>GT</name>
+ <description>Guard time value</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>USART2</name>
+ <baseAddress>0x40004400</baseAddress>
+ <interrupt>
+ <name>USART2</name>
+ <description>USART2 global interrupt</description>
+ <value>38</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>USART6</name>
+ <baseAddress>0x40011400</baseAddress>
+ <interrupt>
+ <name>USART6</name>
+ <description>USART6 global interrupt</description>
+ <value>71</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>USART3</name>
+ <baseAddress>0x40004800</baseAddress>
+ <interrupt>
+ <name>USART3</name>
+ <description>USART3 global interrupt</description>
+ <value>39</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>UART4</name>
+ <baseAddress>0x40004C00</baseAddress>
+ <interrupt>
+ <name>USART4</name>
+ <description>UART 4 global interrupt</description>
+ <value>52</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>UART5</name>
+ <baseAddress>0x40005000</baseAddress>
+ <interrupt>
+ <name>UART5</name>
+ <description>UART 5global interrupt</description>
+ <value>53</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>UART7</name>
+ <baseAddress>0x40007800</baseAddress>
+ <interrupt>
+ <name>USART7</name>
+ <description>USART7 global interrupt</description>
+ <value>82</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>UART8</name>
+ <baseAddress>0x40007C00</baseAddress>
+ <interrupt>
+ <name>USART8</name>
+ <description>USART8 global interrupt</description>
+ <value>83</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>UART9</name>
+ <baseAddress>0x40011800</baseAddress>
+ <interrupt>
+ <name>UART9</name>
+ <description>UART9 global interrupt</description>
+ <value>88</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="USART1">
+ <name>UART10</name>
+ <baseAddress>0x40011C00</baseAddress>
+ <interrupt>
+ <name>UART10</name>
+ <description>UART10 global interrupt</description>
+ <value>89</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>WWDG</name>
+ <description>Window watchdog</description>
+ <groupName>WWDG</groupName>
+ <baseAddress>0x40002C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>WWDG</name>
+ <description>Window Watchdog interrupt</description>
+ <value>0</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>Control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x7F</resetValue>
+ <fields>
+ <field>
+ <name>WDGA</name>
+ <description>Activation bit</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>T</name>
+ <description>7-bit counter (MSB to LSB)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CFR</name>
+ <displayName>CFR</displayName>
+ <description>Configuration register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x7F</resetValue>
+ <fields>
+ <field>
+ <name>EWI</name>
+ <description>Early wakeup interrupt</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WDGTB1</name>
+ <description>Timer base</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WDGTB0</name>
+ <description>Timer base</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>W</name>
+ <description>7-bit window value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>Status register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <fields>
+ <field>
+ <name>EWIF</name>
+ <description>Early wakeup interrupt
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>DMA2</name>
+ <description>DMA controller</description>
+ <groupName>DMA</groupName>
+ <baseAddress>0x40026400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>DMA2_Stream0</name>
+ <description>DMA2 Stream0 global interrupt</description>
+ <value>56</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA2_Stream1</name>
+ <description>DMA2 Stream1 global interrupt</description>
+ <value>57</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA2_Stream2</name>
+ <description>DMA2 Stream2 global interrupt</description>
+ <value>58</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA2_Stream3</name>
+ <description>DMA2 Stream3 global interrupt</description>
+ <value>59</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA2_Stream4</name>
+ <description>DMA2 Stream4 global interrupt</description>
+ <value>60</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA2_Stream5</name>
+ <description>DMA2 Stream5 global interrupt</description>
+ <value>68</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA2_Stream6</name>
+ <description>DMA2 Stream6 global interrupt</description>
+ <value>69</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA2_Stream7</name>
+ <description>DMA2 Stream7 global interrupt</description>
+ <value>70</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>LISR</name>
+ <displayName>LISR</displayName>
+ <description>low interrupt status register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TCIF3</name>
+ <description>Stream x transfer complete interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF3</name>
+ <description>Stream x half transfer interrupt flag
+ (x=3..0)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF3</name>
+ <description>Stream x transfer error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF3</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=3..0)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF3</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF2</name>
+ <description>Stream x transfer complete interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF2</name>
+ <description>Stream x half transfer interrupt flag
+ (x=3..0)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF2</name>
+ <description>Stream x transfer error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF2</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=3..0)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF2</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF1</name>
+ <description>Stream x transfer complete interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF1</name>
+ <description>Stream x half transfer interrupt flag
+ (x=3..0)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF1</name>
+ <description>Stream x transfer error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF1</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=3..0)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF1</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF0</name>
+ <description>Stream x transfer complete interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF0</name>
+ <description>Stream x half transfer interrupt flag
+ (x=3..0)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF0</name>
+ <description>Stream x transfer error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF0</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=3..0)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF0</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=3..0)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HISR</name>
+ <displayName>HISR</displayName>
+ <description>high interrupt status register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TCIF7</name>
+ <description>Stream x transfer complete interrupt
+ flag (x=7..4)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF7</name>
+ <description>Stream x half transfer interrupt flag
+ (x=7..4)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF7</name>
+ <description>Stream x transfer error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF7</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=7..4)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF7</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF6</name>
+ <description>Stream x transfer complete interrupt
+ flag (x=7..4)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF6</name>
+ <description>Stream x half transfer interrupt flag
+ (x=7..4)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF6</name>
+ <description>Stream x transfer error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF6</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=7..4)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF6</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF5</name>
+ <description>Stream x transfer complete interrupt
+ flag (x=7..4)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF5</name>
+ <description>Stream x half transfer interrupt flag
+ (x=7..4)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF5</name>
+ <description>Stream x transfer error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF5</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=7..4)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF5</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF4</name>
+ <description>Stream x transfer complete interrupt
+ flag (x=7..4)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF4</name>
+ <description>Stream x half transfer interrupt flag
+ (x=7..4)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF4</name>
+ <description>Stream x transfer error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIF4</name>
+ <description>Stream x direct mode error interrupt
+ flag (x=7..4)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEIF4</name>
+ <description>Stream x FIFO error interrupt flag
+ (x=7..4)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LIFCR</name>
+ <displayName>LIFCR</displayName>
+ <description>low interrupt flag clear
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CTCIF3</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF3</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF3</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF3</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF3</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 3..0)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF2</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF2</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF2</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF2</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF2</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 3..0)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF1</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF1</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF1</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF1</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF1</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 3..0)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF0</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF0</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF0</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 3..0)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF0</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 3..0)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF0</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 3..0)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HIFCR</name>
+ <displayName>HIFCR</displayName>
+ <description>high interrupt flag clear
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CTCIF7</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF7</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF7</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF7</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF7</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 7..4)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF6</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF6</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF6</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF6</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF6</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 7..4)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF5</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF5</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF5</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF5</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF5</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 7..4)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF4</name>
+ <description>Stream x clear transfer complete
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF4</name>
+ <description>Stream x clear half transfer interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF4</name>
+ <description>Stream x clear transfer error interrupt
+ flag (x = 7..4)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CDMEIF4</name>
+ <description>Stream x clear direct mode error
+ interrupt flag (x = 7..4)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CFEIF4</name>
+ <description>Stream x clear FIFO error interrupt flag
+ (x = 7..4)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S0CR</name>
+ <displayName>S0CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S0NDTR</name>
+ <displayName>S0NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S0PAR</name>
+ <displayName>S0PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S0M0AR</name>
+ <displayName>S0M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S0M1AR</name>
+ <displayName>S0M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S0FCR</name>
+ <displayName>S0FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S1CR</name>
+ <displayName>S1CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S1NDTR</name>
+ <displayName>S1NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S1PAR</name>
+ <displayName>S1PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S1M0AR</name>
+ <displayName>S1M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S1M1AR</name>
+ <displayName>S1M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S1FCR</name>
+ <displayName>S1FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S2CR</name>
+ <displayName>S2CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S2NDTR</name>
+ <displayName>S2NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S2PAR</name>
+ <displayName>S2PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S2M0AR</name>
+ <displayName>S2M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S2M1AR</name>
+ <displayName>S2M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S2FCR</name>
+ <displayName>S2FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0x54</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S3CR</name>
+ <displayName>S3CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0x58</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S3NDTR</name>
+ <displayName>S3NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0x5C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S3PAR</name>
+ <displayName>S3PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0x60</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S3M0AR</name>
+ <displayName>S3M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0x64</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S3M1AR</name>
+ <displayName>S3M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0x68</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S3FCR</name>
+ <displayName>S3FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0x6C</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S4CR</name>
+ <displayName>S4CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0x70</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S4NDTR</name>
+ <displayName>S4NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0x74</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S4PAR</name>
+ <displayName>S4PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0x78</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S4M0AR</name>
+ <displayName>S4M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0x7C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S4M1AR</name>
+ <displayName>S4M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S4FCR</name>
+ <displayName>S4FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S5CR</name>
+ <displayName>S5CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0x88</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S5NDTR</name>
+ <displayName>S5NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S5PAR</name>
+ <displayName>S5PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0x90</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S5M0AR</name>
+ <displayName>S5M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0x94</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S5M1AR</name>
+ <displayName>S5M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0x98</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S5FCR</name>
+ <displayName>S5FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0x9C</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S6CR</name>
+ <displayName>S6CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0xA0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S6NDTR</name>
+ <displayName>S6NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0xA4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S6PAR</name>
+ <displayName>S6PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0xA8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S6M0AR</name>
+ <displayName>S6M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0xAC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S6M1AR</name>
+ <displayName>S6M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0xB0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S6FCR</name>
+ <displayName>S6FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0xB4</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S7CR</name>
+ <displayName>S7CR</displayName>
+ <description>stream x configuration
+ register</description>
+ <addressOffset>0xB8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CHSEL</name>
+ <description>Channel selection</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MBURST</name>
+ <description>Memory burst transfer
+ configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PBURST</name>
+ <description>Peripheral burst transfer
+ configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CT</name>
+ <description>Current target (only in double buffer
+ mode)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBM</name>
+ <description>Double buffer mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Priority level</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PINCOS</name>
+ <description>Peripheral increment offset
+ size</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory data size</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral data size</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PFCTRL</name>
+ <description>Peripheral flow controller</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMEIE</name>
+ <description>Direct mode error interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Stream enable / flag stream ready when
+ read low</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S7NDTR</name>
+ <displayName>S7NDTR</displayName>
+ <description>stream x number of data
+ register</description>
+ <addressOffset>0xBC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data items to
+ transfer</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S7PAR</name>
+ <displayName>S7PAR</displayName>
+ <description>stream x peripheral address
+ register</description>
+ <addressOffset>0xC0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S7M0AR</name>
+ <displayName>S7M0AR</displayName>
+ <description>stream x memory 0 address
+ register</description>
+ <addressOffset>0xC4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M0A</name>
+ <description>Memory 0 address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S7M1AR</name>
+ <displayName>S7M1AR</displayName>
+ <description>stream x memory 1 address
+ register</description>
+ <addressOffset>0xC8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>M1A</name>
+ <description>Memory 1 address (used in case of Double
+ buffer mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>S7FCR</name>
+ <displayName>S7FCR</displayName>
+ <description>stream x FIFO control register</description>
+ <addressOffset>0xCC</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000021</resetValue>
+ <fields>
+ <field>
+ <name>FEIE</name>
+ <description>FIFO error interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FS</name>
+ <description>FIFO status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMDIS</name>
+ <description>Direct mode disable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="DMA2">
+ <name>DMA1</name>
+ <baseAddress>0x40026000</baseAddress>
+ <interrupt>
+ <name>DMA1_Stream0</name>
+ <description>DMA1 Stream0 global interrupt</description>
+ <value>11</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA1_Stream1</name>
+ <description>DMA1 Stream1 global interrupt</description>
+ <value>12</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA1_Stream2</name>
+ <description>DMA1 Stream2 global interrupt</description>
+ <value>13</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA1_Stream3</name>
+ <description>DMA1 Stream3 global interrupt</description>
+ <value>14</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA1_Stream4</name>
+ <description>DMA1 Stream4 global interrupt</description>
+ <value>15</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA1_Stream5</name>
+ <description>DMA1 Stream5 global interrupt</description>
+ <value>16</value>
+ </interrupt>
+ <interrupt>
+ <name>DMA1_Stream7</name>
+ <description>DMA1 global interrupt Channel 7</description>
+ <value>47</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>GPIOH</name>
+ <description>General-purpose I/Os</description>
+ <groupName>GPIO</groupName>
+ <baseAddress>0x40021C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>DMA1_Stream6</name>
+ <description>DMA1 Stream6 global interrupt</description>
+ <value>17</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>MODER</name>
+ <displayName>MODER</displayName>
+ <description>GPIO port mode register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MODER15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OTYPER</name>
+ <displayName>OTYPER</displayName>
+ <description>GPIO port output type register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OT15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OSPEEDR</name>
+ <displayName>OSPEEDR</displayName>
+ <description>GPIO port output speed
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OSPEEDR15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PUPDR</name>
+ <displayName>PUPDR</displayName>
+ <description>GPIO port pull-up/pull-down
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PUPDR15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IDR</name>
+ <displayName>IDR</displayName>
+ <description>GPIO port input data register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IDR15</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR14</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR13</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR12</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR11</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR10</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR9</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR8</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR7</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR6</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR5</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR4</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR3</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR2</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR1</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR0</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ODR</name>
+ <displayName>ODR</displayName>
+ <description>GPIO port output data register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ODR15</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR14</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR13</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR12</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR11</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR10</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR9</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR8</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR7</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR6</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR5</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR4</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR3</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR2</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR1</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR0</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BSRR</name>
+ <displayName>BSRR</displayName>
+ <description>GPIO port bit set/reset
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BR15</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR14</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR13</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR12</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR11</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR10</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR9</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR8</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR7</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR6</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR5</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR4</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR3</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR2</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR1</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR0</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS15</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS14</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS13</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS12</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS11</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS10</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS9</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS8</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS7</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS6</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS5</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS4</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS3</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS2</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS1</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS0</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LCKR</name>
+ <displayName>LCKR</displayName>
+ <description>GPIO port configuration lock
+ register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LCKK</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK15</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK14</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK13</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK12</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK11</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK10</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK9</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK8</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK7</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK6</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK5</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK4</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK3</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK2</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK1</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK0</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AFRL</name>
+ <displayName>AFRL</displayName>
+ <description>GPIO alternate function low
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AFRL7</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL6</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL5</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL4</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL3</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL2</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL1</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL0</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AFRH</name>
+ <displayName>AFRH</displayName>
+ <description>GPIO alternate function high
+ register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AFRH15</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH14</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH13</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH12</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH11</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH10</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH9</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH8</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="GPIOH">
+ <name>GPIOE</name>
+ <baseAddress>0x40021000</baseAddress>
+ </peripheral>
+ <peripheral derivedFrom="GPIOH">
+ <name>GPIOD</name>
+ <baseAddress>0X40020C00</baseAddress>
+ </peripheral>
+ <peripheral derivedFrom="GPIOH">
+ <name>GPIOC</name>
+ <baseAddress>0x40020800</baseAddress>
+ </peripheral>
+ <peripheral derivedFrom="GPIOH">
+ <name>GPIOF</name>
+ <baseAddress>0x40021400</baseAddress>
+ </peripheral>
+ <peripheral derivedFrom="GPIOH">
+ <name>GPIOG</name>
+ <baseAddress>0x40021800</baseAddress>
+ </peripheral>
+ <peripheral>
+ <name>GPIOB</name>
+ <description>General-purpose I/Os</description>
+ <groupName>GPIO</groupName>
+ <baseAddress>0x40020400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>MODER</name>
+ <displayName>MODER</displayName>
+ <description>GPIO port mode register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000280</resetValue>
+ <fields>
+ <field>
+ <name>MODER15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OTYPER</name>
+ <displayName>OTYPER</displayName>
+ <description>GPIO port output type register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OT15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OSPEEDR</name>
+ <displayName>OSPEEDR</displayName>
+ <description>GPIO port output speed
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000000C0</resetValue>
+ <fields>
+ <field>
+ <name>OSPEEDR15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PUPDR</name>
+ <displayName>PUPDR</displayName>
+ <description>GPIO port pull-up/pull-down
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000100</resetValue>
+ <fields>
+ <field>
+ <name>PUPDR15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IDR</name>
+ <displayName>IDR</displayName>
+ <description>GPIO port input data register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IDR15</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR14</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR13</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR12</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR11</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR10</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR9</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR8</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR7</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR6</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR5</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR4</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR3</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR2</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR1</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR0</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ODR</name>
+ <displayName>ODR</displayName>
+ <description>GPIO port output data register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ODR15</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR14</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR13</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR12</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR11</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR10</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR9</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR8</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR7</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR6</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR5</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR4</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR3</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR2</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR1</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR0</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BSRR</name>
+ <displayName>BSRR</displayName>
+ <description>GPIO port bit set/reset
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BR15</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR14</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR13</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR12</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR11</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR10</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR9</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR8</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR7</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR6</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR5</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR4</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR3</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR2</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR1</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR0</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS15</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS14</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS13</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS12</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS11</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS10</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS9</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS8</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS7</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS6</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS5</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS4</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS3</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS2</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS1</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS0</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LCKR</name>
+ <displayName>LCKR</displayName>
+ <description>GPIO port configuration lock
+ register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LCKK</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK15</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK14</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK13</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK12</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK11</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK10</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK9</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK8</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK7</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK6</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK5</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK4</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK3</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK2</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK1</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK0</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AFRL</name>
+ <displayName>AFRL</displayName>
+ <description>GPIO alternate function low
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AFRL7</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL6</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL5</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL4</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL3</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL2</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL1</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL0</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AFRH</name>
+ <displayName>AFRH</displayName>
+ <description>GPIO alternate function high
+ register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AFRH15</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH14</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH13</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH12</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH11</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH10</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH9</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH8</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>GPIOA</name>
+ <description>General-purpose I/Os</description>
+ <groupName>GPIO</groupName>
+ <baseAddress>0x40020000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>MODER</name>
+ <displayName>MODER</displayName>
+ <description>GPIO port mode register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xA8000000</resetValue>
+ <fields>
+ <field>
+ <name>MODER15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODER0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OTYPER</name>
+ <displayName>OTYPER</displayName>
+ <description>GPIO port output type register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OT15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OSPEEDR</name>
+ <displayName>OSPEEDR</displayName>
+ <description>GPIO port output speed
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OSPEEDR15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEEDR0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PUPDR</name>
+ <displayName>PUPDR</displayName>
+ <description>GPIO port pull-up/pull-down
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x64000000</resetValue>
+ <fields>
+ <field>
+ <name>PUPDR15</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR14</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR13</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR12</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR11</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR10</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR9</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR8</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR7</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR6</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR5</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR4</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR3</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR2</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR1</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPDR0</name>
+ <description>Port x configuration bits (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IDR</name>
+ <displayName>IDR</displayName>
+ <description>GPIO port input data register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IDR15</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR14</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR13</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR12</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR11</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR10</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR9</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR8</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR7</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR6</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR5</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR4</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR3</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR2</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR1</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>IDR0</name>
+ <description>Port input data (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ODR</name>
+ <displayName>ODR</displayName>
+ <description>GPIO port output data register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ODR15</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR14</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR13</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR12</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR11</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR10</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR9</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR8</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR7</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR6</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR5</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR4</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR3</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR2</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR1</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODR0</name>
+ <description>Port output data (y =
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BSRR</name>
+ <displayName>BSRR</displayName>
+ <description>GPIO port bit set/reset
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BR15</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR14</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR13</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR12</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR11</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR10</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR9</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR8</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR7</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR6</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR5</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR4</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR3</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR2</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR1</name>
+ <description>Port x reset bit y (y =
+ 0..15)</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR0</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS15</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS14</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS13</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS12</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS11</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS10</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS9</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS8</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS7</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS6</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS5</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS4</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS3</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS2</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS1</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BS0</name>
+ <description>Port x set bit y (y=
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LCKR</name>
+ <displayName>LCKR</displayName>
+ <description>GPIO port configuration lock
+ register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LCKK</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK15</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK14</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK13</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK12</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK11</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK10</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK9</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK8</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK7</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK6</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK5</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK4</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK3</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK2</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK1</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LCK0</name>
+ <description>Port x lock bit y (y=
+ 0..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AFRL</name>
+ <displayName>AFRL</displayName>
+ <description>GPIO alternate function low
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AFRL7</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL6</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL5</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL4</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL3</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL2</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL1</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRL0</name>
+ <description>Alternate function selection for port x
+ bit y (y = 0..7)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AFRH</name>
+ <displayName>AFRH</displayName>
+ <description>GPIO alternate function high
+ register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AFRH15</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH14</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH13</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH12</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH11</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH10</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH9</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>AFRH8</name>
+ <description>Alternate function selection for port x
+ bit y (y = 8..15)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>I2C3</name>
+ <description>Inter-integrated circuit</description>
+ <groupName>I2C</groupName>
+ <baseAddress>0x40005C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>I2C3_EV</name>
+ <description>I2C3 event interrupt</description>
+ <value>72</value>
+ </interrupt>
+ <interrupt>
+ <name>I2C3_ER</name>
+ <description>I2C3 error interrupt</description>
+ <value>73</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>Control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>SWRST</name>
+ <description>Software reset</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALERT</name>
+ <description>SMBus alert</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PEC</name>
+ <description>Packet error checking</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>POS</name>
+ <description>Acknowledge/PEC Position (for data
+ reception)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>Acknowledge enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOP</name>
+ <description>Stop generation</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>START</name>
+ <description>Start generation</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NOSTRETCH</name>
+ <description>Clock stretching disable (Slave
+ mode)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ENGC</name>
+ <description>General call enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ENPEC</name>
+ <description>PEC enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ENARP</name>
+ <description>ARP enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBTYPE</name>
+ <description>SMBus type</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBUS</name>
+ <description>SMBus mode</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PE</name>
+ <description>Peripheral enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>Control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>LAST</name>
+ <description>DMA last transfer</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN</name>
+ <description>DMA requests enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ITBUFEN</name>
+ <description>Buffer interrupt enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ITEVTEN</name>
+ <description>Event interrupt enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ITERREN</name>
+ <description>Error interrupt enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FREQ</name>
+ <description>Peripheral clock frequency</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OAR1</name>
+ <displayName>OAR1</displayName>
+ <description>Own address register 1</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ADDMODE</name>
+ <description>Addressing mode (slave
+ mode)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADD10</name>
+ <description>Interface address</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ADD7</name>
+ <description>Interface address</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ADD0</name>
+ <description>Interface address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OAR2</name>
+ <displayName>OAR2</displayName>
+ <description>Own address register 2</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ADD2</name>
+ <description>Interface address</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ENDUAL</name>
+ <description>Dual addressing mode
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>Data register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DR</name>
+ <description>8-bit data register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR1</name>
+ <displayName>SR1</displayName>
+ <description>Status register 1</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>SMBALERT</name>
+ <description>SMBus alert</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TIMEOUT</name>
+ <description>Timeout or Tlow error</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PECERR</name>
+ <description>PEC Error in reception</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>OVR</name>
+ <description>Overrun/Underrun</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>AF</name>
+ <description>Acknowledge failure</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ARLO</name>
+ <description>Arbitration lost (master
+ mode)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BERR</name>
+ <description>Bus error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TxE</name>
+ <description>Data register empty
+ (transmitters)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>RxNE</name>
+ <description>Data register not empty
+ (receivers)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>STOPF</name>
+ <description>Stop detection (slave
+ mode)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ADD10</name>
+ <description>10-bit header sent (Master
+ mode)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BTF</name>
+ <description>Byte transfer finished</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ADDR</name>
+ <description>Address sent (master mode)/matched
+ (slave mode)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SB</name>
+ <description>Start bit (Master mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR2</name>
+ <displayName>SR2</displayName>
+ <description>Status register 2</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PEC</name>
+ <description>acket error checking
+ register</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DUALF</name>
+ <description>Dual flag (Slave mode)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBHOST</name>
+ <description>SMBus host header (Slave
+ mode)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBDEFAULT</name>
+ <description>SMBus device default address (Slave
+ mode)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GENCALL</name>
+ <description>General call address (Slave
+ mode)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TRA</name>
+ <description>Transmitter/receiver</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BUSY</name>
+ <description>Bus busy</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MSL</name>
+ <description>Master/slave</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR</name>
+ <displayName>CCR</displayName>
+ <description>Clock control register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>F_S</name>
+ <description>I2C master mode selection</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DUTY</name>
+ <description>Fast mode duty cycle</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCR</name>
+ <description>Clock control register in Fast/Standard
+ mode (Master mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TRISE</name>
+ <displayName>TRISE</displayName>
+ <description>TRISE register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0002</resetValue>
+ <fields>
+ <field>
+ <name>TRISE</name>
+ <description>Maximum rise time in Fast/Standard mode
+ (Master mode)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="I2C3">
+ <name>I2C2</name>
+ <baseAddress>0x40005800</baseAddress>
+ <interrupt>
+ <name>I2C2_EVT</name>
+ <description>I2C2 event interrupt</description>
+ <value>33</value>
+ </interrupt>
+ <interrupt>
+ <name>I2C2_ERR</name>
+ <description>I2C2 error interrupt</description>
+ <value>34</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2C3">
+ <name>I2C1</name>
+ <baseAddress>0x40005400</baseAddress>
+ <interrupt>
+ <name>I2C1_EVT</name>
+ <description>I2C1 event interrupt</description>
+ <value>31</value>
+ </interrupt>
+ <interrupt>
+ <name>I2C1_ERR</name>
+ <description>I2C1 error interrupt</description>
+ <value>32</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>I2S2ext</name>
+ <description>Serial peripheral interface</description>
+ <groupName>SPI</groupName>
+ <baseAddress>0x40003400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>BIDIMODE</name>
+ <description>Bidirectional data mode
+ enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BIDIOE</name>
+ <description>Output enable in bidirectional
+ mode</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CRCEN</name>
+ <description>Hardware CRC calculation
+ enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CRCNEXT</name>
+ <description>CRC transfer next</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFF</name>
+ <description>Data frame format</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXONLY</name>
+ <description>Receive only</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SSM</name>
+ <description>Software slave management</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SSI</name>
+ <description>Internal slave select</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSBFIRST</name>
+ <description>Frame format</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPE</name>
+ <description>SPI enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BR</name>
+ <description>Baud rate control</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MSTR</name>
+ <description>Master selection</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPOL</name>
+ <description>Clock polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPHA</name>
+ <description>Clock phase</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TXEIE</name>
+ <description>Tx buffer empty interrupt
+ enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXNEIE</name>
+ <description>RX buffer not empty interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRIE</name>
+ <description>Error interrupt enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRF</name>
+ <description>Frame format</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SSOE</name>
+ <description>SS output enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXDMAEN</name>
+ <description>Tx buffer DMA enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXDMAEN</name>
+ <description>Rx buffer DMA enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x0002</resetValue>
+ <fields>
+ <field>
+ <name>TIFRFE</name>
+ <description>TI frame format error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BSY</name>
+ <description>Busy flag</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>OVR</name>
+ <description>Overrun flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>MODF</name>
+ <description>Mode fault</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>CRCERR</name>
+ <description>CRC error flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>UDR</name>
+ <description>Underrun flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>CHSIDE</name>
+ <description>Channel side</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TXE</name>
+ <description>Transmit buffer empty</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>RXNE</name>
+ <description>Receive buffer not empty</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>data register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>DR</name>
+ <description>Data register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CRCPR</name>
+ <displayName>CRCPR</displayName>
+ <description>CRC polynomial register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0007</resetValue>
+ <fields>
+ <field>
+ <name>CRCPOLY</name>
+ <description>CRC polynomial register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXCRCR</name>
+ <displayName>RXCRCR</displayName>
+ <description>RX CRC register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>RxCRC</name>
+ <description>Rx CRC register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXCRCR</name>
+ <displayName>TXCRCR</displayName>
+ <description>TX CRC register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TxCRC</name>
+ <description>Tx CRC register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2SCFGR</name>
+ <displayName>I2SCFGR</displayName>
+ <description>I2S configuration register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>I2SMOD</name>
+ <description>I2S mode selection</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2SE</name>
+ <description>I2S Enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2SCFG</name>
+ <description>I2S configuration mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PCMSYNC</name>
+ <description>PCM frame synchronization</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2SSTD</name>
+ <description>I2S standard selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CKPOL</name>
+ <description>Steady state clock
+ polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DATLEN</name>
+ <description>Data length to be
+ transferred</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHLEN</name>
+ <description>Channel length (number of bits per audio
+ channel)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2SPR</name>
+ <displayName>I2SPR</displayName>
+ <description>I2S prescaler register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>00000010</resetValue>
+ <fields>
+ <field>
+ <name>MCKOE</name>
+ <description>Master clock output enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ODD</name>
+ <description>Odd factor for the
+ prescaler</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>I2SDIV</name>
+ <description>I2S Linear prescaler</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="I2S2ext">
+ <name>I2S3ext</name>
+ <baseAddress>0x40004000</baseAddress>
+ </peripheral>
+ <peripheral derivedFrom="I2S2ext">
+ <name>SPI1</name>
+ <baseAddress>0x40013000</baseAddress>
+ <interrupt>
+ <name>SPI1</name>
+ <description>SPI1 global interrupt</description>
+ <value>35</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2S2ext">
+ <name>SPI2</name>
+ <baseAddress>0x40003800</baseAddress>
+ <interrupt>
+ <name>SPI2</name>
+ <description>SPI2 global interrupt</description>
+ <value>36</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2S2ext">
+ <name>SPI3</name>
+ <baseAddress>0x40003C00</baseAddress>
+ <interrupt>
+ <name>SPI3</name>
+ <description>SPI3 global interrupt</description>
+ <value>51</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2S2ext">
+ <name>SPI4</name>
+ <baseAddress>0x40013400</baseAddress>
+ <interrupt>
+ <name>SPI4</name>
+ <description>SPI4 global interrupt</description>
+ <value>84</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2S2ext">
+ <name>SPI5</name>
+ <baseAddress>0x40015000</baseAddress>
+ <interrupt>
+ <name>SPI5</name>
+ <description>SPI5 global interrupt</description>
+ <value>85</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2S2ext">
+ <name>SPI6</name>
+ <baseAddress>0x40015400</baseAddress>
+ </peripheral>
+ <peripheral>
+ <name>NVIC</name>
+ <description>Nested Vectored Interrupt
+ Controller</description>
+ <groupName>NVIC</groupName>
+ <baseAddress>0xE000E000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x1001</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>ICTR</name>
+ <displayName>ICTR</displayName>
+ <description>Interrupt Controller Type
+ Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INTLINESNUM</name>
+ <description>Total number of interrupt lines in
+ groups</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STIR</name>
+ <displayName>STIR</displayName>
+ <description>Software Triggered Interrupt
+ Register</description>
+ <addressOffset>0xF00</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INTID</name>
+ <description>interrupt to be triggered</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>9</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISER0</name>
+ <displayName>ISER0</displayName>
+ <description>Interrupt Set-Enable Register</description>
+ <addressOffset>0x100</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SETENA</name>
+ <description>SETENA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISER1</name>
+ <displayName>ISER1</displayName>
+ <description>Interrupt Set-Enable Register</description>
+ <addressOffset>0x104</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SETENA</name>
+ <description>SETENA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISER2</name>
+ <displayName>ISER2</displayName>
+ <description>Interrupt Set-Enable Register</description>
+ <addressOffset>0x108</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SETENA</name>
+ <description>SETENA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICER0</name>
+ <displayName>ICER0</displayName>
+ <description>Interrupt Clear-Enable
+ Register</description>
+ <addressOffset>0x180</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRENA</name>
+ <description>CLRENA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICER1</name>
+ <displayName>ICER1</displayName>
+ <description>Interrupt Clear-Enable
+ Register</description>
+ <addressOffset>0x184</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRENA</name>
+ <description>CLRENA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICER2</name>
+ <displayName>ICER2</displayName>
+ <description>Interrupt Clear-Enable
+ Register</description>
+ <addressOffset>0x188</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRENA</name>
+ <description>CLRENA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISPR0</name>
+ <displayName>ISPR0</displayName>
+ <description>Interrupt Set-Pending Register</description>
+ <addressOffset>0x200</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SETPEND</name>
+ <description>SETPEND</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISPR1</name>
+ <displayName>ISPR1</displayName>
+ <description>Interrupt Set-Pending Register</description>
+ <addressOffset>0x204</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SETPEND</name>
+ <description>SETPEND</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISPR2</name>
+ <displayName>ISPR2</displayName>
+ <description>Interrupt Set-Pending Register</description>
+ <addressOffset>0x208</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SETPEND</name>
+ <description>SETPEND</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICPR0</name>
+ <displayName>ICPR0</displayName>
+ <description>Interrupt Clear-Pending
+ Register</description>
+ <addressOffset>0x280</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRPEND</name>
+ <description>CLRPEND</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICPR1</name>
+ <displayName>ICPR1</displayName>
+ <description>Interrupt Clear-Pending
+ Register</description>
+ <addressOffset>0x284</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRPEND</name>
+ <description>CLRPEND</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICPR2</name>
+ <displayName>ICPR2</displayName>
+ <description>Interrupt Clear-Pending
+ Register</description>
+ <addressOffset>0x288</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRPEND</name>
+ <description>CLRPEND</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IABR0</name>
+ <displayName>IABR0</displayName>
+ <description>Interrupt Active Bit Register</description>
+ <addressOffset>0x300</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ACTIVE</name>
+ <description>ACTIVE</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IABR1</name>
+ <displayName>IABR1</displayName>
+ <description>Interrupt Active Bit Register</description>
+ <addressOffset>0x304</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ACTIVE</name>
+ <description>ACTIVE</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IABR2</name>
+ <displayName>IABR2</displayName>
+ <description>Interrupt Active Bit Register</description>
+ <addressOffset>0x308</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ACTIVE</name>
+ <description>ACTIVE</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR0</name>
+ <displayName>IPR0</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x400</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR1</name>
+ <displayName>IPR1</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x404</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR2</name>
+ <displayName>IPR2</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x408</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR3</name>
+ <displayName>IPR3</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x40C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR4</name>
+ <displayName>IPR4</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x410</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR5</name>
+ <displayName>IPR5</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x414</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR6</name>
+ <displayName>IPR6</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x418</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR7</name>
+ <displayName>IPR7</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x41C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR8</name>
+ <displayName>IPR8</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x420</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR9</name>
+ <displayName>IPR9</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x424</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR10</name>
+ <displayName>IPR10</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x428</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR11</name>
+ <displayName>IPR11</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x42C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR12</name>
+ <displayName>IPR12</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x430</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR13</name>
+ <displayName>IPR13</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x434</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR14</name>
+ <displayName>IPR14</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x438</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR15</name>
+ <displayName>IPR15</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x43C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR16</name>
+ <displayName>IPR16</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x440</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR17</name>
+ <displayName>IPR17</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x444</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR18</name>
+ <displayName>IPR18</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x448</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPR19</name>
+ <displayName>IPR19</displayName>
+ <description>Interrupt Priority Register</description>
+ <addressOffset>0x44C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IPR_N0</name>
+ <description>IPR_N0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N1</name>
+ <description>IPR_N1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N2</name>
+ <description>IPR_N2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IPR_N3</name>
+ <description>IPR_N3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>DFSDM1</name>
+ <description>Digital filter for sigma delta
+ modulators</description>
+ <groupName>DFSDM</groupName>
+ <baseAddress>0x40016000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>DFSDM1_FLT0</name>
+ <description>SD filter0 global interrupt</description>
+ <value>61</value>
+ </interrupt>
+ <interrupt>
+ <name>DFSDM1_FLT1</name>
+ <description>SD filter1 global interrupt</description>
+ <value>62</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CH0CFGR1</name>
+ <displayName>CH0CFGR1</displayName>
+ <description>channel configuration y
+ register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DFSDMEN</name>
+ <description>DFSDMEN</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKOUTSRC</name>
+ <description>CKOUTSRC</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKOUTDIV</name>
+ <description>CKOUTDIV</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH0CFGR2</name>
+ <displayName>CH0CFGR2</displayName>
+ <description>channel configuration y
+ register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH0AWSCDR</name>
+ <displayName>CH0AWSCDR</displayName>
+ <description>analog watchdog and short-circuit detector
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH0WDATR</name>
+ <displayName>CH0WDATR</displayName>
+ <description>channel watchdog filter data
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH0DATINR</name>
+ <displayName>CH0DATINR</displayName>
+ <description>channel data input register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH1CFGR1</name>
+ <displayName>CH1CFGR1</displayName>
+ <description>CHCFG1R1</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH1CFGR2</name>
+ <displayName>CH1CFGR2</displayName>
+ <description>CHCFG1R2</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH1AWSCDR</name>
+ <displayName>CH1AWSCDR</displayName>
+ <description>AWSCD1R</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH1WDATR</name>
+ <displayName>CH1WDATR</displayName>
+ <description>CHWDAT1R</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH1DATINR</name>
+ <displayName>CH1DATINR</displayName>
+ <description>CHDATIN1R</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH2CFGR1</name>
+ <displayName>CH2CFGR1</displayName>
+ <description>CHCFG2R1</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH2CFGR2</name>
+ <displayName>CH2CFGR2</displayName>
+ <description>CHCFG2R2</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH2AWSCDR</name>
+ <displayName>CH2AWSCDR</displayName>
+ <description>AWSCD2R</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH2WDATR</name>
+ <displayName>CH2WDATR</displayName>
+ <description>CHWDAT2R</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH2DATINR</name>
+ <displayName>CH2DATINR</displayName>
+ <description>CHDATIN2R</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH3CFGR1</name>
+ <displayName>CH3CFGR1</displayName>
+ <description>CHCFG3R1</description>
+ <addressOffset>0x60</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH3CFGR2</name>
+ <displayName>CH3CFGR2</displayName>
+ <description>CHCFG3R2</description>
+ <addressOffset>0x64</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH3AWSCDR</name>
+ <displayName>CH3AWSCDR</displayName>
+ <description>AWSCD3R</description>
+ <addressOffset>0x68</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH3WDATR</name>
+ <displayName>CH3WDATR</displayName>
+ <description>CHWDAT3R</description>
+ <addressOffset>0x6C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH3DATINR</name>
+ <displayName>CH3DATINR</displayName>
+ <description>CHDATIN3R</description>
+ <addressOffset>0x70</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH4CFGR1</name>
+ <displayName>CH4CFGR1</displayName>
+ <description>CHCFG4R1</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH4CFGR2</name>
+ <displayName>CH4CFGR2</displayName>
+ <description>CHCFG4R2</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH4AWSCDR</name>
+ <displayName>CH4AWSCDR</displayName>
+ <description>AWSCD4R</description>
+ <addressOffset>0x88</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH4WDATR</name>
+ <displayName>CH4WDATR</displayName>
+ <description>CHWDAT4R</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH4DATINR</name>
+ <displayName>CH4DATINR</displayName>
+ <description>CHDATIN4R</description>
+ <addressOffset>0x90</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH5CFGR1</name>
+ <displayName>CH5CFGR1</displayName>
+ <description>CHCFG5R1</description>
+ <addressOffset>0xA0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH5CFGR2</name>
+ <displayName>CH5CFGR2</displayName>
+ <description>CHCFG5R2</description>
+ <addressOffset>0xA4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH5AWSCDR</name>
+ <displayName>CH5AWSCDR</displayName>
+ <description>AWSCD5R</description>
+ <addressOffset>0xA8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH5WDATR</name>
+ <displayName>CH5WDATR</displayName>
+ <description>CHWDAT5R</description>
+ <addressOffset>0xAC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH5DATINR</name>
+ <displayName>CH5DATINR</displayName>
+ <description>CHDATIN5R</description>
+ <addressOffset>0xB0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH6CFGR1</name>
+ <displayName>CH6CFGR1</displayName>
+ <description>CHCFG6R1</description>
+ <addressOffset>0xC0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH6CFGR2</name>
+ <displayName>CH6CFGR2</displayName>
+ <description>CHCFG6R2</description>
+ <addressOffset>0xC4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH6AWSCDR</name>
+ <displayName>CH6AWSCDR</displayName>
+ <description>AWSCD6R</description>
+ <addressOffset>0xC8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH6WDATR</name>
+ <displayName>CH6WDATR</displayName>
+ <description>CHWDAT6R</description>
+ <addressOffset>0xCC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH6DATINR</name>
+ <displayName>CH6DATINR</displayName>
+ <description>CHDATIN6R</description>
+ <addressOffset>0xD0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH7CFGR1</name>
+ <displayName>CH7CFGR1</displayName>
+ <description>CHCFG7R1</description>
+ <addressOffset>0xE0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>DATPACK</name>
+ <description>DATPACK</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATMPX</name>
+ <description>DATMPX</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CHINSEL</name>
+ <description>CHINSEL</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHEN</name>
+ <description>CHEN</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CKABEN</name>
+ <description>CKABEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDEN</name>
+ <description>SCDEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPICKSEL</name>
+ <description>SPICKSEL</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SITP</name>
+ <description>SITP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH7CFGR2</name>
+ <displayName>CH7CFGR2</displayName>
+ <description>CHCFG7R2</description>
+ <addressOffset>0xE4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>OFFSET</name>
+ <description>OFFSET</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>DTRBS</name>
+ <description>DTRBS</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH7AWSCDR</name>
+ <displayName>CH7AWSCDR</displayName>
+ <description>AWSCD7R</description>
+ <addressOffset>0xE8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>AWFORD</name>
+ <description>AWFORD</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AWFOSR</name>
+ <description>AWFOSR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>BKSCD</name>
+ <description>BKSCD</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCDT</name>
+ <description>SCDT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH7WDATR</name>
+ <displayName>CH7WDATR</displayName>
+ <description>CHWDAT7R</description>
+ <addressOffset>0xEC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>WDATA</name>
+ <description>WDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CH7DATINR</name>
+ <displayName>CH7DATINR</displayName>
+ <description>CHDATIN7R</description>
+ <addressOffset>0xF0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <fields>
+ <field>
+ <name>INDAT1</name>
+ <description>INDAT1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INDAT0</name>
+ <description>INDAT0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0CR1</name>
+ <displayName>FLT0CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x100</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWFSEL</name>
+ <description>Analog watchdog fast mode
+ select</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FAST</name>
+ <description>Fast conversion mode selection for
+ regular conversions</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCH</name>
+ <description>Regular channel selection</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>RDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ regular conversion</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSYNC</name>
+ <description>Launch regular conversion synchronously
+ with DFSDM0</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCONT</name>
+ <description>Continuous mode selection for regular
+ conversions</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSWSTART</name>
+ <description>Software start of a conversion on the
+ regular channel</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEXTEN</name>
+ <description>Trigger enable and trigger edge
+ selection for injected conversions</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>JEXTSEL</name>
+ <description>Trigger signal selection for launching
+ injected conversions</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>JDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ injected channel group</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSCAN</name>
+ <description>Scanning conversion mode for injected
+ conversions</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSYNC</name>
+ <description>Launch an injected conversion
+ synchronously with the DFSDM0 JSWSTART
+ trigger</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSWSTART</name>
+ <description>Start a conversion of the injected group
+ of channels</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFEN</name>
+ <description>DFSDM enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0CR2</name>
+ <displayName>FLT0CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x104</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWDCH</name>
+ <description>Analog watchdog channel
+ selection</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>EXCH</name>
+ <description>Extremes detector channel
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABIE</name>
+ <description>Clock absence interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDIE</name>
+ <description>Short-circuit detector interrupt
+ enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDIE</name>
+ <description>Analog watchdog interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRIE</name>
+ <description>Regular data overrun interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRIE</name>
+ <description>Injected data overrun interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCIE</name>
+ <description>Regular end of conversion interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCIE</name>
+ <description>Injected end of conversion interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0ISR</name>
+ <displayName>FLT0ISR</displayName>
+ <description>interrupt and status register</description>
+ <addressOffset>0x108</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00FF0000</resetValue>
+ <fields>
+ <field>
+ <name>SCDF</name>
+ <description>short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABF</name>
+ <description>Clock absence flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RCIP</name>
+ <description>Regular conversion in progress
+ status</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JCIP</name>
+ <description>Injected conversion in progress
+ status</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDF</name>
+ <description>Analog watchdog</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRF</name>
+ <description>Regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRF</name>
+ <description>Injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCF</name>
+ <description>End of regular conversion
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCF</name>
+ <description>End of injected conversion
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0ICR</name>
+ <displayName>FLT0ICR</displayName>
+ <description>interrupt flag clear register</description>
+ <addressOffset>0x10C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRSCDF</name>
+ <description>Clear the short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRCKABF</name>
+ <description>Clear the clock absence
+ flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRROVRF</name>
+ <description>Clear the regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CLRJOVRF</name>
+ <description>Clear the injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0JCHGR</name>
+ <displayName>FLT0JCHGR</displayName>
+ <description>injected channel group selection
+ register</description>
+ <addressOffset>0x110</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000001</resetValue>
+ <fields>
+ <field>
+ <name>JCHG</name>
+ <description>Injected channel group
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0FCR</name>
+ <displayName>FLT0FCR</displayName>
+ <description>filter control register</description>
+ <addressOffset>0x114</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FORD</name>
+ <description>Sinc filter order</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>FOSR</name>
+ <description>Sinc filter oversampling ratio
+ (decimation rate)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>IOSR</name>
+ <description>Integrator oversampling ratio (averaging
+ length)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0JDATAR</name>
+ <displayName>FLT0JDATAR</displayName>
+ <description>data register for injected
+ group</description>
+ <addressOffset>0x118</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected group conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>JDATACH</name>
+ <description>Injected channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0RDATAR</name>
+ <displayName>FLT0RDATAR</displayName>
+ <description>data register for the regular
+ channel</description>
+ <addressOffset>0x11C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RDATA</name>
+ <description>Regular channel conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>RPEND</name>
+ <description>Regular channel pending
+ data</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RDATACH</name>
+ <description>Regular channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0AWHTR</name>
+ <displayName>FLT0AWHTR</displayName>
+ <description>analog watchdog high threshold
+ register</description>
+ <addressOffset>0x120</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHT</name>
+ <description>Analog watchdog high
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWH</name>
+ <description>Break signal assignment to analog
+ watchdog high threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0AWLTR</name>
+ <displayName>FLT0AWLTR</displayName>
+ <description>analog watchdog low threshold
+ register</description>
+ <addressOffset>0x124</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWLT</name>
+ <description>Analog watchdog low
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWL</name>
+ <description>Break signal assignment to analog
+ watchdog low threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0AWSR</name>
+ <displayName>FLT0AWSR</displayName>
+ <description>analog watchdog status
+ register</description>
+ <addressOffset>0x128</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHTF</name>
+ <description>Analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>AWLTF</name>
+ <description>Analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0AWCFR</name>
+ <displayName>FLT0AWCFR</displayName>
+ <description>analog watchdog clear flag
+ register</description>
+ <addressOffset>0x12C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRAWHTF</name>
+ <description>Clear the analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRAWLTF</name>
+ <description>Clear the analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0EXMAX</name>
+ <displayName>FLT0EXMAX</displayName>
+ <description>Extremes detector maximum
+ register</description>
+ <addressOffset>0x130</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x80000000</resetValue>
+ <fields>
+ <field>
+ <name>EXMAX</name>
+ <description>Extremes detector maximum
+ value</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMAXCH</name>
+ <description>Extremes detector maximum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0EXMIN</name>
+ <displayName>FLT0EXMIN</displayName>
+ <description>Extremes detector minimum
+ register</description>
+ <addressOffset>0x134</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x7FFFFF00</resetValue>
+ <fields>
+ <field>
+ <name>EXMIN</name>
+ <description>EXMIN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMINCH</name>
+ <description>Extremes detector minimum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT0CNVTIMR</name>
+ <displayName>FLT0CNVTIMR</displayName>
+ <description>conversion timer register</description>
+ <addressOffset>0x138</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNVCNT</name>
+ <description>28-bit timer counting conversion time t
+ = CNVCNT[27:0] / fDFSDM_CKIN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>28</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1CR1</name>
+ <displayName>FLT1CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x180</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWFSEL</name>
+ <description>Analog watchdog fast mode
+ select</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FAST</name>
+ <description>Fast conversion mode selection for
+ regular conversions</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCH</name>
+ <description>Regular channel selection</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>RDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ regular conversion</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSYNC</name>
+ <description>Launch regular conversion synchronously
+ with DFSDM0</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCONT</name>
+ <description>Continuous mode selection for regular
+ conversions</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSWSTART</name>
+ <description>Software start of a conversion on the
+ regular channel</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEXTEN</name>
+ <description>Trigger enable and trigger edge
+ selection for injected conversions</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>JEXTSEL</name>
+ <description>Trigger signal selection for launching
+ injected conversions</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>JDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ injected channel group</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSCAN</name>
+ <description>Scanning conversion mode for injected
+ conversions</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSYNC</name>
+ <description>Launch an injected conversion
+ synchronously with the DFSDM0 JSWSTART
+ trigger</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSWSTART</name>
+ <description>Start a conversion of the injected group
+ of channels</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFEN</name>
+ <description>DFSDM enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1CR2</name>
+ <displayName>FLT1CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x184</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWDCH</name>
+ <description>Analog watchdog channel
+ selection</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>EXCH</name>
+ <description>Extremes detector channel
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABIE</name>
+ <description>Clock absence interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDIE</name>
+ <description>Short-circuit detector interrupt
+ enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDIE</name>
+ <description>Analog watchdog interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRIE</name>
+ <description>Regular data overrun interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRIE</name>
+ <description>Injected data overrun interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCIE</name>
+ <description>Regular end of conversion interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCIE</name>
+ <description>Injected end of conversion interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1ISR</name>
+ <displayName>FLT1ISR</displayName>
+ <description>interrupt and status register</description>
+ <addressOffset>0x188</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00FF0000</resetValue>
+ <fields>
+ <field>
+ <name>SCDF</name>
+ <description>short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABF</name>
+ <description>Clock absence flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RCIP</name>
+ <description>Regular conversion in progress
+ status</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JCIP</name>
+ <description>Injected conversion in progress
+ status</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDF</name>
+ <description>Analog watchdog</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRF</name>
+ <description>Regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRF</name>
+ <description>Injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCF</name>
+ <description>End of regular conversion
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCF</name>
+ <description>End of injected conversion
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1ICR</name>
+ <displayName>FLT1ICR</displayName>
+ <description>interrupt flag clear register</description>
+ <addressOffset>0x18C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRSCDF</name>
+ <description>Clear the short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRCKABF</name>
+ <description>Clear the clock absence
+ flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRROVRF</name>
+ <description>Clear the regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CLRJOVRF</name>
+ <description>Clear the injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1JCHGR</name>
+ <displayName>FLT1JCHGR</displayName>
+ <description>injected channel group selection
+ register</description>
+ <addressOffset>0x190</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000001</resetValue>
+ <fields>
+ <field>
+ <name>JCHG</name>
+ <description>Injected channel group
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1FCR</name>
+ <displayName>FLT1FCR</displayName>
+ <description>filter control register</description>
+ <addressOffset>0x194</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FORD</name>
+ <description>Sinc filter order</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>FOSR</name>
+ <description>Sinc filter oversampling ratio
+ (decimation rate)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>IOSR</name>
+ <description>Integrator oversampling ratio (averaging
+ length)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1JDATAR</name>
+ <displayName>FLT1JDATAR</displayName>
+ <description>data register for injected
+ group</description>
+ <addressOffset>0x198</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected group conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>JDATACH</name>
+ <description>Injected channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1RDATAR</name>
+ <displayName>FLT1RDATAR</displayName>
+ <description>data register for the regular
+ channel</description>
+ <addressOffset>0x19C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RDATA</name>
+ <description>Regular channel conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>RPEND</name>
+ <description>Regular channel pending
+ data</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RDATACH</name>
+ <description>Regular channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1AWHTR</name>
+ <displayName>FLT1AWHTR</displayName>
+ <description>analog watchdog high threshold
+ register</description>
+ <addressOffset>0x1A0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHT</name>
+ <description>Analog watchdog high
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWH</name>
+ <description>Break signal assignment to analog
+ watchdog high threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1AWLTR</name>
+ <displayName>FLT1AWLTR</displayName>
+ <description>analog watchdog low threshold
+ register</description>
+ <addressOffset>0x1A4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWLT</name>
+ <description>Analog watchdog low
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWL</name>
+ <description>Break signal assignment to analog
+ watchdog low threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1AWSR</name>
+ <displayName>FLT1AWSR</displayName>
+ <description>analog watchdog status
+ register</description>
+ <addressOffset>0x1A8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHTF</name>
+ <description>Analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>AWLTF</name>
+ <description>Analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1AWCFR</name>
+ <displayName>FLT1AWCFR</displayName>
+ <description>analog watchdog clear flag
+ register</description>
+ <addressOffset>0x1AC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRAWHTF</name>
+ <description>Clear the analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRAWLTF</name>
+ <description>Clear the analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1EXMAX</name>
+ <displayName>FLT1EXMAX</displayName>
+ <description>Extremes detector maximum
+ register</description>
+ <addressOffset>0x1B0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x80000000</resetValue>
+ <fields>
+ <field>
+ <name>EXMAX</name>
+ <description>Extremes detector maximum
+ value</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMAXCH</name>
+ <description>Extremes detector maximum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1EXMIN</name>
+ <displayName>FLT1EXMIN</displayName>
+ <description>Extremes detector minimum
+ register</description>
+ <addressOffset>0x1B4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x7FFFFF00</resetValue>
+ <fields>
+ <field>
+ <name>EXMIN</name>
+ <description>EXMIN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMINCH</name>
+ <description>Extremes detector minimum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT1CNVTIMR</name>
+ <displayName>FLT1CNVTIMR</displayName>
+ <description>conversion timer register</description>
+ <addressOffset>0x1B8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNVCNT</name>
+ <description>28-bit timer counting conversion time t
+ = CNVCNT[27:0] / fDFSDM_CKIN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>28</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2CR1</name>
+ <displayName>FLT2CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x200</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWFSEL</name>
+ <description>Analog watchdog fast mode
+ select</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FAST</name>
+ <description>Fast conversion mode selection for
+ regular conversions</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCH</name>
+ <description>Regular channel selection</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>RDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ regular conversion</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSYNC</name>
+ <description>Launch regular conversion synchronously
+ with DFSDM0</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCONT</name>
+ <description>Continuous mode selection for regular
+ conversions</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSWSTART</name>
+ <description>Software start of a conversion on the
+ regular channel</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEXTEN</name>
+ <description>Trigger enable and trigger edge
+ selection for injected conversions</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>JEXTSEL</name>
+ <description>Trigger signal selection for launching
+ injected conversions</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>JDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ injected channel group</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSCAN</name>
+ <description>Scanning conversion mode for injected
+ conversions</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSYNC</name>
+ <description>Launch an injected conversion
+ synchronously with the DFSDM0 JSWSTART
+ trigger</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSWSTART</name>
+ <description>Start a conversion of the injected group
+ of channels</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFEN</name>
+ <description>DFSDM enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2CR2</name>
+ <displayName>FLT2CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x204</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWDCH</name>
+ <description>Analog watchdog channel
+ selection</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>EXCH</name>
+ <description>Extremes detector channel
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABIE</name>
+ <description>Clock absence interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDIE</name>
+ <description>Short-circuit detector interrupt
+ enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDIE</name>
+ <description>Analog watchdog interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRIE</name>
+ <description>Regular data overrun interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRIE</name>
+ <description>Injected data overrun interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCIE</name>
+ <description>Regular end of conversion interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCIE</name>
+ <description>Injected end of conversion interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2ISR</name>
+ <displayName>FLT2ISR</displayName>
+ <description>interrupt and status register</description>
+ <addressOffset>0x208</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00FF0000</resetValue>
+ <fields>
+ <field>
+ <name>SCDF</name>
+ <description>short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABF</name>
+ <description>Clock absence flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RCIP</name>
+ <description>Regular conversion in progress
+ status</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JCIP</name>
+ <description>Injected conversion in progress
+ status</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDF</name>
+ <description>Analog watchdog</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRF</name>
+ <description>Regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRF</name>
+ <description>Injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCF</name>
+ <description>End of regular conversion
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCF</name>
+ <description>End of injected conversion
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2ICR</name>
+ <displayName>FLT2ICR</displayName>
+ <description>interrupt flag clear register</description>
+ <addressOffset>0x20C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRSCDF</name>
+ <description>Clear the short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRCKABF</name>
+ <description>Clear the clock absence
+ flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRROVRF</name>
+ <description>Clear the regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CLRJOVRF</name>
+ <description>Clear the injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2JCHGR</name>
+ <displayName>FLT2JCHGR</displayName>
+ <description>injected channel group selection
+ register</description>
+ <addressOffset>0x210</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000001</resetValue>
+ <fields>
+ <field>
+ <name>JCHG</name>
+ <description>Injected channel group
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2FCR</name>
+ <displayName>FLT2FCR</displayName>
+ <description>filter control register</description>
+ <addressOffset>0x214</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FORD</name>
+ <description>Sinc filter order</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>FOSR</name>
+ <description>Sinc filter oversampling ratio
+ (decimation rate)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>IOSR</name>
+ <description>Integrator oversampling ratio (averaging
+ length)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2JDATAR</name>
+ <displayName>FLT2JDATAR</displayName>
+ <description>data register for injected
+ group</description>
+ <addressOffset>0x218</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected group conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>JDATACH</name>
+ <description>Injected channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2RDATAR</name>
+ <displayName>FLT2RDATAR</displayName>
+ <description>data register for the regular
+ channel</description>
+ <addressOffset>0x21C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RDATA</name>
+ <description>Regular channel conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>RPEND</name>
+ <description>Regular channel pending
+ data</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RDATACH</name>
+ <description>Regular channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2AWHTR</name>
+ <displayName>FLT2AWHTR</displayName>
+ <description>analog watchdog high threshold
+ register</description>
+ <addressOffset>0x220</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHT</name>
+ <description>Analog watchdog high
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWH</name>
+ <description>Break signal assignment to analog
+ watchdog high threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2AWLTR</name>
+ <displayName>FLT2AWLTR</displayName>
+ <description>analog watchdog low threshold
+ register</description>
+ <addressOffset>0x224</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWLT</name>
+ <description>Analog watchdog low
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWL</name>
+ <description>Break signal assignment to analog
+ watchdog low threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2AWSR</name>
+ <displayName>FLT2AWSR</displayName>
+ <description>analog watchdog status
+ register</description>
+ <addressOffset>0x228</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHTF</name>
+ <description>Analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>AWLTF</name>
+ <description>Analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2AWCFR</name>
+ <displayName>FLT2AWCFR</displayName>
+ <description>analog watchdog clear flag
+ register</description>
+ <addressOffset>0x22C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRAWHTF</name>
+ <description>Clear the analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRAWLTF</name>
+ <description>Clear the analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2EXMAX</name>
+ <displayName>FLT2EXMAX</displayName>
+ <description>Extremes detector maximum
+ register</description>
+ <addressOffset>0x230</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x80000000</resetValue>
+ <fields>
+ <field>
+ <name>EXMAX</name>
+ <description>Extremes detector maximum
+ value</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMAXCH</name>
+ <description>Extremes detector maximum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2EXMIN</name>
+ <displayName>FLT2EXMIN</displayName>
+ <description>Extremes detector minimum
+ register</description>
+ <addressOffset>0x234</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x7FFFFF00</resetValue>
+ <fields>
+ <field>
+ <name>EXMIN</name>
+ <description>EXMIN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMINCH</name>
+ <description>Extremes detector minimum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT2CNVTIMR</name>
+ <displayName>FLT2CNVTIMR</displayName>
+ <description>conversion timer register</description>
+ <addressOffset>0x238</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNVCNT</name>
+ <description>28-bit timer counting conversion time t
+ = CNVCNT[27:0] / fDFSDM_CKIN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>28</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3CR1</name>
+ <displayName>FLT3CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x280</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWFSEL</name>
+ <description>Analog watchdog fast mode
+ select</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FAST</name>
+ <description>Fast conversion mode selection for
+ regular conversions</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCH</name>
+ <description>Regular channel selection</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>RDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ regular conversion</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSYNC</name>
+ <description>Launch regular conversion synchronously
+ with DFSDM0</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RCONT</name>
+ <description>Continuous mode selection for regular
+ conversions</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RSWSTART</name>
+ <description>Software start of a conversion on the
+ regular channel</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEXTEN</name>
+ <description>Trigger enable and trigger edge
+ selection for injected conversions</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>JEXTSEL</name>
+ <description>Trigger signal selection for launching
+ injected conversions</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>JDMAEN</name>
+ <description>DMA channel enabled to read data for the
+ injected channel group</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSCAN</name>
+ <description>Scanning conversion mode for injected
+ conversions</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSYNC</name>
+ <description>Launch an injected conversion
+ synchronously with the DFSDM0 JSWSTART
+ trigger</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JSWSTART</name>
+ <description>Start a conversion of the injected group
+ of channels</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFEN</name>
+ <description>DFSDM enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3CR2</name>
+ <displayName>FLT3CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x284</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWDCH</name>
+ <description>Analog watchdog channel
+ selection</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>EXCH</name>
+ <description>Extremes detector channel
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABIE</name>
+ <description>Clock absence interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCDIE</name>
+ <description>Short-circuit detector interrupt
+ enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDIE</name>
+ <description>Analog watchdog interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRIE</name>
+ <description>Regular data overrun interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRIE</name>
+ <description>Injected data overrun interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCIE</name>
+ <description>Regular end of conversion interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCIE</name>
+ <description>Injected end of conversion interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3ISR</name>
+ <displayName>FLT3ISR</displayName>
+ <description>interrupt and status register</description>
+ <addressOffset>0x288</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00FF0000</resetValue>
+ <fields>
+ <field>
+ <name>SCDF</name>
+ <description>short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CKABF</name>
+ <description>Clock absence flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RCIP</name>
+ <description>Regular conversion in progress
+ status</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JCIP</name>
+ <description>Injected conversion in progress
+ status</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWDF</name>
+ <description>Analog watchdog</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ROVRF</name>
+ <description>Regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JOVRF</name>
+ <description>Injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>REOCF</name>
+ <description>End of regular conversion
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>JEOCF</name>
+ <description>End of injected conversion
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3ICR</name>
+ <displayName>FLT3ICR</displayName>
+ <description>interrupt flag clear register</description>
+ <addressOffset>0x28C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRSCDF</name>
+ <description>Clear the short-circuit detector
+ flag</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRCKABF</name>
+ <description>Clear the clock absence
+ flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRROVRF</name>
+ <description>Clear the regular conversion overrun
+ flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CLRJOVRF</name>
+ <description>Clear the injected conversion overrun
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3JCHGR</name>
+ <displayName>FLT3JCHGR</displayName>
+ <description>injected channel group selection
+ register</description>
+ <addressOffset>0x290</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000001</resetValue>
+ <fields>
+ <field>
+ <name>JCHG</name>
+ <description>Injected channel group
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3FCR</name>
+ <displayName>FLT3FCR</displayName>
+ <description>filter control register</description>
+ <addressOffset>0x294</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FORD</name>
+ <description>Sinc filter order</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>FOSR</name>
+ <description>Sinc filter oversampling ratio
+ (decimation rate)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>IOSR</name>
+ <description>Integrator oversampling ratio (averaging
+ length)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3JDATAR</name>
+ <displayName>FLT3JDATAR</displayName>
+ <description>data register for injected
+ group</description>
+ <addressOffset>0x298</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>JDATA</name>
+ <description>Injected group conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>JDATACH</name>
+ <description>Injected channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3RDATAR</name>
+ <displayName>FLT3RDATAR</displayName>
+ <description>data register for the regular
+ channel</description>
+ <addressOffset>0x29C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RDATA</name>
+ <description>Regular channel conversion
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>RPEND</name>
+ <description>Regular channel pending
+ data</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RDATACH</name>
+ <description>Regular channel most recently
+ converted</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3AWHTR</name>
+ <displayName>FLT3AWHTR</displayName>
+ <description>analog watchdog high threshold
+ register</description>
+ <addressOffset>0x2A0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHT</name>
+ <description>Analog watchdog high
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWH</name>
+ <description>Break signal assignment to analog
+ watchdog high threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3AWLTR</name>
+ <displayName>FLT3AWLTR</displayName>
+ <description>analog watchdog low threshold
+ register</description>
+ <addressOffset>0x2A4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWLT</name>
+ <description>Analog watchdog low
+ threshold</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>BKAWL</name>
+ <description>Break signal assignment to analog
+ watchdog low threshold event</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3AWSR</name>
+ <displayName>FLT3AWSR</displayName>
+ <description>analog watchdog status
+ register</description>
+ <addressOffset>0x2A8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AWHTF</name>
+ <description>Analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>AWLTF</name>
+ <description>Analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3AWCFR</name>
+ <displayName>FLT3AWCFR</displayName>
+ <description>analog watchdog clear flag
+ register</description>
+ <addressOffset>0x2AC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CLRAWHTF</name>
+ <description>Clear the analog watchdog high threshold
+ flag</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>CLRAWLTF</name>
+ <description>Clear the analog watchdog low threshold
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3EXMAX</name>
+ <displayName>FLT3EXMAX</displayName>
+ <description>Extremes detector maximum
+ register</description>
+ <addressOffset>0x2B0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x80000000</resetValue>
+ <fields>
+ <field>
+ <name>EXMAX</name>
+ <description>Extremes detector maximum
+ value</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMAXCH</name>
+ <description>Extremes detector maximum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3EXMIN</name>
+ <displayName>FLT3EXMIN</displayName>
+ <description>Extremes detector minimum
+ register</description>
+ <addressOffset>0x2B4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x7FFFFF00</resetValue>
+ <fields>
+ <field>
+ <name>EXMIN</name>
+ <description>EXMIN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>24</bitWidth>
+ </field>
+ <field>
+ <name>EXMINCH</name>
+ <description>Extremes detector minimum data
+ channel</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLT3CNVTIMR</name>
+ <displayName>FLT3CNVTIMR</displayName>
+ <description>conversion timer register</description>
+ <addressOffset>0x2B8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNVCNT</name>
+ <description>28-bit timer counting conversion time t
+ = CNVCNT[27:0] / fDFSDM_CKIN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>28</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="DFSDM1">
+ <name>DFSDM2</name>
+ <baseAddress>0x40016400</baseAddress>
+ <interrupt>
+ <name>DFSDM2_FILTER2</name>
+ <description>DFSDM2 SD filter 2 global
+ interrupt</description>
+ <value>99</value>
+ </interrupt>
+ <interrupt>
+ <name>DFSDM2_FILTER4</name>
+ <description>DFSDM2 SD filter 4 global
+ interrupt</description>
+ <value>101</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>TIM6</name>
+ <description>Basic timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40001000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM6_GLB_IT_DAC1_DAC2</name>
+ <description>TIM6 global and DAC12 underrun
+ interrupts</description>
+ <value>54</value>
+ </interrupt>
+ <interrupt>
+ <name>DFSDM2_FILTER1</name>
+ <description>DFSDM2 SD filter 1 global
+ interrupt</description>
+ <value>98</value>
+ </interrupt>
+ <interrupt>
+ <name>DFSDM2_FILTER3</name>
+ <description>DFSDM2 SD filter 3 global
+ interrupt</description>
+ <value>100</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPM</name>
+ <description>One-pulse mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIFREMAP</name>
+ <description>UIF status bit remapping</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>MMS</name>
+ <description>Master mode selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>UDE</name>
+ <description>Update DMA request enable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>Low counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>UIFCPY</name>
+ <description>UIF Copy</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Low Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="TIM6">
+ <name>TIM7</name>
+ <baseAddress>0x40001400</baseAddress>
+ <interrupt>
+ <name>TIM7</name>
+ <description>TIM7 global interrupt</description>
+ <value>55</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>TIM12</name>
+ <description>General purpose timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40001800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM8_BRK_TIM12</name>
+ <description>Timer 12 global interrupt</description>
+ <value>43</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OPM</name>
+ <description>One-pulse mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SMCR</name>
+ <displayName>SMCR</displayName>
+ <description>slave mode control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>MSM</name>
+ <description>Master/Slave mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TS</name>
+ <description>Trigger selection</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SMS</name>
+ <description>Slave mode selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TIE</name>
+ <description>Trigger interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IE</name>
+ <description>Capture/Compare 2 interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC2OF</name>
+ <description>Capture/compare 2 overcapture
+ flag</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIF</name>
+ <description>Trigger interrupt flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IF</name>
+ <description>Capture/Compare 2 interrupt
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TG</name>
+ <description>Trigger generation</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2G</name>
+ <description>Capture/compare 2
+ generation</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OC2M</name>
+ <description>Output Compare 2 mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC2PE</name>
+ <description>Output Compare 2 preload
+ enable</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC2FE</name>
+ <description>Output Compare 2 fast
+ enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC1M</name>
+ <description>Output Compare 1 mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>Output Compare 1 preload
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>Output Compare 1 fast
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register 1 (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC2F</name>
+ <description>Input capture 2 filter</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC2PSC</name>
+ <description>Input capture 2 prescaler</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC2S</name>
+ <description>Capture/Compare 2
+ selection</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>IC1PSC</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC2NP</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2P</name>
+ <description>Capture/Compare 2 output
+ Polarity</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2E</name>
+ <description>Capture/Compare 2 output
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1</name>
+ <description>Capture/Compare 1 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR2</name>
+ <displayName>CCR2</displayName>
+ <description>capture/compare register 2</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR2</name>
+ <description>Capture/Compare 2 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>TIM13</name>
+ <description>General purpose timers</description>
+ <groupName>TIM</groupName>
+ <baseAddress>0x40001C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM8_UP_TIM13</name>
+ <description>Timer 13 global interrupt</description>
+ <value>44</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CKD</name>
+ <description>Clock division</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ARPE</name>
+ <description>Auto-reload preload enable</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>URS</name>
+ <description>Update request source</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UDIS</name>
+ <description>Update disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Counter enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIER</name>
+ <displayName>DIER</displayName>
+ <description>DMA/Interrupt enable register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1IE</name>
+ <description>Capture/Compare 1 interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIE</name>
+ <description>Update interrupt enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1OF</name>
+ <description>Capture/Compare 1 overcapture
+ flag</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1IF</name>
+ <description>Capture/compare 1 interrupt
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UIF</name>
+ <description>Update interrupt flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EGR</name>
+ <displayName>EGR</displayName>
+ <description>event generation register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1G</name>
+ <description>Capture/compare 1
+ generation</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UG</name>
+ <description>Update generation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Output</name>
+ <displayName>CCMR1_Output</displayName>
+ <description>capture/compare mode register (output
+ mode)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OC1FE</name>
+ <description>Output compare 1 fast
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1PE</name>
+ <description>Output Compare 1 preload
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OC1M</name>
+ <description>Output Compare 1 mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCMR1_Input</name>
+ <displayName>CCMR1_Input</displayName>
+ <description>capture/compare mode register (input
+ mode)</description>
+ <alternateRegister>CCMR1_Output</alternateRegister>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IC1F</name>
+ <description>Input capture 1 filter</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>IC1PSC</name>
+ <description>Input capture 1 prescaler</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CC1S</name>
+ <description>Capture/Compare 1
+ selection</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCER</name>
+ <displayName>CCER</displayName>
+ <description>capture/compare enable
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>CC1NP</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1P</name>
+ <description>Capture/Compare 1 output
+ Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC1E</name>
+ <description>Capture/Compare 1 output
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>counter</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSC</name>
+ <displayName>PSC</displayName>
+ <description>prescaler</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PSC</name>
+ <description>Prescaler value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>auto-reload register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Auto-reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR1</name>
+ <displayName>CCR1</displayName>
+ <description>capture/compare register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CCR1</name>
+ <description>Capture/Compare 1 value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="TIM13">
+ <name>TIM14</name>
+ <baseAddress>0x40002000</baseAddress>
+ <interrupt>
+ <name>TIM8_TRG_COM_TIM14</name>
+ <description>Timer 14 global interrupt</description>
+ <value>45</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>RNG</name>
+ <description>Random number generator</description>
+ <groupName>RNG</groupName>
+ <baseAddress>0x50060800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IE</name>
+ <description>Interrupt enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RNGEN</name>
+ <description>Random number generator
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SEIS</name>
+ <description>Seed error interrupt
+ status</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CEIS</name>
+ <description>Clock error interrupt
+ status</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SECS</name>
+ <description>Seed error current status</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>CECS</name>
+ <description>Clock error current status</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DRDY</name>
+ <description>Data ready</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>data register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RNDATA</name>
+ <description>Random data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>CAN1</name>
+ <description>Controller area network</description>
+ <groupName>CAN</groupName>
+ <baseAddress>0x40006400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>CAN1_TX</name>
+ <description>CAN1 TX interrupts</description>
+ <value>19</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN1_RX0</name>
+ <description>CAN1 RX0 interrupts</description>
+ <value>20</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN1_RX1</name>
+ <description>CAN1 RX1 interrupts</description>
+ <value>21</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN1_SCE</name>
+ <description>CAN1 SCE interrupt</description>
+ <value>22</value>
+ </interrupt>
+ <interrupt>
+ <name>RNG</name>
+ <description>Rng global interrupt</description>
+ <value>80</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>MCR</name>
+ <displayName>MCR</displayName>
+ <description>master control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00010002</resetValue>
+ <fields>
+ <field>
+ <name>DBF</name>
+ <description>DBF</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RESET</name>
+ <description>RESET</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TTCM</name>
+ <description>TTCM</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ABOM</name>
+ <description>ABOM</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AWUM</name>
+ <description>AWUM</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NART</name>
+ <description>NART</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RFLM</name>
+ <description>RFLM</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFP</name>
+ <description>TXFP</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SLEEP</name>
+ <description>SLEEP</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>INRQ</name>
+ <description>INRQ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MSR</name>
+ <displayName>MSR</displayName>
+ <description>master status register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000C02</resetValue>
+ <fields>
+ <field>
+ <name>RX</name>
+ <description>RX</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SAMP</name>
+ <description>SAMP</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>RXM</name>
+ <description>RXM</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TXM</name>
+ <description>TXM</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SLAKI</name>
+ <description>SLAKI</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>WKUI</name>
+ <description>WKUI</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ERRI</name>
+ <description>ERRI</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SLAK</name>
+ <description>SLAK</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>INAK</name>
+ <description>INAK</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TSR</name>
+ <displayName>TSR</displayName>
+ <description>transmit status register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x1C000000</resetValue>
+ <fields>
+ <field>
+ <name>LOW2</name>
+ <description>Lowest priority flag for mailbox
+ 2</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>LOW1</name>
+ <description>Lowest priority flag for mailbox
+ 1</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>LOW0</name>
+ <description>Lowest priority flag for mailbox
+ 0</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TME2</name>
+ <description>Lowest priority flag for mailbox
+ 2</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TME1</name>
+ <description>Lowest priority flag for mailbox
+ 1</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TME0</name>
+ <description>Lowest priority flag for mailbox
+ 0</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>CODE</name>
+ <description>CODE</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ABRQ2</name>
+ <description>ABRQ2</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TERR2</name>
+ <description>TERR2</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ALST2</name>
+ <description>ALST2</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXOK2</name>
+ <description>TXOK2</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RQCP2</name>
+ <description>RQCP2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ABRQ1</name>
+ <description>ABRQ1</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TERR1</name>
+ <description>TERR1</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ALST1</name>
+ <description>ALST1</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXOK1</name>
+ <description>TXOK1</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RQCP1</name>
+ <description>RQCP1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ABRQ0</name>
+ <description>ABRQ0</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TERR0</name>
+ <description>TERR0</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ALST0</name>
+ <description>ALST0</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXOK0</name>
+ <description>TXOK0</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RQCP0</name>
+ <description>RQCP0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RF0R</name>
+ <displayName>RF0R</displayName>
+ <description>receive FIFO 0 register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RFOM0</name>
+ <description>RFOM0</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FOVR0</name>
+ <description>FOVR0</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FULL0</name>
+ <description>FULL0</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FMP0</name>
+ <description>FMP0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RF1R</name>
+ <displayName>RF1R</displayName>
+ <description>receive FIFO 1 register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RFOM1</name>
+ <description>RFOM1</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FOVR1</name>
+ <description>FOVR1</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FULL1</name>
+ <description>FULL1</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FMP1</name>
+ <description>FMP1</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IER</name>
+ <displayName>IER</displayName>
+ <description>interrupt enable register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SLKIE</name>
+ <description>SLKIE</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WKUIE</name>
+ <description>WKUIE</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRIE</name>
+ <description>ERRIE</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LECIE</name>
+ <description>LECIE</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BOFIE</name>
+ <description>BOFIE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPVIE</name>
+ <description>EPVIE</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EWGIE</name>
+ <description>EWGIE</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FOVIE1</name>
+ <description>FOVIE1</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFIE1</name>
+ <description>FFIE1</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FMPIE1</name>
+ <description>FMPIE1</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FOVIE0</name>
+ <description>FOVIE0</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFIE0</name>
+ <description>FFIE0</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FMPIE0</name>
+ <description>FMPIE0</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TMEIE</name>
+ <description>TMEIE</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ESR</name>
+ <displayName>ESR</displayName>
+ <description>interrupt enable register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>REC</name>
+ <description>REC</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TEC</name>
+ <description>TEC</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>LEC</name>
+ <description>LEC</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BOFF</name>
+ <description>BOFF</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EPVF</name>
+ <description>EPVF</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EWGF</name>
+ <description>EWGF</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BTR</name>
+ <displayName>BTR</displayName>
+ <description>bit timing register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SILM</name>
+ <description>SILM</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LBKM</name>
+ <description>LBKM</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SJW</name>
+ <description>SJW</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>TS2</name>
+ <description>TS2</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TS1</name>
+ <description>TS1</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>BRP</name>
+ <description>BRP</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TI0R</name>
+ <displayName>TI0R</displayName>
+ <description>TX mailbox identifier register</description>
+ <addressOffset>0x180</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>STID</name>
+ <description>STID</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EXID</name>
+ <description>EXID</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>18</bitWidth>
+ </field>
+ <field>
+ <name>IDE</name>
+ <description>IDE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTR</name>
+ <description>RTR</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXRQ</name>
+ <description>TXRQ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDT0R</name>
+ <displayName>TDT0R</displayName>
+ <description>mailbox data length control and time stamp
+ register</description>
+ <addressOffset>0x184</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIME</name>
+ <description>TIME</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>TGT</name>
+ <description>TGT</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DLC</name>
+ <description>DLC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDL0R</name>
+ <displayName>TDL0R</displayName>
+ <description>mailbox data low register</description>
+ <addressOffset>0x188</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA3</name>
+ <description>DATA3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA2</name>
+ <description>DATA2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA1</name>
+ <description>DATA1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA0</name>
+ <description>DATA0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDH0R</name>
+ <displayName>TDH0R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x18C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA7</name>
+ <description>DATA7</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA6</name>
+ <description>DATA6</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA5</name>
+ <description>DATA5</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA4</name>
+ <description>DATA4</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TI1R</name>
+ <displayName>TI1R</displayName>
+ <description>mailbox identifier register</description>
+ <addressOffset>0x190</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>STID</name>
+ <description>STID</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EXID</name>
+ <description>EXID</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>18</bitWidth>
+ </field>
+ <field>
+ <name>IDE</name>
+ <description>IDE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTR</name>
+ <description>RTR</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXRQ</name>
+ <description>TXRQ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDT1R</name>
+ <displayName>TDT1R</displayName>
+ <description>mailbox data length control and time stamp
+ register</description>
+ <addressOffset>0x194</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIME</name>
+ <description>TIME</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>TGT</name>
+ <description>TGT</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DLC</name>
+ <description>DLC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDL1R</name>
+ <displayName>TDL1R</displayName>
+ <description>mailbox data low register</description>
+ <addressOffset>0x198</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA3</name>
+ <description>DATA3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA2</name>
+ <description>DATA2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA1</name>
+ <description>DATA1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA0</name>
+ <description>DATA0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDH1R</name>
+ <displayName>TDH1R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x19C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA7</name>
+ <description>DATA7</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA6</name>
+ <description>DATA6</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA5</name>
+ <description>DATA5</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA4</name>
+ <description>DATA4</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TI2R</name>
+ <displayName>TI2R</displayName>
+ <description>mailbox identifier register</description>
+ <addressOffset>0x1A0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>STID</name>
+ <description>STID</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EXID</name>
+ <description>EXID</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>18</bitWidth>
+ </field>
+ <field>
+ <name>IDE</name>
+ <description>IDE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTR</name>
+ <description>RTR</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXRQ</name>
+ <description>TXRQ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDT2R</name>
+ <displayName>TDT2R</displayName>
+ <description>mailbox data length control and time stamp
+ register</description>
+ <addressOffset>0x1A4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIME</name>
+ <description>TIME</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>TGT</name>
+ <description>TGT</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DLC</name>
+ <description>DLC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDL2R</name>
+ <displayName>TDL2R</displayName>
+ <description>mailbox data low register</description>
+ <addressOffset>0x1A8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA3</name>
+ <description>DATA3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA2</name>
+ <description>DATA2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA1</name>
+ <description>DATA1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA0</name>
+ <description>DATA0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TDH2R</name>
+ <displayName>TDH2R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x1AC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA7</name>
+ <description>DATA7</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA6</name>
+ <description>DATA6</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA5</name>
+ <description>DATA5</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA4</name>
+ <description>DATA4</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RI0R</name>
+ <displayName>RI0R</displayName>
+ <description>receive FIFO mailbox identifier
+ register</description>
+ <addressOffset>0x1B0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>STID</name>
+ <description>STID</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EXID</name>
+ <description>EXID</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>18</bitWidth>
+ </field>
+ <field>
+ <name>IDE</name>
+ <description>IDE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTR</name>
+ <description>RTR</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDT0R</name>
+ <displayName>RDT0R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x1B4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIME</name>
+ <description>TIME</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>FMI</name>
+ <description>FMI</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DLC</name>
+ <description>DLC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDL0R</name>
+ <displayName>RDL0R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x1B8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA3</name>
+ <description>DATA3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA2</name>
+ <description>DATA2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA1</name>
+ <description>DATA1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA0</name>
+ <description>DATA0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDH0R</name>
+ <displayName>RDH0R</displayName>
+ <description>receive FIFO mailbox data high
+ register</description>
+ <addressOffset>0x1BC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA7</name>
+ <description>DATA7</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA6</name>
+ <description>DATA6</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA5</name>
+ <description>DATA5</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA4</name>
+ <description>DATA4</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RI1R</name>
+ <displayName>RI1R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x1C0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>STID</name>
+ <description>STID</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EXID</name>
+ <description>EXID</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>18</bitWidth>
+ </field>
+ <field>
+ <name>IDE</name>
+ <description>IDE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RTR</name>
+ <description>RTR</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDT1R</name>
+ <displayName>RDT1R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x1C4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIME</name>
+ <description>TIME</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>FMI</name>
+ <description>FMI</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DLC</name>
+ <description>DLC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDL1R</name>
+ <displayName>RDL1R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x1C8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA3</name>
+ <description>DATA3</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA2</name>
+ <description>DATA2</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA1</name>
+ <description>DATA1</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA0</name>
+ <description>DATA0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDH1R</name>
+ <displayName>RDH1R</displayName>
+ <description>mailbox data high register</description>
+ <addressOffset>0x1CC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA7</name>
+ <description>DATA7</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA6</name>
+ <description>DATA6</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA5</name>
+ <description>DATA5</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DATA4</name>
+ <description>DATA4</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMR</name>
+ <displayName>FMR</displayName>
+ <description>filter master register</description>
+ <addressOffset>0x200</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x2A1C0E01</resetValue>
+ <fields>
+ <field>
+ <name>CAN2SB</name>
+ <description>CAN2SB</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ <field>
+ <name>FINIT</name>
+ <description>FINIT</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FM1R</name>
+ <displayName>FM1R</displayName>
+ <description>filter mode register</description>
+ <addressOffset>0x204</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FBM0</name>
+ <description>Filter mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM1</name>
+ <description>Filter mode</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM2</name>
+ <description>Filter mode</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM3</name>
+ <description>Filter mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM4</name>
+ <description>Filter mode</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM5</name>
+ <description>Filter mode</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM6</name>
+ <description>Filter mode</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM7</name>
+ <description>Filter mode</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM8</name>
+ <description>Filter mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM9</name>
+ <description>Filter mode</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM10</name>
+ <description>Filter mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM11</name>
+ <description>Filter mode</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM12</name>
+ <description>Filter mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM13</name>
+ <description>Filter mode</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM14</name>
+ <description>Filter mode</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM15</name>
+ <description>Filter mode</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM16</name>
+ <description>Filter mode</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM17</name>
+ <description>Filter mode</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM18</name>
+ <description>Filter mode</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM19</name>
+ <description>Filter mode</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM20</name>
+ <description>Filter mode</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM21</name>
+ <description>Filter mode</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM22</name>
+ <description>Filter mode</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM23</name>
+ <description>Filter mode</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM24</name>
+ <description>Filter mode</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM25</name>
+ <description>Filter mode</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM26</name>
+ <description>Filter mode</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FBM27</name>
+ <description>Filter mode</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS1R</name>
+ <displayName>FS1R</displayName>
+ <description>filter scale register</description>
+ <addressOffset>0x20C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FSC0</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC1</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC2</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC3</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC4</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC5</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC6</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC7</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC8</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC9</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC10</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC11</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC12</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC13</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC14</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC15</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC16</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC17</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC18</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC19</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC20</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC21</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC22</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC23</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC24</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC25</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC26</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSC27</name>
+ <description>Filter scale configuration</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FFA1R</name>
+ <displayName>FFA1R</displayName>
+ <description>filter FIFO assignment
+ register</description>
+ <addressOffset>0x214</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FFA0</name>
+ <description>Filter FIFO assignment for filter
+ 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA1</name>
+ <description>Filter FIFO assignment for filter
+ 1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA2</name>
+ <description>Filter FIFO assignment for filter
+ 2</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA3</name>
+ <description>Filter FIFO assignment for filter
+ 3</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA4</name>
+ <description>Filter FIFO assignment for filter
+ 4</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA5</name>
+ <description>Filter FIFO assignment for filter
+ 5</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA6</name>
+ <description>Filter FIFO assignment for filter
+ 6</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA7</name>
+ <description>Filter FIFO assignment for filter
+ 7</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA8</name>
+ <description>Filter FIFO assignment for filter
+ 8</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA9</name>
+ <description>Filter FIFO assignment for filter
+ 9</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA10</name>
+ <description>Filter FIFO assignment for filter
+ 10</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA11</name>
+ <description>Filter FIFO assignment for filter
+ 11</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA12</name>
+ <description>Filter FIFO assignment for filter
+ 12</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA13</name>
+ <description>Filter FIFO assignment for filter
+ 13</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA14</name>
+ <description>Filter FIFO assignment for filter
+ 14</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA15</name>
+ <description>Filter FIFO assignment for filter
+ 15</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA16</name>
+ <description>Filter FIFO assignment for filter
+ 16</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA17</name>
+ <description>Filter FIFO assignment for filter
+ 17</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA18</name>
+ <description>Filter FIFO assignment for filter
+ 18</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA19</name>
+ <description>Filter FIFO assignment for filter
+ 19</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA20</name>
+ <description>Filter FIFO assignment for filter
+ 20</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA21</name>
+ <description>Filter FIFO assignment for filter
+ 21</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA22</name>
+ <description>Filter FIFO assignment for filter
+ 22</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA23</name>
+ <description>Filter FIFO assignment for filter
+ 23</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA24</name>
+ <description>Filter FIFO assignment for filter
+ 24</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA25</name>
+ <description>Filter FIFO assignment for filter
+ 25</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA26</name>
+ <description>Filter FIFO assignment for filter
+ 26</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFA27</name>
+ <description>Filter FIFO assignment for filter
+ 27</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FA1R</name>
+ <displayName>FA1R</displayName>
+ <description>filter activation register</description>
+ <addressOffset>0x21C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FACT0</name>
+ <description>Filter active</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT1</name>
+ <description>Filter active</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT2</name>
+ <description>Filter active</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT3</name>
+ <description>Filter active</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT4</name>
+ <description>Filter active</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT5</name>
+ <description>Filter active</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT6</name>
+ <description>Filter active</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT7</name>
+ <description>Filter active</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT8</name>
+ <description>Filter active</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT9</name>
+ <description>Filter active</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT10</name>
+ <description>Filter active</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT11</name>
+ <description>Filter active</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT12</name>
+ <description>Filter active</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT13</name>
+ <description>Filter active</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT14</name>
+ <description>Filter active</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT15</name>
+ <description>Filter active</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT16</name>
+ <description>Filter active</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT17</name>
+ <description>Filter active</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT18</name>
+ <description>Filter active</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT19</name>
+ <description>Filter active</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT20</name>
+ <description>Filter active</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT21</name>
+ <description>Filter active</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT22</name>
+ <description>Filter active</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT23</name>
+ <description>Filter active</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT24</name>
+ <description>Filter active</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT25</name>
+ <description>Filter active</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT26</name>
+ <description>Filter active</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACT27</name>
+ <description>Filter active</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F0R1</name>
+ <displayName>F0R1</displayName>
+ <description>Filter bank 0 register 1</description>
+ <addressOffset>0x240</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F0R2</name>
+ <displayName>F0R2</displayName>
+ <description>Filter bank 0 register 2</description>
+ <addressOffset>0x244</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F1R1</name>
+ <displayName>F1R1</displayName>
+ <description>Filter bank 1 register 1</description>
+ <addressOffset>0x248</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F1R2</name>
+ <displayName>F1R2</displayName>
+ <description>Filter bank 1 register 2</description>
+ <addressOffset>0x24C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F2R1</name>
+ <displayName>F2R1</displayName>
+ <description>Filter bank 2 register 1</description>
+ <addressOffset>0x250</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F2R2</name>
+ <displayName>F2R2</displayName>
+ <description>Filter bank 2 register 2</description>
+ <addressOffset>0x254</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F3R1</name>
+ <displayName>F3R1</displayName>
+ <description>Filter bank 3 register 1</description>
+ <addressOffset>0x258</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F3R2</name>
+ <displayName>F3R2</displayName>
+ <description>Filter bank 3 register 2</description>
+ <addressOffset>0x25C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F4R1</name>
+ <displayName>F4R1</displayName>
+ <description>Filter bank 4 register 1</description>
+ <addressOffset>0x260</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F4R2</name>
+ <displayName>F4R2</displayName>
+ <description>Filter bank 4 register 2</description>
+ <addressOffset>0x264</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F5R1</name>
+ <displayName>F5R1</displayName>
+ <description>Filter bank 5 register 1</description>
+ <addressOffset>0x268</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F5R2</name>
+ <displayName>F5R2</displayName>
+ <description>Filter bank 5 register 2</description>
+ <addressOffset>0x26C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F6R1</name>
+ <displayName>F6R1</displayName>
+ <description>Filter bank 6 register 1</description>
+ <addressOffset>0x270</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F6R2</name>
+ <displayName>F6R2</displayName>
+ <description>Filter bank 6 register 2</description>
+ <addressOffset>0x274</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F7R1</name>
+ <displayName>F7R1</displayName>
+ <description>Filter bank 7 register 1</description>
+ <addressOffset>0x278</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F7R2</name>
+ <displayName>F7R2</displayName>
+ <description>Filter bank 7 register 2</description>
+ <addressOffset>0x27C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F8R1</name>
+ <displayName>F8R1</displayName>
+ <description>Filter bank 8 register 1</description>
+ <addressOffset>0x280</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F8R2</name>
+ <displayName>F8R2</displayName>
+ <description>Filter bank 8 register 2</description>
+ <addressOffset>0x284</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F9R1</name>
+ <displayName>F9R1</displayName>
+ <description>Filter bank 9 register 1</description>
+ <addressOffset>0x288</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F9R2</name>
+ <displayName>F9R2</displayName>
+ <description>Filter bank 9 register 2</description>
+ <addressOffset>0x28C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F10R1</name>
+ <displayName>F10R1</displayName>
+ <description>Filter bank 10 register 1</description>
+ <addressOffset>0x290</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F10R2</name>
+ <displayName>F10R2</displayName>
+ <description>Filter bank 10 register 2</description>
+ <addressOffset>0x294</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F11R1</name>
+ <displayName>F11R1</displayName>
+ <description>Filter bank 11 register 1</description>
+ <addressOffset>0x298</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F11R2</name>
+ <displayName>F11R2</displayName>
+ <description>Filter bank 11 register 2</description>
+ <addressOffset>0x29C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F12R1</name>
+ <displayName>F12R1</displayName>
+ <description>Filter bank 4 register 1</description>
+ <addressOffset>0x2A0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F12R2</name>
+ <displayName>F12R2</displayName>
+ <description>Filter bank 12 register 2</description>
+ <addressOffset>0x2A4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F13R1</name>
+ <displayName>F13R1</displayName>
+ <description>Filter bank 13 register 1</description>
+ <addressOffset>0x2A8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F13R2</name>
+ <displayName>F13R2</displayName>
+ <description>Filter bank 13 register 2</description>
+ <addressOffset>0x2AC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F14R1</name>
+ <displayName>F14R1</displayName>
+ <description>Filter bank 14 register 1</description>
+ <addressOffset>0x2B0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F14R2</name>
+ <displayName>F14R2</displayName>
+ <description>Filter bank 14 register 2</description>
+ <addressOffset>0x2B4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F15R1</name>
+ <displayName>F15R1</displayName>
+ <description>Filter bank 15 register 1</description>
+ <addressOffset>0x2B8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F15R2</name>
+ <displayName>F15R2</displayName>
+ <description>Filter bank 15 register 2</description>
+ <addressOffset>0x2BC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F16R1</name>
+ <displayName>F16R1</displayName>
+ <description>Filter bank 16 register 1</description>
+ <addressOffset>0x2C0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F16R2</name>
+ <displayName>F16R2</displayName>
+ <description>Filter bank 16 register 2</description>
+ <addressOffset>0x2C4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F17R1</name>
+ <displayName>F17R1</displayName>
+ <description>Filter bank 17 register 1</description>
+ <addressOffset>0x2C8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F17R2</name>
+ <displayName>F17R2</displayName>
+ <description>Filter bank 17 register 2</description>
+ <addressOffset>0x2CC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F18R1</name>
+ <displayName>F18R1</displayName>
+ <description>Filter bank 18 register 1</description>
+ <addressOffset>0x2D0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F18R2</name>
+ <displayName>F18R2</displayName>
+ <description>Filter bank 18 register 2</description>
+ <addressOffset>0x2D4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F19R1</name>
+ <displayName>F19R1</displayName>
+ <description>Filter bank 19 register 1</description>
+ <addressOffset>0x2D8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F19R2</name>
+ <displayName>F19R2</displayName>
+ <description>Filter bank 19 register 2</description>
+ <addressOffset>0x2DC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F20R1</name>
+ <displayName>F20R1</displayName>
+ <description>Filter bank 20 register 1</description>
+ <addressOffset>0x2E0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F20R2</name>
+ <displayName>F20R2</displayName>
+ <description>Filter bank 20 register 2</description>
+ <addressOffset>0x2E4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F21R1</name>
+ <displayName>F21R1</displayName>
+ <description>Filter bank 21 register 1</description>
+ <addressOffset>0x2E8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F21R2</name>
+ <displayName>F21R2</displayName>
+ <description>Filter bank 21 register 2</description>
+ <addressOffset>0x2EC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F22R1</name>
+ <displayName>F22R1</displayName>
+ <description>Filter bank 22 register 1</description>
+ <addressOffset>0x2F0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F22R2</name>
+ <displayName>F22R2</displayName>
+ <description>Filter bank 22 register 2</description>
+ <addressOffset>0x2F4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F23R1</name>
+ <displayName>F23R1</displayName>
+ <description>Filter bank 23 register 1</description>
+ <addressOffset>0x2F8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F23R2</name>
+ <displayName>F23R2</displayName>
+ <description>Filter bank 23 register 2</description>
+ <addressOffset>0x2FC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F24R1</name>
+ <displayName>F24R1</displayName>
+ <description>Filter bank 24 register 1</description>
+ <addressOffset>0x300</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F24R2</name>
+ <displayName>F24R2</displayName>
+ <description>Filter bank 24 register 2</description>
+ <addressOffset>0x304</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F25R1</name>
+ <displayName>F25R1</displayName>
+ <description>Filter bank 25 register 1</description>
+ <addressOffset>0x308</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F25R2</name>
+ <displayName>F25R2</displayName>
+ <description>Filter bank 25 register 2</description>
+ <addressOffset>0x30C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F26R1</name>
+ <displayName>F26R1</displayName>
+ <description>Filter bank 26 register 1</description>
+ <addressOffset>0x310</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F26R2</name>
+ <displayName>F26R2</displayName>
+ <description>Filter bank 26 register 2</description>
+ <addressOffset>0x314</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F27R1</name>
+ <displayName>F27R1</displayName>
+ <description>Filter bank 27 register 1</description>
+ <addressOffset>0x318</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>F27R2</name>
+ <displayName>F27R2</displayName>
+ <description>Filter bank 27 register 2</description>
+ <addressOffset>0x31C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FB0</name>
+ <description>Filter bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB1</name>
+ <description>Filter bits</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB2</name>
+ <description>Filter bits</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB3</name>
+ <description>Filter bits</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB4</name>
+ <description>Filter bits</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB5</name>
+ <description>Filter bits</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB6</name>
+ <description>Filter bits</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB7</name>
+ <description>Filter bits</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB8</name>
+ <description>Filter bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB9</name>
+ <description>Filter bits</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB10</name>
+ <description>Filter bits</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB11</name>
+ <description>Filter bits</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB12</name>
+ <description>Filter bits</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB13</name>
+ <description>Filter bits</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB14</name>
+ <description>Filter bits</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB15</name>
+ <description>Filter bits</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB16</name>
+ <description>Filter bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB17</name>
+ <description>Filter bits</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB18</name>
+ <description>Filter bits</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB19</name>
+ <description>Filter bits</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB20</name>
+ <description>Filter bits</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB21</name>
+ <description>Filter bits</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB22</name>
+ <description>Filter bits</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB23</name>
+ <description>Filter bits</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB24</name>
+ <description>Filter bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB25</name>
+ <description>Filter bits</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB26</name>
+ <description>Filter bits</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB27</name>
+ <description>Filter bits</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB28</name>
+ <description>Filter bits</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB29</name>
+ <description>Filter bits</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB30</name>
+ <description>Filter bits</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FB31</name>
+ <description>Filter bits</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="CAN1">
+ <name>CAN2</name>
+ <baseAddress>0x40006800</baseAddress>
+ <interrupt>
+ <name>CAN2_TX</name>
+ <description>CAN2 TX interrupt</description>
+ <value>63</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN2_RX0</name>
+ <description>BXCAN2 RX0 interrupt</description>
+ <value>64</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN2_RX1</name>
+ <description>BXCAN2 RX1 interrupt</description>
+ <value>65</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN2_SCE</name>
+ <description>CAN2 SCE interrupt</description>
+ <value>66</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="CAN1">
+ <name>CAN3</name>
+ <baseAddress>0x40006C00</baseAddress>
+ <interrupt>
+ <name>CAN3_TX</name>
+ <description>CAN 3 TX interrupt</description>
+ <value>74</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN3_RX0</name>
+ <description>BxCAN 3 RX0 interrupt</description>
+ <value>75</value>
+ </interrupt>
+ <interrupt>
+ <name>CAN3_SCE</name>
+ <description>CAN 3 SCE interrupt</description>
+ <value>77</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>FMPI2C</name>
+ <description>fast-mode Inter-integrated circuit</description>
+ <groupName>I2C</groupName>
+ <baseAddress>0x40006000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>CAN3_RX1</name>
+ <description>BxCAN 3 RX1 interrupt</description>
+ <value>76</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR1</name>
+ <displayName>CR1</displayName>
+ <description>Control register 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PE</name>
+ <description>Peripheral enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXIE</name>
+ <description>TXIE</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXIE</name>
+ <description>RXIE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADDRE</name>
+ <description>ADDRE</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NACKIE</name>
+ <description>NACKIE</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOPIE</name>
+ <description>STOPIE</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>TCIE</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRIE</name>
+ <description>ERRIE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DNF</name>
+ <description>DNF</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ANFOFF</name>
+ <description>ANFOFF</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCDMAEN</name>
+ <description>TCDMAEN</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXDMAEN</name>
+ <description>RXDMAEN</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SBC</name>
+ <description>SBC</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NOSTRETCH</name>
+ <description>NOSTRETCH</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GCEN</name>
+ <description>GCEN</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBHEN</name>
+ <description>SMBHEN</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBDEN</name>
+ <description>SMBDEN</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALERTEN</name>
+ <description>ALERTEN</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PECEN</name>
+ <description>PECEN</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR2</name>
+ <displayName>CR2</displayName>
+ <description>Control register 2</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>SADD0</name>
+ <description>Slave address bit 0</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD1_7</name>
+ <description>Slave address bit 7_1</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>SADD8_9</name>
+ <description>Slave address bit 8_9</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>RD_WRN</name>
+ <description>Transfer direction</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADD10</name>
+ <description>10-bit addressing mode</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HEAD10R</name>
+ <description>10-bit address header only read
+ direction</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>START</name>
+ <description>Start generation</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOP</name>
+ <description>Stop generation</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NACK</name>
+ <description>NACK generation</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NBYTES</name>
+ <description>Number of bytes</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RELOAD</name>
+ <description>NBYTES reload mode</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AUTOEND</name>
+ <description>Automatic end mode</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PECBYTE</name>
+ <description>Packet error checking byte</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OAR1</name>
+ <displayName>OAR1</displayName>
+ <description>Own address register 1</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>OA1</name>
+ <description>OA1</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OA11_7</name>
+ <description>OA11_7</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>OA18_9</name>
+ <description>OA18_9</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OA1MODE</name>
+ <description>OA1MODE</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OA1EN</name>
+ <description>OA1EN</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OAR2</name>
+ <displayName>OAR2</displayName>
+ <description>Own address register 2</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>OA21_7</name>
+ <description>OA21_7</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>OA2MSK</name>
+ <description>OA2MSK</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OA2EN</name>
+ <description>OA2EN</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TIMINGR</name>
+ <displayName>TIMINGR</displayName>
+ <description>Timing register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>SCLL</name>
+ <description>SCLL</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SCLH</name>
+ <description>SCLH</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SDADEL</name>
+ <description>SDADEL</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCLDEL</name>
+ <description>SCLDEL</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>PRESC</name>
+ <description>PRESC</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TIMEOUTR</name>
+ <displayName>TIMEOUTR</displayName>
+ <description>Timeout register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TIMEOUTA</name>
+ <description>TIMEOUTA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>TIDLE</name>
+ <description>TIDLE</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMOUTEN</name>
+ <description>TIMOUTEN</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMEOUTB</name>
+ <description>TIMEOUTB</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>TEXTEN</name>
+ <description>TEXTEN</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ISR</name>
+ <displayName>ISR</displayName>
+ <description>Interrupt and Status register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x000000001</resetValue>
+ <fields>
+ <field>
+ <name>TXE</name>
+ <description>TXE</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXIS</name>
+ <description>TXIS</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RXNE</name>
+ <description>RXNE</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ADDR</name>
+ <description>ADDR</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>NACKF</name>
+ <description>NACKF</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>STOPF</name>
+ <description>STOPF</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TC</name>
+ <description>TC</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TCR</name>
+ <description>TCR</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BERR</name>
+ <description>BERR</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ARLO</name>
+ <description>ARLO</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>OVR</name>
+ <description>OVR</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PECERR</name>
+ <description>PECERR</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TIMEOUT</name>
+ <description>TIMEOUT</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ALERT</name>
+ <description>ALERT</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BUSY</name>
+ <description>BUSY</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>DIR</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ADDCODE</name>
+ <description>ADDCODE</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>7</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICR</name>
+ <displayName>ICR</displayName>
+ <description>Interrupt clear register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>ADDRCF</name>
+ <description>Address matched flag clear</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NACKCF</name>
+ <description>Not Acknowledge flag clear</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOPCF</name>
+ <description>Stop detection flag clear</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BERRCF</name>
+ <description>Bus error flag clear</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARLOCF</name>
+ <description>Arbitration Lost flag
+ clear</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRCF</name>
+ <description>Overrun/Underrun flag
+ clear</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PECCF</name>
+ <description>PEC Error flag clear</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMOUTCF</name>
+ <description>Timeout detection flag
+ clear</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALERTCF</name>
+ <description>Alert flag clear</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PECR</name>
+ <displayName>PECR</displayName>
+ <description>PEC register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>PEC</name>
+ <description>PEC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXDR</name>
+ <displayName>RXDR</displayName>
+ <description>Receive data register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>RXDATA</name>
+ <description>RXDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXDR</name>
+ <displayName>TXDR</displayName>
+ <description>Transmit data register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000</resetValue>
+ <fields>
+ <field>
+ <name>TXDATA</name>
+ <description>TXDATA</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>FSMC</name>
+ <description>Flexible static memory controller</description>
+ <groupName>FSMC</groupName>
+ <baseAddress>0xA0000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x1000</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>FSMC</name>
+ <description>FSMC global interrupt</description>
+ <value>48</value>
+ </interrupt>
+ <interrupt>
+ <name>I2CFMP1event</name>
+ <description>I2CFMP1 event interrupt</description>
+ <value>95</value>
+ </interrupt>
+ <interrupt>
+ <name>I2CFMP1error</name>
+ <description>I2CFMP1 error interrupt</description>
+ <value>96</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>BCR1</name>
+ <displayName>BCR1</displayName>
+ <description>SRAM/NOR-Flash chip-select control register
+ 1</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030D0</resetValue>
+ <fields>
+ <field>
+ <name>CBURSTRW</name>
+ <description>CBURSTRW</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>ASYNCWAIT</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>EXTMOD</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>WAITEN</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>WREN</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>WAITCFG</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>WAITPOL</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>BURSTEN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>FACCEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>MWID</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>MTYP</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>MUXEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MBKEN</name>
+ <description>MBKEN</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BTR1</name>
+ <displayName>BTR1</displayName>
+ <description>SRAM/NOR-Flash chip-select timing register
+ 1</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>BUSTURN</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BCR2</name>
+ <displayName>BCR2</displayName>
+ <description>SRAM/NOR-Flash chip-select control register
+ 2</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030D0</resetValue>
+ <fields>
+ <field>
+ <name>CBURSTRW</name>
+ <description>CBURSTRW</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>ASYNCWAIT</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>EXTMOD</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>WAITEN</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>WREN</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>WAITCFG</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WRAPMOD</name>
+ <description>WRAPMOD</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>WAITPOL</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>BURSTEN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>FACCEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>MWID</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>MTYP</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>MUXEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MBKEN</name>
+ <description>MBKEN</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BTR2</name>
+ <displayName>BTR2</displayName>
+ <description>SRAM/NOR-Flash chip-select timing register
+ 2</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>BUSTURN</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BCR3</name>
+ <displayName>BCR3</displayName>
+ <description>SRAM/NOR-Flash chip-select control register
+ 3</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030D0</resetValue>
+ <fields>
+ <field>
+ <name>CBURSTRW</name>
+ <description>CBURSTRW</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>ASYNCWAIT</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>EXTMOD</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>WAITEN</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>WREN</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>WAITCFG</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WRAPMOD</name>
+ <description>WRAPMOD</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>WAITPOL</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>BURSTEN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>FACCEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>MWID</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>MTYP</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>MUXEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MBKEN</name>
+ <description>MBKEN</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BTR3</name>
+ <displayName>BTR3</displayName>
+ <description>SRAM/NOR-Flash chip-select timing register
+ 3</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>BUSTURN</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BCR4</name>
+ <displayName>BCR4</displayName>
+ <description>SRAM/NOR-Flash chip-select control register
+ 4</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030D0</resetValue>
+ <fields>
+ <field>
+ <name>CBURSTRW</name>
+ <description>CBURSTRW</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>ASYNCWAIT</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>EXTMOD</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>WAITEN</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>WREN</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>WAITCFG</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WRAPMOD</name>
+ <description>WRAPMOD</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>WAITPOL</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>BURSTEN</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>FACCEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>MWID</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>MTYP</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>MUXEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MBKEN</name>
+ <description>MBKEN</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BTR4</name>
+ <displayName>BTR4</displayName>
+ <description>SRAM/NOR-Flash chip-select timing register
+ 4</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>BUSTURN</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCR2</name>
+ <displayName>PCR2</displayName>
+ <description>PC Card/NAND Flash control register
+ 2</description>
+ <addressOffset>0x60</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000018</resetValue>
+ <fields>
+ <field>
+ <name>ECCPS</name>
+ <description>ECCPS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TAR</name>
+ <description>TAR</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TCLR</name>
+ <description>TCLR</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ECCEN</name>
+ <description>ECCEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWID</name>
+ <description>PWID</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PTYP</name>
+ <description>PTYP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PBKEN</name>
+ <description>PBKEN</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWAITEN</name>
+ <description>PWAITEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR2</name>
+ <displayName>SR2</displayName>
+ <description>FIFO status and interrupt register
+ 2</description>
+ <addressOffset>0x64</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000040</resetValue>
+ <fields>
+ <field>
+ <name>FEMPT</name>
+ <description>FEMPT</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>IFEN</name>
+ <description>IFEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILEN</name>
+ <description>ILEN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IREN</name>
+ <description>IREN</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IFS</name>
+ <description>IFS</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILS</name>
+ <description>ILS</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IRS</name>
+ <description>IRS</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PMEM2</name>
+ <displayName>PMEM2</displayName>
+ <description>Common memory space timing register
+ 2</description>
+ <addressOffset>0x68</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>MEMHIZx</name>
+ <description>MEMHIZx</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMHOLDx</name>
+ <description>MEMHOLDx</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMWAITx</name>
+ <description>MEMWAITx</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMSETx</name>
+ <description>MEMSETx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PATT2</name>
+ <displayName>PATT2</displayName>
+ <description>Attribute memory space timing register
+ 2</description>
+ <addressOffset>0x6C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>ATTHIZx</name>
+ <description>ATTHIZx</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTHOLDx</name>
+ <description>ATTHOLDx</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTWAITx</name>
+ <description>ATTWAITx</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTSETx</name>
+ <description>ATTSETx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ECCR2</name>
+ <displayName>ECCR2</displayName>
+ <description>ECC result register 2</description>
+ <addressOffset>0x74</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ECCx</name>
+ <description>ECCx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCR3</name>
+ <displayName>PCR3</displayName>
+ <description>PC Card/NAND Flash control register
+ 3</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000018</resetValue>
+ <fields>
+ <field>
+ <name>ECCPS</name>
+ <description>ECCPS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TAR</name>
+ <description>TAR</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TCLR</name>
+ <description>TCLR</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ECCEN</name>
+ <description>ECCEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWID</name>
+ <description>PWID</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PTYP</name>
+ <description>PTYP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PBKEN</name>
+ <description>PBKEN</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWAITEN</name>
+ <description>PWAITEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR3</name>
+ <displayName>SR3</displayName>
+ <description>FIFO status and interrupt register
+ 3</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000040</resetValue>
+ <fields>
+ <field>
+ <name>FEMPT</name>
+ <description>FEMPT</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>IFEN</name>
+ <description>IFEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILEN</name>
+ <description>ILEN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IREN</name>
+ <description>IREN</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IFS</name>
+ <description>IFS</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILS</name>
+ <description>ILS</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IRS</name>
+ <description>IRS</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PMEM3</name>
+ <displayName>PMEM3</displayName>
+ <description>Common memory space timing register
+ 3</description>
+ <addressOffset>0x88</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>MEMHIZx</name>
+ <description>MEMHIZx</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMHOLDx</name>
+ <description>MEMHOLDx</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMWAITx</name>
+ <description>MEMWAITx</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMSETx</name>
+ <description>MEMSETx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PATT3</name>
+ <displayName>PATT3</displayName>
+ <description>Attribute memory space timing register
+ 3</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>ATTHIZx</name>
+ <description>ATTHIZx</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTHOLDx</name>
+ <description>ATTHOLDx</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTWAITx</name>
+ <description>ATTWAITx</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTSETx</name>
+ <description>ATTSETx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ECCR3</name>
+ <displayName>ECCR3</displayName>
+ <description>ECC result register 3</description>
+ <addressOffset>0x94</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ECCx</name>
+ <description>ECCx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCR4</name>
+ <displayName>PCR4</displayName>
+ <description>PC Card/NAND Flash control register
+ 4</description>
+ <addressOffset>0xA0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000018</resetValue>
+ <fields>
+ <field>
+ <name>ECCPS</name>
+ <description>ECCPS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TAR</name>
+ <description>TAR</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TCLR</name>
+ <description>TCLR</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ECCEN</name>
+ <description>ECCEN</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWID</name>
+ <description>PWID</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PTYP</name>
+ <description>PTYP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PBKEN</name>
+ <description>PBKEN</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWAITEN</name>
+ <description>PWAITEN</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR4</name>
+ <displayName>SR4</displayName>
+ <description>FIFO status and interrupt register
+ 4</description>
+ <addressOffset>0xA4</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000040</resetValue>
+ <fields>
+ <field>
+ <name>FEMPT</name>
+ <description>FEMPT</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>IFEN</name>
+ <description>IFEN</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILEN</name>
+ <description>ILEN</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IREN</name>
+ <description>IREN</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IFS</name>
+ <description>IFS</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILS</name>
+ <description>ILS</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IRS</name>
+ <description>IRS</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PMEM4</name>
+ <displayName>PMEM4</displayName>
+ <description>Common memory space timing register
+ 4</description>
+ <addressOffset>0xA8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>MEMHIZx</name>
+ <description>MEMHIZx</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMHOLDx</name>
+ <description>MEMHOLDx</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMWAITx</name>
+ <description>MEMWAITx</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMSETx</name>
+ <description>MEMSETx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PATT4</name>
+ <displayName>PATT4</displayName>
+ <description>Attribute memory space timing register
+ 4</description>
+ <addressOffset>0xAC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>ATTHIZx</name>
+ <description>ATTHIZx</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTHOLDx</name>
+ <description>ATTHOLDx</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTWAITx</name>
+ <description>ATTWAITx</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTSETx</name>
+ <description>ATTSETx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PIO4</name>
+ <displayName>PIO4</displayName>
+ <description>I/O space timing register 4</description>
+ <addressOffset>0xB0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>IOHIZx</name>
+ <description>IOHIZx</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IOHOLDx</name>
+ <description>IOHOLDx</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IOWAITx</name>
+ <description>IOWAITx</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>IOSETx</name>
+ <description>IOSETx</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BWTR1</name>
+ <displayName>BWTR1</displayName>
+ <description>SRAM/NOR-Flash write timing registers
+ 1</description>
+ <addressOffset>0x104</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BWTR2</name>
+ <displayName>BWTR2</displayName>
+ <description>SRAM/NOR-Flash write timing registers
+ 2</description>
+ <addressOffset>0x10C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BWTR3</name>
+ <displayName>BWTR3</displayName>
+ <description>SRAM/NOR-Flash write timing registers
+ 3</description>
+ <addressOffset>0x114</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BWTR4</name>
+ <displayName>BWTR4</displayName>
+ <description>SRAM/NOR-Flash write timing registers
+ 4</description>
+ <addressOffset>0x11C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ACCMOD</name>
+ <description>ACCMOD</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>DATLAT</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>CLKDIV</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>DATAST</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>ADDHLD</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDSET</name>
+ <description>ADDSET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>OTG_FS_GLOBAL</name>
+ <description>USB on the go full speed</description>
+ <groupName>USB_OTG_FS</groupName>
+ <baseAddress>0x50000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>EXTI18_OTG_FS_WKUP</name>
+ <description>USB On-The-Go FS Wakeup through EXTI line
+ interrupt</description>
+ <value>42</value>
+ </interrupt>
+ <interrupt>
+ <name>OTG_FS_USB</name>
+ <description>USB On The Go FS global
+ interrupt</description>
+ <value>67</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>FS_GOTGCTL</name>
+ <displayName>FS_GOTGCTL</displayName>
+ <description>OTG_FS control and status register
+ (OTG_FS_GOTGCTL)</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000800</resetValue>
+ <fields>
+ <field>
+ <name>SRQSCS</name>
+ <description>Session request success</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SRQ</name>
+ <description>Session request</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HNGSCS</name>
+ <description>Host negotiation success</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>HNPRQ</name>
+ <description>HNP request</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HSHNPEN</name>
+ <description>Host set HNP enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DHNPEN</name>
+ <description>Device HNP enabled</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CIDSTS</name>
+ <description>Connector ID status</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DBCT</name>
+ <description>Long/short debounce time</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ASVLD</name>
+ <description>A-session valid</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BSVLD</name>
+ <description>B-session valid</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GOTGINT</name>
+ <displayName>FS_GOTGINT</displayName>
+ <description>OTG_FS interrupt register
+ (OTG_FS_GOTGINT)</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SEDET</name>
+ <description>Session end detected</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SRSSCHG</name>
+ <description>Session request success status
+ change</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HNSSCHG</name>
+ <description>Host negotiation success status
+ change</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HNGDET</name>
+ <description>Host negotiation detected</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADTOCHG</name>
+ <description>A-device timeout change</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DBCDNE</name>
+ <description>Debounce done</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GAHBCFG</name>
+ <displayName>FS_GAHBCFG</displayName>
+ <description>OTG_FS AHB configuration register
+ (OTG_FS_GAHBCFG)</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>GINT</name>
+ <description>Global interrupt mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXFELVL</name>
+ <description>TxFIFO empty level</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PTXFELVL</name>
+ <description>Periodic TxFIFO empty
+ level</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GUSBCFG</name>
+ <displayName>FS_GUSBCFG</displayName>
+ <description>OTG_FS USB configuration register
+ (OTG_FS_GUSBCFG)</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000A00</resetValue>
+ <fields>
+ <field>
+ <name>TOCAL</name>
+ <description>FS timeout calibration</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PHYSEL</name>
+ <description>Full Speed serial transceiver
+ select</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SRPCAP</name>
+ <description>SRP-capable</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HNPCAP</name>
+ <description>HNP-capable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TRDT</name>
+ <description>USB turnaround time</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FHMOD</name>
+ <description>Force host mode</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FDMOD</name>
+ <description>Force device mode</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CTXPKT</name>
+ <description>Corrupt Tx packet</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GRSTCTL</name>
+ <displayName>FS_GRSTCTL</displayName>
+ <description>OTG_FS reset register
+ (OTG_FS_GRSTCTL)</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x20000000</resetValue>
+ <fields>
+ <field>
+ <name>CSRST</name>
+ <description>Core soft reset</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HSRST</name>
+ <description>HCLK soft reset</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FCRST</name>
+ <description>Host frame counter reset</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RXFFLSH</name>
+ <description>RxFIFO flush</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXFFLSH</name>
+ <description>TxFIFO flush</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXFNUM</name>
+ <description>TxFIFO number</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>5</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>AHBIDL</name>
+ <description>AHB master idle</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GINTSTS</name>
+ <displayName>FS_GINTSTS</displayName>
+ <description>OTG_FS core interrupt register
+ (OTG_FS_GINTSTS)</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x04000020</resetValue>
+ <fields>
+ <field>
+ <name>CMOD</name>
+ <description>Current mode of operation</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>MMIS</name>
+ <description>Mode mismatch interrupt</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>OTGINT</name>
+ <description>OTG interrupt</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SOF</name>
+ <description>Start of frame</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RXFLVL</name>
+ <description>RxFIFO non-empty</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>NPTXFE</name>
+ <description>Non-periodic TxFIFO empty</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>GINAKEFF</name>
+ <description>Global IN non-periodic NAK
+ effective</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>GOUTNAKEFF</name>
+ <description>Global OUT NAK effective</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ESUSP</name>
+ <description>Early suspend</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>USBSUSP</name>
+ <description>USB suspend</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>USBRST</name>
+ <description>USB reset</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ENUMDNE</name>
+ <description>Enumeration done</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ISOODRP</name>
+ <description>Isochronous OUT packet dropped
+ interrupt</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EOPF</name>
+ <description>End of periodic frame
+ interrupt</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IEPINT</name>
+ <description>IN endpoint interrupt</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>OEPINT</name>
+ <description>OUT endpoint interrupt</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>IISOIXFR</name>
+ <description>Incomplete isochronous IN
+ transfer</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IPXFR_INCOMPISOOUT</name>
+ <description>Incomplete periodic transfer(Host
+ mode)/Incomplete isochronous OUT transfer(Device
+ mode)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>HPRTINT</name>
+ <description>Host port interrupt</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>HCINT</name>
+ <description>Host channels interrupt</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PTXFE</name>
+ <description>Periodic TxFIFO empty</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>CIDSCHG</name>
+ <description>Connector ID status change</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DISCINT</name>
+ <description>Disconnect detected
+ interrupt</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SRQINT</name>
+ <description>Session request/new session detected
+ interrupt</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>WKUPINT</name>
+ <description>Resume/remote wakeup detected
+ interrupt</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GINTMSK</name>
+ <displayName>FS_GINTMSK</displayName>
+ <description>OTG_FS interrupt mask register
+ (OTG_FS_GINTMSK)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MMISM</name>
+ <description>Mode mismatch interrupt
+ mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>OTGINT</name>
+ <description>OTG interrupt mask</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SOFM</name>
+ <description>Start of frame mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RXFLVLM</name>
+ <description>Receive FIFO non-empty
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NPTXFEM</name>
+ <description>Non-periodic TxFIFO empty
+ mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>GINAKEFFM</name>
+ <description>Global non-periodic IN NAK effective
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>GONAKEFFM</name>
+ <description>Global OUT NAK effective
+ mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ESUSPM</name>
+ <description>Early suspend mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>USBSUSPM</name>
+ <description>USB suspend mask</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>USBRST</name>
+ <description>USB reset mask</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ENUMDNEM</name>
+ <description>Enumeration done mask</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ISOODRPM</name>
+ <description>Isochronous OUT packet dropped interrupt
+ mask</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EOPFM</name>
+ <description>End of periodic frame interrupt
+ mask</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPMISM</name>
+ <description>Endpoint mismatch interrupt
+ mask</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IEPINT</name>
+ <description>IN endpoints interrupt
+ mask</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>OEPINT</name>
+ <description>OUT endpoints interrupt
+ mask</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IISOIXFRM</name>
+ <description>Incomplete isochronous IN transfer
+ mask</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IPXFRM_IISOOXFRM</name>
+ <description>Incomplete periodic transfer mask(Host
+ mode)/Incomplete isochronous OUT transfer mask(Device
+ mode)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PRTIM</name>
+ <description>Host port interrupt mask</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>HCIM</name>
+ <description>Host channels interrupt
+ mask</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PTXFEM</name>
+ <description>Periodic TxFIFO empty mask</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CIDSCHGM</name>
+ <description>Connector ID status change
+ mask</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DISCINT</name>
+ <description>Disconnect detected interrupt
+ mask</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SRQIM</name>
+ <description>Session request/new session detected
+ interrupt mask</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>WUIM</name>
+ <description>Resume/remote wakeup detected interrupt
+ mask</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GRXSTSR_Device</name>
+ <displayName>FS_GRXSTSR_Device</displayName>
+ <description>OTG_FS Receive status debug read(Device
+ mode)</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>BCNT</name>
+ <description>Byte count</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTSTS</name>
+ <description>Packet status</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>FRMNUM</name>
+ <description>Frame number</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GRXSTSR_Host</name>
+ <displayName>FS_GRXSTSR_Host</displayName>
+ <description>OTG_FS Receive status debug read(Host
+ mode)</description>
+ <alternateRegister>FS_GRXSTSR_Device</alternateRegister>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>BCNT</name>
+ <description>Byte count</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTSTS</name>
+ <description>Packet status</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>FRMNUM</name>
+ <description>Frame number</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GRXFSIZ</name>
+ <displayName>FS_GRXFSIZ</displayName>
+ <description>OTG_FS Receive FIFO size register
+ (OTG_FS_GRXFSIZ)</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000200</resetValue>
+ <fields>
+ <field>
+ <name>RXFD</name>
+ <description>RxFIFO depth</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GNPTXFSIZ_Device</name>
+ <displayName>FS_GNPTXFSIZ_Device</displayName>
+ <description>OTG_FS non-periodic transmit FIFO size
+ register (Device mode)</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000200</resetValue>
+ <fields>
+ <field>
+ <name>TX0FSA</name>
+ <description>Endpoint 0 transmit RAM start
+ address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>TX0FD</name>
+ <description>Endpoint 0 TxFIFO depth</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GNPTXFSIZ_Host</name>
+ <displayName>FS_GNPTXFSIZ_Host</displayName>
+ <description>OTG_FS non-periodic transmit FIFO size
+ register (Host mode)</description>
+ <alternateRegister>
+ FS_GNPTXFSIZ_Device</alternateRegister>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000200</resetValue>
+ <fields>
+ <field>
+ <name>NPTXFSA</name>
+ <description>Non-periodic transmit RAM start
+ address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>NPTXFD</name>
+ <description>Non-periodic TxFIFO depth</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GNPTXSTS</name>
+ <displayName>FS_GNPTXSTS</displayName>
+ <description>OTG_FS non-periodic transmit FIFO/queue
+ status register (OTG_FS_GNPTXSTS)</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00080200</resetValue>
+ <fields>
+ <field>
+ <name>NPTXFSAV</name>
+ <description>Non-periodic TxFIFO space
+ available</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>NPTQXSAV</name>
+ <description>Non-periodic transmit request queue
+ space available</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>NPTXQTOP</name>
+ <description>Top of the non-periodic transmit request
+ queue</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_GCCFG</name>
+ <displayName>FS_GCCFG</displayName>
+ <description>OTG_FS general core configuration register
+ (OTG_FS_GCCFG)</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DCDET</name>
+ <description>DCDET</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PDET</name>
+ <description>PDET</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDET</name>
+ <description>SDET</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PS2DET</name>
+ <description>PS2DET</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWRDWN</name>
+ <description>PWRDWN</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BCDEN</name>
+ <description>BCDEN</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DCDEN</name>
+ <description>DCDEN</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PDEN</name>
+ <description>PDEN</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDEN</name>
+ <description>SDEN</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>VBDEN</name>
+ <description>VBDEN</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_CID</name>
+ <displayName>FS_CID</displayName>
+ <description>core ID register</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00001000</resetValue>
+ <fields>
+ <field>
+ <name>PRODUCT_ID</name>
+ <description>Product ID field</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HPTXFSIZ</name>
+ <displayName>FS_HPTXFSIZ</displayName>
+ <description>OTG_FS Host periodic transmit FIFO size
+ register (OTG_FS_HPTXFSIZ)</description>
+ <addressOffset>0x100</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x02000600</resetValue>
+ <fields>
+ <field>
+ <name>PTXSA</name>
+ <description>Host periodic TxFIFO start
+ address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>PTXFSIZ</name>
+ <description>Host periodic TxFIFO depth</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DIEPTXF1</name>
+ <displayName>FS_DIEPTXF1</displayName>
+ <description>OTG_FS device IN endpoint transmit FIFO size
+ register (OTG_FS_DIEPTXF2)</description>
+ <addressOffset>0x104</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x02000400</resetValue>
+ <fields>
+ <field>
+ <name>INEPTXSA</name>
+ <description>IN endpoint FIFO2 transmit RAM start
+ address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INEPTXFD</name>
+ <description>IN endpoint TxFIFO depth</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DIEPTXF2</name>
+ <displayName>FS_DIEPTXF2</displayName>
+ <description>OTG_FS device IN endpoint transmit FIFO size
+ register (OTG_FS_DIEPTXF3)</description>
+ <addressOffset>0x108</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x02000400</resetValue>
+ <fields>
+ <field>
+ <name>INEPTXSA</name>
+ <description>IN endpoint FIFO3 transmit RAM start
+ address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INEPTXFD</name>
+ <description>IN endpoint TxFIFO depth</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DIEPTXF3</name>
+ <displayName>FS_DIEPTXF3</displayName>
+ <description>OTG_FS device IN endpoint transmit FIFO size
+ register (OTG_FS_DIEPTXF4)</description>
+ <addressOffset>0x10C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x02000400</resetValue>
+ <fields>
+ <field>
+ <name>INEPTXSA</name>
+ <description>IN endpoint FIFO4 transmit RAM start
+ address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>INEPTXFD</name>
+ <description>IN endpoint TxFIFO depth</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>OTG_FS_HOST</name>
+ <description>USB on the go full speed</description>
+ <groupName>USB_OTG_FS</groupName>
+ <baseAddress>0x50000400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>FS_HCFG</name>
+ <displayName>FS_HCFG</displayName>
+ <description>OTG_FS host configuration register
+ (OTG_FS_HCFG)</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FSLSPCS</name>
+ <description>FS/LS PHY clock select</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FSLSS</name>
+ <description>FS- and LS-only support</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HFIR</name>
+ <displayName>HFIR</displayName>
+ <description>OTG_FS Host frame interval
+ register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0000EA60</resetValue>
+ <fields>
+ <field>
+ <name>FRIVL</name>
+ <description>Frame interval</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HFNUM</name>
+ <displayName>FS_HFNUM</displayName>
+ <description>OTG_FS host frame number/frame time
+ remaining register (OTG_FS_HFNUM)</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00003FFF</resetValue>
+ <fields>
+ <field>
+ <name>FRNUM</name>
+ <description>Frame number</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>FTREM</name>
+ <description>Frame time remaining</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HPTXSTS</name>
+ <displayName>FS_HPTXSTS</displayName>
+ <description>OTG_FS_Host periodic transmit FIFO/queue
+ status register (OTG_FS_HPTXSTS)</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00080100</resetValue>
+ <fields>
+ <field>
+ <name>PTXFSAVL</name>
+ <description>Periodic transmit data FIFO space
+ available</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PTXQSAV</name>
+ <description>Periodic transmit request queue space
+ available</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PTXQTOP</name>
+ <description>Top of the periodic transmit request
+ queue</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HAINT</name>
+ <displayName>HAINT</displayName>
+ <description>OTG_FS Host all channels interrupt
+ register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>HAINT</name>
+ <description>Channel interrupts</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HAINTMSK</name>
+ <displayName>HAINTMSK</displayName>
+ <description>OTG_FS host all channels interrupt mask
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>HAINTM</name>
+ <description>Channel interrupt mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HPRT</name>
+ <displayName>FS_HPRT</displayName>
+ <description>OTG_FS host port control and status register
+ (OTG_FS_HPRT)</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PCSTS</name>
+ <description>Port connect status</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PCDET</name>
+ <description>Port connect detected</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PENA</name>
+ <description>Port enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PENCHNG</name>
+ <description>Port enable/disable change</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>POCA</name>
+ <description>Port overcurrent active</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>POCCHNG</name>
+ <description>Port overcurrent change</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PRES</name>
+ <description>Port resume</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PSUSP</name>
+ <description>Port suspend</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PRST</name>
+ <description>Port reset</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PLSTS</name>
+ <description>Port line status</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PPWR</name>
+ <description>Port power</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PTCTL</name>
+ <description>Port test control</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PSPD</name>
+ <description>Port speed</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR0</name>
+ <displayName>FS_HCCHAR0</displayName>
+ <description>OTG_FS host channel-0 characteristics
+ register (OTG_FS_HCCHAR0)</description>
+ <addressOffset>0x100</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR1</name>
+ <displayName>FS_HCCHAR1</displayName>
+ <description>OTG_FS host channel-1 characteristics
+ register (OTG_FS_HCCHAR1)</description>
+ <addressOffset>0x120</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR2</name>
+ <displayName>FS_HCCHAR2</displayName>
+ <description>OTG_FS host channel-2 characteristics
+ register (OTG_FS_HCCHAR2)</description>
+ <addressOffset>0x140</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR3</name>
+ <displayName>FS_HCCHAR3</displayName>
+ <description>OTG_FS host channel-3 characteristics
+ register (OTG_FS_HCCHAR3)</description>
+ <addressOffset>0x160</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR4</name>
+ <displayName>FS_HCCHAR4</displayName>
+ <description>OTG_FS host channel-4 characteristics
+ register (OTG_FS_HCCHAR4)</description>
+ <addressOffset>0x180</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR5</name>
+ <displayName>FS_HCCHAR5</displayName>
+ <description>OTG_FS host channel-5 characteristics
+ register (OTG_FS_HCCHAR5)</description>
+ <addressOffset>0x1A0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR6</name>
+ <displayName>FS_HCCHAR6</displayName>
+ <description>OTG_FS host channel-6 characteristics
+ register (OTG_FS_HCCHAR6)</description>
+ <addressOffset>0x1C0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCCHAR7</name>
+ <displayName>FS_HCCHAR7</displayName>
+ <description>OTG_FS host channel-7 characteristics
+ register (OTG_FS_HCCHAR7)</description>
+ <addressOffset>0x1E0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>EPNUM</name>
+ <description>Endpoint number</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>EPDIR</name>
+ <description>Endpoint direction</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSDEV</name>
+ <description>Low-speed device</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MCNT</name>
+ <description>Multicount</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>ODDFRM</name>
+ <description>Odd frame</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHDIS</name>
+ <description>Channel disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHENA</name>
+ <description>Channel enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT0</name>
+ <displayName>FS_HCINT0</displayName>
+ <description>OTG_FS host channel-0 interrupt register
+ (OTG_FS_HCINT0)</description>
+ <addressOffset>0x108</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT1</name>
+ <displayName>FS_HCINT1</displayName>
+ <description>OTG_FS host channel-1 interrupt register
+ (OTG_FS_HCINT1)</description>
+ <addressOffset>0x128</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT2</name>
+ <displayName>FS_HCINT2</displayName>
+ <description>OTG_FS host channel-2 interrupt register
+ (OTG_FS_HCINT2)</description>
+ <addressOffset>0x148</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT3</name>
+ <displayName>FS_HCINT3</displayName>
+ <description>OTG_FS host channel-3 interrupt register
+ (OTG_FS_HCINT3)</description>
+ <addressOffset>0x168</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT4</name>
+ <displayName>FS_HCINT4</displayName>
+ <description>OTG_FS host channel-4 interrupt register
+ (OTG_FS_HCINT4)</description>
+ <addressOffset>0x188</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT5</name>
+ <displayName>FS_HCINT5</displayName>
+ <description>OTG_FS host channel-5 interrupt register
+ (OTG_FS_HCINT5)</description>
+ <addressOffset>0x1A8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT6</name>
+ <displayName>FS_HCINT6</displayName>
+ <description>OTG_FS host channel-6 interrupt register
+ (OTG_FS_HCINT6)</description>
+ <addressOffset>0x1C8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINT7</name>
+ <displayName>FS_HCINT7</displayName>
+ <description>OTG_FS host channel-7 interrupt register
+ (OTG_FS_HCINT7)</description>
+ <addressOffset>0x1E8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRC</name>
+ <description>Transfer completed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHH</name>
+ <description>Channel halted</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL response received
+ interrupt</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAK</name>
+ <description>NAK response received
+ interrupt</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACK</name>
+ <description>ACK response received/transmitted
+ interrupt</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Transaction error</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERR</name>
+ <description>Babble error</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMOR</name>
+ <description>Frame overrun</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERR</name>
+ <description>Data toggle error</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK0</name>
+ <displayName>FS_HCINTMSK0</displayName>
+ <description>OTG_FS host channel-0 mask register
+ (OTG_FS_HCINTMSK0)</description>
+ <addressOffset>0x10C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK1</name>
+ <displayName>FS_HCINTMSK1</displayName>
+ <description>OTG_FS host channel-1 mask register
+ (OTG_FS_HCINTMSK1)</description>
+ <addressOffset>0x12C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK2</name>
+ <displayName>FS_HCINTMSK2</displayName>
+ <description>OTG_FS host channel-2 mask register
+ (OTG_FS_HCINTMSK2)</description>
+ <addressOffset>0x14C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK3</name>
+ <displayName>FS_HCINTMSK3</displayName>
+ <description>OTG_FS host channel-3 mask register
+ (OTG_FS_HCINTMSK3)</description>
+ <addressOffset>0x16C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK4</name>
+ <displayName>FS_HCINTMSK4</displayName>
+ <description>OTG_FS host channel-4 mask register
+ (OTG_FS_HCINTMSK4)</description>
+ <addressOffset>0x18C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK5</name>
+ <displayName>FS_HCINTMSK5</displayName>
+ <description>OTG_FS host channel-5 mask register
+ (OTG_FS_HCINTMSK5)</description>
+ <addressOffset>0x1AC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK6</name>
+ <displayName>FS_HCINTMSK6</displayName>
+ <description>OTG_FS host channel-6 mask register
+ (OTG_FS_HCINTMSK6)</description>
+ <addressOffset>0x1CC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCINTMSK7</name>
+ <displayName>FS_HCINTMSK7</displayName>
+ <description>OTG_FS host channel-7 mask register
+ (OTG_FS_HCINTMSK7)</description>
+ <addressOffset>0x1EC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHHM</name>
+ <description>Channel halted mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STALLM</name>
+ <description>STALL response received interrupt
+ mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NAKM</name>
+ <description>NAK response received interrupt
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ACKM</name>
+ <description>ACK response received/transmitted
+ interrupt mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NYET</name>
+ <description>response received interrupt
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRM</name>
+ <description>Transaction error mask</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BBERRM</name>
+ <description>Babble error mask</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FRMORM</name>
+ <description>Frame overrun mask</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DTERRM</name>
+ <description>Data toggle error mask</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ0</name>
+ <displayName>FS_HCTSIZ0</displayName>
+ <description>OTG_FS host channel-0 transfer size
+ register</description>
+ <addressOffset>0x110</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ1</name>
+ <displayName>FS_HCTSIZ1</displayName>
+ <description>OTG_FS host channel-1 transfer size
+ register</description>
+ <addressOffset>0x130</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ2</name>
+ <displayName>FS_HCTSIZ2</displayName>
+ <description>OTG_FS host channel-2 transfer size
+ register</description>
+ <addressOffset>0x150</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ3</name>
+ <displayName>FS_HCTSIZ3</displayName>
+ <description>OTG_FS host channel-3 transfer size
+ register</description>
+ <addressOffset>0x170</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ4</name>
+ <displayName>FS_HCTSIZ4</displayName>
+ <description>OTG_FS host channel-x transfer size
+ register</description>
+ <addressOffset>0x190</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ5</name>
+ <displayName>FS_HCTSIZ5</displayName>
+ <description>OTG_FS host channel-5 transfer size
+ register</description>
+ <addressOffset>0x1B0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ6</name>
+ <displayName>FS_HCTSIZ6</displayName>
+ <description>OTG_FS host channel-6 transfer size
+ register</description>
+ <addressOffset>0x1D0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_HCTSIZ7</name>
+ <displayName>FS_HCTSIZ7</displayName>
+ <description>OTG_FS host channel-7 transfer size
+ register</description>
+ <addressOffset>0x1F0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>DPID</name>
+ <description>Data PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>OTG_FS_DEVICE</name>
+ <description>USB on the go full speed</description>
+ <groupName>USB_OTG_FS</groupName>
+ <baseAddress>0x50000800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>FS_DCFG</name>
+ <displayName>FS_DCFG</displayName>
+ <description>OTG_FS device configuration register
+ (OTG_FS_DCFG)</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x02200000</resetValue>
+ <fields>
+ <field>
+ <name>DSPD</name>
+ <description>Device speed</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NZLSOHSK</name>
+ <description>Non-zero-length status OUT
+ handshake</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DAD</name>
+ <description>Device address</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>PFIVL</name>
+ <description>Periodic frame interval</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DCTL</name>
+ <displayName>FS_DCTL</displayName>
+ <description>OTG_FS device control register
+ (OTG_FS_DCTL)</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RWUSIG</name>
+ <description>Remote wakeup signaling</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SDIS</name>
+ <description>Soft disconnect</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>GINSTS</name>
+ <description>Global IN NAK status</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>GONSTS</name>
+ <description>Global OUT NAK status</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TCTL</name>
+ <description>Test control</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SGINAK</name>
+ <description>Set global IN NAK</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CGINAK</name>
+ <description>Clear global IN NAK</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SGONAK</name>
+ <description>Set global OUT NAK</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CGONAK</name>
+ <description>Clear global OUT NAK</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>POPRGDNE</name>
+ <description>Power-on programming done</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DSTS</name>
+ <displayName>FS_DSTS</displayName>
+ <description>OTG_FS device status register
+ (OTG_FS_DSTS)</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000010</resetValue>
+ <fields>
+ <field>
+ <name>SUSPSTS</name>
+ <description>Suspend status</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ENUMSPD</name>
+ <description>Enumerated speed</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>EERR</name>
+ <description>Erratic error</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FNSOF</name>
+ <description>Frame number of the received
+ SOF</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>14</bitWidth>
+ </field>
+ <field>
+ <name>DEVLNSTS</name>
+ <description>Device line status</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DIEPMSK</name>
+ <displayName>FS_DIEPMSK</displayName>
+ <description>OTG_FS device IN endpoint common interrupt
+ mask register (OTG_FS_DIEPMSK)</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed interrupt
+ mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPDM</name>
+ <description>Endpoint disabled interrupt
+ mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TOM</name>
+ <description>Timeout condition mask (Non-isochronous
+ endpoints)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ITTXFEMSK</name>
+ <description>IN token received when TxFIFO empty
+ mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>INEPNMM</name>
+ <description>IN token received with EP mismatch
+ mask</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>INEPNEM</name>
+ <description>IN endpoint NAK effective
+ mask</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DOEPMSK</name>
+ <displayName>FS_DOEPMSK</displayName>
+ <description>OTG_FS device OUT endpoint common interrupt
+ mask register (OTG_FS_DOEPMSK)</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>XFRCM</name>
+ <description>Transfer completed interrupt
+ mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPDM</name>
+ <description>Endpoint disabled interrupt
+ mask</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STUPM</name>
+ <description>SETUP phase done mask</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OTEPDM</name>
+ <description>OUT token received when endpoint
+ disabled mask</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DAINT</name>
+ <displayName>FS_DAINT</displayName>
+ <description>OTG_FS device all endpoints interrupt
+ register (OTG_FS_DAINT)</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IEPINT</name>
+ <description>IN endpoint interrupt bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>OEPINT</name>
+ <description>OUT endpoint interrupt
+ bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DAINTMSK</name>
+ <displayName>FS_DAINTMSK</displayName>
+ <description>OTG_FS all endpoints interrupt mask register
+ (OTG_FS_DAINTMSK)</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>IEPM</name>
+ <description>IN EP interrupt mask bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>OEPINT</name>
+ <description>OUT endpoint interrupt
+ bits</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DVBUSDIS</name>
+ <displayName>DVBUSDIS</displayName>
+ <description>OTG_FS device VBUS discharge time
+ register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000017D7</resetValue>
+ <fields>
+ <field>
+ <name>VBUSDT</name>
+ <description>Device VBUS discharge time</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DVBUSPULSE</name>
+ <displayName>DVBUSPULSE</displayName>
+ <description>OTG_FS device VBUS pulsing time
+ register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000005B8</resetValue>
+ <fields>
+ <field>
+ <name>DVBUSP</name>
+ <description>Device VBUS pulsing time</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPEMPMSK</name>
+ <displayName>DIEPEMPMSK</displayName>
+ <description>OTG_FS device IN endpoint FIFO empty
+ interrupt mask register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INEPTXFEM</name>
+ <description>IN EP Tx FIFO empty interrupt mask
+ bits</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FS_DIEPCTL0</name>
+ <displayName>FS_DIEPCTL0</displayName>
+ <description>OTG_FS device control IN endpoint 0 control
+ register (OTG_FS_DIEPCTL0)</description>
+ <addressOffset>0x100</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MPSIZ</name>
+ <description>Maximum packet size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USB active endpoint</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAK status</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>Endpoint type</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>STALL</name>
+ <description>STALL handshake</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXFNUM</name>
+ <description>TxFIFO number</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>Clear NAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>Set NAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>Endpoint disable</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EPENA</name>
+ <description>Endpoint enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPCTL1</name>
+ <displayName>DIEPCTL1</displayName>
+ <description>OTG device endpoint-1 control
+ register</description>
+ <addressOffset>0x120</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPENA</name>
+ <description>EPENA</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>EPDIS</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SODDFRM_SD1PID</name>
+ <description>SODDFRM/SD1PID</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SD0PID_SEVNFRM</name>
+ <description>SD0PID/SEVNFRM</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>SNAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>CNAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>TXFNUM</name>
+ <description>TXFNUM</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>Stall</name>
+ <description>Stall</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>EPTYP</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAKSTS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EONUM_DPID</name>
+ <description>EONUM/DPID</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USBAEP</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MPSIZ</name>
+ <description>MPSIZ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPCTL2</name>
+ <displayName>DIEPCTL2</displayName>
+ <description>OTG device endpoint-2 control
+ register</description>
+ <addressOffset>0x140</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPENA</name>
+ <description>EPENA</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>EPDIS</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SODDFRM</name>
+ <description>SODDFRM</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SD0PID_SEVNFRM</name>
+ <description>SD0PID/SEVNFRM</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>SNAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>CNAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>TXFNUM</name>
+ <description>TXFNUM</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>Stall</name>
+ <description>Stall</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>EPTYP</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAKSTS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EONUM_DPID</name>
+ <description>EONUM/DPID</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USBAEP</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MPSIZ</name>
+ <description>MPSIZ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPCTL3</name>
+ <displayName>DIEPCTL3</displayName>
+ <description>OTG device endpoint-3 control
+ register</description>
+ <addressOffset>0x160</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPENA</name>
+ <description>EPENA</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>EPDIS</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SODDFRM</name>
+ <description>SODDFRM</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SD0PID_SEVNFRM</name>
+ <description>SD0PID/SEVNFRM</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>SNAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>CNAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>TXFNUM</name>
+ <description>TXFNUM</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>Stall</name>
+ <description>Stall</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>EPTYP</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAKSTS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EONUM_DPID</name>
+ <description>EONUM/DPID</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USBAEP</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MPSIZ</name>
+ <description>MPSIZ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPCTL0</name>
+ <displayName>DOEPCTL0</displayName>
+ <description>device endpoint-0 control
+ register</description>
+ <addressOffset>0x300</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00008000</resetValue>
+ <fields>
+ <field>
+ <name>EPENA</name>
+ <description>EPENA</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>EPDIS</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>SNAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>CNAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>Stall</name>
+ <description>Stall</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SNPM</name>
+ <description>SNPM</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>EPTYP</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAKSTS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USBAEP</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>MPSIZ</name>
+ <description>MPSIZ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPCTL1</name>
+ <displayName>DOEPCTL1</displayName>
+ <description>device endpoint-1 control
+ register</description>
+ <addressOffset>0x320</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPENA</name>
+ <description>EPENA</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>EPDIS</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SODDFRM</name>
+ <description>SODDFRM</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SD0PID_SEVNFRM</name>
+ <description>SD0PID/SEVNFRM</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>SNAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>CNAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>Stall</name>
+ <description>Stall</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SNPM</name>
+ <description>SNPM</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>EPTYP</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAKSTS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EONUM_DPID</name>
+ <description>EONUM/DPID</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USBAEP</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MPSIZ</name>
+ <description>MPSIZ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPCTL2</name>
+ <displayName>DOEPCTL2</displayName>
+ <description>device endpoint-2 control
+ register</description>
+ <addressOffset>0x340</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPENA</name>
+ <description>EPENA</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>EPDIS</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SODDFRM</name>
+ <description>SODDFRM</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SD0PID_SEVNFRM</name>
+ <description>SD0PID/SEVNFRM</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>SNAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>CNAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>Stall</name>
+ <description>Stall</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SNPM</name>
+ <description>SNPM</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>EPTYP</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAKSTS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EONUM_DPID</name>
+ <description>EONUM/DPID</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USBAEP</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MPSIZ</name>
+ <description>MPSIZ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPCTL3</name>
+ <displayName>DOEPCTL3</displayName>
+ <description>device endpoint-3 control
+ register</description>
+ <addressOffset>0x360</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EPENA</name>
+ <description>EPENA</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDIS</name>
+ <description>EPDIS</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SODDFRM</name>
+ <description>SODDFRM</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SD0PID_SEVNFRM</name>
+ <description>SD0PID/SEVNFRM</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>SNAK</name>
+ <description>SNAK</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>CNAK</name>
+ <description>CNAK</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>Stall</name>
+ <description>Stall</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SNPM</name>
+ <description>SNPM</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPTYP</name>
+ <description>EPTYP</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NAKSTS</name>
+ <description>NAKSTS</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>EONUM_DPID</name>
+ <description>EONUM/DPID</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USBAEP</name>
+ <description>USBAEP</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>MPSIZ</name>
+ <description>MPSIZ</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPINT0</name>
+ <displayName>DIEPINT0</displayName>
+ <description>device endpoint-x interrupt
+ register</description>
+ <addressOffset>0x108</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>TXFE</name>
+ <description>TXFE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>INEPNE</name>
+ <description>INEPNE</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ITTXFE</name>
+ <description>ITTXFE</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TOC</name>
+ <description>TOC</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPINT1</name>
+ <displayName>DIEPINT1</displayName>
+ <description>device endpoint-1 interrupt
+ register</description>
+ <addressOffset>0x128</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>TXFE</name>
+ <description>TXFE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>INEPNE</name>
+ <description>INEPNE</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ITTXFE</name>
+ <description>ITTXFE</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TOC</name>
+ <description>TOC</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPINT2</name>
+ <displayName>DIEPINT2</displayName>
+ <description>device endpoint-2 interrupt
+ register</description>
+ <addressOffset>0x148</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>TXFE</name>
+ <description>TXFE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>INEPNE</name>
+ <description>INEPNE</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ITTXFE</name>
+ <description>ITTXFE</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TOC</name>
+ <description>TOC</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPINT3</name>
+ <displayName>DIEPINT3</displayName>
+ <description>device endpoint-3 interrupt
+ register</description>
+ <addressOffset>0x168</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>TXFE</name>
+ <description>TXFE</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>INEPNE</name>
+ <description>INEPNE</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ITTXFE</name>
+ <description>ITTXFE</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TOC</name>
+ <description>TOC</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPINT0</name>
+ <displayName>DOEPINT0</displayName>
+ <description>device endpoint-0 interrupt
+ register</description>
+ <addressOffset>0x308</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>B2BSTUP</name>
+ <description>B2BSTUP</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OTEPDIS</name>
+ <description>OTEPDIS</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STUP</name>
+ <description>STUP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPINT1</name>
+ <displayName>DOEPINT1</displayName>
+ <description>device endpoint-1 interrupt
+ register</description>
+ <addressOffset>0x328</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>B2BSTUP</name>
+ <description>B2BSTUP</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OTEPDIS</name>
+ <description>OTEPDIS</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STUP</name>
+ <description>STUP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPINT2</name>
+ <displayName>DOEPINT2</displayName>
+ <description>device endpoint-2 interrupt
+ register</description>
+ <addressOffset>0x348</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>B2BSTUP</name>
+ <description>B2BSTUP</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OTEPDIS</name>
+ <description>OTEPDIS</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STUP</name>
+ <description>STUP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPINT3</name>
+ <displayName>DOEPINT3</displayName>
+ <description>device endpoint-3 interrupt
+ register</description>
+ <addressOffset>0x368</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000080</resetValue>
+ <fields>
+ <field>
+ <name>B2BSTUP</name>
+ <description>B2BSTUP</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OTEPDIS</name>
+ <description>OTEPDIS</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STUP</name>
+ <description>STUP</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EPDISD</name>
+ <description>EPDISD</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>XFRC</name>
+ <description>XFRC</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPTSIZ0</name>
+ <displayName>DIEPTSIZ0</displayName>
+ <description>device endpoint-0 transfer size
+ register</description>
+ <addressOffset>0x110</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPTSIZ0</name>
+ <displayName>DOEPTSIZ0</displayName>
+ <description>device OUT endpoint-0 transfer size
+ register</description>
+ <addressOffset>0x310</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>STUPCNT</name>
+ <description>SETUP packet count</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPTSIZ1</name>
+ <displayName>DIEPTSIZ1</displayName>
+ <description>device endpoint-1 transfer size
+ register</description>
+ <addressOffset>0x130</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MCNT</name>
+ <description>Multi count</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPTSIZ2</name>
+ <displayName>DIEPTSIZ2</displayName>
+ <description>device endpoint-2 transfer size
+ register</description>
+ <addressOffset>0x150</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MCNT</name>
+ <description>Multi count</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIEPTSIZ3</name>
+ <displayName>DIEPTSIZ3</displayName>
+ <description>device endpoint-3 transfer size
+ register</description>
+ <addressOffset>0x170</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MCNT</name>
+ <description>Multi count</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DTXFSTS0</name>
+ <displayName>DTXFSTS0</displayName>
+ <description>OTG_FS device IN endpoint transmit FIFO
+ status register</description>
+ <addressOffset>0x118</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INEPTFSAV</name>
+ <description>IN endpoint TxFIFO space
+ available</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DTXFSTS1</name>
+ <displayName>DTXFSTS1</displayName>
+ <description>OTG_FS device IN endpoint transmit FIFO
+ status register</description>
+ <addressOffset>0x138</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INEPTFSAV</name>
+ <description>IN endpoint TxFIFO space
+ available</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DTXFSTS2</name>
+ <displayName>DTXFSTS2</displayName>
+ <description>OTG_FS device IN endpoint transmit FIFO
+ status register</description>
+ <addressOffset>0x158</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INEPTFSAV</name>
+ <description>IN endpoint TxFIFO space
+ available</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DTXFSTS3</name>
+ <displayName>DTXFSTS3</displayName>
+ <description>OTG_FS device IN endpoint transmit FIFO
+ status register</description>
+ <addressOffset>0x178</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INEPTFSAV</name>
+ <description>IN endpoint TxFIFO space
+ available</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPTSIZ1</name>
+ <displayName>DOEPTSIZ1</displayName>
+ <description>device OUT endpoint-1 transfer size
+ register</description>
+ <addressOffset>0x330</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RXDPID_STUPCNT</name>
+ <description>Received data PID/SETUP packet
+ count</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPTSIZ2</name>
+ <displayName>DOEPTSIZ2</displayName>
+ <description>device OUT endpoint-2 transfer size
+ register</description>
+ <addressOffset>0x350</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RXDPID_STUPCNT</name>
+ <description>Received data PID/SETUP packet
+ count</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOEPTSIZ3</name>
+ <displayName>DOEPTSIZ3</displayName>
+ <description>device OUT endpoint-3 transfer size
+ register</description>
+ <addressOffset>0x370</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RXDPID_STUPCNT</name>
+ <description>Received data PID/SETUP packet
+ count</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PKTCNT</name>
+ <description>Packet count</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>XFRSIZ</name>
+ <description>Transfer size</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>19</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>OTG_FS_PWRCLK</name>
+ <description>USB on the go full speed</description>
+ <groupName>USB_OTG_FS</groupName>
+ <baseAddress>0x50000E00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>FS_PCGCCTL</name>
+ <displayName>FS_PCGCCTL</displayName>
+ <description>OTG_FS power and clock gating control
+ register (OTG_FS_PCGCCTL)</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>STPPCLK</name>
+ <description>Stop PHY clock</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GATEHCLK</name>
+ <description>Gate HCLK</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PHYSUSP</name>
+ <description>PHY Suspended</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>QUADSPI</name>
+ <description>QuadSPI interface</description>
+ <groupName>QUADSPI</groupName>
+ <baseAddress>0xA0001000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PRESCALER</name>
+ <description>Clock prescaler</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>PMM</name>
+ <description>Polling match mode</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>APMS</name>
+ <description>Automatic poll mode stop</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TOIE</name>
+ <description>TimeOut interrupt enable</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMIE</name>
+ <description>Status match interrupt
+ enable</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FTIE</name>
+ <description>FIFO threshold interrupt
+ enable</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt
+ enable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt
+ enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FTHRES</name>
+ <description>IFO threshold level</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>FSEL</name>
+ <description>FLASH memory selection</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DFM</name>
+ <description>Dual-flash mode</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SSHIFT</name>
+ <description>Sample shift</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCEN</name>
+ <description>Timeout counter enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN</name>
+ <description>DMA enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ABORT</name>
+ <description>Abort request</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>Enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DCR</name>
+ <displayName>DCR</displayName>
+ <description>device configuration register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FSIZE</name>
+ <description>FLASH memory size</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>CSHT</name>
+ <description>Chip select high time</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CKMODE</name>
+ <description>Mode 0 / mode 3</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FLEVEL</name>
+ <description>FIFO level</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>BUSY</name>
+ <description>Busy</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TOF</name>
+ <description>Timeout flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMF</name>
+ <description>Status match flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FTF</name>
+ <description>FIFO threshold flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCF</name>
+ <description>Transfer complete flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEF</name>
+ <description>Transfer error flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FCR</name>
+ <displayName>FCR</displayName>
+ <description>flag clear register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CTOF</name>
+ <description>Clear timeout flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CSMF</name>
+ <description>Clear status match flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCF</name>
+ <description>Clear transfer complete
+ flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEF</name>
+ <description>Clear transfer error flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DLR</name>
+ <displayName>DLR</displayName>
+ <description>data length register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DL</name>
+ <description>Data length</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR</name>
+ <displayName>CCR</displayName>
+ <description>communication configuration
+ register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DDRM</name>
+ <description>Double data rate mode</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DHHC</name>
+ <description>DDR hold half cycle</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SIOO</name>
+ <description>Send instruction only once
+ mode</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FMODE</name>
+ <description>Functional mode</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DMODE</name>
+ <description>Data mode</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DCYC</name>
+ <description>Number of dummy cycles</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>ABSIZE</name>
+ <description>Alternate bytes size</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ABMODE</name>
+ <description>Alternate bytes mode</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ADSIZE</name>
+ <description>Address size</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ADMODE</name>
+ <description>Address mode</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>IMODE</name>
+ <description>Instruction mode</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>INSTRUCTION</name>
+ <description>Instruction</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AR</name>
+ <displayName>AR</displayName>
+ <description>address register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ADDRESS</name>
+ <description>Address</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ABR</name>
+ <displayName>ABR</displayName>
+ <description>ABR</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ALTERNATE</name>
+ <description>ALTERNATE</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <displayName>DR</displayName>
+ <description>data register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA</name>
+ <description>Data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSMKR</name>
+ <displayName>PSMKR</displayName>
+ <description>polling status mask register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MASK</name>
+ <description>Status mask</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PSMAR</name>
+ <displayName>PSMAR</displayName>
+ <description>polling status match register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MATCH</name>
+ <description>Status match</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PIR</name>
+ <displayName>PIR</displayName>
+ <description>polling interval register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>INTERVAL</name>
+ <description>Polling interval</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LPTR</name>
+ <displayName>LPTR</displayName>
+ <description>low-power timeout register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIMEOUT</name>
+ <description>Timeout period</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>LPTIM</name>
+ <description>Low power timer</description>
+ <groupName>LPTIM</groupName>
+ <baseAddress>0x40002400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>QuadSPI</name>
+ <description>Quad-SPI global interrupt</description>
+ <value>92</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>ISR</name>
+ <displayName>ISR</displayName>
+ <description>Interrupt and Status Register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DOWN</name>
+ <description>Counter direction change up to
+ down</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UP</name>
+ <description>Counter direction change down to
+ up</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARROK</name>
+ <description>Autoreload register update
+ OK</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMPOK</name>
+ <description>Compare register update OK</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTTRIG</name>
+ <description>External trigger edge
+ event</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARRM</name>
+ <description>Autoreload match</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMPM</name>
+ <description>Compare match</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICR</name>
+ <displayName>ICR</displayName>
+ <description>Interrupt Clear Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DOWNCF</name>
+ <description>Direction change to down Clear
+ Flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UPCF</name>
+ <description>Direction change to UP Clear
+ Flag</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARROKCF</name>
+ <description>Autoreload register update OK Clear
+ Flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMPOKCF</name>
+ <description>Compare register update OK Clear
+ Flag</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTTRIGCF</name>
+ <description>External trigger valid edge Clear
+ Flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARRMCF</name>
+ <description>Autoreload match Clear
+ Flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMPMCF</name>
+ <description>compare match Clear Flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IER</name>
+ <displayName>IER</displayName>
+ <description>Interrupt Enable Register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DOWNIE</name>
+ <description>Direction change to down Interrupt
+ Enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>UPIE</name>
+ <description>Direction change to UP Interrupt
+ Enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARROKIE</name>
+ <description>Autoreload register update OK Interrupt
+ Enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMPOKIE</name>
+ <description>Compare register update OK Interrupt
+ Enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTTRIGIE</name>
+ <description>External trigger valid edge Interrupt
+ Enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARRMIE</name>
+ <description>Autoreload match Interrupt
+ Enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CMPMIE</name>
+ <description>Compare match Interrupt
+ Enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CFGR</name>
+ <displayName>CFGR</displayName>
+ <description>Configuration Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ENC</name>
+ <description>Encoder mode enable</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>COUNTMODE</name>
+ <description>counter mode enabled</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PRELOAD</name>
+ <description>Registers update mode</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAVPOL</name>
+ <description>Waveform shape polarity</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAVE</name>
+ <description>Waveform shape</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMOUT</name>
+ <description>Timeout enable</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TRIGEN</name>
+ <description>Trigger enable and
+ polarity</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>TRIGSEL</name>
+ <description>Trigger selector</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>PRESC</name>
+ <description>Clock prescaler</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TRGFLT</name>
+ <description>Configurable digital filter for
+ trigger</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CKFLT</name>
+ <description>Configurable digital filter for external
+ clock</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CKPOL</name>
+ <description>Clock Polarity</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CKSEL</name>
+ <description>Clock selector</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>Control Register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNTSTRT</name>
+ <description>Timer start in continuous
+ mode</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SNGSTRT</name>
+ <description>LPTIM start in single mode</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ENABLE</name>
+ <description>LPTIM Enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMP</name>
+ <displayName>CMP</displayName>
+ <description>Compare Register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CMP</name>
+ <description>Compare value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARR</name>
+ <displayName>ARR</displayName>
+ <description>Autoreload Register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000001</resetValue>
+ <fields>
+ <field>
+ <name>ARR</name>
+ <description>Auto reload value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNT</name>
+ <displayName>CNT</displayName>
+ <description>Counter Register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CNT</name>
+ <description>Counter value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>DAC</name>
+ <description>Digital-to-analog converter</description>
+ <groupName>DAC</groupName>
+ <baseAddress>0x40007400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAUDRIE2</name>
+ <description>DAC channel2 DMA underrun interrupt
+ enable</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN2</name>
+ <description>DAC channel2 DMA enable</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MAMP2</name>
+ <description>DAC channel2 mask/amplitude
+ selector</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>WAVE2</name>
+ <description>DAC channel2 noise/triangle wave
+ generation enable</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>TSEL2</name>
+ <description>DAC channel2 trigger
+ selection</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TEN2</name>
+ <description>DAC channel2 trigger
+ enable</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BOFF2</name>
+ <description>DAC channel2 output buffer
+ disable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN2</name>
+ <description>DAC channel2 enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAUDRIE1</name>
+ <description>DAC channel1 DMA Underrun Interrupt
+ enable</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN1</name>
+ <description>DAC channel1 DMA enable</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MAMP1</name>
+ <description>DAC channel1 mask/amplitude
+ selector</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>WAVE1</name>
+ <description>DAC channel1 noise/triangle wave
+ generation enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>TSEL1</name>
+ <description>DAC channel1 trigger
+ selection</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>TEN1</name>
+ <description>DAC channel1 trigger
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BOFF1</name>
+ <description>DAC channel1 output buffer
+ disable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN1</name>
+ <description>DAC channel1 enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SWTRIGR</name>
+ <displayName>SWTRIGR</displayName>
+ <description>software trigger register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SWTRIG2</name>
+ <description>DAC channel2 software
+ trigger</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWTRIG1</name>
+ <description>DAC channel1 software
+ trigger</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR12R1</name>
+ <displayName>DHR12R1</displayName>
+ <description>channel1 12-bit right-aligned data holding
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit right-aligned
+ data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR12L1</name>
+ <displayName>DHR12L1</displayName>
+ <description>channel1 12-bit left aligned data holding
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit left-aligned
+ data</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR8R1</name>
+ <displayName>DHR8R1</displayName>
+ <description>channel1 8-bit right aligned data holding
+ register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 8-bit right-aligned
+ data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR12R2</name>
+ <displayName>DHR12R2</displayName>
+ <description>channel2 12-bit right aligned data holding
+ register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit right-aligned
+ data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR12L2</name>
+ <displayName>DHR12L2</displayName>
+ <description>channel2 12-bit left aligned data holding
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit left-aligned
+ data</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR8R2</name>
+ <displayName>DHR8R2</displayName>
+ <description>channel2 8-bit right-aligned data holding
+ register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 8-bit right-aligned
+ data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR12RD</name>
+ <displayName>DHR12RD</displayName>
+ <description>Dual DAC 12-bit right-aligned data holding
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit right-aligned
+ data</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit right-aligned
+ data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR12LD</name>
+ <displayName>DHR12LD</displayName>
+ <description>DUAL DAC 12-bit left aligned data holding
+ register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit left-aligned
+ data</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit left-aligned
+ data</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DHR8RD</name>
+ <displayName>DHR8RD</displayName>
+ <description>DUAL DAC 8-bit right aligned data holding
+ register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 8-bit right-aligned
+ data</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 8-bit right-aligned
+ data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOR1</name>
+ <displayName>DOR1</displayName>
+ <description>channel1 data output register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DOR</name>
+ <description>DAC channel1 data output</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOR2</name>
+ <displayName>DOR2</displayName>
+ <description>channel2 data output register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DOR</name>
+ <description>DAC channel2 data output</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAUDR2</name>
+ <description>DAC channel2 DMA underrun
+ flag</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAUDR1</name>
+ <description>DAC channel1 DMA underrun
+ flag</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SAI</name>
+ <description>Serial audio interface</description>
+ <groupName>SAI</groupName>
+ <baseAddress>0x40015800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>BCR1</name>
+ <displayName>BCR1</displayName>
+ <description>BConfiguration register 1</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000040</resetValue>
+ <fields>
+ <field>
+ <name>MCJDIV</name>
+ <description>Master clock divider</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>NODIV</name>
+ <description>No divider</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN</name>
+ <description>DMA enable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SAIBEN</name>
+ <description>Audio block B enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OutDri</name>
+ <description>Output drive</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MONO</name>
+ <description>Mono mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYNCEN</name>
+ <description>Synchronization enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CKSTR</name>
+ <description>Clock strobing edge</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSBFIRST</name>
+ <description>Least significant bit
+ first</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DS</name>
+ <description>Data size</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>PRTCFG</name>
+ <description>Protocol configuration</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE</name>
+ <description>Audio block mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BCR2</name>
+ <displayName>BCR2</displayName>
+ <description>BConfiguration register 2</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>COMP</name>
+ <description>Companding mode</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CPL</name>
+ <description>Complement bit</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTECN</name>
+ <description>Mute counter</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ <field>
+ <name>MUTEVAL</name>
+ <description>Mute value</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTE</name>
+ <description>Mute</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TRIS</name>
+ <description>Tristate management on data
+ line</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFLUS</name>
+ <description>FIFO flush</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BFRCR</name>
+ <displayName>BFRCR</displayName>
+ <description>BFRCR</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000007</resetValue>
+ <fields>
+ <field>
+ <name>FSOFF</name>
+ <description>Frame synchronization
+ offset</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSPOL</name>
+ <description>Frame synchronization
+ polarity</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSDEF</name>
+ <description>Frame synchronization
+ definition</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSALL</name>
+ <description>Frame synchronization active level
+ length</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>FRL</name>
+ <description>Frame length</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BSLOTR</name>
+ <displayName>BSLOTR</displayName>
+ <description>BSlot register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SLOTEN</name>
+ <description>Slot enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>NBSLOT</name>
+ <description>Number of slots in an audio
+ frame</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SLOTSZ</name>
+ <description>Slot size</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FBOFF</name>
+ <description>First bit offset</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BIM</name>
+ <displayName>BIM</displayName>
+ <description>BInterrupt mask register2</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LFSDETIE</name>
+ <description>Late frame synchronization detection
+ interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AFSDETIE</name>
+ <description>Anticipated frame synchronization
+ detection interrupt enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CNRDYIE</name>
+ <description>Codec not ready interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FREQIE</name>
+ <description>FIFO request interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WCKCFG</name>
+ <description>Wrong clock configuration interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTEDET</name>
+ <description>Mute detection interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRUDRIE</name>
+ <description>Overrun/underrun interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BSR</name>
+ <displayName>BSR</displayName>
+ <description>BStatus register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FLVL</name>
+ <description>FIFO level threshold</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>LFSDET</name>
+ <description>Late frame synchronization
+ detection</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AFSDET</name>
+ <description>Anticipated frame synchronization
+ detection</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CNRDY</name>
+ <description>Codec not ready</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FREQ</name>
+ <description>FIFO request</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WCKCFG</name>
+ <description>Wrong clock configuration
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTEDET</name>
+ <description>Mute detection</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRUDR</name>
+ <description>Overrun / underrun</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BCLRFR</name>
+ <displayName>BCLRFR</displayName>
+ <description>BClear flag register</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LFSDET</name>
+ <description>Clear late frame synchronization
+ detection flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAFSDET</name>
+ <description>Clear anticipated frame synchronization
+ detection flag</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CNRDY</name>
+ <description>Clear codec not ready flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WCKCFG</name>
+ <description>Clear wrong clock configuration
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTEDET</name>
+ <description>Mute detection flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRUDR</name>
+ <description>Clear overrun / underrun</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDR</name>
+ <displayName>BDR</displayName>
+ <description>BData register</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA</name>
+ <description>Data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ACR1</name>
+ <displayName>ACR1</displayName>
+ <description>AConfiguration register 1</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000040</resetValue>
+ <fields>
+ <field>
+ <name>MCJDIV</name>
+ <description>Master clock divider</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>NODIV</name>
+ <description>No divider</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN</name>
+ <description>DMA enable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SAIAEN</name>
+ <description>Audio block A enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OutDri</name>
+ <description>Output drive</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MONO</name>
+ <description>Mono mode</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYNCEN</name>
+ <description>Synchronization enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CKSTR</name>
+ <description>Clock strobing edge</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LSBFIRST</name>
+ <description>Least significant bit
+ first</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DS</name>
+ <description>Data size</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>PRTCFG</name>
+ <description>Protocol configuration</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE</name>
+ <description>Audio block mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ACR2</name>
+ <displayName>ACR2</displayName>
+ <description>AConfiguration register 2</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>COMP</name>
+ <description>Companding mode</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CPL</name>
+ <description>Complement bit</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTECN</name>
+ <description>Mute counter</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ <field>
+ <name>MUTEVAL</name>
+ <description>Mute value</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTE</name>
+ <description>Mute</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TRIS</name>
+ <description>Tristate management on data
+ line</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FFLUS</name>
+ <description>FIFO flush</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FTH</name>
+ <description>FIFO threshold</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AFRCR</name>
+ <displayName>AFRCR</displayName>
+ <description>AFRCR</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000007</resetValue>
+ <fields>
+ <field>
+ <name>FSOFF</name>
+ <description>Frame synchronization
+ offset</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSPOL</name>
+ <description>Frame synchronization
+ polarity</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSDEF</name>
+ <description>Frame synchronization
+ definition</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FSALL</name>
+ <description>Frame synchronization active level
+ length</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>FRL</name>
+ <description>Frame length</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ASLOTR</name>
+ <displayName>ASLOTR</displayName>
+ <description>ASlot register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SLOTEN</name>
+ <description>Slot enable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>NBSLOT</name>
+ <description>Number of slots in an audio
+ frame</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SLOTSZ</name>
+ <description>Slot size</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FBOFF</name>
+ <description>First bit offset</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AIM</name>
+ <displayName>AIM</displayName>
+ <description>AInterrupt mask register2</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LFSDET</name>
+ <description>Late frame synchronization detection
+ interrupt enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AFSDETIE</name>
+ <description>Anticipated frame synchronization
+ detection interrupt enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CNRDYIE</name>
+ <description>Codec not ready interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FREQIE</name>
+ <description>FIFO request interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WCKCFG</name>
+ <description>Wrong clock configuration interrupt
+ enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTEDET</name>
+ <description>Mute detection interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRUDRIE</name>
+ <description>Overrun/underrun interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ASR</name>
+ <displayName>ASR</displayName>
+ <description>AStatus register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>FLVL</name>
+ <description>FIFO level threshold</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>LFSDET</name>
+ <description>Late frame synchronization
+ detection</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AFSDET</name>
+ <description>Anticipated frame synchronization
+ detection</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CNRDY</name>
+ <description>Codec not ready</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FREQ</name>
+ <description>FIFO request</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WCKCFG</name>
+ <description>Wrong clock configuration flag. This bit
+ is read only.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTEDET</name>
+ <description>Mute detection</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRUDR</name>
+ <description>Overrun / underrun</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ACLRFR</name>
+ <displayName>ACLRFR</displayName>
+ <description>AClear flag register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LFSDET</name>
+ <description>Clear late frame synchronization
+ detection flag</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAFSDET</name>
+ <description>Clear anticipated frame synchronization
+ detection flag.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CNRDY</name>
+ <description>Clear codec not ready flag</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WCKCFG</name>
+ <description>Clear wrong clock configuration
+ flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUTEDET</name>
+ <description>Mute detection flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRUDR</name>
+ <description>Clear overrun / underrun</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ADR</name>
+ <displayName>ADR</displayName>
+ <description>AData register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DATA</name>
+ <description>Data</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>AES</name>
+ <description>Advanced encryption standard hardware
+ accelerator</description>
+ <groupName>AES</groupName>
+ <baseAddress>0x50060000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>CRYPTO</name>
+ <description>AES global interrupt</description>
+ <value>79</value>
+ </interrupt>
+ <interrupt>
+ <name>SAI1</name>
+ <description>SAI1 global interrupt</description>
+ <value>87</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR</name>
+ <displayName>CR</displayName>
+ <description>control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAOUTEN</name>
+ <description>Enable DMA management of data output
+ phase</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAINEN</name>
+ <description>Enable DMA management of data input
+ phase</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRIE</name>
+ <description>Error interrupt enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCFIE</name>
+ <description>CCF flag interrupt enable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRC</name>
+ <description>Error clear</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCFC</name>
+ <description>Computation Complete Flag
+ Clear</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHMOD</name>
+ <description>AES chaining mode</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE</name>
+ <description>AES operating mode</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>DATATYPE</name>
+ <description>Data type selection (for data in and
+ data out to/from the cryptographic
+ block)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>EN</name>
+ <description>AES enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <displayName>SR</displayName>
+ <description>status register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>WRERR</name>
+ <description>Write error flag</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RDERR</name>
+ <description>Read error flag</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCF</name>
+ <description>Computation complete flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DINR</name>
+ <displayName>DINR</displayName>
+ <description>data input register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_DINR</name>
+ <description>Data Input Register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOUTR</name>
+ <displayName>DOUTR</displayName>
+ <description>data output register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_DOUTR</name>
+ <description>Data output register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>KEYR0</name>
+ <displayName>KEYR0</displayName>
+ <description>key register 0</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_KEYR0</name>
+ <description>Data Output Register (LSB key
+ [31:0])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>KEYR1</name>
+ <displayName>KEYR1</displayName>
+ <description>key register 1</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_KEYR1</name>
+ <description>AES key register (key
+ [63:32])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>KEYR2</name>
+ <displayName>KEYR2</displayName>
+ <description>key register 2</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_KEYR2</name>
+ <description>AES key register (key
+ [95:64])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>KEYR3</name>
+ <displayName>KEYR3</displayName>
+ <description>key register 3</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_KEYR3</name>
+ <description>AES key register (MSB key
+ [127:96])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IVR0</name>
+ <displayName>IVR0</displayName>
+ <description>initialization vector register
+ 0</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_IVR0</name>
+ <description>initialization vector register (LSB IVR
+ [31:0])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IVR1</name>
+ <displayName>IVR1</displayName>
+ <description>initialization vector register
+ 1</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_IVR1</name>
+ <description>Initialization Vector Register (IVR
+ [63:32])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IVR2</name>
+ <displayName>IVR2</displayName>
+ <description>initialization vector register
+ 2</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_IVR2</name>
+ <description>Initialization Vector Register (IVR
+ [95:64])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IVR3</name>
+ <displayName>IVR3</displayName>
+ <description>initialization vector register
+ 3</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AES_IVR3</name>
+ <description>Initialization Vector Register (MSB IVR
+ [127:96])</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
diff --git a/examples/device.rs b/examples/device.rs
new file mode 100644
index 0000000000000000000000000000000000000000..baf5ca2900fa4893d43eda22e4078b55b5b558bc
--- /dev/null
+++ b/examples/device.rs
@@ -0,0 +1,66 @@
+//! Using a device crate
+//!
+//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provide an
+//! API to access the peripherals of a device.
+//!
+//! [`svd2rust`]: https://crates.io/crates/svd2rust
+//!
+//! Device crates also provide an `interrupt!` macro (behind the "rt" feature) to register interrupt
+//! handlers.
+//!
+//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
+//!
+//! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
+//!
+//! ```
+//! $ edit Cargo.toml && tail $_
+//! [dependencies.stm32f103xx]
+//! features = ["rt"]
+//! version = "0.10.0"
+//! ```
+//!
+//! ---
+
+#![no_main]
+#![no_std]
+
+#[allow(unused_extern_crates)]
+extern crate panic_halt;
+
+use cortex_m::{iprint, peripheral::syst::SystClkSource};
+use cortex_m_rt::entry;
+use cortex_m_semihosting::hprintln;
+use stm32f4::stm32f411::{interrupt, Interrupt, ITM, NVIC};
+
+#[entry]
+fn main() -> ! {
+ let p = cortex_m::Peripherals::take().unwrap();
+
+ let mut syst = p.SYST;
+ let mut nvic = p.NVIC;
+
+ nvic.enable(Interrupt::EXTI0);
+
+ // configure the system timer to wrap around every second
+ syst.set_clock_source(SystClkSource::Core);
+ syst.set_reload(16_000_000); // 1s
+ syst.enable_counter();
+
+ loop {
+ // busy wait until the timer wraps around
+ while !syst.has_wrapped() {}
+
+ // trigger the `EXTI0` interrupt
+
+ NVIC::pend(Interrupt::EXTI0);
+ }
+}
+
+// try commenting out this line: you'll end in `default_handler` instead of in `exti0`
+#[interrupt]
+fn EXTI0() {
+ hprintln!(".").unwrap();
+ let itm = unsafe { &mut *ITM::ptr() };
+ let stim = &mut itm.stim[0];
+ iprint!(stim, ".");
+}