diff --git a/LPC43xx_43Sxx.svd b/LPC43xx_43Sxx.svd
index fbac125cbd3037d271a396112236035063174c82..f83a857276d6af9721cdaf87a77d281f7521768f 100644
--- a/LPC43xx_43Sxx.svd
+++ b/LPC43xx_43Sxx.svd
@@ -39688,9 +39688,9 @@
</register>
<register>
- <dim>17</dim>
+ <dim>21</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>0-16</dimIndex>
+ <dimIndex>0-20</dimIndex>
<name>SFSP1_%s</name>
<description>Pin configuration register for pins P1</description>
<addressOffset>0x080</addressOffset>
@@ -39836,149 +39836,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[31:8]</bitRange>
-
- </field>
- </fields>
- </register>
- <register>
-
- <name>SFSP1_17</name>
- <description>Pin configuration register for pins P1_17</description>
- <addressOffset>0x0C4</addressOffset>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>MODE</name>
- <description>Select pin function.</description>
- <bitRange>[2:0]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FUNCTION_0_DEFAULT</name>
- <description>Function 0 (default)</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_1</name>
- <description>Function 1</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_2</name>
- <description>Function 2</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_3</name>
- <description>Function 3</description>
- <value>0x3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_4</name>
- <description>Function 4</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_5</name>
- <description>Function 5</description>
- <value>0x5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_6</name>
- <description>Function 6</description>
- <value>0x6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_7</name>
- <description>Function 7</description>
- <value>0x7</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPD</name>
- <description>Enable pull-down resistor at pad.</description>
- <bitRange>[3:3]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_PULL_DOWN</name>
- <description>Disable pull-down.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_PULL_DOWN</name>
- <description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPUN</name>
- <description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
- <bitRange>[4:4]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_PULL_UP</name>
- <description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_PULL_UP</name>
- <description>Disable pull-up</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[5:5]</bitRange>
-
- </field>
- <field>
- <name>EZI</name>
- <description>Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.</description>
- <bitRange>[6:6]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_INPUT_BUFFER</name>
- <description>Disable input buffer</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_INPUT_BUFFER</name>
- <description>Enable input buffer</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ZIF</name>
- <description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
- <bitRange>[7:7]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_INPUT_GLITCH</name>
- <description>Enable input glitch filter</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_INPUT_GLITCH</name>
- <description>Disable input glitch filter</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>EHD</name>
<description>Select drive strength.</description>
@@ -39994,993 +39851,34 @@
<name>MEDIUM_DRIVE_8_MA_D</name>
<description>Medium-drive: 8 mA drive strength</description>
<value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>HIGH_DRIVE_14_MA_DR</name>
- <description>High-drive: 14 mA drive strength</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ULTRA_HIGH_DRIVE_20</name>
- <description>Ultra high-drive: 20 mA drive strength</description>
- <value>0x3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[31:10]</bitRange>
-
- </field>
- </fields>
-
- </register>
- <register>
- <dim>3</dim>
- <dimIncrement>0x4</dimIncrement>
- <dimIndex>18-20</dimIndex>
- <name>SFSP1_%s</name>
- <description>Pin configuration register for pins P1</description>
- <addressOffset>0x0C8</addressOffset>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>MODE</name>
- <description>Select pin function.</description>
- <bitRange>[2:0]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FUNCTION_0_DEFAULT</name>
- <description>Function 0 (default)</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_1</name>
- <description>Function 1</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_2</name>
- <description>Function 2</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_3</name>
- <description>Function 3</description>
- <value>0x3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_4</name>
- <description>Function 4</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_5</name>
- <description>Function 5</description>
- <value>0x5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_6</name>
- <description>Function 6</description>
- <value>0x6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_7</name>
- <description>Function 7</description>
- <value>0x7</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPD</name>
- <description>Enable pull-down resistor at pad.</description>
- <bitRange>[3:3]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_PULL_DOWN</name>
- <description>Disable pull-down.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_PULL_DOWN</name>
- <description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPUN</name>
- <description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
- <bitRange>[4:4]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_PULL_UP</name>
- <description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_PULL_UP</name>
- <description>Disable pull-up.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EHS</name>
- <description>Select Slew rate.</description>
- <bitRange>[5:5]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>SLOW_LOW_NOISE_WITH</name>
- <description>Slow (low noise with medium speed)</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FAST_MEDIUM_NOISE_W</name>
- <description>Fast (medium noise with fast speed)</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EZI</name>
- <description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
- <bitRange>[6:6]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_INPUT_BUFFER</name>
- <description>Disable input buffer</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_INPUT_BUFFER</name>
- <description>Enable input buffer</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ZIF</name>
- <description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
- <bitRange>[7:7]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_INPUT_GLITCH</name>
- <description>Enable input glitch filter</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_INPUT_GLITCH</name>
- <description>Disable input glitch filter</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[31:8]</bitRange>
-
- </field>
- </fields>
- </register>
- <register>
- <dim>3</dim>
- <dimIncrement>0x4</dimIncrement>
- <dimIndex>0-2</dimIndex>
- <name>SFSP2_%s</name>
- <description>Pin configuration register for pins P2</description>
- <addressOffset>0x100</addressOffset>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>MODE</name>
- <description>Select pin function.</description>
- <bitRange>[2:0]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FUNCTION_0_DEFAULT</name>
- <description>Function 0 (default)</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_1</name>
- <description>Function 1</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_2</name>
- <description>Function 2</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_3</name>
- <description>Function 3</description>
- <value>0x3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_4</name>
- <description>Function 4</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_5</name>
- <description>Function 5</description>
- <value>0x5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_6</name>
- <description>Function 6</description>
- <value>0x6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_7</name>
- <description>Function 7</description>
- <value>0x7</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPD</name>
- <description>Enable pull-down resistor at pad.</description>
- <bitRange>[3:3]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_PULL_DOWN</name>
- <description>Disable pull-down.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_PULL_DOWN</name>
- <description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPUN</name>
- <description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
- <bitRange>[4:4]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_PULL_UP</name>
- <description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_PULL_UP</name>
- <description>Disable pull-up.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EHS</name>
- <description>Select Slew rate.</description>
- <bitRange>[5:5]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>SLOW_LOW_NOISE_WITH</name>
- <description>Slow (low noise with medium speed)</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FAST_MEDIUM_NOISE_W</name>
- <description>Fast (medium noise with fast speed)</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EZI</name>
- <description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
- <bitRange>[6:6]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_INPUT_BUFFER</name>
- <description>Disable input buffer</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_INPUT_BUFFER</name>
- <description>Enable input buffer</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ZIF</name>
- <description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
- <bitRange>[7:7]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_INPUT_GLITCH</name>
- <description>Enable input glitch filter</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_INPUT_GLITCH</name>
- <description>Disable input glitch filter</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[31:8]</bitRange>
-
- </field>
- </fields>
- </register>
- <register>
- <dim>3</dim>
- <dimIncrement>0x4</dimIncrement>
- <dimIndex>3-5</dimIndex>
- <name>SFSP2_%s</name>
- <description>Pin configuration register for pins P2</description>
- <addressOffset>0x10C</addressOffset>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>MODE</name>
- <description>Select pin function.</description>
- <bitRange>[2:0]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FUNCTION_0_DEFAULT</name>
- <description>Function 0 (default)</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_1</name>
- <description>Function 1</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_2</name>
- <description>Function 2</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_3</name>
- <description>Function 3</description>
- <value>0x3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_4</name>
- <description>Function 4</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_5</name>
- <description>Function 5</description>
- <value>0x5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_6</name>
- <description>Function 6</description>
- <value>0x6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_7</name>
- <description>Function 7</description>
- <value>0x7</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPD</name>
- <description>Enable pull-down resistor at pad.</description>
- <bitRange>[3:3]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_PULL_DOWN</name>
- <description>Disable pull-down.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_PULL_DOWN</name>
- <description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPUN</name>
- <description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
- <bitRange>[4:4]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_PULL_UP</name>
- <description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_PULL_UP</name>
- <description>Disable pull-up</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[5:5]</bitRange>
-
- </field>
- <field>
- <name>EZI</name>
- <description>Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.</description>
- <bitRange>[6:6]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_INPUT_BUFFER</name>
- <description>Disable input buffer</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_INPUT_BUFFER</name>
- <description>Enable input buffer</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ZIF</name>
- <description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
- <bitRange>[7:7]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_INPUT_GLITCH</name>
- <description>Enable input glitch filter</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_INPUT_GLITCH</name>
- <description>Disable input glitch filter</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EHD</name>
- <description>Select drive strength.</description>
- <bitRange>[9:8]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>NORMAL_DRIVE_4_MA_D</name>
- <description>Normal-drive: 4 mA drive strength</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>MEDIUM_DRIVE_8_MA_D</name>
- <description>Medium-drive: 8 mA drive strength</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>HIGH_DRIVE_14_MA_DR</name>
- <description>High-drive: 14 mA drive strength</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ULTRA_HIGH_DRIVE_20</name>
- <description>Ultra high-drive: 20 mA drive strength</description>
- <value>0x3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[31:10]</bitRange>
-
- </field>
- </fields>
- </register>
- <register>
- <dim>7</dim>
- <dimIncrement>0x4</dimIncrement>
- <dimIndex>6-12</dimIndex>
- <name>SFSP2_%s</name>
- <description>Pin configuration register for pins P2</description>
- <addressOffset>0x118</addressOffset>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>MODE</name>
- <description>Select pin function.</description>
- <bitRange>[2:0]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FUNCTION_0_DEFAULT</name>
- <description>Function 0 (default)</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_1</name>
- <description>Function 1</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_2</name>
- <description>Function 2</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_3</name>
- <description>Function 3</description>
- <value>0x3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_4</name>
- <description>Function 4</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_5</name>
- <description>Function 5</description>
- <value>0x5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_6</name>
- <description>Function 6</description>
- <value>0x6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_7</name>
- <description>Function 7</description>
- <value>0x7</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPD</name>
- <description>Enable pull-down resistor at pad.</description>
- <bitRange>[3:3]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_PULL_DOWN</name>
- <description>Disable pull-down.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_PULL_DOWN</name>
- <description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPUN</name>
- <description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
- <bitRange>[4:4]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_PULL_UP</name>
- <description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_PULL_UP</name>
- <description>Disable pull-up.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EHS</name>
- <description>Select Slew rate.</description>
- <bitRange>[5:5]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>SLOW_LOW_NOISE_WITH</name>
- <description>Slow (low noise with medium speed)</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FAST_MEDIUM_NOISE_W</name>
- <description>Fast (medium noise with fast speed)</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EZI</name>
- <description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
- <bitRange>[6:6]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_INPUT_BUFFER</name>
- <description>Disable input buffer</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_INPUT_BUFFER</name>
- <description>Enable input buffer</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ZIF</name>
- <description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
- <bitRange>[7:7]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_INPUT_GLITCH</name>
- <description>Enable input glitch filter</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_INPUT_GLITCH</name>
- <description>Disable input glitch filter</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[31:8]</bitRange>
-
- </field>
- </fields>
- </register>
- <register>
- <dim>3</dim>
- <dimIncrement>0x4</dimIncrement>
- <dimIndex>0-2</dimIndex>
- <name>SFSP3_%s</name>
- <description>Pin configuration register for pins P3</description>
- <addressOffset>0x180</addressOffset>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>MODE</name>
- <description>Select pin function.</description>
- <bitRange>[2:0]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FUNCTION_0_DEFAULT</name>
- <description>Function 0 (default)</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_1</name>
- <description>Function 1</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_2</name>
- <description>Function 2</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_3</name>
- <description>Function 3</description>
- <value>0x3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_4</name>
- <description>Function 4</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_5</name>
- <description>Function 5</description>
- <value>0x5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_6</name>
- <description>Function 6</description>
- <value>0x6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_7</name>
- <description>Function 7</description>
- <value>0x7</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPD</name>
- <description>Enable pull-down resistor at pad.</description>
- <bitRange>[3:3]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_PULL_DOWN</name>
- <description>Disable pull-down.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_PULL_DOWN</name>
- <description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPUN</name>
- <description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
- <bitRange>[4:4]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_PULL_UP</name>
- <description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_PULL_UP</name>
- <description>Disable pull-up.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EHS</name>
- <description>Select Slew rate.</description>
- <bitRange>[5:5]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>SLOW_LOW_NOISE_WITH</name>
- <description>Slow (low noise with medium speed)</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FAST_MEDIUM_NOISE_W</name>
- <description>Fast (medium noise with fast speed)</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EZI</name>
- <description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
- <bitRange>[6:6]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_INPUT_BUFFER</name>
- <description>Disable input buffer</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_INPUT_BUFFER</name>
- <description>Enable input buffer</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ZIF</name>
- <description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
- <bitRange>[7:7]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_INPUT_GLITCH</name>
- <description>Enable input glitch filter</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_INPUT_GLITCH</name>
- <description>Disable input glitch filter</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HIGH_DRIVE_14_MA_DR</name>
+ <description>High-drive: 14 mA drive strength</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ULTRA_HIGH_DRIVE_20</name>
+ <description>Ultra high-drive: 20 mA drive strength</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
- <bitRange>[31:8]</bitRange>
+ <bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
-
- <name>SFSP3_3</name>
- <description>Pin configuration register for pins P3</description>
- <addressOffset>0x18C</addressOffset>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <fields>
- <field>
- <name>MODE</name>
- <description>Select pin function.</description>
- <bitRange>[2:0]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FUNCTION_0_DEFAULT</name>
- <description>Function 0 (default)</description>
- <value>0x0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_1</name>
- <description>Function 1</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_2</name>
- <description>Function 2</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_3</name>
- <description>Function 3</description>
- <value>0x3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_4</name>
- <description>Function 4</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_5</name>
- <description>Function 5</description>
- <value>0x5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_6</name>
- <description>Function 6</description>
- <value>0x6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>FUNCTION_7</name>
- <description>Function 7</description>
- <value>0x7</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPD</name>
- <description>Enable pull-down resistor at pad.</description>
- <bitRange>[3:3]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_PULL_DOWN</name>
- <description>Disable pull-down.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_PULL_DOWN</name>
- <description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EPUN</name>
- <description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
- <bitRange>[4:4]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_PULL_UP</name>
- <description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_PULL_UP</name>
- <description>Disable pull-up.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EHS</name>
- <description>Slew rate</description>
- <bitRange>[5:5]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>FAST_LOW_NOISE_WITH</name>
- <description>Fast (low noise with fast speed)</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>HIGH_SPEED_MEDIUM_N</name>
- <description>High-speed (medium noise with high speed)</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>EZI</name>
- <description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
- <bitRange>[6:6]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>DISABLE_INPUT_BUFFER</name>
- <description>Disable input buffer</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ENABLE_INPUT_BUFFER</name>
- <description>Enable input buffer</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ZIF</name>
- <description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
- <bitRange>[7:7]</bitRange>
- <enumeratedValues>
- <name>ENUM</name>
- <enumeratedValue>
- <name>ENABLE_INPUT_FILTER</name>
- <description>Enable input filter</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>DISABLE_INPUT_FILTER</name>
- <description>Disable input filter</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>RESERVED</name>
- <description>Reserved</description>
- <bitRange>[31:8]</bitRange>
-
- </field>
- </fields>
-
- </register>
-
- <register>
- <dim>5</dim>
+ <dim>13</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>4-8</dimIndex>
- <name>SFSP3_%s</name>
- <description>Pin configuration register for pins P3</description>
- <addressOffset>0x190</addressOffset>
+ <dimIndex>0-12</dimIndex>
+ <name>SFSP2_%s</name>
+ <description>Pin configuration register for pins P2</description>
+ <addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
@@ -41123,22 +40021,49 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>EHD</name>
+ <description>Select drive strength.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NORMAL_DRIVE_4_MA_D</name>
+ <description>Normal-drive: 4 mA drive strength</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MEDIUM_DRIVE_8_MA_D</name>
+ <description>Medium-drive: 8 mA drive strength</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HIGH_DRIVE_14_MA_DR</name>
+ <description>High-drive: 14 mA drive strength</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ULTRA_HIGH_DRIVE_20</name>
+ <description>Ultra high-drive: 20 mA drive strength</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
- <bitRange>[31:8]</bitRange>
+ <bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
-
<register>
- <dim>11</dim>
+ <dim>9</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>0-10</dimIndex>
- <name>SFSP4_%s</name>
- <description>Pin configuration register for pins P4</description>
- <addressOffset>0x200</addressOffset>
+ <dimIndex>0-8</dimIndex>
+ <name>SFSP3_%s</name>
+ <description>Pin configuration register for pins P3</description>
+ <addressOffset>0x180</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
@@ -41289,13 +40214,14 @@
</field>
</fields>
</register>
+
<register>
- <dim>8</dim>
+ <dim>11</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>0-7</dimIndex>
- <name>SFSP5_%s</name>
- <description>Pin configuration register for pins P5</description>
- <addressOffset>0x280</addressOffset>
+ <dimIndex>0-10</dimIndex>
+ <name>SFSP4_%s</name>
+ <description>Pin configuration register for pins P4</description>
+ <addressOffset>0x200</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
@@ -41447,12 +40373,12 @@
</fields>
</register>
<register>
- <dim>13</dim>
+ <dim>8</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>0-12</dimIndex>
- <name>SFSP6_%s</name>
- <description>Pin configuration register for pins P6</description>
- <addressOffset>0x300</addressOffset>
+ <dimIndex>0-7</dimIndex>
+ <name>SFSP5_%s</name>
+ <description>Pin configuration register for pins P5</description>
+ <addressOffset>0x280</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
@@ -41604,12 +40530,12 @@
</fields>
</register>
<register>
- <dim>8</dim>
+ <dim>13</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>0-7</dimIndex>
- <name>SFSP7_%s</name>
- <description>Pin configuration register for pins P7</description>
- <addressOffset>0x380</addressOffset>
+ <dimIndex>0-12</dimIndex>
+ <name>SFSP6_%s</name>
+ <description>Pin configuration register for pins P6</description>
+ <addressOffset>0x300</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
@@ -41761,12 +40687,12 @@
</fields>
</register>
<register>
- <dim>3</dim>
+ <dim>8</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>0-2</dimIndex>
- <name>SFSP8_%s</name>
- <description>Pin configuration register for pins P8</description>
- <addressOffset>0x400</addressOffset>
+ <dimIndex>0-7</dimIndex>
+ <name>SFSP7_%s</name>
+ <description>Pin configuration register for pins P7</description>
+ <addressOffset>0x380</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
@@ -41918,12 +40844,12 @@
</fields>
</register>
<register>
- <dim>6</dim>
+ <dim>9</dim>
<dimIncrement>0x4</dimIncrement>
- <dimIndex>3-8</dimIndex>
+ <dimIndex>0-8</dimIndex>
<name>SFSP8_%s</name>
<description>Pin configuration register for pins P8</description>
- <addressOffset>0x40C</addressOffset>
+ <addressOffset>0x400</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
diff --git a/src/lib.rs b/src/lib.rs
index 297e1f5c261be448f7f75f1de83f2d8eafaf995a..723eb07d1b4313852db6c6f43ad235ffe7a103a9 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,12 +1,4 @@
-#![cfg_attr(feature = "rt", feature(global_asm))]
-#![cfg_attr(feature = "rt", feature(macro_reexport))]
-#![cfg_attr(feature = "rt", feature(used))]
-#![doc = "Peripheral access API for LPC43XX microcontrollers (generated using svd2rust v0.11.3)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.11.3/svd2rust/#peripheral-api"]
-#![deny(missing_docs)]
-#![deny(warnings)]
-#![allow(non_camel_case_types)]
-#![feature(const_fn)]
-#![no_std]
+# ! [ cfg_attr ( feature = "rt" , feature ( global_asm ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( macro_reexport ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( used ) ) ] # ! [ doc = "Peripheral access API for LPC43XX microcontrollers (generated using svd2rust v0.11.4)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.11.4/svd2rust/#peripheral-api" ] # ! [ deny ( missing_docs ) ] # ! [ allow ( non_camel_case_types ) ] # ! [ feature ( const_fn ) ] # ! [ no_std ]
extern crate bare_metal;
extern crate cortex_m;
#[macro_reexport(default_handler, exception)]
@@ -21,19 +13,25 @@ pub use interrupt::Interrupt;
#[doc(hidden)]
pub mod interrupt {
use bare_metal::Nr;
- #[cfg(feature = "rt")]
+ #[cfg(all(target_arch = "arm", feature = "rt"))]
global_asm!(
"
- .thumb_func
- DH_TRAMPOLINE:
- b DEFAULT_HANDLER
- "
+ .thumb_func
+ DH_TRAMPOLINE:
+ b DEFAULT_HANDLER
+ "
);
- #[cfg(feature = "rt")]
+ #[doc = r" Hack to compile on x86"]
+ #[cfg(all(target_arch = "x86_64", feature = "rt"))]
global_asm!(
- "\n.weak DAC\nDAC = DH_TRAMPOLINE\n.weak DMA\nDMA = DH_TRAMPOLINE\n.weak FLASH\nFLASH = DH_TRAMPOLINE\n.weak ETHERNET\nETHERNET = DH_TRAMPOLINE\n.weak SDIO\nSDIO = DH_TRAMPOLINE\n.weak LCD\nLCD = DH_TRAMPOLINE\n.weak USB0\nUSB0 = DH_TRAMPOLINE\n.weak USB1\nUSB1 = DH_TRAMPOLINE\n.weak SCT\nSCT = DH_TRAMPOLINE\n.weak RITIMER\nRITIMER = DH_TRAMPOLINE\n.weak TIMER0\nTIMER0 = DH_TRAMPOLINE\n.weak TIMER1\nTIMER1 = DH_TRAMPOLINE\n.weak TIMER2\nTIMER2 = DH_TRAMPOLINE\n.weak TIMER3\nTIMER3 = DH_TRAMPOLINE\n.weak MCPWM\nMCPWM = DH_TRAMPOLINE\n.weak ADC0\nADC0 = DH_TRAMPOLINE\n.weak I2C0\nI2C0 = DH_TRAMPOLINE\n.weak I2C1\nI2C1 = DH_TRAMPOLINE\n.weak SPI_INT\nSPI_INT = DH_TRAMPOLINE\n.weak ADC1\nADC1 = DH_TRAMPOLINE\n.weak SSP0\nSSP0 = DH_TRAMPOLINE\n.weak SSP1\nSSP1 = DH_TRAMPOLINE\n.weak USART0\nUSART0 = DH_TRAMPOLINE\n.weak UART1\nUART1 = DH_TRAMPOLINE\n.weak USART2\nUSART2 = DH_TRAMPOLINE\n.weak USART3\nUSART3 = DH_TRAMPOLINE\n.weak I2S0\nI2S0 = DH_TRAMPOLINE\n.weak I2S1\nI2S1 = DH_TRAMPOLINE\n.weak SPIFI\nSPIFI = DH_TRAMPOLINE\n.weak SGPIO_IINT\nSGPIO_IINT = DH_TRAMPOLINE\n.weak PIN_INT0\nPIN_INT0 = DH_TRAMPOLINE\n.weak PIN_INT1\nPIN_INT1 = DH_TRAMPOLINE\n.weak PIN_INT2\nPIN_INT2 = DH_TRAMPOLINE\n.weak PIN_INT3\nPIN_INT3 = DH_TRAMPOLINE\n.weak PIN_INT4\nPIN_INT4 = DH_TRAMPOLINE\n.weak PIN_INT5\nPIN_INT5 = DH_TRAMPOLINE\n.weak PIN_INT6\nPIN_INT6 = DH_TRAMPOLINE\n.weak PIN_INT7\nPIN_INT7 = DH_TRAMPOLINE\n.weak GINT0\nGINT0 = DH_TRAMPOLINE\n.weak GINT1\nGINT1 = DH_TRAMPOLINE\n.weak EVENTROUTER\nEVENTROUTER = DH_TRAMPOLINE\n.weak C_CAN1\nC_CAN1 = DH_TRAMPOLINE\n.weak ADCHS\nADCHS = DH_TRAMPOLINE\n.weak ATIMER\nATIMER = DH_TRAMPOLINE\n.weak RTC\nRTC = DH_TRAMPOLINE\n.weak WWDT\nWWDT = DH_TRAMPOLINE\n.weak C_CAN0\nC_CAN0 = DH_TRAMPOLINE\n.weak QEI\nQEI = DH_TRAMPOLINE"
+ "
+ DH_TRAMPOLINE:
+ jmp DEFAULT_HANDLER
+ "
);
#[cfg(feature = "rt")]
+ global_asm ! ( "\n.weak DAC\nDAC = DH_TRAMPOLINE\n.weak DMA\nDMA = DH_TRAMPOLINE\n.weak FLASH\nFLASH = DH_TRAMPOLINE\n.weak ETHERNET\nETHERNET = DH_TRAMPOLINE\n.weak SDIO\nSDIO = DH_TRAMPOLINE\n.weak LCD\nLCD = DH_TRAMPOLINE\n.weak USB0\nUSB0 = DH_TRAMPOLINE\n.weak USB1\nUSB1 = DH_TRAMPOLINE\n.weak SCT\nSCT = DH_TRAMPOLINE\n.weak RITIMER\nRITIMER = DH_TRAMPOLINE\n.weak TIMER0\nTIMER0 = DH_TRAMPOLINE\n.weak TIMER1\nTIMER1 = DH_TRAMPOLINE\n.weak TIMER2\nTIMER2 = DH_TRAMPOLINE\n.weak TIMER3\nTIMER3 = DH_TRAMPOLINE\n.weak MCPWM\nMCPWM = DH_TRAMPOLINE\n.weak ADC0\nADC0 = DH_TRAMPOLINE\n.weak I2C0\nI2C0 = DH_TRAMPOLINE\n.weak I2C1\nI2C1 = DH_TRAMPOLINE\n.weak SPI_INT\nSPI_INT = DH_TRAMPOLINE\n.weak ADC1\nADC1 = DH_TRAMPOLINE\n.weak SSP0\nSSP0 = DH_TRAMPOLINE\n.weak SSP1\nSSP1 = DH_TRAMPOLINE\n.weak USART0\nUSART0 = DH_TRAMPOLINE\n.weak UART1\nUART1 = DH_TRAMPOLINE\n.weak USART2\nUSART2 = DH_TRAMPOLINE\n.weak USART3\nUSART3 = DH_TRAMPOLINE\n.weak I2S0\nI2S0 = DH_TRAMPOLINE\n.weak I2S1\nI2S1 = DH_TRAMPOLINE\n.weak SPIFI\nSPIFI = DH_TRAMPOLINE\n.weak SGPIO_IINT\nSGPIO_IINT = DH_TRAMPOLINE\n.weak PIN_INT0\nPIN_INT0 = DH_TRAMPOLINE\n.weak PIN_INT1\nPIN_INT1 = DH_TRAMPOLINE\n.weak PIN_INT2\nPIN_INT2 = DH_TRAMPOLINE\n.weak PIN_INT3\nPIN_INT3 = DH_TRAMPOLINE\n.weak PIN_INT4\nPIN_INT4 = DH_TRAMPOLINE\n.weak PIN_INT5\nPIN_INT5 = DH_TRAMPOLINE\n.weak PIN_INT6\nPIN_INT6 = DH_TRAMPOLINE\n.weak PIN_INT7\nPIN_INT7 = DH_TRAMPOLINE\n.weak GINT0\nGINT0 = DH_TRAMPOLINE\n.weak GINT1\nGINT1 = DH_TRAMPOLINE\n.weak EVENTROUTER\nEVENTROUTER = DH_TRAMPOLINE\n.weak C_CAN1\nC_CAN1 = DH_TRAMPOLINE\n.weak ADCHS\nADCHS = DH_TRAMPOLINE\n.weak ATIMER\nATIMER = DH_TRAMPOLINE\n.weak RTC\nRTC = DH_TRAMPOLINE\n.weak WWDT\nWWDT = DH_TRAMPOLINE\n.weak C_CAN0\nC_CAN0 = DH_TRAMPOLINE\n.weak QEI\nQEI = DH_TRAMPOLINE" ) ;
+ #[cfg(feature = "rt")]
extern "C" {
fn DAC();
fn DMA();
@@ -273,187 +271,7 @@ pub mod sct {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - SCT configuration register"] pub config: CONFIG,
- #[doc = "0x04 - SCT control register"] pub ctrl: CTRL,
- #[doc = "0x08 - SCT limit register"] pub limit: LIMIT,
- #[doc = "0x0c - SCT halt condition register"] pub halt: HALT,
- #[doc = "0x10 - SCT stop condition register"] pub stop: STOP,
- #[doc = "0x14 - SCT start condition register"] pub start: START,
- #[doc = "0x18 - SCT dither condition register"] pub dither: DITHER,
- _reserved0: [u8; 36usize],
- #[doc = "0x40 - SCT counter register"] pub count: COUNT,
- #[doc = "0x44 - SCT state register"] pub state: STATE,
- #[doc = "0x48 - SCT input register"] pub input: INPUT,
- #[doc = "0x4c - SCT match/capture registers mode register"]
- pub regmode: REGMODE,
- #[doc = "0x50 - SCT output register"] pub output: OUTPUT,
- #[doc = "0x54 - SCT output counter direction control register"]
- pub outputdirctrl: OUTPUTDIRCTRL,
- #[doc = "0x58 - SCT conflict resolution register"] pub res: RES,
- #[doc = "0x5c - SCT DMA request 0 register"] pub dmareq0: DMAREQ0,
- #[doc = "0x60 - SCT DMA request 1 register"] pub dmareq1: DMAREQ1,
- _reserved1: [u8; 140usize],
- #[doc = "0xf0 - SCT event enable register"] pub even: EVEN,
- #[doc = "0xf4 - SCT event flag register"] pub evflag: EVFLAG,
- #[doc = "0xf8 - SCT conflict enable register"] pub conen: CONEN,
- #[doc = "0xfc - SCT conflict flag register"] pub conflag: CONFLAG,
- #[doc = "0x100 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match0: MATCH,
- #[doc = "0x104 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match1: MATCH,
- #[doc = "0x108 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match2: MATCH,
- #[doc = "0x10c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match3: MATCH,
- #[doc = "0x110 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match4: MATCH,
- #[doc = "0x114 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match5: MATCH,
- #[doc = "0x118 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match6: MATCH,
- #[doc = "0x11c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match7: MATCH,
- #[doc = "0x120 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match8: MATCH,
- #[doc = "0x124 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match9: MATCH,
- #[doc = "0x128 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match10: MATCH,
- #[doc = "0x12c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match11: MATCH,
- #[doc = "0x130 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match12: MATCH,
- #[doc = "0x134 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match13: MATCH,
- #[doc = "0x138 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match14: MATCH,
- #[doc = "0x13c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0"]
- pub match15: MATCH,
- #[doc = "0x140 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmat0: FRACMAT,
- #[doc = "0x144 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmat1: FRACMAT,
- #[doc = "0x148 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmat2: FRACMAT,
- #[doc = "0x14c - Fractional match registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmat3: FRACMAT,
- #[doc = "0x150 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmat4: FRACMAT,
- #[doc = "0x154 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmat5: FRACMAT,
- _reserved2: [u8; 168usize],
- #[doc = "0x200 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel0: MATCHREL,
- #[doc = "0x204 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel1: MATCHREL,
- #[doc = "0x208 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel2: MATCHREL,
- #[doc = "0x20c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel3: MATCHREL,
- #[doc = "0x210 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel4: MATCHREL,
- #[doc = "0x214 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel5: MATCHREL,
- #[doc = "0x218 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel6: MATCHREL,
- #[doc = "0x21c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel7: MATCHREL,
- #[doc = "0x220 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel8: MATCHREL,
- #[doc = "0x224 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel9: MATCHREL,
- #[doc = "0x228 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel10: MATCHREL,
- #[doc = "0x22c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel11: MATCHREL,
- #[doc = "0x230 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel12: MATCHREL,
- #[doc = "0x234 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel13: MATCHREL,
- #[doc = "0x238 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel14: MATCHREL,
- #[doc = "0x23c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0"]
- pub matchrel15: MATCHREL,
- #[doc = "0x240 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmatrel0: FRACMATREL,
- #[doc = "0x244 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmatrel1: FRACMATREL,
- #[doc = "0x248 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmatrel2: FRACMATREL,
- #[doc = "0x24c - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmatrel3: FRACMATREL,
- #[doc = "0x250 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmatrel4: FRACMATREL,
- #[doc = "0x254 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5."]
- pub fracmatrel5: FRACMATREL,
- _reserved3: [u8; 168usize],
- #[doc = "0x300 - SCT event state register 0"] pub ev0_state: EV_STATE,
- #[doc = "0x304 - SCT event control register 0"] pub ev0_ctrl: EV_CTRL,
- #[doc = "0x308 - SCT event state register 0"] pub ev1_state: EV_STATE,
- #[doc = "0x30c - SCT event control register 0"] pub ev1_ctrl: EV_CTRL,
- #[doc = "0x310 - SCT event state register 0"] pub ev2_state: EV_STATE,
- #[doc = "0x314 - SCT event control register 0"] pub ev2_ctrl: EV_CTRL,
- #[doc = "0x318 - SCT event state register 0"] pub ev3_state: EV_STATE,
- #[doc = "0x31c - SCT event control register 0"] pub ev3_ctrl: EV_CTRL,
- #[doc = "0x320 - SCT event state register 0"] pub ev4_state: EV_STATE,
- #[doc = "0x324 - SCT event control register 0"] pub ev4_ctrl: EV_CTRL,
- #[doc = "0x328 - SCT event state register 0"] pub ev5_state: EV_STATE,
- #[doc = "0x32c - SCT event control register 0"] pub ev5_ctrl: EV_CTRL,
- #[doc = "0x330 - SCT event state register 0"] pub ev6_state: EV_STATE,
- #[doc = "0x334 - SCT event control register 0"] pub ev6_ctrl: EV_CTRL,
- #[doc = "0x338 - SCT event state register 0"] pub ev7_state: EV_STATE,
- #[doc = "0x33c - SCT event control register 0"] pub ev7_ctrl: EV_CTRL,
- #[doc = "0x340 - SCT event state register 0"] pub ev8_state: EV_STATE,
- #[doc = "0x344 - SCT event control register 0"] pub ev8_ctrl: EV_CTRL,
- #[doc = "0x348 - SCT event state register 0"] pub ev9_state: EV_STATE,
- #[doc = "0x34c - SCT event control register 0"] pub ev9_ctrl: EV_CTRL,
- #[doc = "0x350 - SCT event state register 0"] pub ev10_state: EV_STATE,
- #[doc = "0x354 - SCT event control register 0"] pub ev10_ctrl: EV_CTRL,
- #[doc = "0x358 - SCT event state register 0"] pub ev11_state: EV_STATE,
- #[doc = "0x35c - SCT event control register 0"] pub ev11_ctrl: EV_CTRL,
- #[doc = "0x360 - SCT event state register 0"] pub ev12_state: EV_STATE,
- #[doc = "0x364 - SCT event control register 0"] pub ev12_ctrl: EV_CTRL,
- #[doc = "0x368 - SCT event state register 0"] pub ev13_state: EV_STATE,
- #[doc = "0x36c - SCT event control register 0"] pub ev13_ctrl: EV_CTRL,
- #[doc = "0x370 - SCT event state register 0"] pub ev14_state: EV_STATE,
- #[doc = "0x374 - SCT event control register 0"] pub ev14_ctrl: EV_CTRL,
- #[doc = "0x378 - SCT event state register 0"] pub ev15_state: EV_STATE,
- #[doc = "0x37c - SCT event control register 0"] pub ev15_ctrl: EV_CTRL,
- _reserved4: [u8; 384usize],
- #[doc = "0x500 - SCT output 0 set register"] pub out0_set: OUT_SET,
- #[doc = "0x504 - SCT output 0 clear register"] pub out0_clr: OUT_CLR,
- #[doc = "0x508 - SCT output 0 set register"] pub out1_set: OUT_SET,
- #[doc = "0x50c - SCT output 0 clear register"] pub out1_clr: OUT_CLR,
- #[doc = "0x510 - SCT output 0 set register"] pub out2_set: OUT_SET,
- #[doc = "0x514 - SCT output 0 clear register"] pub out2_clr: OUT_CLR,
- #[doc = "0x518 - SCT output 0 set register"] pub out3_set: OUT_SET,
- #[doc = "0x51c - SCT output 0 clear register"] pub out3_clr: OUT_CLR,
- #[doc = "0x520 - SCT output 0 set register"] pub out4_set: OUT_SET,
- #[doc = "0x524 - SCT output 0 clear register"] pub out4_clr: OUT_CLR,
- #[doc = "0x528 - SCT output 0 set register"] pub out5_set: OUT_SET,
- #[doc = "0x52c - SCT output 0 clear register"] pub out5_clr: OUT_CLR,
- #[doc = "0x530 - SCT output 0 set register"] pub out6_set: OUT_SET,
- #[doc = "0x534 - SCT output 0 clear register"] pub out6_clr: OUT_CLR,
- #[doc = "0x538 - SCT output 0 set register"] pub out7_set: OUT_SET,
- #[doc = "0x53c - SCT output 0 clear register"] pub out7_clr: OUT_CLR,
- #[doc = "0x540 - SCT output 0 set register"] pub out8_set: OUT_SET,
- #[doc = "0x544 - SCT output 0 clear register"] pub out8_clr: OUT_CLR,
- #[doc = "0x548 - SCT output 0 set register"] pub out9_set: OUT_SET,
- #[doc = "0x54c - SCT output 0 clear register"] pub out9_clr: OUT_CLR,
- #[doc = "0x550 - SCT output 0 set register"] pub out10_set: OUT_SET,
- #[doc = "0x554 - SCT output 0 clear register"] pub out10_clr: OUT_CLR,
- #[doc = "0x558 - SCT output 0 set register"] pub out11_set: OUT_SET,
- #[doc = "0x55c - SCT output 0 clear register"] pub out11_clr: OUT_CLR,
- #[doc = "0x560 - SCT output 0 set register"] pub out12_set: OUT_SET,
- #[doc = "0x564 - SCT output 0 clear register"] pub out12_clr: OUT_CLR,
- #[doc = "0x568 - SCT output 0 set register"] pub out13_set: OUT_SET,
- #[doc = "0x56c - SCT output 0 clear register"] pub out13_clr: OUT_CLR,
- #[doc = "0x570 - SCT output 0 set register"] pub out14_set: OUT_SET,
- #[doc = "0x574 - SCT output 0 clear register"] pub out14_clr: OUT_CLR,
- #[doc = "0x578 - SCT output 0 set register"] pub out15_set: OUT_SET,
- #[doc = "0x57c - SCT output 0 clear register"] pub out15_clr: OUT_CLR,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - SCT configuration register" ] pub config : CONFIG , # [ doc = "0x04 - SCT control register" ] pub ctrl : CTRL , # [ doc = "0x08 - SCT limit register" ] pub limit : LIMIT , # [ doc = "0x0c - SCT halt condition register" ] pub halt : HALT , # [ doc = "0x10 - SCT stop condition register" ] pub stop : STOP , # [ doc = "0x14 - SCT start condition register" ] pub start : START , # [ doc = "0x18 - SCT dither condition register" ] pub dither : DITHER , _reserved0 : [ u8 ; 36usize ] , # [ doc = "0x40 - SCT counter register" ] pub count : COUNT , # [ doc = "0x44 - SCT state register" ] pub state : STATE , # [ doc = "0x48 - SCT input register" ] pub input : INPUT , # [ doc = "0x4c - SCT match/capture registers mode register" ] pub regmode : REGMODE , # [ doc = "0x50 - SCT output register" ] pub output : OUTPUT , # [ doc = "0x54 - SCT output counter direction control register" ] pub outputdirctrl : OUTPUTDIRCTRL , # [ doc = "0x58 - SCT conflict resolution register" ] pub res : RES , # [ doc = "0x5c - SCT DMA request 0 register" ] pub dmareq0 : DMAREQ0 , # [ doc = "0x60 - SCT DMA request 1 register" ] pub dmareq1 : DMAREQ1 , _reserved1 : [ u8 ; 140usize ] , # [ doc = "0xf0 - SCT event enable register" ] pub even : EVEN , # [ doc = "0xf4 - SCT event flag register" ] pub evflag : EVFLAG , # [ doc = "0xf8 - SCT conflict enable register" ] pub conen : CONEN , # [ doc = "0xfc - SCT conflict flag register" ] pub conflag : CONFLAG , # [ doc = "0x100 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match0 : MATCH , # [ doc = "0x104 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match1 : MATCH , # [ doc = "0x108 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match2 : MATCH , # [ doc = "0x10c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match3 : MATCH , # [ doc = "0x110 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match4 : MATCH , # [ doc = "0x114 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match5 : MATCH , # [ doc = "0x118 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match6 : MATCH , # [ doc = "0x11c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match7 : MATCH , # [ doc = "0x120 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match8 : MATCH , # [ doc = "0x124 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match9 : MATCH , # [ doc = "0x128 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match10 : MATCH , # [ doc = "0x12c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match11 : MATCH , # [ doc = "0x130 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match12 : MATCH , # [ doc = "0x134 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match13 : MATCH , # [ doc = "0x138 - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match14 : MATCH , # [ doc = "0x13c - SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" ] pub match15 : MATCH , # [ doc = "0x140 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmat0 : FRACMAT , # [ doc = "0x144 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmat1 : FRACMAT , # [ doc = "0x148 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmat2 : FRACMAT , # [ doc = "0x14c - Fractional match registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmat3 : FRACMAT , # [ doc = "0x150 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmat4 : FRACMAT , # [ doc = "0x154 - Fractional match registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmat5 : FRACMAT , _reserved2 : [ u8 ; 168usize ] , # [ doc = "0x200 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel0 : MATCHREL , # [ doc = "0x204 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel1 : MATCHREL , # [ doc = "0x208 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel2 : MATCHREL , # [ doc = "0x20c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel3 : MATCHREL , # [ doc = "0x210 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel4 : MATCHREL , # [ doc = "0x214 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel5 : MATCHREL , # [ doc = "0x218 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel6 : MATCHREL , # [ doc = "0x21c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel7 : MATCHREL , # [ doc = "0x220 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel8 : MATCHREL , # [ doc = "0x224 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel9 : MATCHREL , # [ doc = "0x228 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel10 : MATCHREL , # [ doc = "0x22c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel11 : MATCHREL , # [ doc = "0x230 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel12 : MATCHREL , # [ doc = "0x234 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel13 : MATCHREL , # [ doc = "0x238 - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel14 : MATCHREL , # [ doc = "0x23c - SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" ] pub matchrel15 : MATCHREL , # [ doc = "0x240 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmatrel0 : FRACMATREL , # [ doc = "0x244 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmatrel1 : FRACMATREL , # [ doc = "0x248 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmatrel2 : FRACMATREL , # [ doc = "0x24c - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmatrel3 : FRACMATREL , # [ doc = "0x250 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmatrel4 : FRACMATREL , # [ doc = "0x254 - Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." ] pub fracmatrel5 : FRACMATREL , _reserved3 : [ u8 ; 168usize ] , # [ doc = "0x300 - SCT event state register 0" ] pub ev0_state : EV_STATE , # [ doc = "0x304 - SCT event control register 0" ] pub ev0_ctrl : EV_CTRL , # [ doc = "0x308 - SCT event state register 0" ] pub ev1_state : EV_STATE , # [ doc = "0x30c - SCT event control register 0" ] pub ev1_ctrl : EV_CTRL , # [ doc = "0x310 - SCT event state register 0" ] pub ev2_state : EV_STATE , # [ doc = "0x314 - SCT event control register 0" ] pub ev2_ctrl : EV_CTRL , # [ doc = "0x318 - SCT event state register 0" ] pub ev3_state : EV_STATE , # [ doc = "0x31c - SCT event control register 0" ] pub ev3_ctrl : EV_CTRL , # [ doc = "0x320 - SCT event state register 0" ] pub ev4_state : EV_STATE , # [ doc = "0x324 - SCT event control register 0" ] pub ev4_ctrl : EV_CTRL , # [ doc = "0x328 - SCT event state register 0" ] pub ev5_state : EV_STATE , # [ doc = "0x32c - SCT event control register 0" ] pub ev5_ctrl : EV_CTRL , # [ doc = "0x330 - SCT event state register 0" ] pub ev6_state : EV_STATE , # [ doc = "0x334 - SCT event control register 0" ] pub ev6_ctrl : EV_CTRL , # [ doc = "0x338 - SCT event state register 0" ] pub ev7_state : EV_STATE , # [ doc = "0x33c - SCT event control register 0" ] pub ev7_ctrl : EV_CTRL , # [ doc = "0x340 - SCT event state register 0" ] pub ev8_state : EV_STATE , # [ doc = "0x344 - SCT event control register 0" ] pub ev8_ctrl : EV_CTRL , # [ doc = "0x348 - SCT event state register 0" ] pub ev9_state : EV_STATE , # [ doc = "0x34c - SCT event control register 0" ] pub ev9_ctrl : EV_CTRL , # [ doc = "0x350 - SCT event state register 0" ] pub ev10_state : EV_STATE , # [ doc = "0x354 - SCT event control register 0" ] pub ev10_ctrl : EV_CTRL , # [ doc = "0x358 - SCT event state register 0" ] pub ev11_state : EV_STATE , # [ doc = "0x35c - SCT event control register 0" ] pub ev11_ctrl : EV_CTRL , # [ doc = "0x360 - SCT event state register 0" ] pub ev12_state : EV_STATE , # [ doc = "0x364 - SCT event control register 0" ] pub ev12_ctrl : EV_CTRL , # [ doc = "0x368 - SCT event state register 0" ] pub ev13_state : EV_STATE , # [ doc = "0x36c - SCT event control register 0" ] pub ev13_ctrl : EV_CTRL , # [ doc = "0x370 - SCT event state register 0" ] pub ev14_state : EV_STATE , # [ doc = "0x374 - SCT event control register 0" ] pub ev14_ctrl : EV_CTRL , # [ doc = "0x378 - SCT event state register 0" ] pub ev15_state : EV_STATE , # [ doc = "0x37c - SCT event control register 0" ] pub ev15_ctrl : EV_CTRL , _reserved4 : [ u8 ; 384usize ] , # [ doc = "0x500 - SCT output 0 set register" ] pub out0_set : OUT_SET , # [ doc = "0x504 - SCT output 0 clear register" ] pub out0_clr : OUT_CLR , # [ doc = "0x508 - SCT output 0 set register" ] pub out1_set : OUT_SET , # [ doc = "0x50c - SCT output 0 clear register" ] pub out1_clr : OUT_CLR , # [ doc = "0x510 - SCT output 0 set register" ] pub out2_set : OUT_SET , # [ doc = "0x514 - SCT output 0 clear register" ] pub out2_clr : OUT_CLR , # [ doc = "0x518 - SCT output 0 set register" ] pub out3_set : OUT_SET , # [ doc = "0x51c - SCT output 0 clear register" ] pub out3_clr : OUT_CLR , # [ doc = "0x520 - SCT output 0 set register" ] pub out4_set : OUT_SET , # [ doc = "0x524 - SCT output 0 clear register" ] pub out4_clr : OUT_CLR , # [ doc = "0x528 - SCT output 0 set register" ] pub out5_set : OUT_SET , # [ doc = "0x52c - SCT output 0 clear register" ] pub out5_clr : OUT_CLR , # [ doc = "0x530 - SCT output 0 set register" ] pub out6_set : OUT_SET , # [ doc = "0x534 - SCT output 0 clear register" ] pub out6_clr : OUT_CLR , # [ doc = "0x538 - SCT output 0 set register" ] pub out7_set : OUT_SET , # [ doc = "0x53c - SCT output 0 clear register" ] pub out7_clr : OUT_CLR , # [ doc = "0x540 - SCT output 0 set register" ] pub out8_set : OUT_SET , # [ doc = "0x544 - SCT output 0 clear register" ] pub out8_clr : OUT_CLR , # [ doc = "0x548 - SCT output 0 set register" ] pub out9_set : OUT_SET , # [ doc = "0x54c - SCT output 0 clear register" ] pub out9_clr : OUT_CLR , # [ doc = "0x550 - SCT output 0 set register" ] pub out10_set : OUT_SET , # [ doc = "0x554 - SCT output 0 clear register" ] pub out10_clr : OUT_CLR , # [ doc = "0x558 - SCT output 0 set register" ] pub out11_set : OUT_SET , # [ doc = "0x55c - SCT output 0 clear register" ] pub out11_clr : OUT_CLR , # [ doc = "0x560 - SCT output 0 set register" ] pub out12_set : OUT_SET , # [ doc = "0x564 - SCT output 0 clear register" ] pub out12_clr : OUT_CLR , # [ doc = "0x568 - SCT output 0 set register" ] pub out13_set : OUT_SET , # [ doc = "0x56c - SCT output 0 clear register" ] pub out13_clr : OUT_CLR , # [ doc = "0x570 - SCT output 0 set register" ] pub out14_set : OUT_SET , # [ doc = "0x574 - SCT output 0 clear register" ] pub out14_clr : OUT_CLR , # [ doc = "0x578 - SCT output 0 set register" ] pub out15_set : OUT_SET , # [ doc = "0x57c - SCT output 0 clear register" ] pub out15_clr : OUT_CLR , }
#[doc = "SCT configuration register"]
pub struct CONFIG {
register: VolatileCell<u32>,
@@ -507,10 +325,8 @@ pub mod sct {
#[doc = "Possible values of the field `UNIFY`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UNIFYR {
- #[doc = "16-bit.The SCT operates as two 16-bit counters named L and H."]
- _16_BIT,
- #[doc = "32-bit. The SCT operates as a unified 32-bit counter."]
- _32_BIT,
+ #[doc = "16-bit.The SCT operates as two 16-bit counters named L and H."] _16_BIT,
+ #[doc = "32-bit. The SCT operates as a unified 32-bit counter."] _32_BIT,
}
impl UNIFYR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -553,14 +369,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `CLKMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CLKMODER {
- #[doc = "Bus clock. The bus clock clocks the SCT and prescalers."]
- BUS_CLOCK,
- #[doc = "Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode."]
- PRESCALED_BUS_CLOCK,
- #[doc = "SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode."]
- SCT_INPUT,
- }
+ pub enum CLKMODER {# [ doc = "Bus clock. The bus clock clocks the SCT and prescalers." ] BUS_CLOCK , # [ doc = "Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." ] PRESCALED_BUS_CLOCK , # [ doc = "SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." ] SCT_INPUT}
impl CLKMODER {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -843,10 +652,8 @@ pub mod sct {
}
#[doc = "Values that can be written to the field `UNIFY`"]
pub enum UNIFYW {
- #[doc = "16-bit.The SCT operates as two 16-bit counters named L and H."]
- _16_BIT,
- #[doc = "32-bit. The SCT operates as a unified 32-bit counter."]
- _32_BIT,
+ #[doc = "16-bit.The SCT operates as two 16-bit counters named L and H."] _16_BIT,
+ #[doc = "32-bit. The SCT operates as a unified 32-bit counter."] _32_BIT,
}
impl UNIFYW {
#[allow(missing_docs)]
@@ -900,14 +707,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `CLKMODE`"]
- pub enum CLKMODEW {
- #[doc = "Bus clock. The bus clock clocks the SCT and prescalers."]
- BUS_CLOCK,
- #[doc = "Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode."]
- PRESCALED_BUS_CLOCK,
- #[doc = "SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode."]
- SCT_INPUT,
- }
+ pub enum CLKMODEW {# [ doc = "Bus clock. The bus clock clocks the SCT and prescalers." ] BUS_CLOCK , # [ doc = "Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." ] PRESCALED_BUS_CLOCK , # [ doc = "SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." ] SCT_INPUT}
impl CLKMODEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -935,13 +735,11 @@ pub mod sct {
pub fn bus_clock(self) -> &'a mut W {
self.variant(CLKMODEW::BUS_CLOCK)
}
- #[doc = "Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode."]
- #[inline(always)]
+ # [ doc = "Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode." ] # [ inline ( always ) ]
pub fn prescaled_bus_clock(self) -> &'a mut W {
self.variant(CLKMODEW::PRESCALED_BUS_CLOCK)
}
- #[doc = "SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode."]
- #[inline(always)]
+ # [ doc = "SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode." ] # [ inline ( always ) ]
pub fn sct_input(self) -> &'a mut W {
self.variant(CLKMODEW::SCT_INPUT)
}
@@ -1241,8 +1039,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 7 - A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn norelaod_l(&self) -> NORELAOD_LR {
let bits = {
const MASK: bool = true;
@@ -1251,8 +1048,7 @@ pub mod sct {
};
NORELAOD_LR { bits }
}
- #[doc = "Bit 8 - A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn noreload_h(&self) -> NORELOAD_HR {
let bits = {
const MASK: bool = true;
@@ -1261,8 +1057,7 @@ pub mod sct {
};
NORELOAD_HR { bits }
}
- #[doc = "Bits 9:16 - Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used."]
- #[inline(always)]
+ # [ doc = "Bits 9:16 - Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used." ] # [ inline ( always ) ]
pub fn insync(&self) -> INSYNCR {
let bits = {
const MASK: u8 = 255;
@@ -1271,8 +1066,7 @@ pub mod sct {
};
INSYNCR { bits }
}
- #[doc = "Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn autolimit_l(&self) -> AUTOLIMIT_LR {
let bits = {
const MASK: bool = true;
@@ -1281,8 +1075,7 @@ pub mod sct {
};
AUTOLIMIT_LR { bits }
}
- #[doc = "Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn autolimit_h(&self) -> AUTOLIMIT_HR {
let bits = {
const MASK: bool = true;
@@ -1319,28 +1112,23 @@ pub mod sct {
pub fn cksel(&mut self) -> _CKSELW {
_CKSELW { w: self }
}
- #[doc = "Bit 7 - A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn norelaod_l(&mut self) -> _NORELAOD_LW {
_NORELAOD_LW { w: self }
}
- #[doc = "Bit 8 - A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn noreload_h(&mut self) -> _NORELOAD_HW {
_NORELOAD_HW { w: self }
}
- #[doc = "Bits 9:16 - Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used."]
- #[inline(always)]
+ # [ doc = "Bits 9:16 - Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used." ] # [ inline ( always ) ]
pub fn insync(&mut self) -> _INSYNCW {
_INSYNCW { w: self }
}
- #[doc = "Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn autolimit_l(&mut self) -> _AUTOLIMIT_LW {
_AUTOLIMIT_LW { w: self }
}
- #[doc = "Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
- #[inline(always)]
+ # [ doc = "Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set." ] # [ inline ( always ) ]
pub fn autolimit_h(&mut self) -> _AUTOLIMIT_HW {
_AUTOLIMIT_HW { w: self }
}
@@ -1482,12 +1270,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `BIDIR_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BIDIR_LR {
- #[doc = "Up. The counter counts up to its limit condition, then is cleared to zero."]
- UP,
- #[doc = "Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0."]
- UPDOWN,
- }
+ pub enum BIDIR_LR {# [ doc = "Up. The counter counts up to its limit condition, then is cleared to zero." ] UP , # [ doc = "Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." ] UPDOWN}
impl BIDIR_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -1624,12 +1407,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `BIDIR_H`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BIDIR_HR {
- #[doc = "Up. The H counter counts up to its limit condition, then is cleared to zero."]
- UP,
- #[doc = "Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0."]
- UPDOWN,
- }
+ pub enum BIDIR_HR {# [ doc = "Up. The H counter counts up to its limit condition, then is cleared to zero." ] UP , # [ doc = "Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." ] UPDOWN}
impl BIDIR_HR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -1773,12 +1551,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `BIDIR_L`"]
- pub enum BIDIR_LW {
- #[doc = "Up. The counter counts up to its limit condition, then is cleared to zero."]
- UP,
- #[doc = "Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0."]
- UPDOWN,
- }
+ pub enum BIDIR_LW {# [ doc = "Up. The counter counts up to its limit condition, then is cleared to zero." ] UP , # [ doc = "Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." ] UPDOWN}
impl BIDIR_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -1807,8 +1580,7 @@ pub mod sct {
pub fn up(self) -> &'a mut W {
self.variant(BIDIR_LW::UP)
}
- #[doc = "Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0."]
- #[inline(always)]
+ # [ doc = "Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." ] # [ inline ( always ) ]
pub fn updown(self) -> &'a mut W {
self.variant(BIDIR_LW::UPDOWN)
}
@@ -1938,12 +1710,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `BIDIR_H`"]
- pub enum BIDIR_HW {
- #[doc = "Up. The H counter counts up to its limit condition, then is cleared to zero."]
- UP,
- #[doc = "Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0."]
- UPDOWN,
- }
+ pub enum BIDIR_HW {# [ doc = "Up. The H counter counts up to its limit condition, then is cleared to zero." ] UP , # [ doc = "Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." ] UPDOWN}
impl BIDIR_HW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -1972,8 +1739,7 @@ pub mod sct {
pub fn up(self) -> &'a mut W {
self.variant(BIDIR_HW::UP)
}
- #[doc = "Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0."]
- #[inline(always)]
+ # [ doc = "Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." ] # [ inline ( always ) ]
pub fn updown(self) -> &'a mut W {
self.variant(BIDIR_HW::UPDOWN)
}
@@ -2016,8 +1782,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." ] # [ inline ( always ) ]
pub fn down_l(&self) -> DOWN_LR {
let bits = {
const MASK: bool = true;
@@ -2026,8 +1791,7 @@ pub mod sct {
};
DOWN_LR { bits }
}
- #[doc = "Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
- #[inline(always)]
+ # [ doc = "Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." ] # [ inline ( always ) ]
pub fn stop_l(&self) -> STOP_LR {
let bits = {
const MASK: bool = true;
@@ -2036,8 +1800,7 @@ pub mod sct {
};
STOP_LR { bits }
}
- #[doc = "Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation."]
- #[inline(always)]
+ # [ doc = "Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." ] # [ inline ( always ) ]
pub fn halt_l(&self) -> HALT_LR {
let bits = {
const MASK: bool = true;
@@ -2046,8 +1809,7 @@ pub mod sct {
};
HALT_LR { bits }
}
- #[doc = "Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." ] # [ inline ( always ) ]
pub fn clrctr_l(&self) -> CLRCTR_LR {
let bits = {
const MASK: bool = true;
@@ -2065,8 +1827,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
- #[inline(always)]
+ # [ doc = "Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." ] # [ inline ( always ) ]
pub fn pre_l(&self) -> PRE_LR {
let bits = {
const MASK: u8 = 255;
@@ -2075,8 +1836,7 @@ pub mod sct {
};
PRE_LR { bits }
}
- #[doc = "Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs."]
- #[inline(always)]
+ # [ doc = "Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." ] # [ inline ( always ) ]
pub fn down_h(&self) -> DOWN_HR {
let bits = {
const MASK: bool = true;
@@ -2085,8 +1845,7 @@ pub mod sct {
};
DOWN_HR { bits }
}
- #[doc = "Bit 17 - When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
- #[inline(always)]
+ # [ doc = "Bit 17 - When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." ] # [ inline ( always ) ]
pub fn stop_h(&self) -> STOP_HR {
let bits = {
const MASK: bool = true;
@@ -2095,8 +1854,7 @@ pub mod sct {
};
STOP_HR { bits }
}
- #[doc = "Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation."]
- #[inline(always)]
+ # [ doc = "Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." ] # [ inline ( always ) ]
pub fn halt_h(&self) -> HALT_HR {
let bits = {
const MASK: bool = true;
@@ -2105,8 +1863,7 @@ pub mod sct {
};
HALT_HR { bits }
}
- #[doc = "Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0." ] # [ inline ( always ) ]
pub fn clrctr_h(&self) -> CLRCTR_HR {
let bits = {
const MASK: bool = true;
@@ -2124,8 +1881,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
- #[inline(always)]
+ # [ doc = "Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." ] # [ inline ( always ) ]
pub fn pre_h(&self) -> PRE_HR {
let bits = {
const MASK: u8 = 255;
@@ -2147,23 +1903,19 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." ] # [ inline ( always ) ]
pub fn down_l(&mut self) -> _DOWN_LW {
_DOWN_LW { w: self }
}
- #[doc = "Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
- #[inline(always)]
+ # [ doc = "Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." ] # [ inline ( always ) ]
pub fn stop_l(&mut self) -> _STOP_LW {
_STOP_LW { w: self }
}
- #[doc = "Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation."]
- #[inline(always)]
+ # [ doc = "Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." ] # [ inline ( always ) ]
pub fn halt_l(&mut self) -> _HALT_LW {
_HALT_LW { w: self }
}
- #[doc = "Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." ] # [ inline ( always ) ]
pub fn clrctr_l(&mut self) -> _CLRCTR_LW {
_CLRCTR_LW { w: self }
}
@@ -2172,28 +1924,23 @@ pub mod sct {
pub fn bidir_l(&mut self) -> _BIDIR_LW {
_BIDIR_LW { w: self }
}
- #[doc = "Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
- #[inline(always)]
+ # [ doc = "Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." ] # [ inline ( always ) ]
pub fn pre_l(&mut self) -> _PRE_LW {
_PRE_LW { w: self }
}
- #[doc = "Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs."]
- #[inline(always)]
+ # [ doc = "Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." ] # [ inline ( always ) ]
pub fn down_h(&mut self) -> _DOWN_HW {
_DOWN_HW { w: self }
}
- #[doc = "Bit 17 - When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
- #[inline(always)]
+ # [ doc = "Bit 17 - When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes." ] # [ inline ( always ) ]
pub fn stop_h(&mut self) -> _STOP_HW {
_STOP_HW { w: self }
}
- #[doc = "Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation."]
- #[inline(always)]
+ # [ doc = "Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." ] # [ inline ( always ) ]
pub fn halt_h(&mut self) -> _HALT_HW {
_HALT_HW { w: self }
}
- #[doc = "Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0." ] # [ inline ( always ) ]
pub fn clrctr_h(&mut self) -> _CLRCTR_HW {
_CLRCTR_HW { w: self }
}
@@ -2202,8 +1949,7 @@ pub mod sct {
pub fn bidir_h(&mut self) -> _BIDIR_HW {
_BIDIR_HW { w: self }
}
- #[doc = "Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
- #[inline(always)]
+ # [ doc = "Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value." ] # [ inline ( always ) ]
pub fn pre_h(&mut self) -> _PRE_HW {
_PRE_HW { w: self }
}
@@ -2317,8 +2063,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn limmsk_l(&self) -> LIMMSK_LR {
let bits = {
const MASK: u16 = 65535;
@@ -2327,8 +2072,7 @@ pub mod sct {
};
LIMMSK_LR { bits }
}
- #[doc = "Bits 16:31 - If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn limmsk_h(&self) -> LIMMSK_HR {
let bits = {
const MASK: u16 = 65535;
@@ -2350,13 +2094,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn limmsk_l(&mut self) -> _LIMMSK_LW {
_LIMMSK_LW { w: self }
}
- #[doc = "Bits 16:31 - If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn limmsk_h(&mut self) -> _LIMMSK_HW {
_LIMMSK_HW { w: self }
}
@@ -2470,8 +2212,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn haltmsk_l(&self) -> HALTMSK_LR {
let bits = {
const MASK: u16 = 65535;
@@ -2480,8 +2221,7 @@ pub mod sct {
};
HALTMSK_LR { bits }
}
- #[doc = "Bits 16:31 - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn haltmsk_h(&self) -> HALTMSK_HR {
let bits = {
const MASK: u16 = 65535;
@@ -2503,13 +2243,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn haltmsk_l(&mut self) -> _HALTMSK_LW {
_HALTMSK_LW { w: self }
}
- #[doc = "Bits 16:31 - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn haltmsk_h(&mut self) -> _HALTMSK_HW {
_HALTMSK_HW { w: self }
}
@@ -2623,8 +2361,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn stopmsk_l(&self) -> STOPMSK_LR {
let bits = {
const MASK: u16 = 65535;
@@ -2633,8 +2370,7 @@ pub mod sct {
};
STOPMSK_LR { bits }
}
- #[doc = "Bits 16:31 - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn stopmsk_h(&self) -> STOPMSK_HR {
let bits = {
const MASK: u16 = 65535;
@@ -2656,13 +2392,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn stopmsk_l(&mut self) -> _STOPMSK_LW {
_STOPMSK_LW { w: self }
}
- #[doc = "Bits 16:31 - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn stopmsk_h(&mut self) -> _STOPMSK_HW {
_STOPMSK_HW { w: self }
}
@@ -2776,8 +2510,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn startmsk_l(&self) -> STARTMSK_LR {
let bits = {
const MASK: u16 = 65535;
@@ -2786,8 +2519,7 @@ pub mod sct {
};
STARTMSK_LR { bits }
}
- #[doc = "Bits 16:31 - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn startmsk_h(&self) -> STARTMSK_HR {
let bits = {
const MASK: u16 = 65535;
@@ -2809,13 +2541,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn startmsk_l(&mut self) -> _STARTMSK_LW {
_STARTMSK_LW { w: self }
}
- #[doc = "Bits 16:31 - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn startmsk_h(&mut self) -> _STARTMSK_HW {
_STARTMSK_HW { w: self }
}
@@ -2929,8 +2659,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." ] # [ inline ( always ) ]
pub fn dithmsk_l(&self) -> DITHMSK_LR {
let bits = {
const MASK: u16 = 65535;
@@ -2939,8 +2668,7 @@ pub mod sct {
};
DITHMSK_LR { bits }
}
- #[doc = "Bits 16:31 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." ] # [ inline ( always ) ]
pub fn dithmsk_h(&self) -> DITHMSK_HR {
let bits = {
const MASK: u16 = 65535;
@@ -2962,13 +2690,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." ] # [ inline ( always ) ]
pub fn dithmsk_l(&mut self) -> _DITHMSK_LW {
_DITHMSK_LW { w: self }
}
- #[doc = "Bits 16:31 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." ] # [ inline ( always ) ]
pub fn dithmsk_h(&mut self) -> _DITHMSK_HW {
_DITHMSK_HW { w: self }
}
@@ -3082,8 +2808,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." ] # [ inline ( always ) ]
pub fn ctr_l(&self) -> CTR_LR {
let bits = {
const MASK: u16 = 65535;
@@ -3092,8 +2817,7 @@ pub mod sct {
};
CTR_LR { bits }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." ] # [ inline ( always ) ]
pub fn ctr_h(&self) -> CTR_HR {
let bits = {
const MASK: u16 = 65535;
@@ -3115,13 +2839,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." ] # [ inline ( always ) ]
pub fn ctr_l(&mut self) -> _CTR_LW {
_CTR_LW { w: self }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." ] # [ inline ( always ) ]
pub fn ctr_h(&mut self) -> _CTR_HW {
_CTR_HW { w: self }
}
@@ -3911,8 +3633,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers." ] # [ inline ( always ) ]
pub fn regmod_l(&self) -> REGMOD_LR {
let bits = {
const MASK: u16 = 65535;
@@ -3921,8 +3642,7 @@ pub mod sct {
};
REGMOD_LR { bits }
}
- #[doc = "Bits 16:31 - Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." ] # [ inline ( always ) ]
pub fn regmod_h(&self) -> REGMOD_HR {
let bits = {
const MASK: u16 = 65535;
@@ -3944,13 +3664,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers." ] # [ inline ( always ) ]
pub fn regmod_l(&mut self) -> _REGMOD_LW {
_REGMOD_LW { w: self }
}
- #[doc = "Bits 16:31 - Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." ] # [ inline ( always ) ]
pub fn regmod_h(&mut self) -> _REGMOD_HW {
_REGMOD_HW { w: self }
}
@@ -4038,8 +3756,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn out(&self) -> OUTR {
let bits = {
const MASK: u16 = 65535;
@@ -4061,8 +3778,7 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn out(&mut self) -> _OUTW {
_OUTW { w: self }
}
@@ -4120,15 +3836,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR0R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR0R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR0R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4169,15 +3877,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR1R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR1R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR1R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4218,15 +3918,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR2R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR2R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR2R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4267,15 +3959,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR3R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR3R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR3R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4316,15 +4000,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR4R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR4R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR4R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4365,15 +4041,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR5R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR5R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR5R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4414,15 +4082,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR6R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR6R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR6R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4463,15 +4123,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR7R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR7R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR7R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4512,15 +4164,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR8`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR8R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR8R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR8R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4561,15 +4205,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR9`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR9R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR9R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR9R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4610,15 +4246,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR10`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR10R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR10R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR10R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4659,15 +4287,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR11`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR11R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR11R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR11R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4708,15 +4328,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR12`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR12R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR12R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR12R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4757,15 +4369,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR13`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR13R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR13R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR13R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4806,15 +4410,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR14`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR14R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR14R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR14R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4855,15 +4451,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `SETCLR15`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SETCLR15R {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum SETCLR15R {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl SETCLR15R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -4903,14 +4491,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR0`"]
- pub enum SETCLR0W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR0W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR0W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -4938,13 +4519,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR0W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR0W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR0W::H_COUNTER)
}
@@ -4959,14 +4538,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR1`"]
- pub enum SETCLR1W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR1W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR1W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -4994,13 +4566,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR1W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR1W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR1W::H_COUNTER)
}
@@ -5015,14 +4585,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR2`"]
- pub enum SETCLR2W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR2W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR2W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5050,13 +4613,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR2W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR2W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR2W::H_COUNTER)
}
@@ -5071,14 +4632,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR3`"]
- pub enum SETCLR3W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR3W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR3W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5106,13 +4660,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR3W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR3W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR3W::H_COUNTER)
}
@@ -5127,14 +4679,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR4`"]
- pub enum SETCLR4W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR4W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR4W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5162,13 +4707,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR4W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR4W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR4W::H_COUNTER)
}
@@ -5183,14 +4726,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR5`"]
- pub enum SETCLR5W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR5W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR5W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5218,13 +4754,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR5W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR5W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR5W::H_COUNTER)
}
@@ -5239,14 +4773,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR6`"]
- pub enum SETCLR6W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR6W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR6W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5274,13 +4801,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR6W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR6W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR6W::H_COUNTER)
}
@@ -5295,14 +4820,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR7`"]
- pub enum SETCLR7W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR7W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR7W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5330,13 +4848,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR7W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR7W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR7W::H_COUNTER)
}
@@ -5351,14 +4867,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR8`"]
- pub enum SETCLR8W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR8W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR8W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5386,13 +4895,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR8W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR8W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR8W::H_COUNTER)
}
@@ -5407,14 +4914,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR9`"]
- pub enum SETCLR9W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR9W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR9W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5442,13 +4942,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR9W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR9W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR9W::H_COUNTER)
}
@@ -5463,14 +4961,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR10`"]
- pub enum SETCLR10W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR10W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR10W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5498,13 +4989,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR10W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR10W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR10W::H_COUNTER)
}
@@ -5519,14 +5008,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR11`"]
- pub enum SETCLR11W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR11W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR11W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5554,13 +5036,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR11W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR11W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR11W::H_COUNTER)
}
@@ -5575,14 +5055,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR12`"]
- pub enum SETCLR12W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR12W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR12W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5610,13 +5083,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR12W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR12W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR12W::H_COUNTER)
}
@@ -5631,14 +5102,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR13`"]
- pub enum SETCLR13W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR13W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR13W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5666,13 +5130,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR13W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR13W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR13W::H_COUNTER)
}
@@ -5687,14 +5149,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR14`"]
- pub enum SETCLR14W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR14W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR14W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5722,13 +5177,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR14W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR14W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR14W::H_COUNTER)
}
@@ -5743,14 +5196,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `SETCLR15`"]
- pub enum SETCLR15W {
- #[doc = "Independent. Set and clear do not depend on any counter."]
- INDEPENDENT,
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- L_COUNTER,
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- H_COUNTER,
- }
+ pub enum SETCLR15W {# [ doc = "Independent. Set and clear do not depend on any counter." ] INDEPENDENT , # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] L_COUNTER , # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] H_COUNTER}
impl SETCLR15W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -5778,13 +5224,11 @@ pub mod sct {
pub fn independent(self) -> &'a mut W {
self.variant(SETCLR15W::INDEPENDENT)
}
- #[doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down."]
- #[inline(always)]
+ # [ doc = "L counter. Set and clear are reversed when counter L or the unified counter is counting down." ] # [ inline ( always ) ]
pub fn l_counter(self) -> &'a mut W {
self.variant(SETCLR15W::L_COUNTER)
}
- #[doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1."]
- #[inline(always)]
+ # [ doc = "H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." ] # [ inline ( always ) ]
pub fn h_counter(self) -> &'a mut W {
self.variant(SETCLR15W::H_COUNTER)
}
@@ -5804,8 +5248,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr0(&self) -> SETCLR0R {
SETCLR0R::_from({
const MASK: u8 = 3;
@@ -5813,8 +5256,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 2:3 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr1(&self) -> SETCLR1R {
SETCLR1R::_from({
const MASK: u8 = 3;
@@ -5822,8 +5264,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 4:5 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr2(&self) -> SETCLR2R {
SETCLR2R::_from({
const MASK: u8 = 3;
@@ -5831,8 +5272,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 6:7 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr3(&self) -> SETCLR3R {
SETCLR3R::_from({
const MASK: u8 = 3;
@@ -5840,8 +5280,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 8:9 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr4(&self) -> SETCLR4R {
SETCLR4R::_from({
const MASK: u8 = 3;
@@ -5849,8 +5288,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 10:11 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr5(&self) -> SETCLR5R {
SETCLR5R::_from({
const MASK: u8 = 3;
@@ -5858,8 +5296,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 12:13 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr6(&self) -> SETCLR6R {
SETCLR6R::_from({
const MASK: u8 = 3;
@@ -5867,8 +5304,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 14:15 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr7(&self) -> SETCLR7R {
SETCLR7R::_from({
const MASK: u8 = 3;
@@ -5876,8 +5312,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:17 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr8(&self) -> SETCLR8R {
SETCLR8R::_from({
const MASK: u8 = 3;
@@ -5885,8 +5320,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 18:19 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr9(&self) -> SETCLR9R {
SETCLR9R::_from({
const MASK: u8 = 3;
@@ -5894,8 +5328,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 20:21 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 20:21 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr10(&self) -> SETCLR10R {
SETCLR10R::_from({
const MASK: u8 = 3;
@@ -5903,8 +5336,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 22:23 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr11(&self) -> SETCLR11R {
SETCLR11R::_from({
const MASK: u8 = 3;
@@ -5912,8 +5344,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 24:25 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr12(&self) -> SETCLR12R {
SETCLR12R::_from({
const MASK: u8 = 3;
@@ -5921,8 +5352,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 26:27 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr13(&self) -> SETCLR13R {
SETCLR13R::_from({
const MASK: u8 = 3;
@@ -5930,8 +5360,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 28:29 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 28:29 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr14(&self) -> SETCLR14R {
SETCLR14R::_from({
const MASK: u8 = 3;
@@ -5939,8 +5368,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 30:31 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 30:31 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr15(&self) -> SETCLR15R {
SETCLR15R::_from({
const MASK: u8 = 3;
@@ -5961,83 +5389,67 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr0(&mut self) -> _SETCLR0W {
_SETCLR0W { w: self }
}
- #[doc = "Bits 2:3 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr1(&mut self) -> _SETCLR1W {
_SETCLR1W { w: self }
}
- #[doc = "Bits 4:5 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr2(&mut self) -> _SETCLR2W {
_SETCLR2W { w: self }
}
- #[doc = "Bits 6:7 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr3(&mut self) -> _SETCLR3W {
_SETCLR3W { w: self }
}
- #[doc = "Bits 8:9 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr4(&mut self) -> _SETCLR4W {
_SETCLR4W { w: self }
}
- #[doc = "Bits 10:11 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr5(&mut self) -> _SETCLR5W {
_SETCLR5W { w: self }
}
- #[doc = "Bits 12:13 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr6(&mut self) -> _SETCLR6W {
_SETCLR6W { w: self }
}
- #[doc = "Bits 14:15 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr7(&mut self) -> _SETCLR7W {
_SETCLR7W { w: self }
}
- #[doc = "Bits 16:17 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr8(&mut self) -> _SETCLR8W {
_SETCLR8W { w: self }
}
- #[doc = "Bits 18:19 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr9(&mut self) -> _SETCLR9W {
_SETCLR9W { w: self }
}
- #[doc = "Bits 20:21 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 20:21 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr10(&mut self) -> _SETCLR10W {
_SETCLR10W { w: self }
}
- #[doc = "Bits 22:23 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr11(&mut self) -> _SETCLR11W {
_SETCLR11W { w: self }
}
- #[doc = "Bits 24:25 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr12(&mut self) -> _SETCLR12W {
_SETCLR12W { w: self }
}
- #[doc = "Bits 26:27 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr13(&mut self) -> _SETCLR13W {
_SETCLR13W { w: self }
}
- #[doc = "Bits 28:29 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 28:29 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr14(&mut self) -> _SETCLR14W {
_SETCLR14W { w: self }
}
- #[doc = "Bits 30:31 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value."]
- #[inline(always)]
+ # [ doc = "Bits 30:31 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value." ] # [ inline ( always ) ]
pub fn setclr15(&mut self) -> _SETCLR15W {
_SETCLR15W { w: self }
}
@@ -6097,10 +5509,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O0RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR0 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR0 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR0 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR0 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O0RESR {
@@ -6151,10 +5561,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O1RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR1 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR1 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR1 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR1 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O1RESR {
@@ -6205,10 +5613,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O2RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR2 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output n (or set based on the SETCLR2 field)."]
- CLEAR_OUTPUT_N_OR_S,
+ #[doc = "Set output (or clear based on the SETCLR2 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output n (or set based on the SETCLR2 field)."] CLEAR_OUTPUT_N_OR_S,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O2RESR {
@@ -6259,10 +5665,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O3RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR3 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR3 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR3 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR3 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O3RESR {
@@ -6313,10 +5717,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O4RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR4 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR4 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR4 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR4 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O4RESR {
@@ -6367,10 +5769,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O5RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR5 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR5 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR5 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR5 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O5RESR {
@@ -6421,10 +5821,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O6RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR6 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR6 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR6 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR6 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O6RESR {
@@ -6475,10 +5873,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O7RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR7 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR7 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR7 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR7 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O7RESR {
@@ -6529,10 +5925,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O8RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR8 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR8 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR8 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR8 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O8RESR {
@@ -6583,10 +5977,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O9RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR9 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR9 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR9 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR9 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O9RESR {
@@ -6637,10 +6029,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O10RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR10 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR10 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR10 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR10 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O10RESR {
@@ -6691,10 +6081,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O11RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR11 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR11 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR11 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR11 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O11RESR {
@@ -6745,10 +6133,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O12RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR12 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR12 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR12 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR12 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O12RESR {
@@ -6799,10 +6185,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O13RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR13 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR13 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR13 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR13 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O13RESR {
@@ -6853,10 +6237,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O14RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR14 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR14 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR14 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR14 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O14RESR {
@@ -6907,10 +6289,8 @@ pub mod sct {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum O15RESR {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR15 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR15 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR15 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR15 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O15RESR {
@@ -6960,10 +6340,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O0RES`"]
pub enum O0RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR0 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR0 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR0 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR0 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O0RESW {
@@ -7024,10 +6402,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O1RES`"]
pub enum O1RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR1 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR1 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR1 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR1 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O1RESW {
@@ -7088,10 +6464,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O2RES`"]
pub enum O2RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR2 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output n (or set based on the SETCLR2 field)."]
- CLEAR_OUTPUT_N_OR_S,
+ #[doc = "Set output (or clear based on the SETCLR2 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output n (or set based on the SETCLR2 field)."] CLEAR_OUTPUT_N_OR_S,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O2RESW {
@@ -7152,10 +6526,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O3RES`"]
pub enum O3RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR3 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR3 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR3 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR3 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O3RESW {
@@ -7216,10 +6588,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O4RES`"]
pub enum O4RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR4 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR4 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR4 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR4 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O4RESW {
@@ -7280,10 +6650,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O5RES`"]
pub enum O5RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR5 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR5 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR5 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR5 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O5RESW {
@@ -7344,10 +6712,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O6RES`"]
pub enum O6RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR6 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR6 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR6 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR6 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O6RESW {
@@ -7408,10 +6774,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O7RES`"]
pub enum O7RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR7 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR7 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR7 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR7 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O7RESW {
@@ -7472,10 +6836,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O8RES`"]
pub enum O8RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR8 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR8 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR8 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR8 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O8RESW {
@@ -7536,10 +6898,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O9RES`"]
pub enum O9RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR9 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR9 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR9 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR9 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O9RESW {
@@ -7600,10 +6960,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O10RES`"]
pub enum O10RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR10 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR10 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR10 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR10 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O10RESW {
@@ -7664,10 +7022,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O11RES`"]
pub enum O11RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR11 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR11 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR11 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR11 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O11RESW {
@@ -7728,10 +7084,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O12RES`"]
pub enum O12RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR12 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR12 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR12 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR12 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O12RESW {
@@ -7792,10 +7146,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O13RES`"]
pub enum O13RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR13 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR13 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR13 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR13 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O13RESW {
@@ -7856,10 +7208,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O14RES`"]
pub enum O14RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR14 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR14 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR14 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR14 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O14RESW {
@@ -7920,10 +7270,8 @@ pub mod sct {
#[doc = "Values that can be written to the field `O15RES`"]
pub enum O15RESW {
#[doc = "No change."] NO_CHANGE,
- #[doc = "Set output (or clear based on the SETCLR15 field)."]
- SET_OUTPUT_OR_CLEAR,
- #[doc = "Clear output (or set based on the SETCLR15 field)."]
- CLEAR_OUTPUT_OR_SET,
+ #[doc = "Set output (or clear based on the SETCLR15 field)."] SET_OUTPUT_OR_CLEAR,
+ #[doc = "Clear output (or set based on the SETCLR15 field)."] CLEAR_OUTPUT_OR_SET,
#[doc = "Toggle output."] TOGGLE_OUTPUT,
}
impl O15RESW {
@@ -9074,8 +8422,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_00(&self) -> DEV_00R {
let bits = {
const MASK: bool = true;
@@ -9084,8 +8431,7 @@ pub mod sct {
};
DEV_00R { bits }
}
- #[doc = "Bit 1 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_01(&self) -> DEV_01R {
let bits = {
const MASK: bool = true;
@@ -9094,8 +8440,7 @@ pub mod sct {
};
DEV_01R { bits }
}
- #[doc = "Bit 2 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_02(&self) -> DEV_02R {
let bits = {
const MASK: bool = true;
@@ -9104,8 +8449,7 @@ pub mod sct {
};
DEV_02R { bits }
}
- #[doc = "Bit 3 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_03(&self) -> DEV_03R {
let bits = {
const MASK: bool = true;
@@ -9114,8 +8458,7 @@ pub mod sct {
};
DEV_03R { bits }
}
- #[doc = "Bit 4 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_04(&self) -> DEV_04R {
let bits = {
const MASK: bool = true;
@@ -9124,8 +8467,7 @@ pub mod sct {
};
DEV_04R { bits }
}
- #[doc = "Bit 5 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_05(&self) -> DEV_05R {
let bits = {
const MASK: bool = true;
@@ -9134,8 +8476,7 @@ pub mod sct {
};
DEV_05R { bits }
}
- #[doc = "Bit 6 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_06(&self) -> DEV_06R {
let bits = {
const MASK: bool = true;
@@ -9144,8 +8485,7 @@ pub mod sct {
};
DEV_06R { bits }
}
- #[doc = "Bit 7 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_07(&self) -> DEV_07R {
let bits = {
const MASK: bool = true;
@@ -9154,8 +8494,7 @@ pub mod sct {
};
DEV_07R { bits }
}
- #[doc = "Bit 8 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_08(&self) -> DEV_08R {
let bits = {
const MASK: bool = true;
@@ -9164,8 +8503,7 @@ pub mod sct {
};
DEV_08R { bits }
}
- #[doc = "Bit 9 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_09(&self) -> DEV_09R {
let bits = {
const MASK: bool = true;
@@ -9174,8 +8512,7 @@ pub mod sct {
};
DEV_09R { bits }
}
- #[doc = "Bit 10 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_010(&self) -> DEV_010R {
let bits = {
const MASK: bool = true;
@@ -9184,8 +8521,7 @@ pub mod sct {
};
DEV_010R { bits }
}
- #[doc = "Bit 11 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_011(&self) -> DEV_011R {
let bits = {
const MASK: bool = true;
@@ -9194,8 +8530,7 @@ pub mod sct {
};
DEV_011R { bits }
}
- #[doc = "Bit 12 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_012(&self) -> DEV_012R {
let bits = {
const MASK: bool = true;
@@ -9204,8 +8539,7 @@ pub mod sct {
};
DEV_012R { bits }
}
- #[doc = "Bit 13 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_013(&self) -> DEV_013R {
let bits = {
const MASK: bool = true;
@@ -9214,8 +8548,7 @@ pub mod sct {
};
DEV_013R { bits }
}
- #[doc = "Bit 14 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_014(&self) -> DEV_014R {
let bits = {
const MASK: bool = true;
@@ -9224,8 +8557,7 @@ pub mod sct {
};
DEV_014R { bits }
}
- #[doc = "Bit 15 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_015(&self) -> DEV_015R {
let bits = {
const MASK: bool = true;
@@ -9234,8 +8566,7 @@ pub mod sct {
};
DEV_015R { bits }
}
- #[doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers."]
- #[inline(always)]
+ # [ doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers." ] # [ inline ( always ) ]
pub fn drl0(&self) -> DRL0R {
let bits = {
const MASK: bool = true;
@@ -9267,88 +8598,71 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_00(&mut self) -> _DEV_00W {
_DEV_00W { w: self }
}
- #[doc = "Bit 1 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_01(&mut self) -> _DEV_01W {
_DEV_01W { w: self }
}
- #[doc = "Bit 2 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_02(&mut self) -> _DEV_02W {
_DEV_02W { w: self }
}
- #[doc = "Bit 3 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_03(&mut self) -> _DEV_03W {
_DEV_03W { w: self }
}
- #[doc = "Bit 4 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_04(&mut self) -> _DEV_04W {
_DEV_04W { w: self }
}
- #[doc = "Bit 5 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_05(&mut self) -> _DEV_05W {
_DEV_05W { w: self }
}
- #[doc = "Bit 6 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_06(&mut self) -> _DEV_06W {
_DEV_06W { w: self }
}
- #[doc = "Bit 7 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_07(&mut self) -> _DEV_07W {
_DEV_07W { w: self }
}
- #[doc = "Bit 8 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_08(&mut self) -> _DEV_08W {
_DEV_08W { w: self }
}
- #[doc = "Bit 9 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_09(&mut self) -> _DEV_09W {
_DEV_09W { w: self }
}
- #[doc = "Bit 10 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_010(&mut self) -> _DEV_010W {
_DEV_010W { w: self }
}
- #[doc = "Bit 11 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_011(&mut self) -> _DEV_011W {
_DEV_011W { w: self }
}
- #[doc = "Bit 12 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_012(&mut self) -> _DEV_012W {
_DEV_012W { w: self }
}
- #[doc = "Bit 13 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_013(&mut self) -> _DEV_013W {
_DEV_013W { w: self }
}
- #[doc = "Bit 14 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_014(&mut self) -> _DEV_014W {
_DEV_014W { w: self }
}
- #[doc = "Bit 15 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_015(&mut self) -> _DEV_015W {
_DEV_015W { w: self }
}
- #[doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers."]
- #[inline(always)]
+ # [ doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers." ] # [ inline ( always ) ]
pub fn drl0(&mut self) -> _DRL0W {
_DRL0W { w: self }
}
@@ -10207,8 +9521,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_10(&self) -> DEV_10R {
let bits = {
const MASK: bool = true;
@@ -10217,8 +9530,7 @@ pub mod sct {
};
DEV_10R { bits }
}
- #[doc = "Bit 1 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_11(&self) -> DEV_11R {
let bits = {
const MASK: bool = true;
@@ -10227,8 +9539,7 @@ pub mod sct {
};
DEV_11R { bits }
}
- #[doc = "Bit 2 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_12(&self) -> DEV_12R {
let bits = {
const MASK: bool = true;
@@ -10237,8 +9548,7 @@ pub mod sct {
};
DEV_12R { bits }
}
- #[doc = "Bit 3 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_13(&self) -> DEV_13R {
let bits = {
const MASK: bool = true;
@@ -10247,8 +9557,7 @@ pub mod sct {
};
DEV_13R { bits }
}
- #[doc = "Bit 4 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_14(&self) -> DEV_14R {
let bits = {
const MASK: bool = true;
@@ -10257,8 +9566,7 @@ pub mod sct {
};
DEV_14R { bits }
}
- #[doc = "Bit 5 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_15(&self) -> DEV_15R {
let bits = {
const MASK: bool = true;
@@ -10267,8 +9575,7 @@ pub mod sct {
};
DEV_15R { bits }
}
- #[doc = "Bit 6 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_16(&self) -> DEV_16R {
let bits = {
const MASK: bool = true;
@@ -10277,8 +9584,7 @@ pub mod sct {
};
DEV_16R { bits }
}
- #[doc = "Bit 7 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_17(&self) -> DEV_17R {
let bits = {
const MASK: bool = true;
@@ -10287,8 +9593,7 @@ pub mod sct {
};
DEV_17R { bits }
}
- #[doc = "Bit 8 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_18(&self) -> DEV_18R {
let bits = {
const MASK: bool = true;
@@ -10297,8 +9602,7 @@ pub mod sct {
};
DEV_18R { bits }
}
- #[doc = "Bit 9 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_19(&self) -> DEV_19R {
let bits = {
const MASK: bool = true;
@@ -10307,8 +9611,7 @@ pub mod sct {
};
DEV_19R { bits }
}
- #[doc = "Bit 10 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_110(&self) -> DEV_110R {
let bits = {
const MASK: bool = true;
@@ -10317,8 +9620,7 @@ pub mod sct {
};
DEV_110R { bits }
}
- #[doc = "Bit 11 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_111(&self) -> DEV_111R {
let bits = {
const MASK: bool = true;
@@ -10327,8 +9629,7 @@ pub mod sct {
};
DEV_111R { bits }
}
- #[doc = "Bit 12 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_112(&self) -> DEV_112R {
let bits = {
const MASK: bool = true;
@@ -10337,8 +9638,7 @@ pub mod sct {
};
DEV_112R { bits }
}
- #[doc = "Bit 13 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_113(&self) -> DEV_113R {
let bits = {
const MASK: bool = true;
@@ -10347,8 +9647,7 @@ pub mod sct {
};
DEV_113R { bits }
}
- #[doc = "Bit 14 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_114(&self) -> DEV_114R {
let bits = {
const MASK: bool = true;
@@ -10357,8 +9656,7 @@ pub mod sct {
};
DEV_114R { bits }
}
- #[doc = "Bit 15 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_115(&self) -> DEV_115R {
let bits = {
const MASK: bool = true;
@@ -10367,8 +9665,7 @@ pub mod sct {
};
DEV_115R { bits }
}
- #[doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers."]
- #[inline(always)]
+ # [ doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." ] # [ inline ( always ) ]
pub fn drl1(&self) -> DRL1R {
let bits = {
const MASK: bool = true;
@@ -10400,88 +9697,71 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_10(&mut self) -> _DEV_10W {
_DEV_10W { w: self }
}
- #[doc = "Bit 1 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_11(&mut self) -> _DEV_11W {
_DEV_11W { w: self }
}
- #[doc = "Bit 2 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_12(&mut self) -> _DEV_12W {
_DEV_12W { w: self }
}
- #[doc = "Bit 3 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_13(&mut self) -> _DEV_13W {
_DEV_13W { w: self }
}
- #[doc = "Bit 4 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_14(&mut self) -> _DEV_14W {
_DEV_14W { w: self }
}
- #[doc = "Bit 5 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_15(&mut self) -> _DEV_15W {
_DEV_15W { w: self }
}
- #[doc = "Bit 6 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_16(&mut self) -> _DEV_16W {
_DEV_16W { w: self }
}
- #[doc = "Bit 7 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_17(&mut self) -> _DEV_17W {
_DEV_17W { w: self }
}
- #[doc = "Bit 8 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_18(&mut self) -> _DEV_18W {
_DEV_18W { w: self }
}
- #[doc = "Bit 9 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_19(&mut self) -> _DEV_19W {
_DEV_19W { w: self }
}
- #[doc = "Bit 10 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_110(&mut self) -> _DEV_110W {
_DEV_110W { w: self }
}
- #[doc = "Bit 11 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_111(&mut self) -> _DEV_111W {
_DEV_111W { w: self }
}
- #[doc = "Bit 12 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_112(&mut self) -> _DEV_112W {
_DEV_112W { w: self }
}
- #[doc = "Bit 13 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_113(&mut self) -> _DEV_113W {
_DEV_113W { w: self }
}
- #[doc = "Bit 14 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_114(&mut self) -> _DEV_114W {
_DEV_114W { w: self }
}
- #[doc = "Bit 15 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn dev_115(&mut self) -> _DEV_115W {
_DEV_115W { w: self }
}
- #[doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers."]
- #[inline(always)]
+ # [ doc = "Bit 30 - A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." ] # [ inline ( always ) ]
pub fn drl1(&mut self) -> _DRL1W {
_DRL1W { w: self }
}
@@ -11252,8 +10532,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien0(&self) -> IEN0R {
let bits = {
const MASK: bool = true;
@@ -11262,8 +10541,7 @@ pub mod sct {
};
IEN0R { bits }
}
- #[doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien1(&self) -> IEN1R {
let bits = {
const MASK: bool = true;
@@ -11272,8 +10550,7 @@ pub mod sct {
};
IEN1R { bits }
}
- #[doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien2(&self) -> IEN2R {
let bits = {
const MASK: bool = true;
@@ -11282,8 +10559,7 @@ pub mod sct {
};
IEN2R { bits }
}
- #[doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien3(&self) -> IEN3R {
let bits = {
const MASK: bool = true;
@@ -11292,8 +10568,7 @@ pub mod sct {
};
IEN3R { bits }
}
- #[doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien4(&self) -> IEN4R {
let bits = {
const MASK: bool = true;
@@ -11302,8 +10577,7 @@ pub mod sct {
};
IEN4R { bits }
}
- #[doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien5(&self) -> IEN5R {
let bits = {
const MASK: bool = true;
@@ -11312,8 +10586,7 @@ pub mod sct {
};
IEN5R { bits }
}
- #[doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien6(&self) -> IEN6R {
let bits = {
const MASK: bool = true;
@@ -11322,8 +10595,7 @@ pub mod sct {
};
IEN6R { bits }
}
- #[doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien7(&self) -> IEN7R {
let bits = {
const MASK: bool = true;
@@ -11332,8 +10604,7 @@ pub mod sct {
};
IEN7R { bits }
}
- #[doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien8(&self) -> IEN8R {
let bits = {
const MASK: bool = true;
@@ -11342,8 +10613,7 @@ pub mod sct {
};
IEN8R { bits }
}
- #[doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien9(&self) -> IEN9R {
let bits = {
const MASK: bool = true;
@@ -11352,8 +10622,7 @@ pub mod sct {
};
IEN9R { bits }
}
- #[doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien10(&self) -> IEN10R {
let bits = {
const MASK: bool = true;
@@ -11362,8 +10631,7 @@ pub mod sct {
};
IEN10R { bits }
}
- #[doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien11(&self) -> IEN11R {
let bits = {
const MASK: bool = true;
@@ -11372,8 +10640,7 @@ pub mod sct {
};
IEN11R { bits }
}
- #[doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien12(&self) -> IEN12R {
let bits = {
const MASK: bool = true;
@@ -11382,8 +10649,7 @@ pub mod sct {
};
IEN12R { bits }
}
- #[doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien13(&self) -> IEN13R {
let bits = {
const MASK: bool = true;
@@ -11392,8 +10658,7 @@ pub mod sct {
};
IEN13R { bits }
}
- #[doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien14(&self) -> IEN14R {
let bits = {
const MASK: bool = true;
@@ -11402,8 +10667,7 @@ pub mod sct {
};
IEN14R { bits }
}
- #[doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien15(&self) -> IEN15R {
let bits = {
const MASK: bool = true;
@@ -11425,83 +10689,67 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien0(&mut self) -> _IEN0W {
_IEN0W { w: self }
}
- #[doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien1(&mut self) -> _IEN1W {
_IEN1W { w: self }
}
- #[doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien2(&mut self) -> _IEN2W {
_IEN2W { w: self }
}
- #[doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien3(&mut self) -> _IEN3W {
_IEN3W { w: self }
}
- #[doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien4(&mut self) -> _IEN4W {
_IEN4W { w: self }
}
- #[doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien5(&mut self) -> _IEN5W {
_IEN5W { w: self }
}
- #[doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien6(&mut self) -> _IEN6W {
_IEN6W { w: self }
}
- #[doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien7(&mut self) -> _IEN7W {
_IEN7W { w: self }
}
- #[doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien8(&mut self) -> _IEN8W {
_IEN8W { w: self }
}
- #[doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien9(&mut self) -> _IEN9W {
_IEN9W { w: self }
}
- #[doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien10(&mut self) -> _IEN10W {
_IEN10W { w: self }
}
- #[doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien11(&mut self) -> _IEN11W {
_IEN11W { w: self }
}
- #[doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien12(&mut self) -> _IEN12W {
_IEN12W { w: self }
}
- #[doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien13(&mut self) -> _IEN13W {
_IEN13W { w: self }
}
- #[doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien14(&mut self) -> _IEN14W {
_IEN14W { w: self }
}
- #[doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ien15(&mut self) -> _IEN15W {
_IEN15W { w: self }
}
@@ -12267,8 +11515,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag0(&self) -> FLAG0R {
let bits = {
const MASK: bool = true;
@@ -12277,8 +11524,7 @@ pub mod sct {
};
FLAG0R { bits }
}
- #[doc = "Bit 1 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag1(&self) -> FLAG1R {
let bits = {
const MASK: bool = true;
@@ -12287,8 +11533,7 @@ pub mod sct {
};
FLAG1R { bits }
}
- #[doc = "Bit 2 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag2(&self) -> FLAG2R {
let bits = {
const MASK: bool = true;
@@ -12297,8 +11542,7 @@ pub mod sct {
};
FLAG2R { bits }
}
- #[doc = "Bit 3 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag3(&self) -> FLAG3R {
let bits = {
const MASK: bool = true;
@@ -12307,8 +11551,7 @@ pub mod sct {
};
FLAG3R { bits }
}
- #[doc = "Bit 4 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag4(&self) -> FLAG4R {
let bits = {
const MASK: bool = true;
@@ -12317,8 +11560,7 @@ pub mod sct {
};
FLAG4R { bits }
}
- #[doc = "Bit 5 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag5(&self) -> FLAG5R {
let bits = {
const MASK: bool = true;
@@ -12327,8 +11569,7 @@ pub mod sct {
};
FLAG5R { bits }
}
- #[doc = "Bit 6 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag6(&self) -> FLAG6R {
let bits = {
const MASK: bool = true;
@@ -12337,8 +11578,7 @@ pub mod sct {
};
FLAG6R { bits }
}
- #[doc = "Bit 7 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag7(&self) -> FLAG7R {
let bits = {
const MASK: bool = true;
@@ -12347,8 +11587,7 @@ pub mod sct {
};
FLAG7R { bits }
}
- #[doc = "Bit 8 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag8(&self) -> FLAG8R {
let bits = {
const MASK: bool = true;
@@ -12357,8 +11596,7 @@ pub mod sct {
};
FLAG8R { bits }
}
- #[doc = "Bit 9 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag9(&self) -> FLAG9R {
let bits = {
const MASK: bool = true;
@@ -12367,8 +11605,7 @@ pub mod sct {
};
FLAG9R { bits }
}
- #[doc = "Bit 10 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag10(&self) -> FLAG10R {
let bits = {
const MASK: bool = true;
@@ -12377,8 +11614,7 @@ pub mod sct {
};
FLAG10R { bits }
}
- #[doc = "Bit 11 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag11(&self) -> FLAG11R {
let bits = {
const MASK: bool = true;
@@ -12387,8 +11623,7 @@ pub mod sct {
};
FLAG11R { bits }
}
- #[doc = "Bit 12 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag12(&self) -> FLAG12R {
let bits = {
const MASK: bool = true;
@@ -12397,8 +11632,7 @@ pub mod sct {
};
FLAG12R { bits }
}
- #[doc = "Bit 13 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag13(&self) -> FLAG13R {
let bits = {
const MASK: bool = true;
@@ -12407,8 +11641,7 @@ pub mod sct {
};
FLAG13R { bits }
}
- #[doc = "Bit 14 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag14(&self) -> FLAG14R {
let bits = {
const MASK: bool = true;
@@ -12417,8 +11650,7 @@ pub mod sct {
};
FLAG14R { bits }
}
- #[doc = "Bit 15 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag15(&self) -> FLAG15R {
let bits = {
const MASK: bool = true;
@@ -12440,83 +11672,67 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag0(&mut self) -> _FLAG0W {
_FLAG0W { w: self }
}
- #[doc = "Bit 1 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag1(&mut self) -> _FLAG1W {
_FLAG1W { w: self }
}
- #[doc = "Bit 2 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag2(&mut self) -> _FLAG2W {
_FLAG2W { w: self }
}
- #[doc = "Bit 3 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag3(&mut self) -> _FLAG3W {
_FLAG3W { w: self }
}
- #[doc = "Bit 4 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag4(&mut self) -> _FLAG4W {
_FLAG4W { w: self }
}
- #[doc = "Bit 5 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag5(&mut self) -> _FLAG5W {
_FLAG5W { w: self }
}
- #[doc = "Bit 6 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag6(&mut self) -> _FLAG6W {
_FLAG6W { w: self }
}
- #[doc = "Bit 7 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag7(&mut self) -> _FLAG7W {
_FLAG7W { w: self }
}
- #[doc = "Bit 8 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag8(&mut self) -> _FLAG8W {
_FLAG8W { w: self }
}
- #[doc = "Bit 9 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag9(&mut self) -> _FLAG9W {
_FLAG9W { w: self }
}
- #[doc = "Bit 10 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag10(&mut self) -> _FLAG10W {
_FLAG10W { w: self }
}
- #[doc = "Bit 11 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag11(&mut self) -> _FLAG11W {
_FLAG11W { w: self }
}
- #[doc = "Bit 12 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag12(&mut self) -> _FLAG12W {
_FLAG12W { w: self }
}
- #[doc = "Bit 13 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag13(&mut self) -> _FLAG13W {
_FLAG13W { w: self }
}
- #[doc = "Bit 14 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag14(&mut self) -> _FLAG14W {
_FLAG14W { w: self }
}
- #[doc = "Bit 15 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn flag15(&mut self) -> _FLAG15W {
_FLAG15W { w: self }
}
@@ -13282,8 +12498,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen0(&self) -> NCEN0R {
let bits = {
const MASK: bool = true;
@@ -13292,8 +12507,7 @@ pub mod sct {
};
NCEN0R { bits }
}
- #[doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen1(&self) -> NCEN1R {
let bits = {
const MASK: bool = true;
@@ -13302,8 +12516,7 @@ pub mod sct {
};
NCEN1R { bits }
}
- #[doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen2(&self) -> NCEN2R {
let bits = {
const MASK: bool = true;
@@ -13312,8 +12525,7 @@ pub mod sct {
};
NCEN2R { bits }
}
- #[doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen3(&self) -> NCEN3R {
let bits = {
const MASK: bool = true;
@@ -13322,8 +12534,7 @@ pub mod sct {
};
NCEN3R { bits }
}
- #[doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen4(&self) -> NCEN4R {
let bits = {
const MASK: bool = true;
@@ -13332,8 +12543,7 @@ pub mod sct {
};
NCEN4R { bits }
}
- #[doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen5(&self) -> NCEN5R {
let bits = {
const MASK: bool = true;
@@ -13342,8 +12552,7 @@ pub mod sct {
};
NCEN5R { bits }
}
- #[doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen6(&self) -> NCEN6R {
let bits = {
const MASK: bool = true;
@@ -13352,8 +12561,7 @@ pub mod sct {
};
NCEN6R { bits }
}
- #[doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen7(&self) -> NCEN7R {
let bits = {
const MASK: bool = true;
@@ -13362,8 +12570,7 @@ pub mod sct {
};
NCEN7R { bits }
}
- #[doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen8(&self) -> NCEN8R {
let bits = {
const MASK: bool = true;
@@ -13372,8 +12579,7 @@ pub mod sct {
};
NCEN8R { bits }
}
- #[doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen9(&self) -> NCEN9R {
let bits = {
const MASK: bool = true;
@@ -13382,8 +12588,7 @@ pub mod sct {
};
NCEN9R { bits }
}
- #[doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen10(&self) -> NCEN10R {
let bits = {
const MASK: bool = true;
@@ -13392,8 +12597,7 @@ pub mod sct {
};
NCEN10R { bits }
}
- #[doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen11(&self) -> NCEN11R {
let bits = {
const MASK: bool = true;
@@ -13402,8 +12606,7 @@ pub mod sct {
};
NCEN11R { bits }
}
- #[doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen12(&self) -> NCEN12R {
let bits = {
const MASK: bool = true;
@@ -13412,8 +12615,7 @@ pub mod sct {
};
NCEN12R { bits }
}
- #[doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen13(&self) -> NCEN13R {
let bits = {
const MASK: bool = true;
@@ -13422,8 +12624,7 @@ pub mod sct {
};
NCEN13R { bits }
}
- #[doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen14(&self) -> NCEN14R {
let bits = {
const MASK: bool = true;
@@ -13432,8 +12633,7 @@ pub mod sct {
};
NCEN14R { bits }
}
- #[doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen15(&self) -> NCEN15R {
let bits = {
const MASK: bool = true;
@@ -13455,83 +12655,67 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen0(&mut self) -> _NCEN0W {
_NCEN0W { w: self }
}
- #[doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen1(&mut self) -> _NCEN1W {
_NCEN1W { w: self }
}
- #[doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen2(&mut self) -> _NCEN2W {
_NCEN2W { w: self }
}
- #[doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen3(&mut self) -> _NCEN3W {
_NCEN3W { w: self }
}
- #[doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen4(&mut self) -> _NCEN4W {
_NCEN4W { w: self }
}
- #[doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen5(&mut self) -> _NCEN5W {
_NCEN5W { w: self }
}
- #[doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen6(&mut self) -> _NCEN6W {
_NCEN6W { w: self }
}
- #[doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen7(&mut self) -> _NCEN7W {
_NCEN7W { w: self }
}
- #[doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen8(&mut self) -> _NCEN8W {
_NCEN8W { w: self }
}
- #[doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen9(&mut self) -> _NCEN9W {
_NCEN9W { w: self }
}
- #[doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen10(&mut self) -> _NCEN10W {
_NCEN10W { w: self }
}
- #[doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen11(&mut self) -> _NCEN11W {
_NCEN11W { w: self }
}
- #[doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen12(&mut self) -> _NCEN12W {
_NCEN12W { w: self }
}
- #[doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen13(&mut self) -> _NCEN13W {
_NCEN13W { w: self }
}
- #[doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen14(&mut self) -> _NCEN14W {
_NCEN14W { w: self }
}
- #[doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncen15(&mut self) -> _NCEN15W {
_NCEN15W { w: self }
}
@@ -14385,8 +13569,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag0(&self) -> NCFLAG0R {
let bits = {
const MASK: bool = true;
@@ -14395,8 +13578,7 @@ pub mod sct {
};
NCFLAG0R { bits }
}
- #[doc = "Bit 1 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag1(&self) -> NCFLAG1R {
let bits = {
const MASK: bool = true;
@@ -14405,8 +13587,7 @@ pub mod sct {
};
NCFLAG1R { bits }
}
- #[doc = "Bit 2 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag2(&self) -> NCFLAG2R {
let bits = {
const MASK: bool = true;
@@ -14415,8 +13596,7 @@ pub mod sct {
};
NCFLAG2R { bits }
}
- #[doc = "Bit 3 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag3(&self) -> NCFLAG3R {
let bits = {
const MASK: bool = true;
@@ -14425,8 +13605,7 @@ pub mod sct {
};
NCFLAG3R { bits }
}
- #[doc = "Bit 4 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag4(&self) -> NCFLAG4R {
let bits = {
const MASK: bool = true;
@@ -14435,8 +13614,7 @@ pub mod sct {
};
NCFLAG4R { bits }
}
- #[doc = "Bit 5 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag5(&self) -> NCFLAG5R {
let bits = {
const MASK: bool = true;
@@ -14445,8 +13623,7 @@ pub mod sct {
};
NCFLAG5R { bits }
}
- #[doc = "Bit 6 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag6(&self) -> NCFLAG6R {
let bits = {
const MASK: bool = true;
@@ -14455,8 +13632,7 @@ pub mod sct {
};
NCFLAG6R { bits }
}
- #[doc = "Bit 7 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag7(&self) -> NCFLAG7R {
let bits = {
const MASK: bool = true;
@@ -14465,8 +13641,7 @@ pub mod sct {
};
NCFLAG7R { bits }
}
- #[doc = "Bit 8 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag8(&self) -> NCFLAG8R {
let bits = {
const MASK: bool = true;
@@ -14475,8 +13650,7 @@ pub mod sct {
};
NCFLAG8R { bits }
}
- #[doc = "Bit 9 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag9(&self) -> NCFLAG9R {
let bits = {
const MASK: bool = true;
@@ -14485,8 +13659,7 @@ pub mod sct {
};
NCFLAG9R { bits }
}
- #[doc = "Bit 10 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag10(&self) -> NCFLAG10R {
let bits = {
const MASK: bool = true;
@@ -14495,8 +13668,7 @@ pub mod sct {
};
NCFLAG10R { bits }
}
- #[doc = "Bit 11 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag11(&self) -> NCFLAG11R {
let bits = {
const MASK: bool = true;
@@ -14505,8 +13677,7 @@ pub mod sct {
};
NCFLAG11R { bits }
}
- #[doc = "Bit 12 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag12(&self) -> NCFLAG12R {
let bits = {
const MASK: bool = true;
@@ -14515,8 +13686,7 @@ pub mod sct {
};
NCFLAG12R { bits }
}
- #[doc = "Bit 13 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag13(&self) -> NCFLAG13R {
let bits = {
const MASK: bool = true;
@@ -14525,8 +13695,7 @@ pub mod sct {
};
NCFLAG13R { bits }
}
- #[doc = "Bit 14 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag14(&self) -> NCFLAG14R {
let bits = {
const MASK: bool = true;
@@ -14535,8 +13704,7 @@ pub mod sct {
};
NCFLAG14R { bits }
}
- #[doc = "Bit 15 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag15(&self) -> NCFLAG15R {
let bits = {
const MASK: bool = true;
@@ -14545,8 +13713,7 @@ pub mod sct {
};
NCFLAG15R { bits }
}
- #[doc = "Bit 30 - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful."]
- #[inline(always)]
+ # [ doc = "Bit 30 - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful." ] # [ inline ( always ) ]
pub fn buserrl(&self) -> BUSERRLR {
let bits = {
const MASK: bool = true;
@@ -14555,8 +13722,7 @@ pub mod sct {
};
BUSERRLR { bits }
}
- #[doc = "Bit 31 - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted."]
- #[inline(always)]
+ # [ doc = "Bit 31 - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted." ] # [ inline ( always ) ]
pub fn buserrh(&self) -> BUSERRHR {
let bits = {
const MASK: bool = true;
@@ -14578,93 +13744,75 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag0(&mut self) -> _NCFLAG0W {
_NCFLAG0W { w: self }
}
- #[doc = "Bit 1 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag1(&mut self) -> _NCFLAG1W {
_NCFLAG1W { w: self }
}
- #[doc = "Bit 2 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag2(&mut self) -> _NCFLAG2W {
_NCFLAG2W { w: self }
}
- #[doc = "Bit 3 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag3(&mut self) -> _NCFLAG3W {
_NCFLAG3W { w: self }
}
- #[doc = "Bit 4 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag4(&mut self) -> _NCFLAG4W {
_NCFLAG4W { w: self }
}
- #[doc = "Bit 5 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag5(&mut self) -> _NCFLAG5W {
_NCFLAG5W { w: self }
}
- #[doc = "Bit 6 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag6(&mut self) -> _NCFLAG6W {
_NCFLAG6W { w: self }
}
- #[doc = "Bit 7 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag7(&mut self) -> _NCFLAG7W {
_NCFLAG7W { w: self }
}
- #[doc = "Bit 8 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag8(&mut self) -> _NCFLAG8W {
_NCFLAG8W { w: self }
}
- #[doc = "Bit 9 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag9(&mut self) -> _NCFLAG9W {
_NCFLAG9W { w: self }
}
- #[doc = "Bit 10 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag10(&mut self) -> _NCFLAG10W {
_NCFLAG10W { w: self }
}
- #[doc = "Bit 11 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag11(&mut self) -> _NCFLAG11W {
_NCFLAG11W { w: self }
}
- #[doc = "Bit 12 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag12(&mut self) -> _NCFLAG12W {
_NCFLAG12W { w: self }
}
- #[doc = "Bit 13 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag13(&mut self) -> _NCFLAG13W {
_NCFLAG13W { w: self }
}
- #[doc = "Bit 14 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag14(&mut self) -> _NCFLAG14W {
_NCFLAG14W { w: self }
}
- #[doc = "Bit 15 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." ] # [ inline ( always ) ]
pub fn ncflag15(&mut self) -> _NCFLAG15W {
_NCFLAG15W { w: self }
}
- #[doc = "Bit 30 - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful."]
- #[inline(always)]
+ # [ doc = "Bit 30 - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful." ] # [ inline ( always ) ]
pub fn buserrl(&mut self) -> _BUSERRLW {
_BUSERRLW { w: self }
}
- #[doc = "Bit 31 - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted."]
- #[inline(always)]
+ # [ doc = "Bit 31 - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted." ] # [ inline ( always ) ]
pub fn buserrh(&mut self) -> _BUSERRHW {
_BUSERRHW { w: self }
}
@@ -14778,8 +13926,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." ] # [ inline ( always ) ]
pub fn match_l(&self) -> MATCH_LR {
let bits = {
const MASK: u16 = 65535;
@@ -14788,8 +13935,7 @@ pub mod sct {
};
MATCH_LR { bits }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." ] # [ inline ( always ) ]
pub fn match_h(&self) -> MATCH_HR {
let bits = {
const MASK: u16 = 65535;
@@ -14811,13 +13957,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." ] # [ inline ( always ) ]
pub fn match_l(&mut self) -> _MATCH_LW {
_MATCH_LW { w: self }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." ] # [ inline ( always ) ]
pub fn match_h(&mut self) -> _MATCH_HW {
_MATCH_HW { w: self }
}
@@ -14931,8 +14075,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." ] # [ inline ( always ) ]
pub fn fracmat_l(&self) -> FRACMAT_LR {
let bits = {
const MASK: u8 = 15;
@@ -14941,8 +14084,7 @@ pub mod sct {
};
FRACMAT_LR { bits }
}
- #[doc = "Bits 16:19 - When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." ] # [ inline ( always ) ]
pub fn fracmat_h(&self) -> FRACMAT_HR {
let bits = {
const MASK: u8 = 15;
@@ -14964,13 +14106,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." ] # [ inline ( always ) ]
pub fn fracmat_l(&mut self) -> _FRACMAT_LW {
_FRACMAT_LW { w: self }
}
- #[doc = "Bits 16:19 - When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." ] # [ inline ( always ) ]
pub fn fracmat_h(&mut self) -> _FRACMAT_HW {
_FRACMAT_HW { w: self }
}
@@ -15084,8 +14224,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." ] # [ inline ( always ) ]
pub fn cap_l(&self) -> CAP_LR {
let bits = {
const MASK: u16 = 65535;
@@ -15094,8 +14233,7 @@ pub mod sct {
};
CAP_LR { bits }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." ] # [ inline ( always ) ]
pub fn cap_h(&self) -> CAP_HR {
let bits = {
const MASK: u16 = 65535;
@@ -15117,13 +14255,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." ] # [ inline ( always ) ]
pub fn cap_l(&mut self) -> _CAP_LW {
_CAP_LW { w: self }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." ] # [ inline ( always ) ]
pub fn cap_h(&mut self) -> _CAP_HW {
_CAP_HW { w: self }
}
@@ -15237,8 +14373,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." ] # [ inline ( always ) ]
pub fn reload_l(&self) -> RELOAD_LR {
let bits = {
const MASK: u16 = 65535;
@@ -15247,8 +14382,7 @@ pub mod sct {
};
RELOAD_LR { bits }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." ] # [ inline ( always ) ]
pub fn reload_h(&self) -> RELOAD_HR {
let bits = {
const MASK: u16 = 65535;
@@ -15270,13 +14404,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." ] # [ inline ( always ) ]
pub fn reload_l(&mut self) -> _RELOAD_LW {
_RELOAD_LW { w: self }
}
- #[doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." ] # [ inline ( always ) ]
pub fn reload_h(&mut self) -> _RELOAD_HW {
_RELOAD_HW { w: self }
}
@@ -15390,8 +14522,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." ] # [ inline ( always ) ]
pub fn relfrac_l(&self) -> RELFRAC_LR {
let bits = {
const MASK: u8 = 15;
@@ -15400,8 +14531,7 @@ pub mod sct {
};
RELFRAC_LR { bits }
}
- #[doc = "Bits 16:19 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." ] # [ inline ( always ) ]
pub fn relfrac_h(&self) -> RELFRAC_HR {
let bits = {
const MASK: u8 = 15;
@@ -15423,13 +14553,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." ] # [ inline ( always ) ]
pub fn relfrac_l(&mut self) -> _RELFRAC_LW {
_RELFRAC_LW { w: self }
}
- #[doc = "Bits 16:19 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." ] # [ inline ( always ) ]
pub fn relfrac_h(&mut self) -> _RELFRAC_HW {
_RELFRAC_HW { w: self }
}
@@ -15543,8 +14671,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn capcon_l(&self) -> CAPCON_LR {
let bits = {
const MASK: u16 = 65535;
@@ -15553,8 +14680,7 @@ pub mod sct {
};
CAPCON_LR { bits }
}
- #[doc = "Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn capcon_h(&self) -> CAPCON_HR {
let bits = {
const MASK: u16 = 65535;
@@ -15576,13 +14702,11 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." ] # [ inline ( always ) ]
pub fn capcon_l(&mut self) -> _CAPCON_LW {
_CAPCON_LW { w: self }
}
- #[doc = "Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." ] # [ inline ( always ) ]
pub fn capcon_h(&mut self) -> _CAPCON_HW {
_CAPCON_HW { w: self }
}
@@ -17052,8 +16176,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk0(&self) -> STATEMSK0R {
let bits = {
const MASK: bool = true;
@@ -17062,8 +16185,7 @@ pub mod sct {
};
STATEMSK0R { bits }
}
- #[doc = "Bit 1 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk1(&self) -> STATEMSK1R {
let bits = {
const MASK: bool = true;
@@ -17072,8 +16194,7 @@ pub mod sct {
};
STATEMSK1R { bits }
}
- #[doc = "Bit 2 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk2(&self) -> STATEMSK2R {
let bits = {
const MASK: bool = true;
@@ -17082,8 +16203,7 @@ pub mod sct {
};
STATEMSK2R { bits }
}
- #[doc = "Bit 3 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk3(&self) -> STATEMSK3R {
let bits = {
const MASK: bool = true;
@@ -17092,8 +16212,7 @@ pub mod sct {
};
STATEMSK3R { bits }
}
- #[doc = "Bit 4 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk4(&self) -> STATEMSK4R {
let bits = {
const MASK: bool = true;
@@ -17102,8 +16221,7 @@ pub mod sct {
};
STATEMSK4R { bits }
}
- #[doc = "Bit 5 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk5(&self) -> STATEMSK5R {
let bits = {
const MASK: bool = true;
@@ -17112,8 +16230,7 @@ pub mod sct {
};
STATEMSK5R { bits }
}
- #[doc = "Bit 6 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk6(&self) -> STATEMSK6R {
let bits = {
const MASK: bool = true;
@@ -17122,8 +16239,7 @@ pub mod sct {
};
STATEMSK6R { bits }
}
- #[doc = "Bit 7 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk7(&self) -> STATEMSK7R {
let bits = {
const MASK: bool = true;
@@ -17132,8 +16248,7 @@ pub mod sct {
};
STATEMSK7R { bits }
}
- #[doc = "Bit 8 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk8(&self) -> STATEMSK8R {
let bits = {
const MASK: bool = true;
@@ -17142,8 +16257,7 @@ pub mod sct {
};
STATEMSK8R { bits }
}
- #[doc = "Bit 9 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk9(&self) -> STATEMSK9R {
let bits = {
const MASK: bool = true;
@@ -17152,8 +16266,7 @@ pub mod sct {
};
STATEMSK9R { bits }
}
- #[doc = "Bit 10 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk10(&self) -> STATEMSK10R {
let bits = {
const MASK: bool = true;
@@ -17162,8 +16275,7 @@ pub mod sct {
};
STATEMSK10R { bits }
}
- #[doc = "Bit 11 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk11(&self) -> STATEMSK11R {
let bits = {
const MASK: bool = true;
@@ -17172,8 +16284,7 @@ pub mod sct {
};
STATEMSK11R { bits }
}
- #[doc = "Bit 12 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk12(&self) -> STATEMSK12R {
let bits = {
const MASK: bool = true;
@@ -17182,8 +16293,7 @@ pub mod sct {
};
STATEMSK12R { bits }
}
- #[doc = "Bit 13 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk13(&self) -> STATEMSK13R {
let bits = {
const MASK: bool = true;
@@ -17192,8 +16302,7 @@ pub mod sct {
};
STATEMSK13R { bits }
}
- #[doc = "Bit 14 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk14(&self) -> STATEMSK14R {
let bits = {
const MASK: bool = true;
@@ -17202,8 +16311,7 @@ pub mod sct {
};
STATEMSK14R { bits }
}
- #[doc = "Bit 15 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk15(&self) -> STATEMSK15R {
let bits = {
const MASK: bool = true;
@@ -17212,8 +16320,7 @@ pub mod sct {
};
STATEMSK15R { bits }
}
- #[doc = "Bit 16 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 16 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk16(&self) -> STATEMSK16R {
let bits = {
const MASK: bool = true;
@@ -17222,8 +16329,7 @@ pub mod sct {
};
STATEMSK16R { bits }
}
- #[doc = "Bit 17 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 17 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk17(&self) -> STATEMSK17R {
let bits = {
const MASK: bool = true;
@@ -17232,8 +16338,7 @@ pub mod sct {
};
STATEMSK17R { bits }
}
- #[doc = "Bit 18 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 18 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk18(&self) -> STATEMSK18R {
let bits = {
const MASK: bool = true;
@@ -17242,8 +16347,7 @@ pub mod sct {
};
STATEMSK18R { bits }
}
- #[doc = "Bit 19 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 19 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk19(&self) -> STATEMSK19R {
let bits = {
const MASK: bool = true;
@@ -17252,8 +16356,7 @@ pub mod sct {
};
STATEMSK19R { bits }
}
- #[doc = "Bit 20 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 20 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk20(&self) -> STATEMSK20R {
let bits = {
const MASK: bool = true;
@@ -17262,8 +16365,7 @@ pub mod sct {
};
STATEMSK20R { bits }
}
- #[doc = "Bit 21 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 21 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk21(&self) -> STATEMSK21R {
let bits = {
const MASK: bool = true;
@@ -17272,8 +16374,7 @@ pub mod sct {
};
STATEMSK21R { bits }
}
- #[doc = "Bit 22 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 22 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk22(&self) -> STATEMSK22R {
let bits = {
const MASK: bool = true;
@@ -17282,8 +16383,7 @@ pub mod sct {
};
STATEMSK22R { bits }
}
- #[doc = "Bit 23 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 23 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk23(&self) -> STATEMSK23R {
let bits = {
const MASK: bool = true;
@@ -17292,8 +16392,7 @@ pub mod sct {
};
STATEMSK23R { bits }
}
- #[doc = "Bit 24 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 24 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk24(&self) -> STATEMSK24R {
let bits = {
const MASK: bool = true;
@@ -17302,8 +16401,7 @@ pub mod sct {
};
STATEMSK24R { bits }
}
- #[doc = "Bit 25 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 25 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk25(&self) -> STATEMSK25R {
let bits = {
const MASK: bool = true;
@@ -17312,8 +16410,7 @@ pub mod sct {
};
STATEMSK25R { bits }
}
- #[doc = "Bit 26 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 26 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk26(&self) -> STATEMSK26R {
let bits = {
const MASK: bool = true;
@@ -17322,8 +16419,7 @@ pub mod sct {
};
STATEMSK26R { bits }
}
- #[doc = "Bit 27 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 27 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk27(&self) -> STATEMSK27R {
let bits = {
const MASK: bool = true;
@@ -17332,8 +16428,7 @@ pub mod sct {
};
STATEMSK27R { bits }
}
- #[doc = "Bit 28 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 28 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk28(&self) -> STATEMSK28R {
let bits = {
const MASK: bool = true;
@@ -17342,8 +16437,7 @@ pub mod sct {
};
STATEMSK28R { bits }
}
- #[doc = "Bit 29 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 29 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk29(&self) -> STATEMSK29R {
let bits = {
const MASK: bool = true;
@@ -17352,8 +16446,7 @@ pub mod sct {
};
STATEMSK29R { bits }
}
- #[doc = "Bit 30 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 30 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk30(&self) -> STATEMSK30R {
let bits = {
const MASK: bool = true;
@@ -17362,8 +16455,7 @@ pub mod sct {
};
STATEMSK30R { bits }
}
- #[doc = "Bit 31 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 31 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk31(&self) -> STATEMSK31R {
let bits = {
const MASK: bool = true;
@@ -17385,163 +16477,131 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk0(&mut self) -> _STATEMSK0W {
_STATEMSK0W { w: self }
}
- #[doc = "Bit 1 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk1(&mut self) -> _STATEMSK1W {
_STATEMSK1W { w: self }
}
- #[doc = "Bit 2 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk2(&mut self) -> _STATEMSK2W {
_STATEMSK2W { w: self }
}
- #[doc = "Bit 3 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk3(&mut self) -> _STATEMSK3W {
_STATEMSK3W { w: self }
}
- #[doc = "Bit 4 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk4(&mut self) -> _STATEMSK4W {
_STATEMSK4W { w: self }
}
- #[doc = "Bit 5 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk5(&mut self) -> _STATEMSK5W {
_STATEMSK5W { w: self }
}
- #[doc = "Bit 6 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk6(&mut self) -> _STATEMSK6W {
_STATEMSK6W { w: self }
}
- #[doc = "Bit 7 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk7(&mut self) -> _STATEMSK7W {
_STATEMSK7W { w: self }
}
- #[doc = "Bit 8 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 8 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk8(&mut self) -> _STATEMSK8W {
_STATEMSK8W { w: self }
}
- #[doc = "Bit 9 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk9(&mut self) -> _STATEMSK9W {
_STATEMSK9W { w: self }
}
- #[doc = "Bit 10 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 10 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk10(&mut self) -> _STATEMSK10W {
_STATEMSK10W { w: self }
}
- #[doc = "Bit 11 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 11 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk11(&mut self) -> _STATEMSK11W {
_STATEMSK11W { w: self }
}
- #[doc = "Bit 12 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk12(&mut self) -> _STATEMSK12W {
_STATEMSK12W { w: self }
}
- #[doc = "Bit 13 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk13(&mut self) -> _STATEMSK13W {
_STATEMSK13W { w: self }
}
- #[doc = "Bit 14 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk14(&mut self) -> _STATEMSK14W {
_STATEMSK14W { w: self }
}
- #[doc = "Bit 15 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk15(&mut self) -> _STATEMSK15W {
_STATEMSK15W { w: self }
}
- #[doc = "Bit 16 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 16 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk16(&mut self) -> _STATEMSK16W {
_STATEMSK16W { w: self }
}
- #[doc = "Bit 17 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 17 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk17(&mut self) -> _STATEMSK17W {
_STATEMSK17W { w: self }
}
- #[doc = "Bit 18 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 18 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk18(&mut self) -> _STATEMSK18W {
_STATEMSK18W { w: self }
}
- #[doc = "Bit 19 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 19 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk19(&mut self) -> _STATEMSK19W {
_STATEMSK19W { w: self }
}
- #[doc = "Bit 20 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 20 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk20(&mut self) -> _STATEMSK20W {
_STATEMSK20W { w: self }
}
- #[doc = "Bit 21 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 21 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk21(&mut self) -> _STATEMSK21W {
_STATEMSK21W { w: self }
}
- #[doc = "Bit 22 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 22 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk22(&mut self) -> _STATEMSK22W {
_STATEMSK22W { w: self }
}
- #[doc = "Bit 23 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 23 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk23(&mut self) -> _STATEMSK23W {
_STATEMSK23W { w: self }
}
- #[doc = "Bit 24 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 24 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk24(&mut self) -> _STATEMSK24W {
_STATEMSK24W { w: self }
}
- #[doc = "Bit 25 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 25 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk25(&mut self) -> _STATEMSK25W {
_STATEMSK25W { w: self }
}
- #[doc = "Bit 26 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 26 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk26(&mut self) -> _STATEMSK26W {
_STATEMSK26W { w: self }
}
- #[doc = "Bit 27 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 27 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk27(&mut self) -> _STATEMSK27W {
_STATEMSK27W { w: self }
}
- #[doc = "Bit 28 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 28 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk28(&mut self) -> _STATEMSK28W {
_STATEMSK28W { w: self }
}
- #[doc = "Bit 29 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 29 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk29(&mut self) -> _STATEMSK29W {
_STATEMSK29W { w: self }
}
- #[doc = "Bit 30 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 30 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk30(&mut self) -> _STATEMSK30W {
_STATEMSK30W { w: self }
}
- #[doc = "Bit 31 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)."]
- #[inline(always)]
+ # [ doc = "Bit 31 - If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." ] # [ inline ( always ) ]
pub fn statemsk31(&mut self) -> _STATEMSK31W {
_STATEMSK31W { w: self }
}
@@ -17765,14 +16825,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `COMBMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum COMBMODER {
- #[doc = "OR. The event occurs when either the specified match or I/O condition occurs."]
- OR,
- #[doc = "MATCH. Uses the specified match only."] MATCH,
- #[doc = "IO. Uses the specified I/O condition only."] IO,
- #[doc = "AND. The event occurs when the specified match and I/O condition occur simultaneously."]
- AND,
- }
+ pub enum COMBMODER {# [ doc = "OR. The event occurs when either the specified match or I/O condition occurs." ] OR , # [ doc = "MATCH. Uses the specified match only." ] MATCH , # [ doc = "IO. Uses the specified I/O condition only." ] IO , # [ doc = "AND. The event occurs when the specified match and I/O condition occur simultaneously." ] AND}
impl COMBMODER {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -17897,15 +16950,7 @@ pub mod sct {
}
#[doc = "Possible values of the field `DIRECTION`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DIRECTIONR {
- #[doc = "Direction independent. This event is triggered regardless of the count direction."]
- DIRECTION_INDEPENDEN,
- #[doc = "Counting up. This event is triggered only during up-counting when BIDIR = 1."]
- COUNTING_UP,
- #[doc = "Counting down. This event is triggered only during down-counting when BIDIR = 1."]
- COUNTING_DOWN,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum DIRECTIONR {# [ doc = "Direction independent. This event is triggered regardless of the count direction." ] DIRECTION_INDEPENDEN , # [ doc = "Counting up. This event is triggered only during up-counting when BIDIR = 1." ] COUNTING_UP , # [ doc = "Counting down. This event is triggered only during down-counting when BIDIR = 1." ] COUNTING_DOWN , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl DIRECTIONR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -18151,14 +17196,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `COMBMODE`"]
- pub enum COMBMODEW {
- #[doc = "OR. The event occurs when either the specified match or I/O condition occurs."]
- OR,
- #[doc = "MATCH. Uses the specified match only."] MATCH,
- #[doc = "IO. Uses the specified I/O condition only."] IO,
- #[doc = "AND. The event occurs when the specified match and I/O condition occur simultaneously."]
- AND,
- }
+ pub enum COMBMODEW {# [ doc = "OR. The event occurs when either the specified match or I/O condition occurs." ] OR , # [ doc = "MATCH. Uses the specified match only." ] MATCH , # [ doc = "IO. Uses the specified I/O condition only." ] IO , # [ doc = "AND. The event occurs when the specified match and I/O condition occur simultaneously." ] AND}
impl COMBMODEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -18199,8 +17237,7 @@ pub mod sct {
pub fn io(self) -> &'a mut W {
self.variant(COMBMODEW::IO)
}
- #[doc = "AND. The event occurs when the specified match and I/O condition occur simultaneously."]
- #[inline(always)]
+ # [ doc = "AND. The event occurs when the specified match and I/O condition occur simultaneously." ] # [ inline ( always ) ]
pub fn and(self) -> &'a mut W {
self.variant(COMBMODEW::AND)
}
@@ -18310,14 +17347,7 @@ pub mod sct {
}
}
#[doc = "Values that can be written to the field `DIRECTION`"]
- pub enum DIRECTIONW {
- #[doc = "Direction independent. This event is triggered regardless of the count direction."]
- DIRECTION_INDEPENDEN,
- #[doc = "Counting up. This event is triggered only during up-counting when BIDIR = 1."]
- COUNTING_UP,
- #[doc = "Counting down. This event is triggered only during down-counting when BIDIR = 1."]
- COUNTING_DOWN,
- }
+ pub enum DIRECTIONW {# [ doc = "Direction independent. This event is triggered regardless of the count direction." ] DIRECTION_INDEPENDEN , # [ doc = "Counting up. This event is triggered only during up-counting when BIDIR = 1." ] COUNTING_UP , # [ doc = "Counting down. This event is triggered only during down-counting when BIDIR = 1." ] COUNTING_DOWN}
impl DIRECTIONW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -18340,8 +17370,7 @@ pub mod sct {
pub fn variant(self, variant: DIRECTIONW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
- #[doc = "Direction independent. This event is triggered regardless of the count direction."]
- #[inline(always)]
+ # [ doc = "Direction independent. This event is triggered regardless of the count direction." ] # [ inline ( always ) ]
pub fn direction_independen(self) -> &'a mut W {
self.variant(DIRECTIONW::DIRECTION_INDEPENDEN)
}
@@ -18350,8 +17379,7 @@ pub mod sct {
pub fn counting_up(self) -> &'a mut W {
self.variant(DIRECTIONW::COUNTING_UP)
}
- #[doc = "Counting down. This event is triggered only during down-counting when BIDIR = 1."]
- #[inline(always)]
+ # [ doc = "Counting down. This event is triggered only during down-counting when BIDIR = 1." ] # [ inline ( always ) ]
pub fn counting_down(self) -> &'a mut W {
self.variant(DIRECTIONW::COUNTING_DOWN)
}
@@ -18371,8 +17399,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." ] # [ inline ( always ) ]
pub fn matchsel(&self) -> MATCHSELR {
let bits = {
const MASK: u8 = 15;
@@ -18399,8 +17426,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 6:9 - Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."]
- #[inline(always)]
+ # [ doc = "Bits 6:9 - Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." ] # [ inline ( always ) ]
pub fn iosel(&self) -> IOSELR {
let bits = {
const MASK: u8 = 15;
@@ -18409,8 +17435,7 @@ pub mod sct {
};
IOSELR { bits }
}
- #[doc = "Bits 10:11 - Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ." ] # [ inline ( always ) ]
pub fn iocond(&self) -> IOCONDR {
IOCONDR::_from({
const MASK: u8 = 3;
@@ -18418,8 +17443,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 12:13 - Selects how the specified match and I/O condition are used and combined."]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Selects how the specified match and I/O condition are used and combined." ] # [ inline ( always ) ]
pub fn combmode(&self) -> COMBMODER {
COMBMODER::_from({
const MASK: u8 = 3;
@@ -18427,8 +17451,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 14 - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."]
- #[inline(always)]
+ # [ doc = "Bit 14 - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." ] # [ inline ( always ) ]
pub fn stateld(&self) -> STATELDR {
STATELDR::_from({
const MASK: bool = true;
@@ -18436,8 +17459,7 @@ pub mod sct {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 15:19 - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value."]
- #[inline(always)]
+ # [ doc = "Bits 15:19 - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." ] # [ inline ( always ) ]
pub fn statev(&self) -> STATEVR {
let bits = {
const MASK: u8 = 31;
@@ -18446,8 +17468,7 @@ pub mod sct {
};
STATEVR { bits }
}
- #[doc = "Bit 20 - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value."]
- #[inline(always)]
+ # [ doc = "Bit 20 - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." ] # [ inline ( always ) ]
pub fn matchmem(&self) -> MATCHMEMR {
let bits = {
const MASK: bool = true;
@@ -18456,8 +17477,7 @@ pub mod sct {
};
MATCHMEMR { bits }
}
- #[doc = "Bits 21:22 - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."]
- #[inline(always)]
+ # [ doc = "Bits 21:22 - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved." ] # [ inline ( always ) ]
pub fn direction(&self) -> DIRECTIONR {
DIRECTIONR::_from({
const MASK: u8 = 3;
@@ -18478,8 +17498,7 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running." ] # [ inline ( always ) ]
pub fn matchsel(&mut self) -> _MATCHSELW {
_MATCHSELW { w: self }
}
@@ -18493,38 +17512,31 @@ pub mod sct {
pub fn outsel(&mut self) -> _OUTSELW {
_OUTSELW { w: self }
}
- #[doc = "Bits 6:9 - Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."]
- #[inline(always)]
+ # [ doc = "Bits 6:9 - Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event." ] # [ inline ( always ) ]
pub fn iosel(&mut self) -> _IOSELW {
_IOSELW { w: self }
}
- #[doc = "Bits 10:11 - Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ." ] # [ inline ( always ) ]
pub fn iocond(&mut self) -> _IOCONDW {
_IOCONDW { w: self }
}
- #[doc = "Bits 12:13 - Selects how the specified match and I/O condition are used and combined."]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Selects how the specified match and I/O condition are used and combined." ] # [ inline ( always ) ]
pub fn combmode(&mut self) -> _COMBMODEW {
_COMBMODEW { w: self }
}
- #[doc = "Bit 14 - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."]
- #[inline(always)]
+ # [ doc = "Bit 14 - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." ] # [ inline ( always ) ]
pub fn stateld(&mut self) -> _STATELDW {
_STATELDW { w: self }
}
- #[doc = "Bits 15:19 - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value."]
- #[inline(always)]
+ # [ doc = "Bits 15:19 - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value." ] # [ inline ( always ) ]
pub fn statev(&mut self) -> _STATEVW {
_STATEVW { w: self }
}
- #[doc = "Bit 20 - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value."]
- #[inline(always)]
+ # [ doc = "Bit 20 - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value." ] # [ inline ( always ) ]
pub fn matchmem(&mut self) -> _MATCHMEMW {
_MATCHMEMW { w: self }
}
- #[doc = "Bits 21:22 - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."]
- #[inline(always)]
+ # [ doc = "Bits 21:22 - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved." ] # [ inline ( always ) ]
pub fn direction(&mut self) -> _DIRECTIONW {
_DIRECTIONW { w: self }
}
@@ -19290,8 +18302,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 0 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set0(&self) -> SET0R {
let bits = {
const MASK: bool = true;
@@ -19300,8 +18311,7 @@ pub mod sct {
};
SET0R { bits }
}
- #[doc = "Bit 1 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 1 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set1(&self) -> SET1R {
let bits = {
const MASK: bool = true;
@@ -19310,8 +18320,7 @@ pub mod sct {
};
SET1R { bits }
}
- #[doc = "Bit 2 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 2 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set2(&self) -> SET2R {
let bits = {
const MASK: bool = true;
@@ -19320,8 +18329,7 @@ pub mod sct {
};
SET2R { bits }
}
- #[doc = "Bit 3 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 3 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set3(&self) -> SET3R {
let bits = {
const MASK: bool = true;
@@ -19330,8 +18338,7 @@ pub mod sct {
};
SET3R { bits }
}
- #[doc = "Bit 4 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 4 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set4(&self) -> SET4R {
let bits = {
const MASK: bool = true;
@@ -19340,8 +18347,7 @@ pub mod sct {
};
SET4R { bits }
}
- #[doc = "Bit 5 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 5 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set5(&self) -> SET5R {
let bits = {
const MASK: bool = true;
@@ -19350,8 +18356,7 @@ pub mod sct {
};
SET5R { bits }
}
- #[doc = "Bit 6 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 6 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set6(&self) -> SET6R {
let bits = {
const MASK: bool = true;
@@ -19360,8 +18365,7 @@ pub mod sct {
};
SET6R { bits }
}
- #[doc = "Bit 7 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set7(&self) -> SET7R {
let bits = {
const MASK: bool = true;
@@ -19370,8 +18374,7 @@ pub mod sct {
};
SET7R { bits }
}
- #[doc = "Bit 8 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set8(&self) -> SET8R {
let bits = {
const MASK: bool = true;
@@ -19380,8 +18383,7 @@ pub mod sct {
};
SET8R { bits }
}
- #[doc = "Bit 9 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set9(&self) -> SET9R {
let bits = {
const MASK: bool = true;
@@ -19390,8 +18392,7 @@ pub mod sct {
};
SET9R { bits }
}
- #[doc = "Bit 10 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set10(&self) -> SET10R {
let bits = {
const MASK: bool = true;
@@ -19400,8 +18401,7 @@ pub mod sct {
};
SET10R { bits }
}
- #[doc = "Bit 11 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 11 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set11(&self) -> SET11R {
let bits = {
const MASK: bool = true;
@@ -19410,8 +18410,7 @@ pub mod sct {
};
SET11R { bits }
}
- #[doc = "Bit 12 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 12 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set12(&self) -> SET12R {
let bits = {
const MASK: bool = true;
@@ -19420,8 +18419,7 @@ pub mod sct {
};
SET12R { bits }
}
- #[doc = "Bit 13 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 13 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set13(&self) -> SET13R {
let bits = {
const MASK: bool = true;
@@ -19430,8 +18428,7 @@ pub mod sct {
};
SET13R { bits }
}
- #[doc = "Bit 14 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 14 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set14(&self) -> SET14R {
let bits = {
const MASK: bool = true;
@@ -19440,8 +18437,7 @@ pub mod sct {
};
SET14R { bits }
}
- #[doc = "Bit 15 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 15 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set15(&self) -> SET15R {
let bits = {
const MASK: bool = true;
@@ -19463,83 +18459,67 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 0 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set0(&mut self) -> _SET0W {
_SET0W { w: self }
}
- #[doc = "Bit 1 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 1 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set1(&mut self) -> _SET1W {
_SET1W { w: self }
}
- #[doc = "Bit 2 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 2 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set2(&mut self) -> _SET2W {
_SET2W { w: self }
}
- #[doc = "Bit 3 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 3 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set3(&mut self) -> _SET3W {
_SET3W { w: self }
}
- #[doc = "Bit 4 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 4 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set4(&mut self) -> _SET4W {
_SET4W { w: self }
}
- #[doc = "Bit 5 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 5 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set5(&mut self) -> _SET5W {
_SET5W { w: self }
}
- #[doc = "Bit 6 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 6 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set6(&mut self) -> _SET6W {
_SET6W { w: self }
}
- #[doc = "Bit 7 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set7(&mut self) -> _SET7W {
_SET7W { w: self }
}
- #[doc = "Bit 8 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set8(&mut self) -> _SET8W {
_SET8W { w: self }
}
- #[doc = "Bit 9 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set9(&mut self) -> _SET9W {
_SET9W { w: self }
}
- #[doc = "Bit 10 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set10(&mut self) -> _SET10W {
_SET10W { w: self }
}
- #[doc = "Bit 11 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 11 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set11(&mut self) -> _SET11W {
_SET11W { w: self }
}
- #[doc = "Bit 12 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 12 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set12(&mut self) -> _SET12W {
_SET12W { w: self }
}
- #[doc = "Bit 13 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 13 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set13(&mut self) -> _SET13W {
_SET13W { w: self }
}
- #[doc = "Bit 14 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 14 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set14(&mut self) -> _SET14W {
_SET14W { w: self }
}
- #[doc = "Bit 15 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 15 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn set15(&mut self) -> _SET15W {
_SET15W { w: self }
}
@@ -20305,8 +19285,7 @@ pub mod sct {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 0 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr0(&self) -> CLR0R {
let bits = {
const MASK: bool = true;
@@ -20315,8 +19294,7 @@ pub mod sct {
};
CLR0R { bits }
}
- #[doc = "Bit 1 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 1 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr1(&self) -> CLR1R {
let bits = {
const MASK: bool = true;
@@ -20325,8 +19303,7 @@ pub mod sct {
};
CLR1R { bits }
}
- #[doc = "Bit 2 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 2 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr2(&self) -> CLR2R {
let bits = {
const MASK: bool = true;
@@ -20335,8 +19312,7 @@ pub mod sct {
};
CLR2R { bits }
}
- #[doc = "Bit 3 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 3 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr3(&self) -> CLR3R {
let bits = {
const MASK: bool = true;
@@ -20345,8 +19321,7 @@ pub mod sct {
};
CLR3R { bits }
}
- #[doc = "Bit 4 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 4 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr4(&self) -> CLR4R {
let bits = {
const MASK: bool = true;
@@ -20355,8 +19330,7 @@ pub mod sct {
};
CLR4R { bits }
}
- #[doc = "Bit 5 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 5 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr5(&self) -> CLR5R {
let bits = {
const MASK: bool = true;
@@ -20365,8 +19339,7 @@ pub mod sct {
};
CLR5R { bits }
}
- #[doc = "Bit 6 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 6 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr6(&self) -> CLR6R {
let bits = {
const MASK: bool = true;
@@ -20375,8 +19348,7 @@ pub mod sct {
};
CLR6R { bits }
}
- #[doc = "Bit 7 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr7(&self) -> CLR7R {
let bits = {
const MASK: bool = true;
@@ -20385,8 +19357,7 @@ pub mod sct {
};
CLR7R { bits }
}
- #[doc = "Bit 8 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr8(&self) -> CLR8R {
let bits = {
const MASK: bool = true;
@@ -20395,8 +19366,7 @@ pub mod sct {
};
CLR8R { bits }
}
- #[doc = "Bit 9 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr9(&self) -> CLR9R {
let bits = {
const MASK: bool = true;
@@ -20405,8 +19375,7 @@ pub mod sct {
};
CLR9R { bits }
}
- #[doc = "Bit 10 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr10(&self) -> CLR10R {
let bits = {
const MASK: bool = true;
@@ -20415,8 +19384,7 @@ pub mod sct {
};
CLR10R { bits }
}
- #[doc = "Bit 11 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 11 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr11(&self) -> CLR11R {
let bits = {
const MASK: bool = true;
@@ -20425,8 +19393,7 @@ pub mod sct {
};
CLR11R { bits }
}
- #[doc = "Bit 12 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 12 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr12(&self) -> CLR12R {
let bits = {
const MASK: bool = true;
@@ -20435,8 +19402,7 @@ pub mod sct {
};
CLR12R { bits }
}
- #[doc = "Bit 13 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 13 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr13(&self) -> CLR13R {
let bits = {
const MASK: bool = true;
@@ -20445,8 +19411,7 @@ pub mod sct {
};
CLR13R { bits }
}
- #[doc = "Bit 14 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 14 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr14(&self) -> CLR14R {
let bits = {
const MASK: bool = true;
@@ -20455,8 +19420,7 @@ pub mod sct {
};
CLR14R { bits }
}
- #[doc = "Bit 15 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 15 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr15(&self) -> CLR15R {
let bits = {
const MASK: bool = true;
@@ -20478,83 +19442,67 @@ pub mod sct {
self.bits = bits;
self
}
- #[doc = "Bit 0 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 0 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr0(&mut self) -> _CLR0W {
_CLR0W { w: self }
}
- #[doc = "Bit 1 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 1 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr1(&mut self) -> _CLR1W {
_CLR1W { w: self }
}
- #[doc = "Bit 2 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 2 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr2(&mut self) -> _CLR2W {
_CLR2W { w: self }
}
- #[doc = "Bit 3 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 3 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr3(&mut self) -> _CLR3W {
_CLR3W { w: self }
}
- #[doc = "Bit 4 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 4 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr4(&mut self) -> _CLR4W {
_CLR4W { w: self }
}
- #[doc = "Bit 5 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 5 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr5(&mut self) -> _CLR5W {
_CLR5W { w: self }
}
- #[doc = "Bit 6 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 6 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr6(&mut self) -> _CLR6W {
_CLR6W { w: self }
}
- #[doc = "Bit 7 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr7(&mut self) -> _CLR7W {
_CLR7W { w: self }
}
- #[doc = "Bit 8 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr8(&mut self) -> _CLR8W {
_CLR8W { w: self }
}
- #[doc = "Bit 9 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr9(&mut self) -> _CLR9W {
_CLR9W { w: self }
}
- #[doc = "Bit 10 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr10(&mut self) -> _CLR10W {
_CLR10W { w: self }
}
- #[doc = "Bit 11 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 11 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr11(&mut self) -> _CLR11W {
_CLR11W { w: self }
}
- #[doc = "Bit 12 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 12 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr12(&mut self) -> _CLR12W {
_CLR12W { w: self }
}
- #[doc = "Bit 13 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 13 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr13(&mut self) -> _CLR13W {
_CLR13W { w: self }
}
- #[doc = "Bit 14 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 14 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr14(&mut self) -> _CLR14W {
_CLR14W { w: self }
}
- #[doc = "Bit 15 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15."]
- #[inline(always)]
+ # [ doc = "Bit 15 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." ] # [ inline ( always ) ]
pub fn clr15(&mut self) -> _CLR15W {
_CLR15W { w: self }
}
@@ -20584,105 +19532,66 @@ pub mod gpdma {
pub inttcstat: INTTCSTAT,
#[doc = "0x08 - DMA Interrupt Terminal Count Request Clear Register"]
pub inttcclear: INTTCCLEAR,
- #[doc = "0x0c - DMA Interrupt Error Status Register"]
- pub interrstat: INTERRSTAT,
- #[doc = "0x10 - DMA Interrupt Error Clear Register"]
- pub interrclr: INTERRCLR,
+ #[doc = "0x0c - DMA Interrupt Error Status Register"] pub interrstat: INTERRSTAT,
+ #[doc = "0x10 - DMA Interrupt Error Clear Register"] pub interrclr: INTERRCLR,
#[doc = "0x14 - DMA Raw Interrupt Terminal Count Status Register"]
pub rawinttcstat: RAWINTTCSTAT,
- #[doc = "0x18 - DMA Raw Error Interrupt Status Register"]
- pub rawinterrstat: RAWINTERRSTAT,
+ #[doc = "0x18 - DMA Raw Error Interrupt Status Register"] pub rawinterrstat: RAWINTERRSTAT,
#[doc = "0x1c - DMA Enabled Channel Register"] pub enbldchns: ENBLDCHNS,
- #[doc = "0x20 - DMA Software Burst Request Register"]
- pub softbreq: SOFTBREQ,
- #[doc = "0x24 - DMA Software Single Request Register"]
- pub softsreq: SOFTSREQ,
- #[doc = "0x28 - DMA Software Last Burst Request Register"]
- pub softlbreq: SOFTLBREQ,
- #[doc = "0x2c - DMA Software Last Single Request Register"]
- pub softlsreq: SOFTLSREQ,
+ #[doc = "0x20 - DMA Software Burst Request Register"] pub softbreq: SOFTBREQ,
+ #[doc = "0x24 - DMA Software Single Request Register"] pub softsreq: SOFTSREQ,
+ #[doc = "0x28 - DMA Software Last Burst Request Register"] pub softlbreq: SOFTLBREQ,
+ #[doc = "0x2c - DMA Software Last Single Request Register"] pub softlsreq: SOFTLSREQ,
#[doc = "0x30 - DMA Configuration Register"] pub config: CONFIG,
#[doc = "0x34 - DMA Synchronization Register"] pub sync: SYNC,
_reserved0: [u8; 200usize],
- #[doc = "0x100 - DMA Channel Source Address Register"]
- pub c0srcaddr: CSRCADDR,
- #[doc = "0x104 - DMA Channel Destination Address Register"]
- pub c0destaddr: CDESTADDR,
- #[doc = "0x108 - DMA Channel Linked List Item Register"]
- pub c0lli: CLLI,
+ #[doc = "0x100 - DMA Channel Source Address Register"] pub c0srcaddr: CSRCADDR,
+ #[doc = "0x104 - DMA Channel Destination Address Register"] pub c0destaddr: CDESTADDR,
+ #[doc = "0x108 - DMA Channel Linked List Item Register"] pub c0lli: CLLI,
#[doc = "0x10c - DMA Channel Control Register"] pub c0control: CCONTROL,
- #[doc = "0x110 - DMA Channel Configuration Register"]
- pub c0config: CCONFIG,
+ #[doc = "0x110 - DMA Channel Configuration Register"] pub c0config: CCONFIG,
_reserved1: [u8; 12usize],
- #[doc = "0x120 - DMA Channel Source Address Register"]
- pub c1srcaddr: CSRCADDR,
- #[doc = "0x124 - DMA Channel Destination Address Register"]
- pub c1destaddr: CDESTADDR,
- #[doc = "0x128 - DMA Channel Linked List Item Register"]
- pub c1lli: CLLI,
+ #[doc = "0x120 - DMA Channel Source Address Register"] pub c1srcaddr: CSRCADDR,
+ #[doc = "0x124 - DMA Channel Destination Address Register"] pub c1destaddr: CDESTADDR,
+ #[doc = "0x128 - DMA Channel Linked List Item Register"] pub c1lli: CLLI,
#[doc = "0x12c - DMA Channel Control Register"] pub c1control: CCONTROL,
- #[doc = "0x130 - DMA Channel Configuration Register"]
- pub c1config: CCONFIG,
+ #[doc = "0x130 - DMA Channel Configuration Register"] pub c1config: CCONFIG,
_reserved2: [u8; 12usize],
- #[doc = "0x140 - DMA Channel Source Address Register"]
- pub c2srcaddr: CSRCADDR,
- #[doc = "0x144 - DMA Channel Destination Address Register"]
- pub c2destaddr: CDESTADDR,
- #[doc = "0x148 - DMA Channel Linked List Item Register"]
- pub c2lli: CLLI,
+ #[doc = "0x140 - DMA Channel Source Address Register"] pub c2srcaddr: CSRCADDR,
+ #[doc = "0x144 - DMA Channel Destination Address Register"] pub c2destaddr: CDESTADDR,
+ #[doc = "0x148 - DMA Channel Linked List Item Register"] pub c2lli: CLLI,
#[doc = "0x14c - DMA Channel Control Register"] pub c2control: CCONTROL,
- #[doc = "0x150 - DMA Channel Configuration Register"]
- pub c2config: CCONFIG,
+ #[doc = "0x150 - DMA Channel Configuration Register"] pub c2config: CCONFIG,
_reserved3: [u8; 12usize],
- #[doc = "0x160 - DMA Channel Source Address Register"]
- pub c3srcaddr: CSRCADDR,
- #[doc = "0x164 - DMA Channel Destination Address Register"]
- pub c3destaddr: CDESTADDR,
- #[doc = "0x168 - DMA Channel Linked List Item Register"]
- pub c3lli: CLLI,
+ #[doc = "0x160 - DMA Channel Source Address Register"] pub c3srcaddr: CSRCADDR,
+ #[doc = "0x164 - DMA Channel Destination Address Register"] pub c3destaddr: CDESTADDR,
+ #[doc = "0x168 - DMA Channel Linked List Item Register"] pub c3lli: CLLI,
#[doc = "0x16c - DMA Channel Control Register"] pub c3control: CCONTROL,
- #[doc = "0x170 - DMA Channel Configuration Register"]
- pub c3config: CCONFIG,
+ #[doc = "0x170 - DMA Channel Configuration Register"] pub c3config: CCONFIG,
_reserved4: [u8; 12usize],
- #[doc = "0x180 - DMA Channel Source Address Register"]
- pub c4srcaddr: CSRCADDR,
- #[doc = "0x184 - DMA Channel Destination Address Register"]
- pub c4destaddr: CDESTADDR,
- #[doc = "0x188 - DMA Channel Linked List Item Register"]
- pub c4lli: CLLI,
+ #[doc = "0x180 - DMA Channel Source Address Register"] pub c4srcaddr: CSRCADDR,
+ #[doc = "0x184 - DMA Channel Destination Address Register"] pub c4destaddr: CDESTADDR,
+ #[doc = "0x188 - DMA Channel Linked List Item Register"] pub c4lli: CLLI,
#[doc = "0x18c - DMA Channel Control Register"] pub c4control: CCONTROL,
- #[doc = "0x190 - DMA Channel Configuration Register"]
- pub c4config: CCONFIG,
+ #[doc = "0x190 - DMA Channel Configuration Register"] pub c4config: CCONFIG,
_reserved5: [u8; 12usize],
- #[doc = "0x1a0 - DMA Channel Source Address Register"]
- pub c5srcaddr: CSRCADDR,
- #[doc = "0x1a4 - DMA Channel Destination Address Register"]
- pub c5destaddr: CDESTADDR,
- #[doc = "0x1a8 - DMA Channel Linked List Item Register"]
- pub c5lli: CLLI,
+ #[doc = "0x1a0 - DMA Channel Source Address Register"] pub c5srcaddr: CSRCADDR,
+ #[doc = "0x1a4 - DMA Channel Destination Address Register"] pub c5destaddr: CDESTADDR,
+ #[doc = "0x1a8 - DMA Channel Linked List Item Register"] pub c5lli: CLLI,
#[doc = "0x1ac - DMA Channel Control Register"] pub c5control: CCONTROL,
- #[doc = "0x1b0 - DMA Channel Configuration Register"]
- pub c5config: CCONFIG,
+ #[doc = "0x1b0 - DMA Channel Configuration Register"] pub c5config: CCONFIG,
_reserved6: [u8; 12usize],
- #[doc = "0x1c0 - DMA Channel Source Address Register"]
- pub c6srcaddr: CSRCADDR,
- #[doc = "0x1c4 - DMA Channel Destination Address Register"]
- pub c6destaddr: CDESTADDR,
- #[doc = "0x1c8 - DMA Channel Linked List Item Register"]
- pub c6lli: CLLI,
+ #[doc = "0x1c0 - DMA Channel Source Address Register"] pub c6srcaddr: CSRCADDR,
+ #[doc = "0x1c4 - DMA Channel Destination Address Register"] pub c6destaddr: CDESTADDR,
+ #[doc = "0x1c8 - DMA Channel Linked List Item Register"] pub c6lli: CLLI,
#[doc = "0x1cc - DMA Channel Control Register"] pub c6control: CCONTROL,
- #[doc = "0x1d0 - DMA Channel Configuration Register"]
- pub c6config: CCONFIG,
+ #[doc = "0x1d0 - DMA Channel Configuration Register"] pub c6config: CCONFIG,
_reserved7: [u8; 12usize],
- #[doc = "0x1e0 - DMA Channel Source Address Register"]
- pub c7srcaddr: CSRCADDR,
- #[doc = "0x1e4 - DMA Channel Destination Address Register"]
- pub c7destaddr: CDESTADDR,
- #[doc = "0x1e8 - DMA Channel Linked List Item Register"]
- pub c7lli: CLLI,
+ #[doc = "0x1e0 - DMA Channel Source Address Register"] pub c7srcaddr: CSRCADDR,
+ #[doc = "0x1e4 - DMA Channel Destination Address Register"] pub c7destaddr: CDESTADDR,
+ #[doc = "0x1e8 - DMA Channel Linked List Item Register"] pub c7lli: CLLI,
#[doc = "0x1ec - DMA Channel Control Register"] pub c7control: CCONTROL,
- #[doc = "0x1f0 - DMA Channel Configuration Register"]
- pub c7config: CCONFIG,
+ #[doc = "0x1f0 - DMA Channel Configuration Register"] pub c7config: CCONFIG,
}
#[doc = "DMA Interrupt Status Register"]
pub struct INTSTAT {
@@ -20877,8 +19786,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat0(&self) -> INTSTAT0R {
let bits = {
const MASK: bool = true;
@@ -20887,8 +19795,7 @@ pub mod gpdma {
};
INTSTAT0R { bits }
}
- #[doc = "Bit 1 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat1(&self) -> INTSTAT1R {
let bits = {
const MASK: bool = true;
@@ -20897,8 +19804,7 @@ pub mod gpdma {
};
INTSTAT1R { bits }
}
- #[doc = "Bit 2 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat2(&self) -> INTSTAT2R {
let bits = {
const MASK: bool = true;
@@ -20907,8 +19813,7 @@ pub mod gpdma {
};
INTSTAT2R { bits }
}
- #[doc = "Bit 3 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat3(&self) -> INTSTAT3R {
let bits = {
const MASK: bool = true;
@@ -20917,8 +19822,7 @@ pub mod gpdma {
};
INTSTAT3R { bits }
}
- #[doc = "Bit 4 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat4(&self) -> INTSTAT4R {
let bits = {
const MASK: bool = true;
@@ -20927,8 +19831,7 @@ pub mod gpdma {
};
INTSTAT4R { bits }
}
- #[doc = "Bit 5 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat5(&self) -> INTSTAT5R {
let bits = {
const MASK: bool = true;
@@ -20937,8 +19840,7 @@ pub mod gpdma {
};
INTSTAT5R { bits }
}
- #[doc = "Bit 6 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat6(&self) -> INTSTAT6R {
let bits = {
const MASK: bool = true;
@@ -20947,8 +19849,7 @@ pub mod gpdma {
};
INTSTAT6R { bits }
}
- #[doc = "Bit 7 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." ] # [ inline ( always ) ]
pub fn intstat7(&self) -> INTSTAT7R {
let bits = {
const MASK: bool = true;
@@ -21152,8 +20053,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat0(&self) -> INTTCSTAT0R {
let bits = {
const MASK: bool = true;
@@ -21162,8 +20062,7 @@ pub mod gpdma {
};
INTTCSTAT0R { bits }
}
- #[doc = "Bit 1 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat1(&self) -> INTTCSTAT1R {
let bits = {
const MASK: bool = true;
@@ -21172,8 +20071,7 @@ pub mod gpdma {
};
INTTCSTAT1R { bits }
}
- #[doc = "Bit 2 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat2(&self) -> INTTCSTAT2R {
let bits = {
const MASK: bool = true;
@@ -21182,8 +20080,7 @@ pub mod gpdma {
};
INTTCSTAT2R { bits }
}
- #[doc = "Bit 3 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat3(&self) -> INTTCSTAT3R {
let bits = {
const MASK: bool = true;
@@ -21192,8 +20089,7 @@ pub mod gpdma {
};
INTTCSTAT3R { bits }
}
- #[doc = "Bit 4 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat4(&self) -> INTTCSTAT4R {
let bits = {
const MASK: bool = true;
@@ -21202,8 +20098,7 @@ pub mod gpdma {
};
INTTCSTAT4R { bits }
}
- #[doc = "Bit 5 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat5(&self) -> INTTCSTAT5R {
let bits = {
const MASK: bool = true;
@@ -21212,8 +20107,7 @@ pub mod gpdma {
};
INTTCSTAT5R { bits }
}
- #[doc = "Bit 6 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat6(&self) -> INTTCSTAT6R {
let bits = {
const MASK: bool = true;
@@ -21222,8 +20116,7 @@ pub mod gpdma {
};
INTTCSTAT6R { bits }
}
- #[doc = "Bit 7 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn inttcstat7(&self) -> INTTCSTAT7R {
let bits = {
const MASK: bool = true;
@@ -21452,43 +20345,35 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear0(&mut self) -> _INTTCCLEAR0W {
_INTTCCLEAR0W { w: self }
}
- #[doc = "Bit 1 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear1(&mut self) -> _INTTCCLEAR1W {
_INTTCCLEAR1W { w: self }
}
- #[doc = "Bit 2 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear2(&mut self) -> _INTTCCLEAR2W {
_INTTCCLEAR2W { w: self }
}
- #[doc = "Bit 3 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear3(&mut self) -> _INTTCCLEAR3W {
_INTTCCLEAR3W { w: self }
}
- #[doc = "Bit 4 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear4(&mut self) -> _INTTCCLEAR4W {
_INTTCCLEAR4W { w: self }
}
- #[doc = "Bit 5 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear5(&mut self) -> _INTTCCLEAR5W {
_INTTCCLEAR5W { w: self }
}
- #[doc = "Bit 6 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear6(&mut self) -> _INTTCCLEAR6W {
_INTTCCLEAR6W { w: self }
}
- #[doc = "Bit 7 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." ] # [ inline ( always ) ]
pub fn inttcclear7(&mut self) -> _INTTCCLEAR7W {
_INTTCCLEAR7W { w: self }
}
@@ -21687,8 +20572,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat0(&self) -> INTERRSTAT0R {
let bits = {
const MASK: bool = true;
@@ -21697,8 +20581,7 @@ pub mod gpdma {
};
INTERRSTAT0R { bits }
}
- #[doc = "Bit 1 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat1(&self) -> INTERRSTAT1R {
let bits = {
const MASK: bool = true;
@@ -21707,8 +20590,7 @@ pub mod gpdma {
};
INTERRSTAT1R { bits }
}
- #[doc = "Bit 2 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat2(&self) -> INTERRSTAT2R {
let bits = {
const MASK: bool = true;
@@ -21717,8 +20599,7 @@ pub mod gpdma {
};
INTERRSTAT2R { bits }
}
- #[doc = "Bit 3 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat3(&self) -> INTERRSTAT3R {
let bits = {
const MASK: bool = true;
@@ -21727,8 +20608,7 @@ pub mod gpdma {
};
INTERRSTAT3R { bits }
}
- #[doc = "Bit 4 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat4(&self) -> INTERRSTAT4R {
let bits = {
const MASK: bool = true;
@@ -21737,8 +20617,7 @@ pub mod gpdma {
};
INTERRSTAT4R { bits }
}
- #[doc = "Bit 5 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat5(&self) -> INTERRSTAT5R {
let bits = {
const MASK: bool = true;
@@ -21747,8 +20626,7 @@ pub mod gpdma {
};
INTERRSTAT5R { bits }
}
- #[doc = "Bit 6 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat6(&self) -> INTERRSTAT6R {
let bits = {
const MASK: bool = true;
@@ -21757,8 +20635,7 @@ pub mod gpdma {
};
INTERRSTAT6R { bits }
}
- #[doc = "Bit 7 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn interrstat7(&self) -> INTERRSTAT7R {
let bits = {
const MASK: bool = true;
@@ -21987,43 +20864,35 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr0(&mut self) -> _INTERRCLR0W {
_INTERRCLR0W { w: self }
}
- #[doc = "Bit 1 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr1(&mut self) -> _INTERRCLR1W {
_INTERRCLR1W { w: self }
}
- #[doc = "Bit 2 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr2(&mut self) -> _INTERRCLR2W {
_INTERRCLR2W { w: self }
}
- #[doc = "Bit 3 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr3(&mut self) -> _INTERRCLR3W {
_INTERRCLR3W { w: self }
}
- #[doc = "Bit 4 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr4(&mut self) -> _INTERRCLR4W {
_INTERRCLR4W { w: self }
}
- #[doc = "Bit 5 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr5(&mut self) -> _INTERRCLR5W {
_INTERRCLR5W { w: self }
}
- #[doc = "Bit 6 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr6(&mut self) -> _INTERRCLR6W {
_INTERRCLR6W { w: self }
}
- #[doc = "Bit 7 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." ] # [ inline ( always ) ]
pub fn interrclr7(&mut self) -> _INTERRCLR7W {
_INTERRCLR7W { w: self }
}
@@ -22222,8 +21091,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat0(&self) -> RAWINTTCSTAT0R {
let bits = {
const MASK: bool = true;
@@ -22232,8 +21100,7 @@ pub mod gpdma {
};
RAWINTTCSTAT0R { bits }
}
- #[doc = "Bit 1 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat1(&self) -> RAWINTTCSTAT1R {
let bits = {
const MASK: bool = true;
@@ -22242,8 +21109,7 @@ pub mod gpdma {
};
RAWINTTCSTAT1R { bits }
}
- #[doc = "Bit 2 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat2(&self) -> RAWINTTCSTAT2R {
let bits = {
const MASK: bool = true;
@@ -22252,8 +21118,7 @@ pub mod gpdma {
};
RAWINTTCSTAT2R { bits }
}
- #[doc = "Bit 3 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat3(&self) -> RAWINTTCSTAT3R {
let bits = {
const MASK: bool = true;
@@ -22262,8 +21127,7 @@ pub mod gpdma {
};
RAWINTTCSTAT3R { bits }
}
- #[doc = "Bit 4 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat4(&self) -> RAWINTTCSTAT4R {
let bits = {
const MASK: bool = true;
@@ -22272,8 +21136,7 @@ pub mod gpdma {
};
RAWINTTCSTAT4R { bits }
}
- #[doc = "Bit 5 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat5(&self) -> RAWINTTCSTAT5R {
let bits = {
const MASK: bool = true;
@@ -22282,8 +21145,7 @@ pub mod gpdma {
};
RAWINTTCSTAT5R { bits }
}
- #[doc = "Bit 6 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat6(&self) -> RAWINTTCSTAT6R {
let bits = {
const MASK: bool = true;
@@ -22292,8 +21154,7 @@ pub mod gpdma {
};
RAWINTTCSTAT6R { bits }
}
- #[doc = "Bit 7 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." ] # [ inline ( always ) ]
pub fn rawinttcstat7(&self) -> RAWINTTCSTAT7R {
let bits = {
const MASK: bool = true;
@@ -22497,8 +21358,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat0(&self) -> RAWINTERRSTAT0R {
let bits = {
const MASK: bool = true;
@@ -22507,8 +21367,7 @@ pub mod gpdma {
};
RAWINTERRSTAT0R { bits }
}
- #[doc = "Bit 1 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat1(&self) -> RAWINTERRSTAT1R {
let bits = {
const MASK: bool = true;
@@ -22517,8 +21376,7 @@ pub mod gpdma {
};
RAWINTERRSTAT1R { bits }
}
- #[doc = "Bit 2 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat2(&self) -> RAWINTERRSTAT2R {
let bits = {
const MASK: bool = true;
@@ -22527,8 +21385,7 @@ pub mod gpdma {
};
RAWINTERRSTAT2R { bits }
}
- #[doc = "Bit 3 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat3(&self) -> RAWINTERRSTAT3R {
let bits = {
const MASK: bool = true;
@@ -22537,8 +21394,7 @@ pub mod gpdma {
};
RAWINTERRSTAT3R { bits }
}
- #[doc = "Bit 4 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat4(&self) -> RAWINTERRSTAT4R {
let bits = {
const MASK: bool = true;
@@ -22547,8 +21403,7 @@ pub mod gpdma {
};
RAWINTERRSTAT4R { bits }
}
- #[doc = "Bit 5 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat5(&self) -> RAWINTERRSTAT5R {
let bits = {
const MASK: bool = true;
@@ -22557,8 +21412,7 @@ pub mod gpdma {
};
RAWINTERRSTAT5R { bits }
}
- #[doc = "Bit 6 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat6(&self) -> RAWINTERRSTAT6R {
let bits = {
const MASK: bool = true;
@@ -22567,8 +21421,7 @@ pub mod gpdma {
};
RAWINTERRSTAT6R { bits }
}
- #[doc = "Bit 7 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." ] # [ inline ( always ) ]
pub fn rawinterrstat7(&self) -> RAWINTERRSTAT7R {
let bits = {
const MASK: bool = true;
@@ -22772,8 +21625,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels0(&self) -> ENABLEDCHANNELS0R {
let bits = {
const MASK: bool = true;
@@ -22782,8 +21634,7 @@ pub mod gpdma {
};
ENABLEDCHANNELS0R { bits }
}
- #[doc = "Bit 1 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels1(&self) -> ENABLEDCHANNELS1R {
let bits = {
const MASK: bool = true;
@@ -22792,8 +21643,7 @@ pub mod gpdma {
};
ENABLEDCHANNELS1R { bits }
}
- #[doc = "Bit 2 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels2(&self) -> ENABLEDCHANNELS2R {
let bits = {
const MASK: bool = true;
@@ -22802,8 +21652,7 @@ pub mod gpdma {
};
ENABLEDCHANNELS2R { bits }
}
- #[doc = "Bit 3 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels3(&self) -> ENABLEDCHANNELS3R {
let bits = {
const MASK: bool = true;
@@ -22812,8 +21661,7 @@ pub mod gpdma {
};
ENABLEDCHANNELS3R { bits }
}
- #[doc = "Bit 4 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels4(&self) -> ENABLEDCHANNELS4R {
let bits = {
const MASK: bool = true;
@@ -22822,8 +21670,7 @@ pub mod gpdma {
};
ENABLEDCHANNELS4R { bits }
}
- #[doc = "Bit 5 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels5(&self) -> ENABLEDCHANNELS5R {
let bits = {
const MASK: bool = true;
@@ -22832,8 +21679,7 @@ pub mod gpdma {
};
ENABLEDCHANNELS5R { bits }
}
- #[doc = "Bit 6 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels6(&self) -> ENABLEDCHANNELS6R {
let bits = {
const MASK: bool = true;
@@ -22842,8 +21688,7 @@ pub mod gpdma {
};
ENABLEDCHANNELS6R { bits }
}
- #[doc = "Bit 7 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." ] # [ inline ( always ) ]
pub fn enabledchannels7(&self) -> ENABLEDCHANNELS7R {
let bits = {
const MASK: bool = true;
@@ -23614,8 +22459,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq0(&self) -> SOFTBREQ0R {
let bits = {
const MASK: bool = true;
@@ -23624,8 +22468,7 @@ pub mod gpdma {
};
SOFTBREQ0R { bits }
}
- #[doc = "Bit 1 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq1(&self) -> SOFTBREQ1R {
let bits = {
const MASK: bool = true;
@@ -23634,8 +22477,7 @@ pub mod gpdma {
};
SOFTBREQ1R { bits }
}
- #[doc = "Bit 2 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq2(&self) -> SOFTBREQ2R {
let bits = {
const MASK: bool = true;
@@ -23644,8 +22486,7 @@ pub mod gpdma {
};
SOFTBREQ2R { bits }
}
- #[doc = "Bit 3 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq3(&self) -> SOFTBREQ3R {
let bits = {
const MASK: bool = true;
@@ -23654,8 +22495,7 @@ pub mod gpdma {
};
SOFTBREQ3R { bits }
}
- #[doc = "Bit 4 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq4(&self) -> SOFTBREQ4R {
let bits = {
const MASK: bool = true;
@@ -23664,8 +22504,7 @@ pub mod gpdma {
};
SOFTBREQ4R { bits }
}
- #[doc = "Bit 5 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq5(&self) -> SOFTBREQ5R {
let bits = {
const MASK: bool = true;
@@ -23674,8 +22513,7 @@ pub mod gpdma {
};
SOFTBREQ5R { bits }
}
- #[doc = "Bit 6 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq6(&self) -> SOFTBREQ6R {
let bits = {
const MASK: bool = true;
@@ -23684,8 +22522,7 @@ pub mod gpdma {
};
SOFTBREQ6R { bits }
}
- #[doc = "Bit 7 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq7(&self) -> SOFTBREQ7R {
let bits = {
const MASK: bool = true;
@@ -23694,8 +22531,7 @@ pub mod gpdma {
};
SOFTBREQ7R { bits }
}
- #[doc = "Bit 8 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq8(&self) -> SOFTBREQ8R {
let bits = {
const MASK: bool = true;
@@ -23704,8 +22540,7 @@ pub mod gpdma {
};
SOFTBREQ8R { bits }
}
- #[doc = "Bit 9 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq9(&self) -> SOFTBREQ9R {
let bits = {
const MASK: bool = true;
@@ -23714,8 +22549,7 @@ pub mod gpdma {
};
SOFTBREQ9R { bits }
}
- #[doc = "Bit 10 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq10(&self) -> SOFTBREQ10R {
let bits = {
const MASK: bool = true;
@@ -23724,8 +22558,7 @@ pub mod gpdma {
};
SOFTBREQ10R { bits }
}
- #[doc = "Bit 11 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq11(&self) -> SOFTBREQ11R {
let bits = {
const MASK: bool = true;
@@ -23734,8 +22567,7 @@ pub mod gpdma {
};
SOFTBREQ11R { bits }
}
- #[doc = "Bit 12 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq12(&self) -> SOFTBREQ12R {
let bits = {
const MASK: bool = true;
@@ -23744,8 +22576,7 @@ pub mod gpdma {
};
SOFTBREQ12R { bits }
}
- #[doc = "Bit 13 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq13(&self) -> SOFTBREQ13R {
let bits = {
const MASK: bool = true;
@@ -23754,8 +22585,7 @@ pub mod gpdma {
};
SOFTBREQ13R { bits }
}
- #[doc = "Bit 14 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq14(&self) -> SOFTBREQ14R {
let bits = {
const MASK: bool = true;
@@ -23764,8 +22594,7 @@ pub mod gpdma {
};
SOFTBREQ14R { bits }
}
- #[doc = "Bit 15 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq15(&self) -> SOFTBREQ15R {
let bits = {
const MASK: bool = true;
@@ -23787,83 +22616,67 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq0(&mut self) -> _SOFTBREQ0W {
_SOFTBREQ0W { w: self }
}
- #[doc = "Bit 1 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq1(&mut self) -> _SOFTBREQ1W {
_SOFTBREQ1W { w: self }
}
- #[doc = "Bit 2 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq2(&mut self) -> _SOFTBREQ2W {
_SOFTBREQ2W { w: self }
}
- #[doc = "Bit 3 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq3(&mut self) -> _SOFTBREQ3W {
_SOFTBREQ3W { w: self }
}
- #[doc = "Bit 4 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq4(&mut self) -> _SOFTBREQ4W {
_SOFTBREQ4W { w: self }
}
- #[doc = "Bit 5 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq5(&mut self) -> _SOFTBREQ5W {
_SOFTBREQ5W { w: self }
}
- #[doc = "Bit 6 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq6(&mut self) -> _SOFTBREQ6W {
_SOFTBREQ6W { w: self }
}
- #[doc = "Bit 7 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq7(&mut self) -> _SOFTBREQ7W {
_SOFTBREQ7W { w: self }
}
- #[doc = "Bit 8 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq8(&mut self) -> _SOFTBREQ8W {
_SOFTBREQ8W { w: self }
}
- #[doc = "Bit 9 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq9(&mut self) -> _SOFTBREQ9W {
_SOFTBREQ9W { w: self }
}
- #[doc = "Bit 10 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq10(&mut self) -> _SOFTBREQ10W {
_SOFTBREQ10W { w: self }
}
- #[doc = "Bit 11 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq11(&mut self) -> _SOFTBREQ11W {
_SOFTBREQ11W { w: self }
}
- #[doc = "Bit 12 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq12(&mut self) -> _SOFTBREQ12W {
_SOFTBREQ12W { w: self }
}
- #[doc = "Bit 13 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq13(&mut self) -> _SOFTBREQ13W {
_SOFTBREQ13W { w: self }
}
- #[doc = "Bit 14 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq14(&mut self) -> _SOFTBREQ14W {
_SOFTBREQ14W { w: self }
}
- #[doc = "Bit 15 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softbreq15(&mut self) -> _SOFTBREQ15W {
_SOFTBREQ15W { w: self }
}
@@ -24629,8 +23442,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq0(&self) -> SOFTSREQ0R {
let bits = {
const MASK: bool = true;
@@ -24639,8 +23451,7 @@ pub mod gpdma {
};
SOFTSREQ0R { bits }
}
- #[doc = "Bit 1 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq1(&self) -> SOFTSREQ1R {
let bits = {
const MASK: bool = true;
@@ -24649,8 +23460,7 @@ pub mod gpdma {
};
SOFTSREQ1R { bits }
}
- #[doc = "Bit 2 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq2(&self) -> SOFTSREQ2R {
let bits = {
const MASK: bool = true;
@@ -24659,8 +23469,7 @@ pub mod gpdma {
};
SOFTSREQ2R { bits }
}
- #[doc = "Bit 3 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq3(&self) -> SOFTSREQ3R {
let bits = {
const MASK: bool = true;
@@ -24669,8 +23478,7 @@ pub mod gpdma {
};
SOFTSREQ3R { bits }
}
- #[doc = "Bit 4 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq4(&self) -> SOFTSREQ4R {
let bits = {
const MASK: bool = true;
@@ -24679,8 +23487,7 @@ pub mod gpdma {
};
SOFTSREQ4R { bits }
}
- #[doc = "Bit 5 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq5(&self) -> SOFTSREQ5R {
let bits = {
const MASK: bool = true;
@@ -24689,8 +23496,7 @@ pub mod gpdma {
};
SOFTSREQ5R { bits }
}
- #[doc = "Bit 6 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq6(&self) -> SOFTSREQ6R {
let bits = {
const MASK: bool = true;
@@ -24699,8 +23505,7 @@ pub mod gpdma {
};
SOFTSREQ6R { bits }
}
- #[doc = "Bit 7 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq7(&self) -> SOFTSREQ7R {
let bits = {
const MASK: bool = true;
@@ -24709,8 +23514,7 @@ pub mod gpdma {
};
SOFTSREQ7R { bits }
}
- #[doc = "Bit 8 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq8(&self) -> SOFTSREQ8R {
let bits = {
const MASK: bool = true;
@@ -24719,8 +23523,7 @@ pub mod gpdma {
};
SOFTSREQ8R { bits }
}
- #[doc = "Bit 9 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq9(&self) -> SOFTSREQ9R {
let bits = {
const MASK: bool = true;
@@ -24729,8 +23532,7 @@ pub mod gpdma {
};
SOFTSREQ9R { bits }
}
- #[doc = "Bit 10 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq10(&self) -> SOFTSREQ10R {
let bits = {
const MASK: bool = true;
@@ -24739,8 +23541,7 @@ pub mod gpdma {
};
SOFTSREQ10R { bits }
}
- #[doc = "Bit 11 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq11(&self) -> SOFTSREQ11R {
let bits = {
const MASK: bool = true;
@@ -24749,8 +23550,7 @@ pub mod gpdma {
};
SOFTSREQ11R { bits }
}
- #[doc = "Bit 12 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq12(&self) -> SOFTSREQ12R {
let bits = {
const MASK: bool = true;
@@ -24759,8 +23559,7 @@ pub mod gpdma {
};
SOFTSREQ12R { bits }
}
- #[doc = "Bit 13 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq13(&self) -> SOFTSREQ13R {
let bits = {
const MASK: bool = true;
@@ -24769,8 +23568,7 @@ pub mod gpdma {
};
SOFTSREQ13R { bits }
}
- #[doc = "Bit 14 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq14(&self) -> SOFTSREQ14R {
let bits = {
const MASK: bool = true;
@@ -24779,8 +23577,7 @@ pub mod gpdma {
};
SOFTSREQ14R { bits }
}
- #[doc = "Bit 15 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq15(&self) -> SOFTSREQ15R {
let bits = {
const MASK: bool = true;
@@ -24802,83 +23599,67 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq0(&mut self) -> _SOFTSREQ0W {
_SOFTSREQ0W { w: self }
}
- #[doc = "Bit 1 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq1(&mut self) -> _SOFTSREQ1W {
_SOFTSREQ1W { w: self }
}
- #[doc = "Bit 2 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq2(&mut self) -> _SOFTSREQ2W {
_SOFTSREQ2W { w: self }
}
- #[doc = "Bit 3 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq3(&mut self) -> _SOFTSREQ3W {
_SOFTSREQ3W { w: self }
}
- #[doc = "Bit 4 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq4(&mut self) -> _SOFTSREQ4W {
_SOFTSREQ4W { w: self }
}
- #[doc = "Bit 5 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq5(&mut self) -> _SOFTSREQ5W {
_SOFTSREQ5W { w: self }
}
- #[doc = "Bit 6 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq6(&mut self) -> _SOFTSREQ6W {
_SOFTSREQ6W { w: self }
}
- #[doc = "Bit 7 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq7(&mut self) -> _SOFTSREQ7W {
_SOFTSREQ7W { w: self }
}
- #[doc = "Bit 8 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq8(&mut self) -> _SOFTSREQ8W {
_SOFTSREQ8W { w: self }
}
- #[doc = "Bit 9 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq9(&mut self) -> _SOFTSREQ9W {
_SOFTSREQ9W { w: self }
}
- #[doc = "Bit 10 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq10(&mut self) -> _SOFTSREQ10W {
_SOFTSREQ10W { w: self }
}
- #[doc = "Bit 11 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq11(&mut self) -> _SOFTSREQ11W {
_SOFTSREQ11W { w: self }
}
- #[doc = "Bit 12 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq12(&mut self) -> _SOFTSREQ12W {
_SOFTSREQ12W { w: self }
}
- #[doc = "Bit 13 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq13(&mut self) -> _SOFTSREQ13W {
_SOFTSREQ13W { w: self }
}
- #[doc = "Bit 14 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq14(&mut self) -> _SOFTSREQ14W {
_SOFTSREQ14W { w: self }
}
- #[doc = "Bit 15 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softsreq15(&mut self) -> _SOFTSREQ15W {
_SOFTSREQ15W { w: self }
}
@@ -25644,8 +24425,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq0(&self) -> SOFTLBREQ0R {
let bits = {
const MASK: bool = true;
@@ -25654,8 +24434,7 @@ pub mod gpdma {
};
SOFTLBREQ0R { bits }
}
- #[doc = "Bit 1 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq1(&self) -> SOFTLBREQ1R {
let bits = {
const MASK: bool = true;
@@ -25664,8 +24443,7 @@ pub mod gpdma {
};
SOFTLBREQ1R { bits }
}
- #[doc = "Bit 2 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq2(&self) -> SOFTLBREQ2R {
let bits = {
const MASK: bool = true;
@@ -25674,8 +24452,7 @@ pub mod gpdma {
};
SOFTLBREQ2R { bits }
}
- #[doc = "Bit 3 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq3(&self) -> SOFTLBREQ3R {
let bits = {
const MASK: bool = true;
@@ -25684,8 +24461,7 @@ pub mod gpdma {
};
SOFTLBREQ3R { bits }
}
- #[doc = "Bit 4 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq4(&self) -> SOFTLBREQ4R {
let bits = {
const MASK: bool = true;
@@ -25694,8 +24470,7 @@ pub mod gpdma {
};
SOFTLBREQ4R { bits }
}
- #[doc = "Bit 5 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq5(&self) -> SOFTLBREQ5R {
let bits = {
const MASK: bool = true;
@@ -25704,8 +24479,7 @@ pub mod gpdma {
};
SOFTLBREQ5R { bits }
}
- #[doc = "Bit 6 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq6(&self) -> SOFTLBREQ6R {
let bits = {
const MASK: bool = true;
@@ -25714,8 +24488,7 @@ pub mod gpdma {
};
SOFTLBREQ6R { bits }
}
- #[doc = "Bit 7 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq7(&self) -> SOFTLBREQ7R {
let bits = {
const MASK: bool = true;
@@ -25724,8 +24497,7 @@ pub mod gpdma {
};
SOFTLBREQ7R { bits }
}
- #[doc = "Bit 8 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq8(&self) -> SOFTLBREQ8R {
let bits = {
const MASK: bool = true;
@@ -25734,8 +24506,7 @@ pub mod gpdma {
};
SOFTLBREQ8R { bits }
}
- #[doc = "Bit 9 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq9(&self) -> SOFTLBREQ9R {
let bits = {
const MASK: bool = true;
@@ -25744,8 +24515,7 @@ pub mod gpdma {
};
SOFTLBREQ9R { bits }
}
- #[doc = "Bit 10 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq10(&self) -> SOFTLBREQ10R {
let bits = {
const MASK: bool = true;
@@ -25754,8 +24524,7 @@ pub mod gpdma {
};
SOFTLBREQ10R { bits }
}
- #[doc = "Bit 11 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq11(&self) -> SOFTLBREQ11R {
let bits = {
const MASK: bool = true;
@@ -25764,8 +24533,7 @@ pub mod gpdma {
};
SOFTLBREQ11R { bits }
}
- #[doc = "Bit 12 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq12(&self) -> SOFTLBREQ12R {
let bits = {
const MASK: bool = true;
@@ -25774,8 +24542,7 @@ pub mod gpdma {
};
SOFTLBREQ12R { bits }
}
- #[doc = "Bit 13 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq13(&self) -> SOFTLBREQ13R {
let bits = {
const MASK: bool = true;
@@ -25784,8 +24551,7 @@ pub mod gpdma {
};
SOFTLBREQ13R { bits }
}
- #[doc = "Bit 14 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq14(&self) -> SOFTLBREQ14R {
let bits = {
const MASK: bool = true;
@@ -25794,8 +24560,7 @@ pub mod gpdma {
};
SOFTLBREQ14R { bits }
}
- #[doc = "Bit 15 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq15(&self) -> SOFTLBREQ15R {
let bits = {
const MASK: bool = true;
@@ -25817,83 +24582,67 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq0(&mut self) -> _SOFTLBREQ0W {
_SOFTLBREQ0W { w: self }
}
- #[doc = "Bit 1 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq1(&mut self) -> _SOFTLBREQ1W {
_SOFTLBREQ1W { w: self }
}
- #[doc = "Bit 2 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq2(&mut self) -> _SOFTLBREQ2W {
_SOFTLBREQ2W { w: self }
}
- #[doc = "Bit 3 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq3(&mut self) -> _SOFTLBREQ3W {
_SOFTLBREQ3W { w: self }
}
- #[doc = "Bit 4 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq4(&mut self) -> _SOFTLBREQ4W {
_SOFTLBREQ4W { w: self }
}
- #[doc = "Bit 5 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq5(&mut self) -> _SOFTLBREQ5W {
_SOFTLBREQ5W { w: self }
}
- #[doc = "Bit 6 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq6(&mut self) -> _SOFTLBREQ6W {
_SOFTLBREQ6W { w: self }
}
- #[doc = "Bit 7 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq7(&mut self) -> _SOFTLBREQ7W {
_SOFTLBREQ7W { w: self }
}
- #[doc = "Bit 8 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq8(&mut self) -> _SOFTLBREQ8W {
_SOFTLBREQ8W { w: self }
}
- #[doc = "Bit 9 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq9(&mut self) -> _SOFTLBREQ9W {
_SOFTLBREQ9W { w: self }
}
- #[doc = "Bit 10 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq10(&mut self) -> _SOFTLBREQ10W {
_SOFTLBREQ10W { w: self }
}
- #[doc = "Bit 11 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq11(&mut self) -> _SOFTLBREQ11W {
_SOFTLBREQ11W { w: self }
}
- #[doc = "Bit 12 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq12(&mut self) -> _SOFTLBREQ12W {
_SOFTLBREQ12W { w: self }
}
- #[doc = "Bit 13 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq13(&mut self) -> _SOFTLBREQ13W {
_SOFTLBREQ13W { w: self }
}
- #[doc = "Bit 14 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq14(&mut self) -> _SOFTLBREQ14W {
_SOFTLBREQ14W { w: self }
}
- #[doc = "Bit 15 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlbreq15(&mut self) -> _SOFTLBREQ15W {
_SOFTLBREQ15W { w: self }
}
@@ -26659,8 +25408,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq0(&self) -> SOFTLSREQ0R {
let bits = {
const MASK: bool = true;
@@ -26669,8 +25417,7 @@ pub mod gpdma {
};
SOFTLSREQ0R { bits }
}
- #[doc = "Bit 1 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq1(&self) -> SOFTLSREQ1R {
let bits = {
const MASK: bool = true;
@@ -26679,8 +25426,7 @@ pub mod gpdma {
};
SOFTLSREQ1R { bits }
}
- #[doc = "Bit 2 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq2(&self) -> SOFTLSREQ2R {
let bits = {
const MASK: bool = true;
@@ -26689,8 +25435,7 @@ pub mod gpdma {
};
SOFTLSREQ2R { bits }
}
- #[doc = "Bit 3 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq3(&self) -> SOFTLSREQ3R {
let bits = {
const MASK: bool = true;
@@ -26699,8 +25444,7 @@ pub mod gpdma {
};
SOFTLSREQ3R { bits }
}
- #[doc = "Bit 4 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq4(&self) -> SOFTLSREQ4R {
let bits = {
const MASK: bool = true;
@@ -26709,8 +25453,7 @@ pub mod gpdma {
};
SOFTLSREQ4R { bits }
}
- #[doc = "Bit 5 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq5(&self) -> SOFTLSREQ5R {
let bits = {
const MASK: bool = true;
@@ -26719,8 +25462,7 @@ pub mod gpdma {
};
SOFTLSREQ5R { bits }
}
- #[doc = "Bit 6 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq6(&self) -> SOFTLSREQ6R {
let bits = {
const MASK: bool = true;
@@ -26729,8 +25471,7 @@ pub mod gpdma {
};
SOFTLSREQ6R { bits }
}
- #[doc = "Bit 7 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq7(&self) -> SOFTLSREQ7R {
let bits = {
const MASK: bool = true;
@@ -26739,8 +25480,7 @@ pub mod gpdma {
};
SOFTLSREQ7R { bits }
}
- #[doc = "Bit 8 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq8(&self) -> SOFTLSREQ8R {
let bits = {
const MASK: bool = true;
@@ -26749,8 +25489,7 @@ pub mod gpdma {
};
SOFTLSREQ8R { bits }
}
- #[doc = "Bit 9 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq9(&self) -> SOFTLSREQ9R {
let bits = {
const MASK: bool = true;
@@ -26759,8 +25498,7 @@ pub mod gpdma {
};
SOFTLSREQ9R { bits }
}
- #[doc = "Bit 10 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq10(&self) -> SOFTLSREQ10R {
let bits = {
const MASK: bool = true;
@@ -26769,8 +25507,7 @@ pub mod gpdma {
};
SOFTLSREQ10R { bits }
}
- #[doc = "Bit 11 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq11(&self) -> SOFTLSREQ11R {
let bits = {
const MASK: bool = true;
@@ -26779,8 +25516,7 @@ pub mod gpdma {
};
SOFTLSREQ11R { bits }
}
- #[doc = "Bit 12 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq12(&self) -> SOFTLSREQ12R {
let bits = {
const MASK: bool = true;
@@ -26789,8 +25525,7 @@ pub mod gpdma {
};
SOFTLSREQ12R { bits }
}
- #[doc = "Bit 13 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq13(&self) -> SOFTLSREQ13R {
let bits = {
const MASK: bool = true;
@@ -26799,8 +25534,7 @@ pub mod gpdma {
};
SOFTLSREQ13R { bits }
}
- #[doc = "Bit 14 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq14(&self) -> SOFTLSREQ14R {
let bits = {
const MASK: bool = true;
@@ -26809,8 +25543,7 @@ pub mod gpdma {
};
SOFTLSREQ14R { bits }
}
- #[doc = "Bit 15 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq15(&self) -> SOFTLSREQ15R {
let bits = {
const MASK: bool = true;
@@ -26832,83 +25565,67 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq0(&mut self) -> _SOFTLSREQ0W {
_SOFTLSREQ0W { w: self }
}
- #[doc = "Bit 1 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq1(&mut self) -> _SOFTLSREQ1W {
_SOFTLSREQ1W { w: self }
}
- #[doc = "Bit 2 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq2(&mut self) -> _SOFTLSREQ2W {
_SOFTLSREQ2W { w: self }
}
- #[doc = "Bit 3 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq3(&mut self) -> _SOFTLSREQ3W {
_SOFTLSREQ3W { w: self }
}
- #[doc = "Bit 4 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq4(&mut self) -> _SOFTLSREQ4W {
_SOFTLSREQ4W { w: self }
}
- #[doc = "Bit 5 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq5(&mut self) -> _SOFTLSREQ5W {
_SOFTLSREQ5W { w: self }
}
- #[doc = "Bit 6 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq6(&mut self) -> _SOFTLSREQ6W {
_SOFTLSREQ6W { w: self }
}
- #[doc = "Bit 7 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq7(&mut self) -> _SOFTLSREQ7W {
_SOFTLSREQ7W { w: self }
}
- #[doc = "Bit 8 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq8(&mut self) -> _SOFTLSREQ8W {
_SOFTLSREQ8W { w: self }
}
- #[doc = "Bit 9 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq9(&mut self) -> _SOFTLSREQ9W {
_SOFTLSREQ9W { w: self }
}
- #[doc = "Bit 10 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq10(&mut self) -> _SOFTLSREQ10W {
_SOFTLSREQ10W { w: self }
}
- #[doc = "Bit 11 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq11(&mut self) -> _SOFTLSREQ11W {
_SOFTLSREQ11W { w: self }
}
- #[doc = "Bit 12 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq12(&mut self) -> _SOFTLSREQ12W {
_SOFTLSREQ12W { w: self }
}
- #[doc = "Bit 13 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq13(&mut self) -> _SOFTLSREQ13W {
_SOFTLSREQ13W { w: self }
}
- #[doc = "Bit 14 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq14(&mut self) -> _SOFTLSREQ14W {
_SOFTLSREQ14W { w: self }
}
- #[doc = "Bit 15 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." ] # [ inline ( always ) ]
pub fn softlsreq15(&mut self) -> _SOFTLSREQ15W {
_SOFTLSREQ15W { w: self }
}
@@ -28092,8 +26809,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync0(&self) -> DMACSYNC0R {
let bits = {
const MASK: bool = true;
@@ -28102,8 +26818,7 @@ pub mod gpdma {
};
DMACSYNC0R { bits }
}
- #[doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync1(&self) -> DMACSYNC1R {
let bits = {
const MASK: bool = true;
@@ -28112,8 +26827,7 @@ pub mod gpdma {
};
DMACSYNC1R { bits }
}
- #[doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync2(&self) -> DMACSYNC2R {
let bits = {
const MASK: bool = true;
@@ -28122,8 +26836,7 @@ pub mod gpdma {
};
DMACSYNC2R { bits }
}
- #[doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync3(&self) -> DMACSYNC3R {
let bits = {
const MASK: bool = true;
@@ -28132,8 +26845,7 @@ pub mod gpdma {
};
DMACSYNC3R { bits }
}
- #[doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync4(&self) -> DMACSYNC4R {
let bits = {
const MASK: bool = true;
@@ -28142,8 +26854,7 @@ pub mod gpdma {
};
DMACSYNC4R { bits }
}
- #[doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync5(&self) -> DMACSYNC5R {
let bits = {
const MASK: bool = true;
@@ -28152,8 +26863,7 @@ pub mod gpdma {
};
DMACSYNC5R { bits }
}
- #[doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync6(&self) -> DMACSYNC6R {
let bits = {
const MASK: bool = true;
@@ -28162,8 +26872,7 @@ pub mod gpdma {
};
DMACSYNC6R { bits }
}
- #[doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync7(&self) -> DMACSYNC7R {
let bits = {
const MASK: bool = true;
@@ -28172,8 +26881,7 @@ pub mod gpdma {
};
DMACSYNC7R { bits }
}
- #[doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync8(&self) -> DMACSYNC8R {
let bits = {
const MASK: bool = true;
@@ -28182,8 +26890,7 @@ pub mod gpdma {
};
DMACSYNC8R { bits }
}
- #[doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync9(&self) -> DMACSYNC9R {
let bits = {
const MASK: bool = true;
@@ -28192,8 +26899,7 @@ pub mod gpdma {
};
DMACSYNC9R { bits }
}
- #[doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync10(&self) -> DMACSYNC10R {
let bits = {
const MASK: bool = true;
@@ -28202,8 +26908,7 @@ pub mod gpdma {
};
DMACSYNC10R { bits }
}
- #[doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync11(&self) -> DMACSYNC11R {
let bits = {
const MASK: bool = true;
@@ -28212,8 +26917,7 @@ pub mod gpdma {
};
DMACSYNC11R { bits }
}
- #[doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync12(&self) -> DMACSYNC12R {
let bits = {
const MASK: bool = true;
@@ -28222,8 +26926,7 @@ pub mod gpdma {
};
DMACSYNC12R { bits }
}
- #[doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync13(&self) -> DMACSYNC13R {
let bits = {
const MASK: bool = true;
@@ -28232,8 +26935,7 @@ pub mod gpdma {
};
DMACSYNC13R { bits }
}
- #[doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync14(&self) -> DMACSYNC14R {
let bits = {
const MASK: bool = true;
@@ -28242,8 +26944,7 @@ pub mod gpdma {
};
DMACSYNC14R { bits }
}
- #[doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync15(&self) -> DMACSYNC15R {
let bits = {
const MASK: bool = true;
@@ -28265,83 +26966,67 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync0(&mut self) -> _DMACSYNC0W {
_DMACSYNC0W { w: self }
}
- #[doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync1(&mut self) -> _DMACSYNC1W {
_DMACSYNC1W { w: self }
}
- #[doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync2(&mut self) -> _DMACSYNC2W {
_DMACSYNC2W { w: self }
}
- #[doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync3(&mut self) -> _DMACSYNC3W {
_DMACSYNC3W { w: self }
}
- #[doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync4(&mut self) -> _DMACSYNC4W {
_DMACSYNC4W { w: self }
}
- #[doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync5(&mut self) -> _DMACSYNC5W {
_DMACSYNC5W { w: self }
}
- #[doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync6(&mut self) -> _DMACSYNC6W {
_DMACSYNC6W { w: self }
}
- #[doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync7(&mut self) -> _DMACSYNC7W {
_DMACSYNC7W { w: self }
}
- #[doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync8(&mut self) -> _DMACSYNC8W {
_DMACSYNC8W { w: self }
}
- #[doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync9(&mut self) -> _DMACSYNC9W {
_DMACSYNC9W { w: self }
}
- #[doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync10(&mut self) -> _DMACSYNC10W {
_DMACSYNC10W { w: self }
}
- #[doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync11(&mut self) -> _DMACSYNC11W {
_DMACSYNC11W { w: self }
}
- #[doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync12(&mut self) -> _DMACSYNC12W {
_DMACSYNC12W { w: self }
}
- #[doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync13(&mut self) -> _DMACSYNC13W {
_DMACSYNC13W { w: self }
}
- #[doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync14(&mut self) -> _DMACSYNC14W {
_DMACSYNC14W { w: self }
}
- #[doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." ] # [ inline ( always ) ]
pub fn dmacsync15(&mut self) -> _DMACSYNC15W {
_DMACSYNC15W { w: self }
}
@@ -28429,8 +27114,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - DMA source address. Reading this register will return the current source address."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - DMA source address. Reading this register will return the current source address." ] # [ inline ( always ) ]
pub fn srcaddr(&self) -> SRCADDRR {
let bits = {
const MASK: u32 = 4294967295;
@@ -28452,8 +27136,7 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - DMA source address. Reading this register will return the current source address."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - DMA source address. Reading this register will return the current source address." ] # [ inline ( always ) ]
pub fn srcaddr(&mut self) -> _SRCADDRW {
_SRCADDRW { w: self }
}
@@ -28541,8 +27224,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - DMA Destination address. Reading this register will return the current destination address."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - DMA Destination address. Reading this register will return the current destination address." ] # [ inline ( always ) ]
pub fn destaddr(&self) -> DESTADDRR {
let bits = {
const MASK: u32 = 4294967295;
@@ -28564,8 +27246,7 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - DMA Destination address. Reading this register will return the current destination address."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - DMA Destination address. Reading this register will return the current destination address." ] # [ inline ( always ) ]
pub fn destaddr(&mut self) -> _DESTADDRW {
_DESTADDRW { w: self }
}
@@ -28817,8 +27498,7 @@ pub mod gpdma {
};
RR { bits }
}
- #[doc = "Bits 2:31 - Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0."]
- #[inline(always)]
+ # [ doc = "Bits 2:31 - Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." ] # [ inline ( always ) ]
pub fn lli(&self) -> LLIR {
let bits = {
const MASK: u32 = 1073741823;
@@ -28850,8 +27530,7 @@ pub mod gpdma {
pub fn r(&mut self) -> _RW {
_RW { w: self }
}
- #[doc = "Bits 2:31 - Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0."]
- #[inline(always)]
+ # [ doc = "Bits 2:31 - Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." ] # [ inline ( always ) ]
pub fn lli(&mut self) -> _LLIW {
_LLIW { w: self }
}
@@ -29181,10 +27860,8 @@ pub mod gpdma {
#[doc = "Possible values of the field `S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SR {
- #[doc = "AHB Master 0 selected for source transfer."]
- AHB_MASTER_0_SELECTE,
- #[doc = "AHB Master 1 selected for source transfer."]
- AHB_MASTER_1_SELECTE,
+ #[doc = "AHB Master 0 selected for source transfer."] AHB_MASTER_0_SELECTE,
+ #[doc = "AHB Master 1 selected for source transfer."] AHB_MASTER_1_SELECTE,
}
impl SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -29228,10 +27905,8 @@ pub mod gpdma {
#[doc = "Possible values of the field `D`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DR {
- #[doc = "AHB Master 0 selected for destination transfer."]
- AHB_MASTER_0_SELECTE,
- #[doc = "AHB Master 1 selected for destination transfer."]
- AHB_MASTER_1_SELECTE,
+ #[doc = "AHB Master 0 selected for destination transfer."] AHB_MASTER_0_SELECTE,
+ #[doc = "AHB Master 1 selected for destination transfer."] AHB_MASTER_1_SELECTE,
}
impl DR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -29275,10 +27950,8 @@ pub mod gpdma {
#[doc = "Possible values of the field `SI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIR {
- #[doc = "The source address is not incremented after each transfer."]
- NOT_INCREMENT,
- #[doc = "The source address is incremented after each transfer."]
- INCREMENT,
+ #[doc = "The source address is not incremented after each transfer."] NOT_INCREMENT,
+ #[doc = "The source address is incremented after each transfer."] INCREMENT,
}
impl SIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -29322,10 +27995,8 @@ pub mod gpdma {
#[doc = "Possible values of the field `DI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIR {
- #[doc = "The destination address is not incremented after each transfer."]
- DISABLED,
- #[doc = "The destination address is incremented after each transfer."]
- ENABLED,
+ #[doc = "The destination address is not incremented after each transfer."] DISABLED,
+ #[doc = "The destination address is incremented after each transfer."] ENABLED,
}
impl DIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -29849,10 +28520,8 @@ pub mod gpdma {
}
#[doc = "Values that can be written to the field `S`"]
pub enum SW {
- #[doc = "AHB Master 0 selected for source transfer."]
- AHB_MASTER_0_SELECTE,
- #[doc = "AHB Master 1 selected for source transfer."]
- AHB_MASTER_1_SELECTE,
+ #[doc = "AHB Master 0 selected for source transfer."] AHB_MASTER_0_SELECTE,
+ #[doc = "AHB Master 1 selected for source transfer."] AHB_MASTER_1_SELECTE,
}
impl SW {
#[allow(missing_docs)]
@@ -29907,10 +28576,8 @@ pub mod gpdma {
}
#[doc = "Values that can be written to the field `D`"]
pub enum DW {
- #[doc = "AHB Master 0 selected for destination transfer."]
- AHB_MASTER_0_SELECTE,
- #[doc = "AHB Master 1 selected for destination transfer."]
- AHB_MASTER_1_SELECTE,
+ #[doc = "AHB Master 0 selected for destination transfer."] AHB_MASTER_0_SELECTE,
+ #[doc = "AHB Master 1 selected for destination transfer."] AHB_MASTER_1_SELECTE,
}
impl DW {
#[allow(missing_docs)]
@@ -29965,10 +28632,8 @@ pub mod gpdma {
}
#[doc = "Values that can be written to the field `SI`"]
pub enum SIW {
- #[doc = "The source address is not incremented after each transfer."]
- NOT_INCREMENT,
- #[doc = "The source address is incremented after each transfer."]
- INCREMENT,
+ #[doc = "The source address is not incremented after each transfer."] NOT_INCREMENT,
+ #[doc = "The source address is incremented after each transfer."] INCREMENT,
}
impl SIW {
#[allow(missing_docs)]
@@ -30023,10 +28688,8 @@ pub mod gpdma {
}
#[doc = "Values that can be written to the field `DI`"]
pub enum DIW {
- #[doc = "The destination address is not incremented after each transfer."]
- DISABLED,
- #[doc = "The destination address is incremented after each transfer."]
- ENABLED,
+ #[doc = "The destination address is not incremented after each transfer."] DISABLED,
+ #[doc = "The destination address is incremented after each transfer."] ENABLED,
}
impl DIW {
#[allow(missing_docs)]
@@ -30309,8 +28972,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:11 - Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." ] # [ inline ( always ) ]
pub fn transfersize(&self) -> TRANSFERSIZER {
let bits = {
const MASK: u16 = 4095;
@@ -30319,8 +28981,7 @@ pub mod gpdma {
};
TRANSFERSIZER { bits }
}
- #[doc = "Bits 12:14 - Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral."]
- #[inline(always)]
+ # [ doc = "Bits 12:14 - Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral." ] # [ inline ( always ) ]
pub fn sbsize(&self) -> SBSIZER {
SBSIZER::_from({
const MASK: u8 = 7;
@@ -30328,8 +28989,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 15:17 - Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral."]
- #[inline(always)]
+ # [ doc = "Bits 15:17 - Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral." ] # [ inline ( always ) ]
pub fn dbsize(&self) -> DBSIZER {
DBSIZER::_from({
const MASK: u8 = 7;
@@ -30337,8 +28997,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 18:20 - Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved."]
- #[inline(always)]
+ # [ doc = "Bits 18:20 - Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved." ] # [ inline ( always ) ]
pub fn swidth(&self) -> SWIDTHR {
SWIDTHR::_from({
const MASK: u8 = 7;
@@ -30346,8 +29005,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 21:23 - Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved."]
- #[inline(always)]
+ # [ doc = "Bits 21:23 - Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved." ] # [ inline ( always ) ]
pub fn dwidth(&self) -> DWIDTHR {
DWIDTHR::_from({
const MASK: u8 = 7;
@@ -30364,8 +29022,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 25 - Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory." ] # [ inline ( always ) ]
pub fn d(&self) -> DR {
DR::_from({
const MASK: bool = true;
@@ -30440,28 +29097,23 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bits 0:11 - Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." ] # [ inline ( always ) ]
pub fn transfersize(&mut self) -> _TRANSFERSIZEW {
_TRANSFERSIZEW { w: self }
}
- #[doc = "Bits 12:14 - Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral."]
- #[inline(always)]
+ # [ doc = "Bits 12:14 - Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral." ] # [ inline ( always ) ]
pub fn sbsize(&mut self) -> _SBSIZEW {
_SBSIZEW { w: self }
}
- #[doc = "Bits 15:17 - Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral."]
- #[inline(always)]
+ # [ doc = "Bits 15:17 - Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral." ] # [ inline ( always ) ]
pub fn dbsize(&mut self) -> _DBSIZEW {
_DBSIZEW { w: self }
}
- #[doc = "Bits 18:20 - Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved."]
- #[inline(always)]
+ # [ doc = "Bits 18:20 - Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved." ] # [ inline ( always ) ]
pub fn swidth(&mut self) -> _SWIDTHW {
_SWIDTHW { w: self }
}
- #[doc = "Bits 21:23 - Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved."]
- #[inline(always)]
+ # [ doc = "Bits 21:23 - Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved." ] # [ inline ( always ) ]
pub fn dwidth(&mut self) -> _DWIDTHW {
_DWIDTHW { w: self }
}
@@ -30470,8 +29122,7 @@ pub mod gpdma {
pub fn s(&mut self) -> _SW {
_SW { w: self }
}
- #[doc = "Bit 25 - Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory." ] # [ inline ( always ) ]
pub fn d(&mut self) -> _DW {
_DW { w: self }
}
@@ -30606,25 +29257,18 @@ pub mod gpdma {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SRCPERIPHERALR {
#[doc = "Source = SPIFI"] SOURCE_EQ_SPIFI,
- #[doc = "Source = Timer 0 match 0/UART0 transmit"]
- SOURCE_EQ_TIMER_0_MAT0_UART0_T,
- #[doc = "Source = Timer 0 match 1/UART0 receive"]
- SOURCE_EQ_TIMER_0_MAT1_UART0_R,
- #[doc = "Source = Timer 1 match 0/UART1 transmit"]
- SOURCE_EQ_TIMER_1_MAT0_UART1_T,
- #[doc = "Source = Timer 1 match 1/UART 1 receive"]
- SOURCE_EQ_TIMER_1_MAT1_UART1_R,
- #[doc = "Source = Timer 2 match 0/UART 2 transmit"]
- SOURCE_EQ_TIMER_2_MAT0_UART2_T,
- #[doc = "Source = Timer 2 match 1/UART 2 receive"]
- SOURCE_EQ_TIMER_2_MAT1_UART2R,
+ #[doc = "Source = Timer 0 match 0/UART0 transmit"] SOURCE_EQ_TIMER_0_MAT0_UART0_T,
+ #[doc = "Source = Timer 0 match 1/UART0 receive"] SOURCE_EQ_TIMER_0_MAT1_UART0_R,
+ #[doc = "Source = Timer 1 match 0/UART1 transmit"] SOURCE_EQ_TIMER_1_MAT0_UART1_T,
+ #[doc = "Source = Timer 1 match 1/UART 1 receive"] SOURCE_EQ_TIMER_1_MAT1_UART1_R,
+ #[doc = "Source = Timer 2 match 0/UART 2 transmit"] SOURCE_EQ_TIMER_2_MAT0_UART2_T,
+ #[doc = "Source = Timer 2 match 1/UART 2 receive"] SOURCE_EQ_TIMER_2_MAT1_UART2R,
#[doc = "Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
SOURCE_EQ_TIMER_3_MAT0_DMA_R0,
#[doc = "Source = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
SOURCE_EQ_TIMER_3_MAT1_DMA_R1,
#[doc = "Source = SSP0 receive/I2S channel 0"] SOURCE_EQ_SSP0_RECEIV,
- #[doc = "Source = SSP0 transmit/I2S channel 1"]
- SOURCE_EQ_SSP0_TRANSM,
+ #[doc = "Source = SSP0 transmit/I2S channel 1"] SOURCE_EQ_SSP0_TRANSM,
#[doc = "Source = SSP1 receive"] SOURCE_EQ_SSP1_RECEIV,
#[doc = "Source = SSP1 transmit"] SOURCE_EQ_SSP1_TRANSM,
#[doc = "Source = ADC0"] SOURCE_EQ_ADC0,
@@ -30765,26 +29409,18 @@ pub mod gpdma {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DESTPERIPHERALR {
#[doc = "Destination = SPIFI"] DESTINATION_EQ_SPIFI,
- #[doc = "Destination = Timer 0 match 0/UART0 transmit"]
- TIMER_0_MATCH_0_UART0_TRANSMIT,
- #[doc = "Destination = Timer 0 match 1/UART0 receive"]
- TIMER_0_MATCH_1_UART0_RECEIVE,
- #[doc = "Destination = Timer 1 match 0/UART1 transmit"]
- TIMER_1_MATCH_0_UART1_TRANSMIT,
- #[doc = "Destination = Timer 1 match 1/UART1 receive"]
- TIMER_1_MATCH_1_UART1_RECEIVE,
- #[doc = "Destination = Timer 2 match 0/UART2 transmit"]
- TIMER_2_MATCH_0_UART2_TRANSMIT,
- #[doc = "Destination = Timer 2 match 1/UART2 receive"]
- TIMER_2_MATCH_1_UART2_RECEIVE,
+ #[doc = "Destination = Timer 0 match 0/UART0 transmit"] TIMER_0_MATCH_0_UART0_TRANSMIT,
+ #[doc = "Destination = Timer 0 match 1/UART0 receive"] TIMER_0_MATCH_1_UART0_RECEIVE,
+ #[doc = "Destination = Timer 1 match 0/UART1 transmit"] TIMER_1_MATCH_0_UART1_TRANSMIT,
+ #[doc = "Destination = Timer 1 match 1/UART1 receive"] TIMER_1_MATCH_1_UART1_RECEIVE,
+ #[doc = "Destination = Timer 2 match 0/UART2 transmit"] TIMER_2_MATCH_0_UART2_TRANSMIT,
+ #[doc = "Destination = Timer 2 match 1/UART2 receive"] TIMER_2_MATCH_1_UART2_RECEIVE,
#[doc = "Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0,
#[doc = "Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1,
- #[doc = "Destination = SSP0 receive/I2S channel 0"]
- DESTINATION_EQ_SSP0_R,
- #[doc = "Destination = SSP0 transmit/I2S channel 1"]
- DESTINATION_EQ_SSP0_T,
+ #[doc = "Destination = SSP0 receive/I2S channel 0"] DESTINATION_EQ_SSP0_R,
+ #[doc = "Destination = SSP0 transmit/I2S channel 1"] DESTINATION_EQ_SSP0_T,
#[doc = "Destination = SSP1 receive"] DESTINATION_EQ_SSP1_R,
#[doc = "Destination = SSP1 transmit"] DESTINATION_EQ_SSP1_T,
#[doc = "Destination = ADC0"] DESTINATION_EQ_ADC0,
@@ -30796,13 +29432,49 @@ pub mod gpdma {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
- match * self { DESTPERIPHERALR :: DESTINATION_EQ_SPIFI => 0 , DESTPERIPHERALR :: TIMER_0_MATCH_0_UART0_TRANSMIT => 1 , DESTPERIPHERALR :: TIMER_0_MATCH_1_UART0_RECEIVE => 2 , DESTPERIPHERALR :: TIMER_1_MATCH_0_UART1_TRANSMIT => 3 , DESTPERIPHERALR :: TIMER_1_MATCH_1_UART1_RECEIVE => 4 , DESTPERIPHERALR :: TIMER_2_MATCH_0_UART2_TRANSMIT => 5 , DESTPERIPHERALR :: TIMER_2_MATCH_1_UART2_RECEIVE => 6 , DESTPERIPHERALR :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 => 7 , DESTPERIPHERALR :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 => 8 , DESTPERIPHERALR :: DESTINATION_EQ_SSP0_R => 9 , DESTPERIPHERALR :: DESTINATION_EQ_SSP0_T => 10 , DESTPERIPHERALR :: DESTINATION_EQ_SSP1_R => 11 , DESTPERIPHERALR :: DESTINATION_EQ_SSP1_T => 12 , DESTPERIPHERALR :: DESTINATION_EQ_ADC0 => 13 , DESTPERIPHERALR :: DESTINATION_EQ_ADC1 => 14 , DESTPERIPHERALR :: DESTINATION_EQ_DAC => 15 , DESTPERIPHERALR :: _Reserved ( bits ) => bits }
+ match *self {
+ DESTPERIPHERALR::DESTINATION_EQ_SPIFI => 0,
+ DESTPERIPHERALR::TIMER_0_MATCH_0_UART0_TRANSMIT => 1,
+ DESTPERIPHERALR::TIMER_0_MATCH_1_UART0_RECEIVE => 2,
+ DESTPERIPHERALR::TIMER_1_MATCH_0_UART1_TRANSMIT => 3,
+ DESTPERIPHERALR::TIMER_1_MATCH_1_UART1_RECEIVE => 4,
+ DESTPERIPHERALR::TIMER_2_MATCH_0_UART2_TRANSMIT => 5,
+ DESTPERIPHERALR::TIMER_2_MATCH_1_UART2_RECEIVE => 6,
+ DESTPERIPHERALR::TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 => 7,
+ DESTPERIPHERALR::TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 => 8,
+ DESTPERIPHERALR::DESTINATION_EQ_SSP0_R => 9,
+ DESTPERIPHERALR::DESTINATION_EQ_SSP0_T => 10,
+ DESTPERIPHERALR::DESTINATION_EQ_SSP1_R => 11,
+ DESTPERIPHERALR::DESTINATION_EQ_SSP1_T => 12,
+ DESTPERIPHERALR::DESTINATION_EQ_ADC0 => 13,
+ DESTPERIPHERALR::DESTINATION_EQ_ADC1 => 14,
+ DESTPERIPHERALR::DESTINATION_EQ_DAC => 15,
+ DESTPERIPHERALR::_Reserved(bits) => bits,
+ }
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> DESTPERIPHERALR {
- match value { 0 => DESTPERIPHERALR :: DESTINATION_EQ_SPIFI , 1 => DESTPERIPHERALR :: TIMER_0_MATCH_0_UART0_TRANSMIT , 2 => DESTPERIPHERALR :: TIMER_0_MATCH_1_UART0_RECEIVE , 3 => DESTPERIPHERALR :: TIMER_1_MATCH_0_UART1_TRANSMIT , 4 => DESTPERIPHERALR :: TIMER_1_MATCH_1_UART1_RECEIVE , 5 => DESTPERIPHERALR :: TIMER_2_MATCH_0_UART2_TRANSMIT , 6 => DESTPERIPHERALR :: TIMER_2_MATCH_1_UART2_RECEIVE , 7 => DESTPERIPHERALR :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 , 8 => DESTPERIPHERALR :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 , 9 => DESTPERIPHERALR :: DESTINATION_EQ_SSP0_R , 10 => DESTPERIPHERALR :: DESTINATION_EQ_SSP0_T , 11 => DESTPERIPHERALR :: DESTINATION_EQ_SSP1_R , 12 => DESTPERIPHERALR :: DESTINATION_EQ_SSP1_T , 13 => DESTPERIPHERALR :: DESTINATION_EQ_ADC0 , 14 => DESTPERIPHERALR :: DESTINATION_EQ_ADC1 , 15 => DESTPERIPHERALR :: DESTINATION_EQ_DAC , i => DESTPERIPHERALR :: _Reserved ( i ) , }
+ match value {
+ 0 => DESTPERIPHERALR::DESTINATION_EQ_SPIFI,
+ 1 => DESTPERIPHERALR::TIMER_0_MATCH_0_UART0_TRANSMIT,
+ 2 => DESTPERIPHERALR::TIMER_0_MATCH_1_UART0_RECEIVE,
+ 3 => DESTPERIPHERALR::TIMER_1_MATCH_0_UART1_TRANSMIT,
+ 4 => DESTPERIPHERALR::TIMER_1_MATCH_1_UART1_RECEIVE,
+ 5 => DESTPERIPHERALR::TIMER_2_MATCH_0_UART2_TRANSMIT,
+ 6 => DESTPERIPHERALR::TIMER_2_MATCH_1_UART2_RECEIVE,
+ 7 => DESTPERIPHERALR::TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0,
+ 8 => DESTPERIPHERALR::TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1,
+ 9 => DESTPERIPHERALR::DESTINATION_EQ_SSP0_R,
+ 10 => DESTPERIPHERALR::DESTINATION_EQ_SSP0_T,
+ 11 => DESTPERIPHERALR::DESTINATION_EQ_SSP1_R,
+ 12 => DESTPERIPHERALR::DESTINATION_EQ_SSP1_T,
+ 13 => DESTPERIPHERALR::DESTINATION_EQ_ADC0,
+ 14 => DESTPERIPHERALR::DESTINATION_EQ_ADC1,
+ 15 => DESTPERIPHERALR::DESTINATION_EQ_DAC,
+ i => DESTPERIPHERALR::_Reserved(i),
+ }
}
#[doc = "Checks if the value of the field is `DESTINATION_EQ_SPIFI`"]
#[inline(always)]
@@ -30839,19 +29511,13 @@ pub mod gpdma {
pub fn is_timer_2_match_1_uart2_receive(&self) -> bool {
*self == DESTPERIPHERALR::TIMER_2_MATCH_1_UART2_RECEIVE
}
- #[doc = "Checks if the value of the field is `TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0`"]
- #[inline(always)]
- pub fn is_timer_3_match_0_uart3_transmit_sct_dma_request_0(
- &self,
- ) -> bool {
- * self == DESTPERIPHERALR :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0
+ # [ doc = "Checks if the value of the field is `TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0`" ] # [ inline ( always ) ]
+ pub fn is_timer_3_match_0_uart3_transmit_sct_dma_request_0(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0
}
- #[doc = "Checks if the value of the field is `TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1`"]
- #[inline(always)]
- pub fn is_timer_3_match_1_uart3_receive_sct_dma_request_1(
- &self,
- ) -> bool {
- * self == DESTPERIPHERALR :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1
+ # [ doc = "Checks if the value of the field is `TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1`" ] # [ inline ( always ) ]
+ pub fn is_timer_3_match_1_uart3_receive_sct_dma_request_1(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1
}
#[doc = "Checks if the value of the field is `DESTINATION_EQ_SSP0_R`"]
#[inline(always)]
@@ -30892,18 +29558,14 @@ pub mod gpdma {
#[doc = "Possible values of the field `FLOWCNTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLOWCNTRLR {
- #[doc = "Memory to memory (DMA control)"]
- MEMORY_TO_MEMORY_DMA_CONTROL,
- #[doc = "Memory to peripheral (DMA control)"]
- MEMORY_TO_PERIPHERAL_DMA_CONTROL,
- #[doc = "Peripheral to memory (DMA control)"]
- PERIPHERAL_TO_MEMORY_DMA_CONTROL,
+ #[doc = "Memory to memory (DMA control)"] MEMORY_TO_MEMORY_DMA_CONTROL,
+ #[doc = "Memory to peripheral (DMA control)"] MEMORY_TO_PERIPHERAL_DMA_CONTROL,
+ #[doc = "Peripheral to memory (DMA control)"] PERIPHERAL_TO_MEMORY_DMA_CONTROL,
#[doc = "Source peripheral to destination peripheral (DMA control)"]
SOURCE_PERIPHERAL_TO_DMA_CONTROL,
#[doc = "Source peripheral to destination peripheral (destination control)"]
SOURCE_PERIPHERAL_TO_DESTINATION_CONTROL,
- #[doc = "Memory to peripheral (peripheral control)"]
- MEMORY_TO_PERIPHERAL_CONTROL,
+ #[doc = "Memory to peripheral (peripheral control)"] MEMORY_TO_PERIPHERAL_CONTROL,
#[doc = "Peripheral to memory (peripheral control)"]
PERIPHERAL_TO_MEMORY_PERIPHERAL_CONTROL,
#[doc = "Source peripheral to destination peripheral (source control)"]
@@ -31169,25 +29831,18 @@ pub mod gpdma {
#[doc = "Values that can be written to the field `SRCPERIPHERAL`"]
pub enum SRCPERIPHERALW {
#[doc = "Source = SPIFI"] SOURCE_EQ_SPIFI,
- #[doc = "Source = Timer 0 match 0/UART0 transmit"]
- SOURCE_EQ_TIMER_0_MAT0_UART0_T,
- #[doc = "Source = Timer 0 match 1/UART0 receive"]
- SOURCE_EQ_TIMER_0_MAT1_UART0_R,
- #[doc = "Source = Timer 1 match 0/UART1 transmit"]
- SOURCE_EQ_TIMER_1_MAT0_UART1_T,
- #[doc = "Source = Timer 1 match 1/UART 1 receive"]
- SOURCE_EQ_TIMER_1_MAT1_UART1_R,
- #[doc = "Source = Timer 2 match 0/UART 2 transmit"]
- SOURCE_EQ_TIMER_2_MAT0_UART2_T,
- #[doc = "Source = Timer 2 match 1/UART 2 receive"]
- SOURCE_EQ_TIMER_2_MAT1_UART2R,
+ #[doc = "Source = Timer 0 match 0/UART0 transmit"] SOURCE_EQ_TIMER_0_MAT0_UART0_T,
+ #[doc = "Source = Timer 0 match 1/UART0 receive"] SOURCE_EQ_TIMER_0_MAT1_UART0_R,
+ #[doc = "Source = Timer 1 match 0/UART1 transmit"] SOURCE_EQ_TIMER_1_MAT0_UART1_T,
+ #[doc = "Source = Timer 1 match 1/UART 1 receive"] SOURCE_EQ_TIMER_1_MAT1_UART1_R,
+ #[doc = "Source = Timer 2 match 0/UART 2 transmit"] SOURCE_EQ_TIMER_2_MAT0_UART2_T,
+ #[doc = "Source = Timer 2 match 1/UART 2 receive"] SOURCE_EQ_TIMER_2_MAT1_UART2R,
#[doc = "Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
SOURCE_EQ_TIMER_3_MAT0_DMA_R0,
#[doc = "Source = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
SOURCE_EQ_TIMER_3_MAT1_DMA_R1,
#[doc = "Source = SSP0 receive/I2S channel 0"] SOURCE_EQ_SSP0_RECEIV,
- #[doc = "Source = SSP0 transmit/I2S channel 1"]
- SOURCE_EQ_SSP0_TRANSM,
+ #[doc = "Source = SSP0 transmit/I2S channel 1"] SOURCE_EQ_SSP0_TRANSM,
#[doc = "Source = SSP1 receive"] SOURCE_EQ_SSP1_RECEIV,
#[doc = "Source = SSP1 transmit"] SOURCE_EQ_SSP1_TRANSM,
#[doc = "Source = ADC0"] SOURCE_EQ_ADC0,
@@ -31322,26 +29977,18 @@ pub mod gpdma {
#[doc = "Values that can be written to the field `DESTPERIPHERAL`"]
pub enum DESTPERIPHERALW {
#[doc = "Destination = SPIFI"] DESTINATION_EQ_SPIFI,
- #[doc = "Destination = Timer 0 match 0/UART0 transmit"]
- TIMER_0_MATCH_0_UART0_TRANSMIT,
- #[doc = "Destination = Timer 0 match 1/UART0 receive"]
- TIMER_0_MATCH_1_UART0_RECEIVE,
- #[doc = "Destination = Timer 1 match 0/UART1 transmit"]
- TIMER_1_MATCH_0_UART1_TRANSMIT,
- #[doc = "Destination = Timer 1 match 1/UART1 receive"]
- TIMER_1_MATCH_1_UART1_RECEIVE,
- #[doc = "Destination = Timer 2 match 0/UART2 transmit"]
- TIMER_2_MATCH_0_UART2_TRANSMIT,
- #[doc = "Destination = Timer 2 match 1/UART2 receive"]
- TIMER_2_MATCH_1_UART2_RECEIVE,
+ #[doc = "Destination = Timer 0 match 0/UART0 transmit"] TIMER_0_MATCH_0_UART0_TRANSMIT,
+ #[doc = "Destination = Timer 0 match 1/UART0 receive"] TIMER_0_MATCH_1_UART0_RECEIVE,
+ #[doc = "Destination = Timer 1 match 0/UART1 transmit"] TIMER_1_MATCH_0_UART1_TRANSMIT,
+ #[doc = "Destination = Timer 1 match 1/UART1 receive"] TIMER_1_MATCH_1_UART1_RECEIVE,
+ #[doc = "Destination = Timer 2 match 0/UART2 transmit"] TIMER_2_MATCH_0_UART2_TRANSMIT,
+ #[doc = "Destination = Timer 2 match 1/UART2 receive"] TIMER_2_MATCH_1_UART2_RECEIVE,
#[doc = "Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0,
#[doc = "Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1,
- #[doc = "Destination = SSP0 receive/I2S channel 0"]
- DESTINATION_EQ_SSP0_R,
- #[doc = "Destination = SSP0 transmit/I2S channel 1"]
- DESTINATION_EQ_SSP0_T,
+ #[doc = "Destination = SSP0 receive/I2S channel 0"] DESTINATION_EQ_SSP0_R,
+ #[doc = "Destination = SSP0 transmit/I2S channel 1"] DESTINATION_EQ_SSP0_T,
#[doc = "Destination = SSP1 receive"] DESTINATION_EQ_SSP1_R,
#[doc = "Destination = SSP1 transmit"] DESTINATION_EQ_SSP1_T,
#[doc = "Destination = ADC0"] DESTINATION_EQ_ADC0,
@@ -31353,7 +30000,24 @@ pub mod gpdma {
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
- match * self { DESTPERIPHERALW :: DESTINATION_EQ_SPIFI => 0 , DESTPERIPHERALW :: TIMER_0_MATCH_0_UART0_TRANSMIT => 1 , DESTPERIPHERALW :: TIMER_0_MATCH_1_UART0_RECEIVE => 2 , DESTPERIPHERALW :: TIMER_1_MATCH_0_UART1_TRANSMIT => 3 , DESTPERIPHERALW :: TIMER_1_MATCH_1_UART1_RECEIVE => 4 , DESTPERIPHERALW :: TIMER_2_MATCH_0_UART2_TRANSMIT => 5 , DESTPERIPHERALW :: TIMER_2_MATCH_1_UART2_RECEIVE => 6 , DESTPERIPHERALW :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 => 7 , DESTPERIPHERALW :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 => 8 , DESTPERIPHERALW :: DESTINATION_EQ_SSP0_R => 9 , DESTPERIPHERALW :: DESTINATION_EQ_SSP0_T => 10 , DESTPERIPHERALW :: DESTINATION_EQ_SSP1_R => 11 , DESTPERIPHERALW :: DESTINATION_EQ_SSP1_T => 12 , DESTPERIPHERALW :: DESTINATION_EQ_ADC0 => 13 , DESTPERIPHERALW :: DESTINATION_EQ_ADC1 => 14 , DESTPERIPHERALW :: DESTINATION_EQ_DAC => 15 }
+ match *self {
+ DESTPERIPHERALW::DESTINATION_EQ_SPIFI => 0,
+ DESTPERIPHERALW::TIMER_0_MATCH_0_UART0_TRANSMIT => 1,
+ DESTPERIPHERALW::TIMER_0_MATCH_1_UART0_RECEIVE => 2,
+ DESTPERIPHERALW::TIMER_1_MATCH_0_UART1_TRANSMIT => 3,
+ DESTPERIPHERALW::TIMER_1_MATCH_1_UART1_RECEIVE => 4,
+ DESTPERIPHERALW::TIMER_2_MATCH_0_UART2_TRANSMIT => 5,
+ DESTPERIPHERALW::TIMER_2_MATCH_1_UART2_RECEIVE => 6,
+ DESTPERIPHERALW::TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 => 7,
+ DESTPERIPHERALW::TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 => 8,
+ DESTPERIPHERALW::DESTINATION_EQ_SSP0_R => 9,
+ DESTPERIPHERALW::DESTINATION_EQ_SSP0_T => 10,
+ DESTPERIPHERALW::DESTINATION_EQ_SSP1_R => 11,
+ DESTPERIPHERALW::DESTINATION_EQ_SSP1_T => 12,
+ DESTPERIPHERALW::DESTINATION_EQ_ADC0 => 13,
+ DESTPERIPHERALW::DESTINATION_EQ_ADC1 => 14,
+ DESTPERIPHERALW::DESTINATION_EQ_DAC => 15,
+ }
}
}
#[doc = r" Proxy"]
@@ -31403,17 +30067,13 @@ pub mod gpdma {
}
#[doc = "Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
#[inline(always)]
- pub fn timer_3_match_0_uart3_transmit_sct_dma_request_0(
- self,
- ) -> &'a mut W {
- self . variant ( DESTPERIPHERALW :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 )
+ pub fn timer_3_match_0_uart3_transmit_sct_dma_request_0(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0)
}
#[doc = "Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
#[inline(always)]
- pub fn timer_3_match_1_uart3_receive_sct_dma_request_1(
- self,
- ) -> &'a mut W {
- self . variant ( DESTPERIPHERALW :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 )
+ pub fn timer_3_match_1_uart3_receive_sct_dma_request_1(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1)
}
#[doc = "Destination = SSP0 receive/I2S channel 0"]
#[inline(always)]
@@ -31462,18 +30122,14 @@ pub mod gpdma {
}
#[doc = "Values that can be written to the field `FLOWCNTRL`"]
pub enum FLOWCNTRLW {
- #[doc = "Memory to memory (DMA control)"]
- MEMORY_TO_MEMORY_DMA_CONTROL,
- #[doc = "Memory to peripheral (DMA control)"]
- MEMORY_TO_PERIPHERAL_DMA_CONTROL,
- #[doc = "Peripheral to memory (DMA control)"]
- PERIPHERAL_TO_MEMORY_DMA_CONTROL,
+ #[doc = "Memory to memory (DMA control)"] MEMORY_TO_MEMORY_DMA_CONTROL,
+ #[doc = "Memory to peripheral (DMA control)"] MEMORY_TO_PERIPHERAL_DMA_CONTROL,
+ #[doc = "Peripheral to memory (DMA control)"] PERIPHERAL_TO_MEMORY_DMA_CONTROL,
#[doc = "Source peripheral to destination peripheral (DMA control)"]
SOURCE_PERIPHERAL_TO_DMA_CONTROL,
#[doc = "Source peripheral to destination peripheral (destination control)"]
SOURCE_PERIPHERAL_TO_DESTINATION_CONTROL,
- #[doc = "Memory to peripheral (peripheral control)"]
- MEMORY_TO_PERIPHERAL_CONTROL,
+ #[doc = "Memory to peripheral (peripheral control)"] MEMORY_TO_PERIPHERAL_CONTROL,
#[doc = "Peripheral to memory (peripheral control)"]
PERIPHERAL_TO_MEMORY_PERIPHERAL_CONTROL,
#[doc = "Source peripheral to destination peripheral (source control)"]
@@ -31531,9 +30187,7 @@ pub mod gpdma {
#[doc = "Source peripheral to destination peripheral (destination control)"]
#[inline(always)]
pub fn source_peripheral_to_destination_control(self) -> &'a mut W {
- self.variant(
- FLOWCNTRLW::SOURCE_PERIPHERAL_TO_DESTINATION_CONTROL,
- )
+ self.variant(FLOWCNTRLW::SOURCE_PERIPHERAL_TO_DESTINATION_CONTROL)
}
#[doc = "Memory to peripheral (peripheral control)"]
#[inline(always)]
@@ -31543,9 +30197,7 @@ pub mod gpdma {
#[doc = "Peripheral to memory (peripheral control)"]
#[inline(always)]
pub fn peripheral_to_memory_peripheral_control(self) -> &'a mut W {
- self.variant(
- FLOWCNTRLW::PERIPHERAL_TO_MEMORY_PERIPHERAL_CONTROL,
- )
+ self.variant(FLOWCNTRLW::PERIPHERAL_TO_MEMORY_PERIPHERAL_CONTROL)
}
#[doc = "Source peripheral to destination peripheral (source control)"]
#[inline(always)]
@@ -31716,8 +30368,7 @@ pub mod gpdma {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." ] # [ inline ( always ) ]
pub fn e(&self) -> ER {
ER::_from({
const MASK: bool = true;
@@ -31725,8 +30376,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 1:5 - Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details."]
- #[inline(always)]
+ # [ doc = "Bits 1:5 - Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details." ] # [ inline ( always ) ]
pub fn srcperipheral(&self) -> SRCPERIPHERALR {
SRCPERIPHERALR::_from({
const MASK: u8 = 31;
@@ -31734,8 +30384,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 6:10 - Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details."]
- #[inline(always)]
+ # [ doc = "Bits 6:10 - Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details." ] # [ inline ( always ) ]
pub fn destperipheral(&self) -> DESTPERIPHERALR {
DESTPERIPHERALR::_from({
const MASK: u8 = 31;
@@ -31743,8 +30392,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 11:13 - Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field."]
- #[inline(always)]
+ # [ doc = "Bits 11:13 - Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field." ] # [ inline ( always ) ]
pub fn flowcntrl(&self) -> FLOWCNTRLR {
FLOWCNTRLR::_from({
const MASK: u8 = 7;
@@ -31752,8 +30400,7 @@ pub mod gpdma {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 14 - Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." ] # [ inline ( always ) ]
pub fn ie(&self) -> IER {
let bits = {
const MASK: bool = true;
@@ -31762,8 +30409,7 @@ pub mod gpdma {
};
IER { bits }
}
- #[doc = "Bit 15 - Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." ] # [ inline ( always ) ]
pub fn itc(&self) -> ITCR {
let bits = {
const MASK: bool = true;
@@ -31782,8 +30428,7 @@ pub mod gpdma {
};
LR { bits }
}
- #[doc = "Bit 17 - Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." ] # [ inline ( always ) ]
pub fn a(&self) -> AR {
let bits = {
const MASK: bool = true;
@@ -31792,8 +30437,7 @@ pub mod gpdma {
};
AR { bits }
}
- #[doc = "Bit 18 - Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." ] # [ inline ( always ) ]
pub fn h(&self) -> HR {
HR::_from({
const MASK: bool = true;
@@ -31814,33 +30458,27 @@ pub mod gpdma {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." ] # [ inline ( always ) ]
pub fn e(&mut self) -> _EW {
_EW { w: self }
}
- #[doc = "Bits 1:5 - Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details."]
- #[inline(always)]
+ # [ doc = "Bits 1:5 - Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details." ] # [ inline ( always ) ]
pub fn srcperipheral(&mut self) -> _SRCPERIPHERALW {
_SRCPERIPHERALW { w: self }
}
- #[doc = "Bits 6:10 - Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details."]
- #[inline(always)]
+ # [ doc = "Bits 6:10 - Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details." ] # [ inline ( always ) ]
pub fn destperipheral(&mut self) -> _DESTPERIPHERALW {
_DESTPERIPHERALW { w: self }
}
- #[doc = "Bits 11:13 - Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field."]
- #[inline(always)]
+ # [ doc = "Bits 11:13 - Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field." ] # [ inline ( always ) ]
pub fn flowcntrl(&mut self) -> _FLOWCNTRLW {
_FLOWCNTRLW { w: self }
}
- #[doc = "Bit 14 - Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." ] # [ inline ( always ) ]
pub fn ie(&mut self) -> _IEW {
_IEW { w: self }
}
- #[doc = "Bit 15 - Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." ] # [ inline ( always ) ]
pub fn itc(&mut self) -> _ITCW {
_ITCW { w: self }
}
@@ -31849,13 +30487,11 @@ pub mod gpdma {
pub fn l(&mut self) -> _LW {
_LW { w: self }
}
- #[doc = "Bit 17 - Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." ] # [ inline ( always ) ]
pub fn a(&mut self) -> _AW {
_AW { w: self }
}
- #[doc = "Bit 18 - Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." ] # [ inline ( always ) ]
pub fn h(&mut self) -> _HW {
_HW { w: self }
}
@@ -32005,12 +30641,7 @@ pub mod spifi {
}
#[doc = "Possible values of the field `MODE3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODE3R {
- #[doc = "SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH."]
- SCK_LOW,
- #[doc = "SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- SCK_HIGH,
- }
+ pub enum MODE3R {# [ doc = "SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." ] SCK_LOW , # [ doc = "SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] SCK_HIGH}
impl MODE3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -32142,12 +30773,7 @@ pub mod spifi {
}
#[doc = "Possible values of the field `RFCLK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RFCLKR {
- #[doc = "Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation."]
- RISING_EDGE,
- #[doc = "Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- FALLING_EDGE,
- }
+ pub enum RFCLKR {# [ doc = "Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." ] RISING_EDGE , # [ doc = "Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] FALLING_EDGE}
impl RFCLKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -32189,12 +30815,7 @@ pub mod spifi {
}
#[doc = "Possible values of the field `FBCLK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum FBCLKR {
- #[doc = "Internal clock. The SPIFI samples read data using an internal clock."]
- INTERNAL_CLOCK,
- #[doc = "Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- FEEDBACK_CLOCK,
- }
+ pub enum FBCLKR {# [ doc = "Internal clock. The SPIFI samples read data using an internal clock." ] INTERNAL_CLOCK , # [ doc = "Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] FEEDBACK_CLOCK}
impl FBCLKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -32332,12 +30953,7 @@ pub mod spifi {
}
}
#[doc = "Values that can be written to the field `MODE3`"]
- pub enum MODE3W {
- #[doc = "SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH."]
- SCK_LOW,
- #[doc = "SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- SCK_HIGH,
- }
+ pub enum MODE3W {# [ doc = "SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." ] SCK_LOW , # [ doc = "SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] SCK_HIGH}
impl MODE3W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -32361,13 +30977,11 @@ pub mod spifi {
self.bit(variant._bits())
}
}
- #[doc = "SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH."]
- #[inline(always)]
+ # [ doc = "SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." ] # [ inline ( always ) ]
pub fn sck_low(self) -> &'a mut W {
self.variant(MODE3W::SCK_LOW)
}
- #[doc = "SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- #[inline(always)]
+ # [ doc = "SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] # [ inline ( always ) ]
pub fn sck_high(self) -> &'a mut W {
self.variant(MODE3W::SCK_HIGH)
}
@@ -32502,12 +31116,7 @@ pub mod spifi {
}
}
#[doc = "Values that can be written to the field `RFCLK`"]
- pub enum RFCLKW {
- #[doc = "Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation."]
- RISING_EDGE,
- #[doc = "Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- FALLING_EDGE,
- }
+ pub enum RFCLKW {# [ doc = "Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." ] RISING_EDGE , # [ doc = "Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] FALLING_EDGE}
impl RFCLKW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -32531,13 +31140,11 @@ pub mod spifi {
self.bit(variant._bits())
}
}
- #[doc = "Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation."]
- #[inline(always)]
+ # [ doc = "Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." ] # [ inline ( always ) ]
pub fn rising_edge(self) -> &'a mut W {
self.variant(RFCLKW::RISING_EDGE)
}
- #[doc = "Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- #[inline(always)]
+ # [ doc = "Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] # [ inline ( always ) ]
pub fn falling_edge(self) -> &'a mut W {
self.variant(RFCLKW::FALLING_EDGE)
}
@@ -32560,12 +31167,7 @@ pub mod spifi {
}
}
#[doc = "Values that can be written to the field `FBCLK`"]
- pub enum FBCLKW {
- #[doc = "Internal clock. The SPIFI samples read data using an internal clock."]
- INTERNAL_CLOCK,
- #[doc = "Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- FEEDBACK_CLOCK,
- }
+ pub enum FBCLKW {# [ doc = "Internal clock. The SPIFI samples read data using an internal clock." ] INTERNAL_CLOCK , # [ doc = "Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] FEEDBACK_CLOCK}
impl FBCLKW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -32594,8 +31196,7 @@ pub mod spifi {
pub fn internal_clock(self) -> &'a mut W {
self.variant(FBCLKW::INTERNAL_CLOCK)
}
- #[doc = "Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame."]
- #[inline(always)]
+ # [ doc = "Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." ] # [ inline ( always ) ]
pub fn feedback_clock(self) -> &'a mut W {
self.variant(FBCLKW::FEEDBACK_CLOCK)
}
@@ -32646,8 +31247,7 @@ pub mod spifi {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." ] # [ inline ( always ) ]
pub fn timeout(&self) -> TIMEOUTR {
let bits = {
const MASK: u16 = 65535;
@@ -32656,8 +31256,7 @@ pub mod spifi {
};
TIMEOUTR { bits }
}
- #[doc = "Bits 16:19 - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." ] # [ inline ( always ) ]
pub fn cshigh(&self) -> CSHIGHR {
let bits = {
const MASK: u8 = 15;
@@ -32666,8 +31265,7 @@ pub mod spifi {
};
CSHIGHR { bits }
}
- #[doc = "Bit 21 - This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses."]
- #[inline(always)]
+ # [ doc = "Bit 21 - This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." ] # [ inline ( always ) ]
pub fn d_prftch_dis(&self) -> D_PRFTCH_DISR {
let bits = {
const MASK: bool = true;
@@ -32676,8 +31274,7 @@ pub mod spifi {
};
D_PRFTCH_DISR { bits }
}
- #[doc = "Bit 22 - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details."]
- #[inline(always)]
+ # [ doc = "Bit 22 - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." ] # [ inline ( always ) ]
pub fn inten(&self) -> INTENR {
let bits = {
const MASK: bool = true;
@@ -32695,8 +31292,7 @@ pub mod spifi {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 27 - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines." ] # [ inline ( always ) ]
pub fn prftch_dis(&self) -> PRFTCH_DISR {
PRFTCH_DISR::_from({
const MASK: bool = true;
@@ -32731,8 +31327,7 @@ pub mod spifi {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 31 - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode."]
- #[inline(always)]
+ # [ doc = "Bit 31 - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." ] # [ inline ( always ) ]
pub fn dmaen(&self) -> DMAENR {
let bits = {
const MASK: bool = true;
@@ -32754,23 +31349,19 @@ pub mod spifi {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." ] # [ inline ( always ) ]
pub fn timeout(&mut self) -> _TIMEOUTW {
_TIMEOUTW { w: self }
}
- #[doc = "Bits 16:19 - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." ] # [ inline ( always ) ]
pub fn cshigh(&mut self) -> _CSHIGHW {
_CSHIGHW { w: self }
}
- #[doc = "Bit 21 - This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses."]
- #[inline(always)]
+ # [ doc = "Bit 21 - This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." ] # [ inline ( always ) ]
pub fn d_prftch_dis(&mut self) -> _D_PRFTCH_DISW {
_D_PRFTCH_DISW { w: self }
}
- #[doc = "Bit 22 - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details."]
- #[inline(always)]
+ # [ doc = "Bit 22 - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." ] # [ inline ( always ) ]
pub fn inten(&mut self) -> _INTENW {
_INTENW { w: self }
}
@@ -32779,8 +31370,7 @@ pub mod spifi {
pub fn mode3(&mut self) -> _MODE3W {
_MODE3W { w: self }
}
- #[doc = "Bit 27 - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines." ] # [ inline ( always ) ]
pub fn prftch_dis(&mut self) -> _PRFTCH_DISW {
_PRFTCH_DISW { w: self }
}
@@ -32799,8 +31389,7 @@ pub mod spifi {
pub fn fbclk(&mut self) -> _FBCLKW {
_FBCLKW { w: self }
}
- #[doc = "Bit 31 - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode."]
- #[inline(always)]
+ # [ doc = "Bit 31 - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." ] # [ inline ( always ) ]
pub fn dmaen(&mut self) -> _DMAENW {
_DMAENW { w: self }
}
@@ -32947,8 +31536,7 @@ pub mod spifi {
#[doc = "Possible values of the field `FIELDFORM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIELDFORMR {
- #[doc = "All serial. All fields of the command are serial."]
- ALL_SERIAL,
+ #[doc = "All serial. All fields of the command are serial."] ALL_SERIAL,
#[doc = "Quad/dual data. Data field is quad/dual, other fields are serial."]
QUADDUAL_DATA,
#[doc = "Serial opcode. Opcode field is serial. Other fields are quad/dual."]
@@ -33004,18 +31592,15 @@ pub mod spifi {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRAMEFORMR {
#[doc = "Opcode. Opcode only, no address."] OPCODE,
- #[doc = "Opcode one byte. Opcode, least significant byte of address."]
- OPCODE_ONE_BYTE,
+ #[doc = "Opcode one byte. Opcode, least significant byte of address."] OPCODE_ONE_BYTE,
#[doc = "Opcode two bytes. Opcode, two least significant bytes of address."]
OPCODE_TWO_BYTES,
#[doc = "Opcode three bytes. Opcode, three least significant bytes of address."]
OPCODE_THREE_BYTES,
- #[doc = "Opcode four bytes. Opcode, 4 bytes of address."]
- OPCODE_FOUR_BYTES,
+ #[doc = "Opcode four bytes. Opcode, 4 bytes of address."] OPCODE_FOUR_BYTES,
#[doc = "No opcode three bytes. No opcode, 3 least significant bytes of address."]
NO_OPCODE_THREE_BYTE,
- #[doc = "No opcode four bytes. No opcode, 4 bytes of address."]
- NO_OPCODE_FOUR_BYTES,
+ #[doc = "No opcode four bytes. No opcode, 4 bytes of address."] NO_OPCODE_FOUR_BYTES,
}
impl FRAMEFORMR {
#[doc = r" Value of the field as raw bits"]
@@ -33204,8 +31789,7 @@ pub mod spifi {
}
#[doc = "Values that can be written to the field `FIELDFORM`"]
pub enum FIELDFORMW {
- #[doc = "All serial. All fields of the command are serial."]
- ALL_SERIAL,
+ #[doc = "All serial. All fields of the command are serial."] ALL_SERIAL,
#[doc = "Quad/dual data. Data field is quad/dual, other fields are serial."]
QUADDUAL_DATA,
#[doc = "Serial opcode. Opcode field is serial. Other fields are quad/dual."]
@@ -33271,18 +31855,15 @@ pub mod spifi {
#[doc = "Values that can be written to the field `FRAMEFORM`"]
pub enum FRAMEFORMW {
#[doc = "Opcode. Opcode only, no address."] OPCODE,
- #[doc = "Opcode one byte. Opcode, least significant byte of address."]
- OPCODE_ONE_BYTE,
+ #[doc = "Opcode one byte. Opcode, least significant byte of address."] OPCODE_ONE_BYTE,
#[doc = "Opcode two bytes. Opcode, two least significant bytes of address."]
OPCODE_TWO_BYTES,
#[doc = "Opcode three bytes. Opcode, three least significant bytes of address."]
OPCODE_THREE_BYTES,
- #[doc = "Opcode four bytes. Opcode, 4 bytes of address."]
- OPCODE_FOUR_BYTES,
+ #[doc = "Opcode four bytes. Opcode, 4 bytes of address."] OPCODE_FOUR_BYTES,
#[doc = "No opcode three bytes. No opcode, 3 least significant bytes of address."]
NO_OPCODE_THREE_BYTE,
- #[doc = "No opcode four bytes. No opcode, 4 bytes of address."]
- NO_OPCODE_FOUR_BYTES,
+ #[doc = "No opcode four bytes. No opcode, 4 bytes of address."] NO_OPCODE_FOUR_BYTES,
}
impl FRAMEFORMW {
#[allow(missing_docs)]
@@ -33376,8 +31957,7 @@ pub mod spifi {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:13 - Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field."]
- #[inline(always)]
+ # [ doc = "Bits 0:13 - Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." ] # [ inline ( always ) ]
pub fn datalen(&self) -> DATALENR {
let bits = {
const MASK: u16 = 16383;
@@ -33386,8 +31966,7 @@ pub mod spifi {
};
DATALENR { bits }
}
- #[doc = "Bit 14 - This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs"]
- #[inline(always)]
+ # [ doc = "Bit 14 - This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs" ] # [ inline ( always ) ]
pub fn poll(&self) -> POLLR {
let bits = {
const MASK: bool = true;
@@ -33396,8 +31975,7 @@ pub mod spifi {
};
POLLR { bits }
}
- #[doc = "Bit 15 - If the DATALEN field is not zero, this bit controls the direction of the data:"]
- #[inline(always)]
+ # [ doc = "Bit 15 - If the DATALEN field is not zero, this bit controls the direction of the data:" ] # [ inline ( always ) ]
pub fn dout(&self) -> DOUTR {
DOUTR::_from({
const MASK: bool = true;
@@ -33405,8 +31983,7 @@ pub mod spifi {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes."]
- #[inline(always)]
+ # [ doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." ] # [ inline ( always ) ]
pub fn intlen(&self) -> INTLENR {
let bits = {
const MASK: u8 = 7;
@@ -33456,23 +32033,19 @@ pub mod spifi {
self.bits = bits;
self
}
- #[doc = "Bits 0:13 - Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field."]
- #[inline(always)]
+ # [ doc = "Bits 0:13 - Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." ] # [ inline ( always ) ]
pub fn datalen(&mut self) -> _DATALENW {
_DATALENW { w: self }
}
- #[doc = "Bit 14 - This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs"]
- #[inline(always)]
+ # [ doc = "Bit 14 - This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs" ] # [ inline ( always ) ]
pub fn poll(&mut self) -> _POLLW {
_POLLW { w: self }
}
- #[doc = "Bit 15 - If the DATALEN field is not zero, this bit controls the direction of the data:"]
- #[inline(always)]
+ # [ doc = "Bit 15 - If the DATALEN field is not zero, this bit controls the direction of the data:" ] # [ inline ( always ) ]
pub fn dout(&mut self) -> _DOUTW {
_DOUTW { w: self }
}
- #[doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes."]
- #[inline(always)]
+ # [ doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." ] # [ inline ( always ) ]
pub fn intlen(&mut self) -> _INTLENW {
_INTLENW { w: self }
}
@@ -34047,8 +32620,7 @@ pub mod spifi {
#[doc = "Possible values of the field `FIELDFORM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIELDFORMR {
- #[doc = "All serial. All fields of the command are serial."]
- ALL_SERIAL,
+ #[doc = "All serial. All fields of the command are serial."] ALL_SERIAL,
#[doc = "Quad/dual data. Data field is quad/dual, other fields are serial."]
QUADDUAL_DATA,
#[doc = "Serial opcode. Opcode field is serial. Other fields are quad/dual."]
@@ -34103,14 +32675,12 @@ pub mod spifi {
#[doc = "Possible values of the field `FRAMEFORM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRAMEFORMR {
- #[doc = "Opcode one byte. Opcode, least-significant byte of address."]
- OPCODE_ONE_BYTE,
+ #[doc = "Opcode one byte. Opcode, least-significant byte of address."] OPCODE_ONE_BYTE,
#[doc = "Opcode two bytes. Opcode, 2 least-significant bytes of address."]
OPCODE_TWO_BYTES,
#[doc = "Opcode three bytes. Opcode, 3 least-significant bytes of address."]
OPCODE_THREE_BYTES,
- #[doc = "Opcode four bytes. Opcode, 4 bytes of address."]
- OPCODE_FOUR_BYTES,
+ #[doc = "Opcode four bytes. Opcode, 4 bytes of address."] OPCODE_FOUR_BYTES,
#[doc = "No opcode three bytes. No opcode, 3 least-significant bytes of address."]
NO_OPCODE_THREE_BYTE,
#[doc = "No opcode, 4 bytes of address."] NO_OPCODE_FOUR_BYTES,
@@ -34247,8 +32817,7 @@ pub mod spifi {
}
#[doc = "Values that can be written to the field `FIELDFORM`"]
pub enum FIELDFORMW {
- #[doc = "All serial. All fields of the command are serial."]
- ALL_SERIAL,
+ #[doc = "All serial. All fields of the command are serial."] ALL_SERIAL,
#[doc = "Quad/dual data. Data field is quad/dual, other fields are serial."]
QUADDUAL_DATA,
#[doc = "Serial opcode. Opcode field is serial. Other fields are quad/dual."]
@@ -34313,14 +32882,12 @@ pub mod spifi {
}
#[doc = "Values that can be written to the field `FRAMEFORM`"]
pub enum FRAMEFORMW {
- #[doc = "Opcode one byte. Opcode, least-significant byte of address."]
- OPCODE_ONE_BYTE,
+ #[doc = "Opcode one byte. Opcode, least-significant byte of address."] OPCODE_ONE_BYTE,
#[doc = "Opcode two bytes. Opcode, 2 least-significant bytes of address."]
OPCODE_TWO_BYTES,
#[doc = "Opcode three bytes. Opcode, 3 least-significant bytes of address."]
OPCODE_THREE_BYTES,
- #[doc = "Opcode four bytes. Opcode, 4 bytes of address."]
- OPCODE_FOUR_BYTES,
+ #[doc = "Opcode four bytes. Opcode, 4 bytes of address."] OPCODE_FOUR_BYTES,
#[doc = "No opcode three bytes. No opcode, 3 least-significant bytes of address."]
NO_OPCODE_THREE_BYTE,
#[doc = "No opcode, 4 bytes of address."] NO_OPCODE_FOUR_BYTES,
@@ -34431,8 +32998,7 @@ pub mod spifi {
};
DOUTR { bits }
}
- #[doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes."]
- #[inline(always)]
+ # [ doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." ] # [ inline ( always ) ]
pub fn intlen(&self) -> INTLENR {
let bits = {
const MASK: u8 = 7;
@@ -34492,8 +33058,7 @@ pub mod spifi {
pub fn dout(&mut self) -> _DOUTW {
_DOUTW { w: self }
}
- #[doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes."]
- #[inline(always)]
+ # [ doc = "Bits 16:18 - This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." ] # [ inline ( always ) ]
pub fn intlen(&mut self) -> _INTLENW {
_INTLENW { w: self }
}
@@ -34772,8 +33337,7 @@ pub mod spifi {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." ] # [ inline ( always ) ]
pub fn mcinit(&self) -> MCINITR {
let bits = {
const MASK: bool = true;
@@ -34782,8 +33346,7 @@ pub mod spifi {
};
MCINITR { bits }
}
- #[doc = "Bit 1 - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash."]
- #[inline(always)]
+ # [ doc = "Bit 1 - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." ] # [ inline ( always ) ]
pub fn cmd(&self) -> CMDR {
let bits = {
const MASK: bool = true;
@@ -34792,8 +33355,7 @@ pub mod spifi {
};
CMDR { bits }
}
- #[doc = "Bit 4 - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." ] # [ inline ( always ) ]
pub fn reset(&self) -> RESETR {
let bits = {
const MASK: bool = true;
@@ -34802,8 +33364,7 @@ pub mod spifi {
};
RESETR { bits }
}
- #[doc = "Bit 5 - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS."]
- #[inline(always)]
+ # [ doc = "Bit 5 - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." ] # [ inline ( always ) ]
pub fn intrq(&self) -> INTRQR {
let bits = {
const MASK: bool = true;
@@ -34835,23 +33396,19 @@ pub mod spifi {
self.bits = bits;
self
}
- #[doc = "Bit 0 - This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." ] # [ inline ( always ) ]
pub fn mcinit(&mut self) -> _MCINITW {
_MCINITW { w: self }
}
- #[doc = "Bit 1 - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash."]
- #[inline(always)]
+ # [ doc = "Bit 1 - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." ] # [ inline ( always ) ]
pub fn cmd(&mut self) -> _CMDW {
_CMDW { w: self }
}
- #[doc = "Bit 4 - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." ] # [ inline ( always ) ]
pub fn reset(&mut self) -> _RESETW {
_RESETW { w: self }
}
- #[doc = "Bit 5 - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS."]
- #[inline(always)]
+ # [ doc = "Bit 5 - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." ] # [ inline ( always ) ]
pub fn intrq(&mut self) -> _INTRQW {
_INTRQW { w: self }
}
@@ -34880,7 +33437,44 @@ pub mod sdmmc {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock { # [ doc = "0x00 - Control Register" ] pub ctrl : CTRL , # [ doc = "0x04 - Power Enable Register" ] pub pwren : PWREN , # [ doc = "0x08 - Clock Divider Register" ] pub clkdiv : CLKDIV , # [ doc = "0x0c - SD Clock Source Register" ] pub clksrc : CLKSRC , # [ doc = "0x10 - Clock Enable Register" ] pub clkena : CLKENA , # [ doc = "0x14 - Time-out Register" ] pub tmout : TMOUT , # [ doc = "0x18 - Card Type Register" ] pub ctype : CTYPE , # [ doc = "0x1c - Block Size Register" ] pub blksiz : BLKSIZ , # [ doc = "0x20 - Byte Count Register" ] pub bytcnt : BYTCNT , # [ doc = "0x24 - Interrupt Mask Register" ] pub intmask : INTMASK , # [ doc = "0x28 - Command Argument Register" ] pub cmdarg : CMDARG , # [ doc = "0x2c - Command Register" ] pub cmd : CMD , # [ doc = "0x30 - Response Register 0" ] pub resp0 : RESP0 , # [ doc = "0x34 - Response Register 1" ] pub resp1 : RESP1 , # [ doc = "0x38 - Response Register 2" ] pub resp2 : RESP2 , # [ doc = "0x3c - Response Register 3" ] pub resp3 : RESP3 , # [ doc = "0x40 - Masked Interrupt Status Register" ] pub mintsts : MINTSTS , # [ doc = "0x44 - Raw Interrupt Status Register" ] pub rintsts : RINTSTS , # [ doc = "0x48 - Status Register" ] pub status : STATUS , # [ doc = "0x4c - FIFO Threshold Watermark Register" ] pub fifoth : FIFOTH , # [ doc = "0x50 - Card Detect Register" ] pub cdetect : CDETECT , # [ doc = "0x54 - Write Protect Register" ] pub wrtprt : WRTPRT , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x5c - Transferred CIU Card Byte Count Register" ] pub tcbcnt : TCBCNT , # [ doc = "0x60 - Transferred Host to BIU-FIFO Byte Count Register" ] pub tbbcnt : TBBCNT , # [ doc = "0x64 - Debounce Count Register" ] pub debnce : DEBNCE , _reserved1 : [ u8 ; 16usize ] , # [ doc = "0x78 - Hardware Reset" ] pub rst_n : RST_N , _reserved2 : [ u8 ; 4usize ] , # [ doc = "0x80 - Bus Mode Register" ] pub bmod : BMOD , # [ doc = "0x84 - Poll Demand Register" ] pub pldmnd : PLDMND , # [ doc = "0x88 - Descriptor List Base Address Register" ] pub dbaddr : DBADDR , # [ doc = "0x8c - Internal DMAC Status Register" ] pub idsts : IDSTS , # [ doc = "0x90 - Internal DMAC Interrupt Enable Register" ] pub idinten : IDINTEN , # [ doc = "0x94 - Current Host Descriptor Address Register" ] pub dscaddr : DSCADDR , # [ doc = "0x98 - Current Buffer Descriptor Address Register" ] pub bufaddr : BUFADDR , }
+ pub struct RegisterBlock {
+ #[doc = "0x00 - Control Register"] pub ctrl: CTRL,
+ #[doc = "0x04 - Power Enable Register"] pub pwren: PWREN,
+ #[doc = "0x08 - Clock Divider Register"] pub clkdiv: CLKDIV,
+ #[doc = "0x0c - SD Clock Source Register"] pub clksrc: CLKSRC,
+ #[doc = "0x10 - Clock Enable Register"] pub clkena: CLKENA,
+ #[doc = "0x14 - Time-out Register"] pub tmout: TMOUT,
+ #[doc = "0x18 - Card Type Register"] pub ctype: CTYPE,
+ #[doc = "0x1c - Block Size Register"] pub blksiz: BLKSIZ,
+ #[doc = "0x20 - Byte Count Register"] pub bytcnt: BYTCNT,
+ #[doc = "0x24 - Interrupt Mask Register"] pub intmask: INTMASK,
+ #[doc = "0x28 - Command Argument Register"] pub cmdarg: CMDARG,
+ #[doc = "0x2c - Command Register"] pub cmd: CMD,
+ #[doc = "0x30 - Response Register 0"] pub resp0: RESP0,
+ #[doc = "0x34 - Response Register 1"] pub resp1: RESP1,
+ #[doc = "0x38 - Response Register 2"] pub resp2: RESP2,
+ #[doc = "0x3c - Response Register 3"] pub resp3: RESP3,
+ #[doc = "0x40 - Masked Interrupt Status Register"] pub mintsts: MINTSTS,
+ #[doc = "0x44 - Raw Interrupt Status Register"] pub rintsts: RINTSTS,
+ #[doc = "0x48 - Status Register"] pub status: STATUS,
+ #[doc = "0x4c - FIFO Threshold Watermark Register"] pub fifoth: FIFOTH,
+ #[doc = "0x50 - Card Detect Register"] pub cdetect: CDETECT,
+ #[doc = "0x54 - Write Protect Register"] pub wrtprt: WRTPRT,
+ _reserved0: [u8; 4usize],
+ #[doc = "0x5c - Transferred CIU Card Byte Count Register"] pub tcbcnt: TCBCNT,
+ #[doc = "0x60 - Transferred Host to BIU-FIFO Byte Count Register"] pub tbbcnt: TBBCNT,
+ #[doc = "0x64 - Debounce Count Register"] pub debnce: DEBNCE,
+ _reserved1: [u8; 16usize],
+ #[doc = "0x78 - Hardware Reset"] pub rst_n: RST_N,
+ _reserved2: [u8; 4usize],
+ #[doc = "0x80 - Bus Mode Register"] pub bmod: BMOD,
+ #[doc = "0x84 - Poll Demand Register"] pub pldmnd: PLDMND,
+ #[doc = "0x88 - Descriptor List Base Address Register"] pub dbaddr: DBADDR,
+ #[doc = "0x8c - Internal DMAC Status Register"] pub idsts: IDSTS,
+ #[doc = "0x90 - Internal DMAC Interrupt Enable Register"] pub idinten: IDINTEN,
+ #[doc = "0x94 - Current Host Descriptor Address Register"] pub dscaddr: DSCADDR,
+ #[doc = "0x98 - Current Buffer Descriptor Address Register"] pub bufaddr: BUFADDR,
+ }
#[doc = "Control Register"]
pub struct CTRL {
register: VolatileCell<u32>,
@@ -35203,11 +33797,7 @@ pub mod sdmmc {
}
#[doc = "Possible values of the field `ABORT_READ_DATA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ABORT_READ_DATAR {
- #[doc = "No change"] NO_CHANGE,
- #[doc = "Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence."]
- ABORT,
- }
+ pub enum ABORT_READ_DATAR {# [ doc = "No change" ] NO_CHANGE , # [ doc = "Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." ] ABORT}
impl ABORT_READ_DATAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -35250,8 +33840,7 @@ pub mod sdmmc {
#[doc = "Possible values of the field `SEND_CCSD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SEND_CCSDR {
- #[doc = "Clear bit if the SD/MMC controller does not reset the bit."]
- CLEAR_BIT,
+ #[doc = "Clear bit if the SD/MMC controller does not reset the bit."] CLEAR_BIT,
#[doc = "Send Command Completion Signal Disable (CCSD) to CE-ATA device"]
SEND_COMMAND_COMPLET,
}
@@ -35343,12 +33932,7 @@ pub mod sdmmc {
}
#[doc = "Possible values of the field `CEATA_DEVICE_INTERRUPT_STATUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CEATA_DEVICE_INTERRUPT_STATUSR {
- #[doc = "Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)"]
- DISABLED,
- #[doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)"]
- ENABLED,
- }
+ pub enum CEATA_DEVICE_INTERRUPT_STATUSR {# [ doc = "Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" ] DISABLED , # [ doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" ] ENABLED}
impl CEATA_DEVICE_INTERRUPT_STATUSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -35454,8 +34038,7 @@ pub mod sdmmc {
#[doc = "Possible values of the field `USE_INTERNAL_DMAC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USE_INTERNAL_DMACR {
- #[doc = "Host. The host performs data transfers through the slave interface"]
- HOST,
+ #[doc = "Host. The host performs data transfers through the slave interface"] HOST,
#[doc = "DMA. Internal DMA used for data transfer"] DMA,
}
impl USE_INTERNAL_DMACR {
@@ -35834,11 +34417,7 @@ pub mod sdmmc {
}
}
#[doc = "Values that can be written to the field `ABORT_READ_DATA`"]
- pub enum ABORT_READ_DATAW {
- #[doc = "No change"] NO_CHANGE,
- #[doc = "Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence."]
- ABORT,
- }
+ pub enum ABORT_READ_DATAW {# [ doc = "No change" ] NO_CHANGE , # [ doc = "Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." ] ABORT}
impl ABORT_READ_DATAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -35867,8 +34446,7 @@ pub mod sdmmc {
pub fn no_change(self) -> &'a mut W {
self.variant(ABORT_READ_DATAW::NO_CHANGE)
}
- #[doc = "Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence."]
- #[inline(always)]
+ # [ doc = "Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." ] # [ inline ( always ) ]
pub fn abort(self) -> &'a mut W {
self.variant(ABORT_READ_DATAW::ABORT)
}
@@ -35892,8 +34470,7 @@ pub mod sdmmc {
}
#[doc = "Values that can be written to the field `SEND_CCSD`"]
pub enum SEND_CCSDW {
- #[doc = "Clear bit if the SD/MMC controller does not reset the bit."]
- CLEAR_BIT,
+ #[doc = "Clear bit if the SD/MMC controller does not reset the bit."] CLEAR_BIT,
#[doc = "Send Command Completion Signal Disable (CCSD) to CE-ATA device"]
SEND_COMMAND_COMPLET,
}
@@ -36007,12 +34584,7 @@ pub mod sdmmc {
}
}
#[doc = "Values that can be written to the field `CEATA_DEVICE_INTERRUPT_STATUS`"]
- pub enum CEATA_DEVICE_INTERRUPT_STATUSW {
- #[doc = "Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)"]
- DISABLED,
- #[doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)"]
- ENABLED,
- }
+ pub enum CEATA_DEVICE_INTERRUPT_STATUSW {# [ doc = "Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" ] DISABLED , # [ doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" ] ENABLED}
impl CEATA_DEVICE_INTERRUPT_STATUSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -36031,21 +34603,16 @@ pub mod sdmmc {
impl<'a> _CEATA_DEVICE_INTERRUPT_STATUSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline(always)]
- pub fn variant(
- self,
- variant: CEATA_DEVICE_INTERRUPT_STATUSW,
- ) -> &'a mut W {
+ pub fn variant(self, variant: CEATA_DEVICE_INTERRUPT_STATUSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
- #[doc = "Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)"]
- #[inline(always)]
+ # [ doc = "Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" ] # [ inline ( always ) ]
pub fn disabled(self) -> &'a mut W {
self.variant(CEATA_DEVICE_INTERRUPT_STATUSW::DISABLED)
}
- #[doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)"]
- #[inline(always)]
+ # [ doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(CEATA_DEVICE_INTERRUPT_STATUSW::ENABLED)
}
@@ -36138,8 +34705,7 @@ pub mod sdmmc {
}
#[doc = "Values that can be written to the field `USE_INTERNAL_DMAC`"]
pub enum USE_INTERNAL_DMACW {
- #[doc = "Host. The host performs data transfers through the slave interface"]
- HOST,
+ #[doc = "Host. The host performs data transfers through the slave interface"] HOST,
#[doc = "DMA. Internal DMA used for data transfer"] DMA,
}
impl USE_INTERNAL_DMACW {
@@ -36199,8 +34765,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts." ] # [ inline ( always ) ]
pub fn controller_reset(&self) -> CONTROLLER_RESETR {
CONTROLLER_RESETR::_from({
const MASK: bool = true;
@@ -36208,8 +34773,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks." ] # [ inline ( always ) ]
pub fn fifo_reset(&self) -> FIFO_RESETR {
FIFO_RESETR::_from({
const MASK: bool = true;
@@ -36217,8 +34781,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks." ] # [ inline ( always ) ]
pub fn dma_reset(&self) -> DMA_RESETR {
DMA_RESETR::_from({
const MASK: bool = true;
@@ -36226,8 +34789,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set." ] # [ inline ( always ) ]
pub fn int_enable(&self) -> INT_ENABLER {
INT_ENABLER::_from({
const MASK: bool = true;
@@ -36244,8 +34806,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state." ] # [ inline ( always ) ]
pub fn send_irq_response(&self) -> SEND_IRQ_RESPONSER {
SEND_IRQ_RESPONSER::_from({
const MASK: bool = true;
@@ -36262,8 +34823,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 9 - Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS." ] # [ inline ( always ) ]
pub fn send_ccsd(&self) -> SEND_CCSDR {
SEND_CCSDR::_from({
const MASK: bool = true;
@@ -36271,8 +34831,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 10 - Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit." ] # [ inline ( always ) ]
pub fn send_auto_stop(&self) -> SEND_AUTO_STOPR {
SEND_AUTO_STOPR::_from({
const MASK: bool = true;
@@ -36280,19 +34839,15 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 11 - CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit."]
- #[inline(always)]
- pub fn ceata_device_interrupt_status(
- &self,
- ) -> CEATA_DEVICE_INTERRUPT_STATUSR {
+ # [ doc = "Bit 11 - CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit." ] # [ inline ( always ) ]
+ pub fn ceata_device_interrupt_status(&self) -> CEATA_DEVICE_INTERRUPT_STATUSR {
CEATA_DEVICE_INTERRUPT_STATUSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 16 - Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." ] # [ inline ( always ) ]
pub fn card_voltage_a0(&self) -> CARD_VOLTAGE_A0R {
let bits = {
const MASK: bool = true;
@@ -36301,8 +34856,7 @@ pub mod sdmmc {
};
CARD_VOLTAGE_A0R { bits }
}
- #[doc = "Bit 17 - Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." ] # [ inline ( always ) ]
pub fn card_voltage_a1(&self) -> CARD_VOLTAGE_A1R {
let bits = {
const MASK: bool = true;
@@ -36311,8 +34865,7 @@ pub mod sdmmc {
};
CARD_VOLTAGE_A1R { bits }
}
- #[doc = "Bit 18 - Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." ] # [ inline ( always ) ]
pub fn card_voltage_a2(&self) -> CARD_VOLTAGE_A2R {
let bits = {
const MASK: bool = true;
@@ -36343,23 +34896,19 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts." ] # [ inline ( always ) ]
pub fn controller_reset(&mut self) -> _CONTROLLER_RESETW {
_CONTROLLER_RESETW { w: self }
}
- #[doc = "Bit 1 - Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks." ] # [ inline ( always ) ]
pub fn fifo_reset(&mut self) -> _FIFO_RESETW {
_FIFO_RESETW { w: self }
}
- #[doc = "Bit 2 - Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks." ] # [ inline ( always ) ]
pub fn dma_reset(&mut self) -> _DMA_RESETW {
_DMA_RESETW { w: self }
}
- #[doc = "Bit 4 - Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set." ] # [ inline ( always ) ]
pub fn int_enable(&mut self) -> _INT_ENABLEW {
_INT_ENABLEW { w: self }
}
@@ -36368,8 +34917,7 @@ pub mod sdmmc {
pub fn read_wait(&mut self) -> _READ_WAITW {
_READ_WAITW { w: self }
}
- #[doc = "Bit 7 - Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state." ] # [ inline ( always ) ]
pub fn send_irq_response(&mut self) -> _SEND_IRQ_RESPONSEW {
_SEND_IRQ_RESPONSEW { w: self }
}
@@ -36378,35 +34926,27 @@ pub mod sdmmc {
pub fn abort_read_data(&mut self) -> _ABORT_READ_DATAW {
_ABORT_READ_DATAW { w: self }
}
- #[doc = "Bit 9 - Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS." ] # [ inline ( always ) ]
pub fn send_ccsd(&mut self) -> _SEND_CCSDW {
_SEND_CCSDW { w: self }
}
- #[doc = "Bit 10 - Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit." ] # [ inline ( always ) ]
pub fn send_auto_stop(&mut self) -> _SEND_AUTO_STOPW {
_SEND_AUTO_STOPW { w: self }
}
- #[doc = "Bit 11 - CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit."]
- #[inline(always)]
- pub fn ceata_device_interrupt_status(
- &mut self,
- ) -> _CEATA_DEVICE_INTERRUPT_STATUSW {
+ # [ doc = "Bit 11 - CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit." ] # [ inline ( always ) ]
+ pub fn ceata_device_interrupt_status(&mut self) -> _CEATA_DEVICE_INTERRUPT_STATUSW {
_CEATA_DEVICE_INTERRUPT_STATUSW { w: self }
}
- #[doc = "Bit 16 - Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." ] # [ inline ( always ) ]
pub fn card_voltage_a0(&mut self) -> _CARD_VOLTAGE_A0W {
_CARD_VOLTAGE_A0W { w: self }
}
- #[doc = "Bit 17 - Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." ] # [ inline ( always ) ]
pub fn card_voltage_a1(&mut self) -> _CARD_VOLTAGE_A1W {
_CARD_VOLTAGE_A1W { w: self }
}
- #[doc = "Bit 18 - Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." ] # [ inline ( always ) ]
pub fn card_voltage_a2(&mut self) -> _CARD_VOLTAGE_A2W {
_CARD_VOLTAGE_A2W { w: self }
}
@@ -36517,8 +35057,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Optional feature: port can be used as general-purpose output on the SD_POW pin."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Optional feature: port can be used as general-purpose output on the SD_POW pin." ] # [ inline ( always ) ]
pub fn power_enable(&self) -> POWER_ENABLER {
let bits = {
const MASK: bool = true;
@@ -36540,8 +35079,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Optional feature: port can be used as general-purpose output on the SD_POW pin."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Optional feature: port can be used as general-purpose output on the SD_POW pin." ] # [ inline ( always ) ]
pub fn power_enable(&mut self) -> _POWER_ENABLEW {
_POWER_ENABLEW { w: self }
}
@@ -36707,8 +35245,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on." ] # [ inline ( always ) ]
pub fn clk_divider0(&self) -> CLK_DIVIDER0R {
let bits = {
const MASK: u8 = 255;
@@ -36717,8 +35254,7 @@ pub mod sdmmc {
};
CLK_DIVIDER0R { bits }
}
- #[doc = "Bits 8:15 - Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." ] # [ inline ( always ) ]
pub fn clk_divider1(&self) -> CLK_DIVIDER1R {
let bits = {
const MASK: u8 = 255;
@@ -36727,8 +35263,7 @@ pub mod sdmmc {
};
CLK_DIVIDER1R { bits }
}
- #[doc = "Bits 16:23 - Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." ] # [ inline ( always ) ]
pub fn clk_divider2(&self) -> CLK_DIVIDER2R {
let bits = {
const MASK: u8 = 255;
@@ -36737,8 +35272,7 @@ pub mod sdmmc {
};
CLK_DIVIDER2R { bits }
}
- #[doc = "Bits 24:31 - Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported."]
- #[inline(always)]
+ # [ doc = "Bits 24:31 - Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." ] # [ inline ( always ) ]
pub fn clk_divider3(&self) -> CLK_DIVIDER3R {
let bits = {
const MASK: u8 = 255;
@@ -36760,23 +35294,19 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on." ] # [ inline ( always ) ]
pub fn clk_divider0(&mut self) -> _CLK_DIVIDER0W {
_CLK_DIVIDER0W { w: self }
}
- #[doc = "Bits 8:15 - Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." ] # [ inline ( always ) ]
pub fn clk_divider1(&mut self) -> _CLK_DIVIDER1W {
_CLK_DIVIDER1W { w: self }
}
- #[doc = "Bits 16:23 - Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." ] # [ inline ( always ) ]
pub fn clk_divider2(&mut self) -> _CLK_DIVIDER2W {
_CLK_DIVIDER2W { w: self }
}
- #[doc = "Bits 24:31 - Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported."]
- #[inline(always)]
+ # [ doc = "Bits 24:31 - Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." ] # [ inline ( always ) ]
pub fn clk_divider3(&mut self) -> _CLK_DIVIDER3W {
_CLK_DIVIDER3W { w: self }
}
@@ -36864,8 +35394,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." ] # [ inline ( always ) ]
pub fn clk_source(&self) -> CLK_SOURCER {
let bits = {
const MASK: u8 = 3;
@@ -36887,8 +35416,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." ] # [ inline ( always ) ]
pub fn clk_source(&mut self) -> _CLK_SOURCEW {
_CLK_SOURCEW { w: self }
}
@@ -37038,8 +35566,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Clock-enable control for SD card clock. One MMC card clock supported. 0 - Clock disabled 1 - Clock enabled"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Clock-enable control for SD card clock. One MMC card clock supported. 0 - Clock disabled 1 - Clock enabled" ] # [ inline ( always ) ]
pub fn cclk_enable(&self) -> CCLK_ENABLER {
let bits = {
const MASK: bool = true;
@@ -37048,8 +35575,7 @@ pub mod sdmmc {
};
CCLK_ENABLER { bits }
}
- #[doc = "Bit 16 - Low-power control for SD card clock. One MMC card clock supported. 0 - Non-low-power mode 1 - Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Low-power control for SD card clock. One MMC card clock supported. 0 - Non-low-power mode 1 - Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." ] # [ inline ( always ) ]
pub fn cclk_low_power(&self) -> CCLK_LOW_POWERR {
let bits = {
const MASK: bool = true;
@@ -37071,13 +35597,11 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Clock-enable control for SD card clock. One MMC card clock supported. 0 - Clock disabled 1 - Clock enabled"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Clock-enable control for SD card clock. One MMC card clock supported. 0 - Clock disabled 1 - Clock enabled" ] # [ inline ( always ) ]
pub fn cclk_enable(&mut self) -> _CCLK_ENABLEW {
_CCLK_ENABLEW { w: self }
}
- #[doc = "Bit 16 - Low-power control for SD card clock. One MMC card clock supported. 0 - Non-low-power mode 1 - Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Low-power control for SD card clock. One MMC card clock supported. 0 - Non-low-power mode 1 - Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." ] # [ inline ( always ) ]
pub fn cclk_low_power(&mut self) -> _CCLK_LOW_POWERW {
_CCLK_LOW_POWERW { w: self }
}
@@ -37191,8 +35715,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Response time-out value. Value is in number of card output clocks - cclk_out."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Response time-out value. Value is in number of card output clocks - cclk_out." ] # [ inline ( always ) ]
pub fn response_timeout(&self) -> RESPONSE_TIMEOUTR {
let bits = {
const MASK: u8 = 255;
@@ -37201,8 +35724,7 @@ pub mod sdmmc {
};
RESPONSE_TIMEOUTR { bits }
}
- #[doc = "Bits 8:31 - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card."]
- #[inline(always)]
+ # [ doc = "Bits 8:31 - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." ] # [ inline ( always ) ]
pub fn data_timeout(&self) -> DATA_TIMEOUTR {
let bits = {
const MASK: u32 = 16777215;
@@ -37224,13 +35746,11 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Response time-out value. Value is in number of card output clocks - cclk_out."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Response time-out value. Value is in number of card output clocks - cclk_out." ] # [ inline ( always ) ]
pub fn response_timeout(&mut self) -> _RESPONSE_TIMEOUTW {
_RESPONSE_TIMEOUTW { w: self }
}
- #[doc = "Bits 8:31 - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card."]
- #[inline(always)]
+ # [ doc = "Bits 8:31 - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." ] # [ inline ( always ) ]
pub fn data_timeout(&mut self) -> _DATA_TIMEOUTW {
_DATA_TIMEOUTW { w: self }
}
@@ -37380,8 +35900,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." ] # [ inline ( always ) ]
pub fn card_width0(&self) -> CARD_WIDTH0R {
let bits = {
const MASK: bool = true;
@@ -37413,8 +35932,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." ] # [ inline ( always ) ]
pub fn card_width0(&mut self) -> _CARD_WIDTH0W {
_CARD_WIDTH0W { w: self }
}
@@ -37619,8 +36137,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." ] # [ inline ( always ) ]
pub fn byte_count(&self) -> BYTE_COUNTR {
let bits = {
const MASK: u32 = 4294967295;
@@ -37642,8 +36159,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." ] # [ inline ( always ) ]
pub fn byte_count(&mut self) -> _BYTE_COUNTW {
_BYTE_COUNTW { w: self }
}
@@ -38453,8 +36969,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn cdet(&self) -> CDETR {
let bits = {
const MASK: bool = true;
@@ -38463,8 +36978,7 @@ pub mod sdmmc {
};
CDETR { bits }
}
- #[doc = "Bit 1 - Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn re(&self) -> RER {
let bits = {
const MASK: bool = true;
@@ -38473,8 +36987,7 @@ pub mod sdmmc {
};
RER { bits }
}
- #[doc = "Bit 2 - Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn cdone(&self) -> CDONER {
let bits = {
const MASK: bool = true;
@@ -38483,8 +36996,7 @@ pub mod sdmmc {
};
CDONER { bits }
}
- #[doc = "Bit 3 - Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn dto(&self) -> DTOR {
let bits = {
const MASK: bool = true;
@@ -38493,8 +37005,7 @@ pub mod sdmmc {
};
DTOR { bits }
}
- #[doc = "Bit 4 - Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn txdr(&self) -> TXDRR {
let bits = {
const MASK: bool = true;
@@ -38503,8 +37014,7 @@ pub mod sdmmc {
};
TXDRR { bits }
}
- #[doc = "Bit 5 - Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn rxdr(&self) -> RXDRR {
let bits = {
const MASK: bool = true;
@@ -38513,8 +37023,7 @@ pub mod sdmmc {
};
RXDRR { bits }
}
- #[doc = "Bit 6 - Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn rcrc(&self) -> RCRCR {
let bits = {
const MASK: bool = true;
@@ -38523,8 +37032,7 @@ pub mod sdmmc {
};
RCRCR { bits }
}
- #[doc = "Bit 7 - Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn dcrc(&self) -> DCRCR {
let bits = {
const MASK: bool = true;
@@ -38533,8 +37041,7 @@ pub mod sdmmc {
};
DCRCR { bits }
}
- #[doc = "Bit 8 - Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn rto(&self) -> RTOR {
let bits = {
const MASK: bool = true;
@@ -38543,8 +37050,7 @@ pub mod sdmmc {
};
RTOR { bits }
}
- #[doc = "Bit 9 - Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn drto(&self) -> DRTOR {
let bits = {
const MASK: bool = true;
@@ -38553,8 +37059,7 @@ pub mod sdmmc {
};
DRTOR { bits }
}
- #[doc = "Bit 10 - Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn hto(&self) -> HTOR {
let bits = {
const MASK: bool = true;
@@ -38563,8 +37068,7 @@ pub mod sdmmc {
};
HTOR { bits }
}
- #[doc = "Bit 11 - FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 11 - FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn frun(&self) -> FRUNR {
let bits = {
const MASK: bool = true;
@@ -38573,8 +37077,7 @@ pub mod sdmmc {
};
FRUNR { bits }
}
- #[doc = "Bit 12 - Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn hle(&self) -> HLER {
let bits = {
const MASK: bool = true;
@@ -38583,8 +37086,7 @@ pub mod sdmmc {
};
HLER { bits }
}
- #[doc = "Bit 13 - Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn sbe(&self) -> SBER {
let bits = {
const MASK: bool = true;
@@ -38593,8 +37095,7 @@ pub mod sdmmc {
};
SBER { bits }
}
- #[doc = "Bit 14 - Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn acd(&self) -> ACDR {
let bits = {
const MASK: bool = true;
@@ -38603,8 +37104,7 @@ pub mod sdmmc {
};
ACDR { bits }
}
- #[doc = "Bit 15 - End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn ebe(&self) -> EBER {
let bits = {
const MASK: bool = true;
@@ -38613,8 +37113,7 @@ pub mod sdmmc {
};
EBER { bits }
}
- #[doc = "Bit 16 - Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." ] # [ inline ( always ) ]
pub fn sdio_int_mask(&self) -> SDIO_INT_MASKR {
let bits = {
const MASK: bool = true;
@@ -38636,88 +37135,71 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn cdet(&mut self) -> _CDETW {
_CDETW { w: self }
}
- #[doc = "Bit 1 - Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn re(&mut self) -> _REW {
_REW { w: self }
}
- #[doc = "Bit 2 - Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn cdone(&mut self) -> _CDONEW {
_CDONEW { w: self }
}
- #[doc = "Bit 3 - Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn dto(&mut self) -> _DTOW {
_DTOW { w: self }
}
- #[doc = "Bit 4 - Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn txdr(&mut self) -> _TXDRW {
_TXDRW { w: self }
}
- #[doc = "Bit 5 - Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn rxdr(&mut self) -> _RXDRW {
_RXDRW { w: self }
}
- #[doc = "Bit 6 - Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn rcrc(&mut self) -> _RCRCW {
_RCRCW { w: self }
}
- #[doc = "Bit 7 - Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn dcrc(&mut self) -> _DCRCW {
_DCRCW { w: self }
}
- #[doc = "Bit 8 - Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn rto(&mut self) -> _RTOW {
_RTOW { w: self }
}
- #[doc = "Bit 9 - Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn drto(&mut self) -> _DRTOW {
_DRTOW { w: self }
}
- #[doc = "Bit 10 - Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn hto(&mut self) -> _HTOW {
_HTOW { w: self }
}
- #[doc = "Bit 11 - FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 11 - FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn frun(&mut self) -> _FRUNW {
_FRUNW { w: self }
}
- #[doc = "Bit 12 - Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn hle(&mut self) -> _HLEW {
_HLEW { w: self }
}
- #[doc = "Bit 13 - Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn sbe(&mut self) -> _SBEW {
_SBEW { w: self }
}
- #[doc = "Bit 14 - Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn acd(&mut self) -> _ACDW {
_ACDW { w: self }
}
- #[doc = "Bit 15 - End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." ] # [ inline ( always ) ]
pub fn ebe(&mut self) -> _EBEW {
_EBEW { w: self }
}
- #[doc = "Bit 16 - Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." ] # [ inline ( always ) ]
pub fn sdio_int_mask(&mut self) -> _SDIO_INT_MASKW {
_SDIO_INT_MASKW { w: self }
}
@@ -39169,10 +37651,8 @@ pub mod sdmmc {
#[doc = "Possible values of the field `SEND_AUTO_STOP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SEND_AUTO_STOPR {
- #[doc = "No stop command sent at end of data transfer"]
- NO_STOP_COMMAND_SENT,
- #[doc = "Send stop command at end of data transfer"]
- SEND_STOP_COMMAND_AT,
+ #[doc = "No stop command sent at end of data transfer"] NO_STOP_COMMAND_SENT,
+ #[doc = "Send stop command at end of data transfer"] SEND_STOP_COMMAND_AT,
}
impl SEND_AUTO_STOPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -39262,12 +37742,7 @@ pub mod sdmmc {
}
#[doc = "Possible values of the field `STOP_ABORT_CMD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum STOP_ABORT_CMDR {
- #[doc = "Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0."]
- DISABLED,
- #[doc = "Enabled. Stop or abort command intended to stop current data transfer in progress."]
- ENABLED,
- }
+ pub enum STOP_ABORT_CMDR {# [ doc = "Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." ] DISABLED , # [ doc = "Enabled. Stop or abort command intended to stop current data transfer in progress." ] ENABLED}
impl STOP_ABORT_CMDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -39309,12 +37784,7 @@ pub mod sdmmc {
}
#[doc = "Possible values of the field `SEND_INITIALIZATION`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SEND_INITIALIZATIONR {
- #[doc = "No. Do not send initialization sequence (80 clocks of 1) before sending this command."]
- NO,
- #[doc = "Send. Send initialization sequence before sending this command."]
- SEND,
- }
+ pub enum SEND_INITIALIZATIONR {# [ doc = "No. Do not send initialization sequence (80 clocks of 1) before sending this command." ] NO , # [ doc = "Send. Send initialization sequence before sending this command." ] SEND}
impl SEND_INITIALIZATIONR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -39356,11 +37826,7 @@ pub mod sdmmc {
}
#[doc = "Possible values of the field `UPDATE_CLOCK_REGISTERS_ONLY`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UPDATE_CLOCK_REGISTERS_ONLYR {
- #[doc = "Normal. Normal command sequence"] NORMAL,
- #[doc = "No. Do not send commands, just update clock register value into card clock domain"]
- NO,
- }
+ pub enum UPDATE_CLOCK_REGISTERS_ONLYR {# [ doc = "Normal. Normal command sequence" ] NORMAL , # [ doc = "No. Do not send commands, just update clock register value into card clock domain" ] NO}
impl UPDATE_CLOCK_REGISTERS_ONLYR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -39402,12 +37868,7 @@ pub mod sdmmc {
}
#[doc = "Possible values of the field `READ_CEATA_DEVICE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum READ_CEATA_DEVICER {
- #[doc = "No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device."]
- NO_READ,
- #[doc = "Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device."]
- READ,
- }
+ pub enum READ_CEATA_DEVICER {# [ doc = "No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." ] NO_READ , # [ doc = "Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." ] READ}
impl READ_CEATA_DEVICER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -39449,12 +37910,7 @@ pub mod sdmmc {
}
#[doc = "Possible values of the field `CCS_EXPECTED`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CCS_EXPECTEDR {
- #[doc = "Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device."]
- DISABLED,
- #[doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device."]
- ENABLED,
- }
+ pub enum CCS_EXPECTEDR {# [ doc = "Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." ] DISABLED , # [ doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." ] ENABLED}
impl CCS_EXPECTEDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -39606,8 +38062,7 @@ pub mod sdmmc {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum VOLT_SWITCHR {
#[doc = "Disabled. No voltage switching"] DISABLED,
- #[doc = "Enabled. Voltage switching enabled; must be set for CMD11 only"]
- ENABLED,
+ #[doc = "Enabled. Voltage switching enabled; must be set for CMD11 only"] ENABLED,
}
impl VOLT_SWITCHR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -40022,10 +38477,8 @@ pub mod sdmmc {
}
#[doc = "Values that can be written to the field `SEND_AUTO_STOP`"]
pub enum SEND_AUTO_STOPW {
- #[doc = "No stop command sent at end of data transfer"]
- NO_STOP_COMMAND_SENT,
- #[doc = "Send stop command at end of data transfer"]
- SEND_STOP_COMMAND_AT,
+ #[doc = "No stop command sent at end of data transfer"] NO_STOP_COMMAND_SENT,
+ #[doc = "Send stop command at end of data transfer"] SEND_STOP_COMMAND_AT,
}
impl SEND_AUTO_STOPW {
#[allow(missing_docs)]
@@ -40137,12 +38590,7 @@ pub mod sdmmc {
}
}
#[doc = "Values that can be written to the field `STOP_ABORT_CMD`"]
- pub enum STOP_ABORT_CMDW {
- #[doc = "Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0."]
- DISABLED,
- #[doc = "Enabled. Stop or abort command intended to stop current data transfer in progress."]
- ENABLED,
- }
+ pub enum STOP_ABORT_CMDW {# [ doc = "Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." ] DISABLED , # [ doc = "Enabled. Stop or abort command intended to stop current data transfer in progress." ] ENABLED}
impl STOP_ABORT_CMDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -40166,13 +38614,11 @@ pub mod sdmmc {
self.bit(variant._bits())
}
}
- #[doc = "Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0."]
- #[inline(always)]
+ # [ doc = "Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." ] # [ inline ( always ) ]
pub fn disabled(self) -> &'a mut W {
self.variant(STOP_ABORT_CMDW::DISABLED)
}
- #[doc = "Enabled. Stop or abort command intended to stop current data transfer in progress."]
- #[inline(always)]
+ # [ doc = "Enabled. Stop or abort command intended to stop current data transfer in progress." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(STOP_ABORT_CMDW::ENABLED)
}
@@ -40195,12 +38641,7 @@ pub mod sdmmc {
}
}
#[doc = "Values that can be written to the field `SEND_INITIALIZATION`"]
- pub enum SEND_INITIALIZATIONW {
- #[doc = "No. Do not send initialization sequence (80 clocks of 1) before sending this command."]
- NO,
- #[doc = "Send. Send initialization sequence before sending this command."]
- SEND,
- }
+ pub enum SEND_INITIALIZATIONW {# [ doc = "No. Do not send initialization sequence (80 clocks of 1) before sending this command." ] NO , # [ doc = "Send. Send initialization sequence before sending this command." ] SEND}
impl SEND_INITIALIZATIONW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -40224,8 +38665,7 @@ pub mod sdmmc {
self.bit(variant._bits())
}
}
- #[doc = "No. Do not send initialization sequence (80 clocks of 1) before sending this command."]
- #[inline(always)]
+ # [ doc = "No. Do not send initialization sequence (80 clocks of 1) before sending this command." ] # [ inline ( always ) ]
pub fn no(self) -> &'a mut W {
self.variant(SEND_INITIALIZATIONW::NO)
}
@@ -40253,11 +38693,7 @@ pub mod sdmmc {
}
}
#[doc = "Values that can be written to the field `UPDATE_CLOCK_REGISTERS_ONLY`"]
- pub enum UPDATE_CLOCK_REGISTERS_ONLYW {
- #[doc = "Normal. Normal command sequence"] NORMAL,
- #[doc = "No. Do not send commands, just update clock register value into card clock domain"]
- NO,
- }
+ pub enum UPDATE_CLOCK_REGISTERS_ONLYW {# [ doc = "Normal. Normal command sequence" ] NORMAL , # [ doc = "No. Do not send commands, just update clock register value into card clock domain" ] NO}
impl UPDATE_CLOCK_REGISTERS_ONLYW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -40276,10 +38712,7 @@ pub mod sdmmc {
impl<'a> _UPDATE_CLOCK_REGISTERS_ONLYW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline(always)]
- pub fn variant(
- self,
- variant: UPDATE_CLOCK_REGISTERS_ONLYW,
- ) -> &'a mut W {
+ pub fn variant(self, variant: UPDATE_CLOCK_REGISTERS_ONLYW) -> &'a mut W {
{
self.bit(variant._bits())
}
@@ -40289,8 +38722,7 @@ pub mod sdmmc {
pub fn normal(self) -> &'a mut W {
self.variant(UPDATE_CLOCK_REGISTERS_ONLYW::NORMAL)
}
- #[doc = "No. Do not send commands, just update clock register value into card clock domain"]
- #[inline(always)]
+ # [ doc = "No. Do not send commands, just update clock register value into card clock domain" ] # [ inline ( always ) ]
pub fn no(self) -> &'a mut W {
self.variant(UPDATE_CLOCK_REGISTERS_ONLYW::NO)
}
@@ -40313,12 +38745,7 @@ pub mod sdmmc {
}
}
#[doc = "Values that can be written to the field `READ_CEATA_DEVICE`"]
- pub enum READ_CEATA_DEVICEW {
- #[doc = "No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device."]
- NO_READ,
- #[doc = "Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device."]
- READ,
- }
+ pub enum READ_CEATA_DEVICEW {# [ doc = "No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." ] NO_READ , # [ doc = "Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." ] READ}
impl READ_CEATA_DEVICEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -40342,8 +38769,7 @@ pub mod sdmmc {
self.bit(variant._bits())
}
}
- #[doc = "No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device."]
- #[inline(always)]
+ # [ doc = "No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." ] # [ inline ( always ) ]
pub fn no_read(self) -> &'a mut W {
self.variant(READ_CEATA_DEVICEW::NO_READ)
}
@@ -40371,12 +38797,7 @@ pub mod sdmmc {
}
}
#[doc = "Values that can be written to the field `CCS_EXPECTED`"]
- pub enum CCS_EXPECTEDW {
- #[doc = "Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device."]
- DISABLED,
- #[doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device."]
- ENABLED,
- }
+ pub enum CCS_EXPECTEDW {# [ doc = "Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." ] DISABLED , # [ doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." ] ENABLED}
impl CCS_EXPECTEDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -40400,13 +38821,11 @@ pub mod sdmmc {
self.bit(variant._bits())
}
}
- #[doc = "Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device."]
- #[inline(always)]
+ # [ doc = "Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." ] # [ inline ( always ) ]
pub fn disabled(self) -> &'a mut W {
self.variant(CCS_EXPECTEDW::DISABLED)
}
- #[doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device."]
- #[inline(always)]
+ # [ doc = "Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(CCS_EXPECTEDW::ENABLED)
}
@@ -40556,8 +38975,7 @@ pub mod sdmmc {
#[doc = "Values that can be written to the field `VOLT_SWITCH`"]
pub enum VOLT_SWITCHW {
#[doc = "Disabled. No voltage switching"] DISABLED,
- #[doc = "Enabled. Voltage switching enabled; must be set for CMD11 only"]
- ENABLED,
+ #[doc = "Enabled. Voltage switching enabled; must be set for CMD11 only"] ENABLED,
}
impl VOLT_SWITCHW {
#[allow(missing_docs)]
@@ -40667,8 +39085,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller." ] # [ inline ( always ) ]
pub fn check_response_crc(&self) -> CHECK_RESPONSE_CRCR {
CHECK_RESPONSE_CRCR::_from({
const MASK: bool = true;
@@ -40703,8 +39120,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 12 - Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card." ] # [ inline ( always ) ]
pub fn send_auto_stop(&self) -> SEND_AUTO_STOPR {
SEND_AUTO_STOPR::_from({
const MASK: bool = true;
@@ -40712,8 +39128,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 13 - Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command." ] # [ inline ( always ) ]
pub fn wait_prvdata_complete(&self) -> WAIT_PRVDATA_COMPLETER {
WAIT_PRVDATA_COMPLETER::_from({
const MASK: bool = true;
@@ -40721,8 +39136,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 14 - Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot." ] # [ inline ( always ) ]
pub fn stop_abort_cmd(&self) -> STOP_ABORT_CMDR {
STOP_ABORT_CMDR::_from({
const MASK: bool = true;
@@ -40730,8 +39144,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 15 - Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory)." ] # [ inline ( always ) ]
pub fn send_initialization(&self) -> SEND_INITIALIZATIONR {
SEND_INITIALIZATIONR::_from({
const MASK: bool = true;
@@ -40739,19 +39152,15 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 21 - Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
- #[inline(always)]
- pub fn update_clock_registers_only(
- &self,
- ) -> UPDATE_CLOCK_REGISTERS_ONLYR {
+ # [ doc = "Bit 21 - Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards." ] # [ inline ( always ) ]
+ pub fn update_clock_registers_only(&self) -> UPDATE_CLOCK_REGISTERS_ONLYR {
UPDATE_CLOCK_REGISTERS_ONLYR::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 22 - Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device." ] # [ inline ( always ) ]
pub fn read_ceata_device(&self) -> READ_CEATA_DEVICER {
READ_CEATA_DEVICER::_from({
const MASK: bool = true;
@@ -40759,8 +39168,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 23 - CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked."]
- #[inline(always)]
+ # [ doc = "Bit 23 - CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked." ] # [ inline ( always ) ]
pub fn ccs_expected(&self) -> CCS_EXPECTEDR {
CCS_EXPECTEDR::_from({
const MASK: bool = true;
@@ -40768,8 +39176,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 24 - Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." ] # [ inline ( always ) ]
pub fn enable_boot(&self) -> ENABLE_BOOTR {
let bits = {
const MASK: bool = true;
@@ -40778,8 +39185,7 @@ pub mod sdmmc {
};
ENABLE_BOOTR { bits }
}
- #[doc = "Bit 25 - Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." ] # [ inline ( always ) ]
pub fn expect_boot_ack(&self) -> EXPECT_BOOT_ACKR {
let bits = {
const MASK: bool = true;
@@ -40788,8 +39194,7 @@ pub mod sdmmc {
};
EXPECT_BOOT_ACKR { bits }
}
- #[doc = "Bit 26 - Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." ] # [ inline ( always ) ]
pub fn disable_boot(&self) -> DISABLE_BOOTR {
let bits = {
const MASK: bool = true;
@@ -40816,8 +39221,7 @@ pub mod sdmmc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 31 - Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." ] # [ inline ( always ) ]
pub fn start_cmd(&self) -> START_CMDR {
let bits = {
const MASK: bool = true;
@@ -40854,8 +39258,7 @@ pub mod sdmmc {
pub fn response_length(&mut self) -> _RESPONSE_LENGTHW {
_RESPONSE_LENGTHW { w: self }
}
- #[doc = "Bit 8 - Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller." ] # [ inline ( always ) ]
pub fn check_response_crc(&mut self) -> _CHECK_RESPONSE_CRCW {
_CHECK_RESPONSE_CRCW { w: self }
}
@@ -40874,55 +39277,43 @@ pub mod sdmmc {
pub fn transfer_mode(&mut self) -> _TRANSFER_MODEW {
_TRANSFER_MODEW { w: self }
}
- #[doc = "Bit 12 - Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card." ] # [ inline ( always ) ]
pub fn send_auto_stop(&mut self) -> _SEND_AUTO_STOPW {
_SEND_AUTO_STOPW { w: self }
}
- #[doc = "Bit 13 - Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command." ] # [ inline ( always ) ]
pub fn wait_prvdata_complete(&mut self) -> _WAIT_PRVDATA_COMPLETEW {
_WAIT_PRVDATA_COMPLETEW { w: self }
}
- #[doc = "Bit 14 - Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot." ] # [ inline ( always ) ]
pub fn stop_abort_cmd(&mut self) -> _STOP_ABORT_CMDW {
_STOP_ABORT_CMDW { w: self }
}
- #[doc = "Bit 15 - Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory)." ] # [ inline ( always ) ]
pub fn send_initialization(&mut self) -> _SEND_INITIALIZATIONW {
_SEND_INITIALIZATIONW { w: self }
}
- #[doc = "Bit 21 - Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
- #[inline(always)]
- pub fn update_clock_registers_only(
- &mut self,
- ) -> _UPDATE_CLOCK_REGISTERS_ONLYW {
+ # [ doc = "Bit 21 - Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards." ] # [ inline ( always ) ]
+ pub fn update_clock_registers_only(&mut self) -> _UPDATE_CLOCK_REGISTERS_ONLYW {
_UPDATE_CLOCK_REGISTERS_ONLYW { w: self }
}
- #[doc = "Bit 22 - Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device." ] # [ inline ( always ) ]
pub fn read_ceata_device(&mut self) -> _READ_CEATA_DEVICEW {
_READ_CEATA_DEVICEW { w: self }
}
- #[doc = "Bit 23 - CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked."]
- #[inline(always)]
+ # [ doc = "Bit 23 - CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked." ] # [ inline ( always ) ]
pub fn ccs_expected(&mut self) -> _CCS_EXPECTEDW {
_CCS_EXPECTEDW { w: self }
}
- #[doc = "Bit 24 - Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." ] # [ inline ( always ) ]
pub fn enable_boot(&mut self) -> _ENABLE_BOOTW {
_ENABLE_BOOTW { w: self }
}
- #[doc = "Bit 25 - Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." ] # [ inline ( always ) ]
pub fn expect_boot_ack(&mut self) -> _EXPECT_BOOT_ACKW {
_EXPECT_BOOT_ACKW { w: self }
}
- #[doc = "Bit 26 - Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." ] # [ inline ( always ) ]
pub fn disable_boot(&mut self) -> _DISABLE_BOOTW {
_DISABLE_BOOTW { w: self }
}
@@ -40936,8 +39327,7 @@ pub mod sdmmc {
pub fn volt_switch(&mut self) -> _VOLT_SWITCHW {
_VOLT_SWITCHW { w: self }
}
- #[doc = "Bit 31 - Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." ] # [ inline ( always ) ]
pub fn start_cmd(&mut self) -> _START_CMDW {
_START_CMDW { w: self }
}
@@ -41027,8 +39417,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always short for them. For information on when CIU sends auto-stop commands, refer to Auto-Stop ."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always short for them. For information on when CIU sends auto-stop commands, refer to Auto-Stop ." ] # [ inline ( always ) ]
pub fn response1(&self) -> RESPONSE1R {
let bits = {
const MASK: u32 = 4294967295;
@@ -41517,8 +39906,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn cdet(&self) -> CDETR {
let bits = {
const MASK: bool = true;
@@ -41527,8 +39915,7 @@ pub mod sdmmc {
};
CDETR { bits }
}
- #[doc = "Bit 1 - Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn re(&self) -> RER {
let bits = {
const MASK: bool = true;
@@ -41537,8 +39924,7 @@ pub mod sdmmc {
};
RER { bits }
}
- #[doc = "Bit 2 - Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn cdone(&self) -> CDONER {
let bits = {
const MASK: bool = true;
@@ -41547,8 +39933,7 @@ pub mod sdmmc {
};
CDONER { bits }
}
- #[doc = "Bit 3 - Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn dto(&self) -> DTOR {
let bits = {
const MASK: bool = true;
@@ -41557,8 +39942,7 @@ pub mod sdmmc {
};
DTOR { bits }
}
- #[doc = "Bit 4 - Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn txdr(&self) -> TXDRR {
let bits = {
const MASK: bool = true;
@@ -41567,8 +39951,7 @@ pub mod sdmmc {
};
TXDRR { bits }
}
- #[doc = "Bit 5 - Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn rxdr(&self) -> RXDRR {
let bits = {
const MASK: bool = true;
@@ -41577,8 +39960,7 @@ pub mod sdmmc {
};
RXDRR { bits }
}
- #[doc = "Bit 6 - Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn rcrc(&self) -> RCRCR {
let bits = {
const MASK: bool = true;
@@ -41587,8 +39969,7 @@ pub mod sdmmc {
};
RCRCR { bits }
}
- #[doc = "Bit 7 - Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn dcrc(&self) -> DCRCR {
let bits = {
const MASK: bool = true;
@@ -41597,8 +39978,7 @@ pub mod sdmmc {
};
DCRCR { bits }
}
- #[doc = "Bit 8 - Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn rto(&self) -> RTOR {
let bits = {
const MASK: bool = true;
@@ -41607,8 +39987,7 @@ pub mod sdmmc {
};
RTOR { bits }
}
- #[doc = "Bit 9 - Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn drto(&self) -> DRTOR {
let bits = {
const MASK: bool = true;
@@ -41617,8 +39996,7 @@ pub mod sdmmc {
};
DRTOR { bits }
}
- #[doc = "Bit 10 - Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn hto(&self) -> HTOR {
let bits = {
const MASK: bool = true;
@@ -41627,8 +40005,7 @@ pub mod sdmmc {
};
HTOR { bits }
}
- #[doc = "Bit 11 - FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 11 - FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn frun(&self) -> FRUNR {
let bits = {
const MASK: bool = true;
@@ -41637,8 +40014,7 @@ pub mod sdmmc {
};
FRUNR { bits }
}
- #[doc = "Bit 12 - Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn hle(&self) -> HLER {
let bits = {
const MASK: bool = true;
@@ -41647,8 +40023,7 @@ pub mod sdmmc {
};
HLER { bits }
}
- #[doc = "Bit 13 - Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn sbe(&self) -> SBER {
let bits = {
const MASK: bool = true;
@@ -41657,8 +40032,7 @@ pub mod sdmmc {
};
SBER { bits }
}
- #[doc = "Bit 14 - Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn acd(&self) -> ACDR {
let bits = {
const MASK: bool = true;
@@ -41667,8 +40041,7 @@ pub mod sdmmc {
};
ACDR { bits }
}
- #[doc = "Bit 15 - End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set."]
- #[inline(always)]
+ # [ doc = "Bit 15 - End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." ] # [ inline ( always ) ]
pub fn ebe(&self) -> EBER {
let bits = {
const MASK: bool = true;
@@ -41677,8 +40050,7 @@ pub mod sdmmc {
};
EBER { bits }
}
- #[doc = "Bit 16 - Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, this bit is always 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, this bit is always 0." ] # [ inline ( always ) ]
pub fn sdio_interrupt(&self) -> SDIO_INTERRUPTR {
let bits = {
const MASK: bool = true;
@@ -42493,8 +40865,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn cdet(&self) -> CDETR {
let bits = {
const MASK: bool = true;
@@ -42503,8 +40874,7 @@ pub mod sdmmc {
};
CDETR { bits }
}
- #[doc = "Bit 1 - Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn re(&self) -> RER {
let bits = {
const MASK: bool = true;
@@ -42513,8 +40883,7 @@ pub mod sdmmc {
};
RER { bits }
}
- #[doc = "Bit 2 - Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn cdone(&self) -> CDONER {
let bits = {
const MASK: bool = true;
@@ -42523,8 +40892,7 @@ pub mod sdmmc {
};
CDONER { bits }
}
- #[doc = "Bit 3 - Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn dto(&self) -> DTOR {
let bits = {
const MASK: bool = true;
@@ -42533,8 +40901,7 @@ pub mod sdmmc {
};
DTOR { bits }
}
- #[doc = "Bit 4 - Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn txdr(&self) -> TXDRR {
let bits = {
const MASK: bool = true;
@@ -42543,8 +40910,7 @@ pub mod sdmmc {
};
TXDRR { bits }
}
- #[doc = "Bit 5 - Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn rxdr(&self) -> RXDRR {
let bits = {
const MASK: bool = true;
@@ -42553,8 +40919,7 @@ pub mod sdmmc {
};
RXDRR { bits }
}
- #[doc = "Bit 6 - Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn rcrc(&self) -> RCRCR {
let bits = {
const MASK: bool = true;
@@ -42563,8 +40928,7 @@ pub mod sdmmc {
};
RCRCR { bits }
}
- #[doc = "Bit 7 - Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn dcrc(&self) -> DCRCR {
let bits = {
const MASK: bool = true;
@@ -42573,8 +40937,7 @@ pub mod sdmmc {
};
DCRCR { bits }
}
- #[doc = "Bit 8 - Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn rto_bar(&self) -> RTO_BARR {
let bits = {
const MASK: bool = true;
@@ -42583,8 +40946,7 @@ pub mod sdmmc {
};
RTO_BARR { bits }
}
- #[doc = "Bit 9 - Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn drto_bds(&self) -> DRTO_BDSR {
let bits = {
const MASK: bool = true;
@@ -42593,8 +40955,7 @@ pub mod sdmmc {
};
DRTO_BDSR { bits }
}
- #[doc = "Bit 10 - Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int"]
- #[inline(always)]
+ # [ doc = "Bit 10 - Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" ] # [ inline ( always ) ]
pub fn hto(&self) -> HTOR {
let bits = {
const MASK: bool = true;
@@ -42603,8 +40964,7 @@ pub mod sdmmc {
};
HTOR { bits }
}
- #[doc = "Bit 11 - FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 11 - FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn frun(&self) -> FRUNR {
let bits = {
const MASK: bool = true;
@@ -42613,8 +40973,7 @@ pub mod sdmmc {
};
FRUNR { bits }
}
- #[doc = "Bit 12 - Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn hle(&self) -> HLER {
let bits = {
const MASK: bool = true;
@@ -42623,8 +40982,7 @@ pub mod sdmmc {
};
HLER { bits }
}
- #[doc = "Bit 13 - Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn sbe(&self) -> SBER {
let bits = {
const MASK: bool = true;
@@ -42633,8 +40991,7 @@ pub mod sdmmc {
};
SBER { bits }
}
- #[doc = "Bit 14 - Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn acd(&self) -> ACDR {
let bits = {
const MASK: bool = true;
@@ -42643,8 +41000,7 @@ pub mod sdmmc {
};
ACDR { bits }
}
- #[doc = "Bit 15 - End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 15 - End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn ebe(&self) -> EBER {
let bits = {
const MASK: bool = true;
@@ -42653,8 +41009,7 @@ pub mod sdmmc {
};
EBER { bits }
}
- #[doc = "Bit 16 - Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." ] # [ inline ( always ) ]
pub fn sdio_interrupt(&self) -> SDIO_INTERRUPTR {
let bits = {
const MASK: bool = true;
@@ -42676,88 +41031,71 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn cdet(&mut self) -> _CDETW {
_CDETW { w: self }
}
- #[doc = "Bit 1 - Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn re(&mut self) -> _REW {
_REW { w: self }
}
- #[doc = "Bit 2 - Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn cdone(&mut self) -> _CDONEW {
_CDONEW { w: self }
}
- #[doc = "Bit 3 - Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn dto(&mut self) -> _DTOW {
_DTOW { w: self }
}
- #[doc = "Bit 4 - Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn txdr(&mut self) -> _TXDRW {
_TXDRW { w: self }
}
- #[doc = "Bit 5 - Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn rxdr(&mut self) -> _RXDRW {
_RXDRW { w: self }
}
- #[doc = "Bit 6 - Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn rcrc(&mut self) -> _RCRCW {
_RCRCW { w: self }
}
- #[doc = "Bit 7 - Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn dcrc(&mut self) -> _DCRCW {
_DCRCW { w: self }
}
- #[doc = "Bit 8 - Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn rto_bar(&mut self) -> _RTO_BARW {
_RTO_BARW { w: self }
}
- #[doc = "Bit 9 - Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn drto_bds(&mut self) -> _DRTO_BDSW {
_DRTO_BDSW { w: self }
}
- #[doc = "Bit 10 - Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int"]
- #[inline(always)]
+ # [ doc = "Bit 10 - Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" ] # [ inline ( always ) ]
pub fn hto(&mut self) -> _HTOW {
_HTOW { w: self }
}
- #[doc = "Bit 11 - FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 11 - FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn frun(&mut self) -> _FRUNW {
_FRUNW { w: self }
}
- #[doc = "Bit 12 - Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn hle(&mut self) -> _HLEW {
_HLEW { w: self }
}
- #[doc = "Bit 13 - Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn sbe(&mut self) -> _SBEW {
_SBEW { w: self }
}
- #[doc = "Bit 14 - Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn acd(&mut self) -> _ACDW {
_ACDW { w: self }
}
- #[doc = "Bit 15 - End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status."]
- #[inline(always)]
+ # [ doc = "Bit 15 - End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." ] # [ inline ( always ) ]
pub fn ebe(&mut self) -> _EBEW {
_EBEW { w: self }
}
- #[doc = "Bit 16 - Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." ] # [ inline ( always ) ]
pub fn sdio_interrupt(&mut self) -> _SDIO_INTERRUPTW {
_SDIO_INTERRUPTW { w: self }
}
@@ -43010,8 +41348,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - FIFO reached Receive watermark level; not qualified with data transfer."]
- #[inline(always)]
+ # [ doc = "Bit 0 - FIFO reached Receive watermark level; not qualified with data transfer." ] # [ inline ( always ) ]
pub fn fifo_rx_watermark(&self) -> FIFO_RX_WATERMARKR {
let bits = {
const MASK: bool = true;
@@ -43020,8 +41357,7 @@ pub mod sdmmc {
};
FIFO_RX_WATERMARKR { bits }
}
- #[doc = "Bit 1 - FIFO reached Transmit watermark level; not qualified with data transfer."]
- #[inline(always)]
+ # [ doc = "Bit 1 - FIFO reached Transmit watermark level; not qualified with data transfer." ] # [ inline ( always ) ]
pub fn fifo_tx_watermark(&self) -> FIFO_TX_WATERMARKR {
let bits = {
const MASK: bool = true;
@@ -43050,8 +41386,7 @@ pub mod sdmmc {
};
FIFO_FULLR { bits }
}
- #[doc = "Bits 4:7 - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are: - Bit 16 - Wait for CCS - Bit 17 - Send CCSD - Bit 18 - Boot Mode Due to this, while command FSM is in Wait for CCS state or Send CCSD or Boot Mode, the Status register indicates status as 0 for the bit field 7:4."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are: - Bit 16 - Wait for CCS - Bit 17 - Send CCSD - Bit 18 - Boot Mode Due to this, while command FSM is in Wait for CCS state or Send CCSD or Boot Mode, the Status register indicates status as 0 for the bit field 7:4." ] # [ inline ( always ) ]
pub fn cmdfsmstates(&self) -> CMDFSMSTATESR {
let bits = {
const MASK: u8 = 15;
@@ -43060,8 +41395,7 @@ pub mod sdmmc {
};
CMDFSMSTATESR { bits }
}
- #[doc = "Bit 8 - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present" ] # [ inline ( always ) ]
pub fn data_3_status(&self) -> DATA_3_STATUSR {
let bits = {
const MASK: bool = true;
@@ -43070,8 +41404,7 @@ pub mod sdmmc {
};
DATA_3_STATUSR { bits }
}
- #[doc = "Bit 9 - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy" ] # [ inline ( always ) ]
pub fn data_busy(&self) -> DATA_BUSYR {
let bits = {
const MASK: bool = true;
@@ -43414,8 +41747,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." ] # [ inline ( always ) ]
pub fn tx_wmark(&self) -> TX_WMARKR {
let bits = {
const MASK: u16 = 4095;
@@ -43424,8 +41756,7 @@ pub mod sdmmc {
};
TX_WMARKR { bits }
}
- #[doc = "Bits 16:27 - FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out."]
- #[inline(always)]
+ # [ doc = "Bits 16:27 - FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." ] # [ inline ( always ) ]
pub fn rx_wmark(&self) -> RX_WMARKR {
let bits = {
const MASK: u16 = 4095;
@@ -43434,8 +41765,7 @@ pub mod sdmmc {
};
RX_WMARKR { bits }
}
- #[doc = "Bits 28:30 - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7"]
- #[inline(always)]
+ # [ doc = "Bits 28:30 - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7" ] # [ inline ( always ) ]
pub fn dma_mts(&self) -> DMA_MTSR {
DMA_MTSR::_from({
const MASK: u8 = 7;
@@ -43456,18 +41786,15 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." ] # [ inline ( always ) ]
pub fn tx_wmark(&mut self) -> _TX_WMARKW {
_TX_WMARKW { w: self }
}
- #[doc = "Bits 16:27 - FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out."]
- #[inline(always)]
+ # [ doc = "Bits 16:27 - FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." ] # [ inline ( always ) ]
pub fn rx_wmark(&mut self) -> _RX_WMARKW {
_RX_WMARKW { w: self }
}
- #[doc = "Bits 28:30 - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7"]
- #[inline(always)]
+ # [ doc = "Bits 28:30 - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7" ] # [ inline ( always ) ]
pub fn dma_mts(&mut self) -> _DMA_MTSW {
_DMA_MTSW { w: self }
}
@@ -43625,8 +41952,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Number of bytes transferred by CIU unit to card. Register should be read only after data transfer completes; during data transfer, register returns 0."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Number of bytes transferred by CIU unit to card. Register should be read only after data transfer completes; during data transfer, register returns 0." ] # [ inline ( always ) ]
pub fn trans_card_byte_count(&self) -> TRANS_CARD_BYTE_COUNTR {
let bits = {
const MASK: u32 = 4294967295;
@@ -43767,8 +42093,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms."]
- #[inline(always)]
+ # [ doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." ] # [ inline ( always ) ]
pub fn debounce_count(&self) -> DEBOUNCE_COUNTR {
let bits = {
const MASK: u32 = 16777215;
@@ -43790,8 +42115,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms."]
- #[inline(always)]
+ # [ doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." ] # [ inline ( always ) ]
pub fn debounce_count(&mut self) -> _DEBOUNCE_COUNTW {
_DEBOUNCE_COUNTW { w: self }
}
@@ -43897,8 +42221,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Hardware reset. 1 - Active mode 0 - Reset Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Hardware reset. 1 - Active mode 0 - Reset Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." ] # [ inline ( always ) ]
pub fn card_reset(&self) -> CARD_RESETR {
let bits = {
const MASK: bool = true;
@@ -43920,8 +42243,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Hardware reset. 1 - Active mode 0 - Reset Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Hardware reset. 1 - Active mode 0 - Reset Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." ] # [ inline ( always ) ]
pub fn card_reset(&mut self) -> _CARD_RESETW {
_CARD_RESETW { w: self }
}
@@ -44315,8 +42637,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." ] # [ inline ( always ) ]
pub fn swr(&self) -> SWRR {
let bits = {
const MASK: bool = true;
@@ -44325,8 +42646,7 @@ pub mod sdmmc {
};
SWRR { bits }
}
- #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." ] # [ inline ( always ) ]
pub fn fb(&self) -> FBR {
let bits = {
const MASK: bool = true;
@@ -44335,8 +42655,7 @@ pub mod sdmmc {
};
FBR { bits }
}
- #[doc = "Bits 2:6 - Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write."]
- #[inline(always)]
+ # [ doc = "Bits 2:6 - Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." ] # [ inline ( always ) ]
pub fn dsl(&self) -> DSLR {
let bits = {
const MASK: u8 = 31;
@@ -44345,8 +42664,7 @@ pub mod sdmmc {
};
DSLR { bits }
}
- #[doc = "Bit 7 - SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write."]
- #[inline(always)]
+ # [ doc = "Bit 7 - SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." ] # [ inline ( always ) ]
pub fn de(&self) -> DER {
let bits = {
const MASK: bool = true;
@@ -44355,8 +42673,7 @@ pub mod sdmmc {
};
DER { bits }
}
- #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value."]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value." ] # [ inline ( always ) ]
pub fn pbl(&self) -> PBLR {
PBLR::_from({
const MASK: u8 = 7;
@@ -44377,28 +42694,23 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." ] # [ inline ( always ) ]
pub fn swr(&mut self) -> _SWRW {
_SWRW { w: self }
}
- #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." ] # [ inline ( always ) ]
pub fn fb(&mut self) -> _FBW {
_FBW { w: self }
}
- #[doc = "Bits 2:6 - Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write."]
- #[inline(always)]
+ # [ doc = "Bits 2:6 - Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." ] # [ inline ( always ) ]
pub fn dsl(&mut self) -> _DSLW {
_DSLW { w: self }
}
- #[doc = "Bit 7 - SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write."]
- #[inline(always)]
+ # [ doc = "Bit 7 - SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." ] # [ inline ( always ) ]
pub fn de(&mut self) -> _DEW {
_DEW { w: self }
}
- #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value."]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value." ] # [ inline ( always ) ]
pub fn pbl(&mut self) -> _PBLW {
_PBLW { w: self }
}
@@ -44453,8 +42765,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." ] # [ inline ( always ) ]
pub fn pd(&mut self) -> _PDW {
_PDW { w: self }
}
@@ -44542,8 +42853,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." ] # [ inline ( always ) ]
pub fn sdl(&self) -> SDLR {
let bits = {
const MASK: u32 = 4294967295;
@@ -44565,8 +42875,7 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." ] # [ inline ( always ) ]
pub fn sdl(&mut self) -> _SDLW {
_SDLW { w: self }
}
@@ -44988,8 +43297,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ti(&self) -> TIR {
let bits = {
const MASK: bool = true;
@@ -44998,8 +43306,7 @@ pub mod sdmmc {
};
TIR { bits }
}
- #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ri(&self) -> RIR {
let bits = {
const MASK: bool = true;
@@ -45008,8 +43315,7 @@ pub mod sdmmc {
};
RIR { bits }
}
- #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn fbe(&self) -> FBER {
let bits = {
const MASK: bool = true;
@@ -45018,8 +43324,7 @@ pub mod sdmmc {
};
FBER { bits }
}
- #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn du(&self) -> DUR {
let bits = {
const MASK: bool = true;
@@ -45028,8 +43333,7 @@ pub mod sdmmc {
};
DUR { bits }
}
- #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ces(&self) -> CESR {
let bits = {
const MASK: bool = true;
@@ -45038,8 +43342,7 @@ pub mod sdmmc {
};
CESR { bits }
}
- #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn nis(&self) -> NISR {
let bits = {
const MASK: bool = true;
@@ -45048,8 +43351,7 @@ pub mod sdmmc {
};
NISR { bits }
}
- #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ais(&self) -> AISR {
let bits = {
const MASK: bool = true;
@@ -45058,8 +43360,7 @@ pub mod sdmmc {
};
AISR { bits }
}
- #[doc = "Bits 10:12 - Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only."]
- #[inline(always)]
+ # [ doc = "Bits 10:12 - Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only." ] # [ inline ( always ) ]
pub fn eb(&self) -> EBR {
let bits = {
const MASK: u8 = 7;
@@ -45068,8 +43369,7 @@ pub mod sdmmc {
};
EBR { bits }
}
- #[doc = "Bits 13:16 - DMAC state machine present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only."]
- #[inline(always)]
+ # [ doc = "Bits 13:16 - DMAC state machine present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only." ] # [ inline ( always ) ]
pub fn fsm(&self) -> FSMR {
let bits = {
const MASK: u8 = 15;
@@ -45091,48 +43391,39 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ti(&mut self) -> _TIW {
_TIW { w: self }
}
- #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ri(&mut self) -> _RIW {
_RIW { w: self }
}
- #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn fbe(&mut self) -> _FBEW {
_FBEW { w: self }
}
- #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn du(&mut self) -> _DUW {
_DUW { w: self }
}
- #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ces(&mut self) -> _CESW {
_CESW { w: self }
}
- #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn nis(&mut self) -> _NISW {
_NISW { w: self }
}
- #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." ] # [ inline ( always ) ]
pub fn ais(&mut self) -> _AISW {
_AISW { w: self }
}
- #[doc = "Bits 10:12 - Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only."]
- #[inline(always)]
+ # [ doc = "Bits 10:12 - Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only." ] # [ inline ( always ) ]
pub fn eb(&mut self) -> _EBW {
_EBW { w: self }
}
- #[doc = "Bits 13:16 - DMAC state machine present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only."]
- #[inline(always)]
+ # [ doc = "Bits 13:16 - DMAC state machine present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only." ] # [ inline ( always ) ]
pub fn fsm(&mut self) -> _FSMW {
_FSMW { w: self }
}
@@ -45502,8 +43793,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ti(&self) -> TIR {
let bits = {
const MASK: bool = true;
@@ -45512,8 +43802,7 @@ pub mod sdmmc {
};
TIR { bits }
}
- #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ri(&self) -> RIR {
let bits = {
const MASK: bool = true;
@@ -45522,8 +43811,7 @@ pub mod sdmmc {
};
RIR { bits }
}
- #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn fbe(&self) -> FBER {
let bits = {
const MASK: bool = true;
@@ -45532,8 +43820,7 @@ pub mod sdmmc {
};
FBER { bits }
}
- #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." ] # [ inline ( always ) ]
pub fn du(&self) -> DUR {
let bits = {
const MASK: bool = true;
@@ -45542,8 +43829,7 @@ pub mod sdmmc {
};
DUR { bits }
}
- #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." ] # [ inline ( always ) ]
pub fn ces(&self) -> CESR {
let bits = {
const MASK: bool = true;
@@ -45552,8 +43838,7 @@ pub mod sdmmc {
};
CESR { bits }
}
- #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" ] # [ inline ( always ) ]
pub fn nis(&self) -> NISR {
let bits = {
const MASK: bool = true;
@@ -45562,8 +43847,7 @@ pub mod sdmmc {
};
NISR { bits }
}
- #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" ] # [ inline ( always ) ]
pub fn ais(&self) -> AISR {
let bits = {
const MASK: bool = true;
@@ -45585,38 +43869,31 @@ pub mod sdmmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ti(&mut self) -> _TIW {
_TIW { w: self }
}
- #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ri(&mut self) -> _RIW {
_RIW { w: self }
}
- #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn fbe(&mut self) -> _FBEW {
_FBEW { w: self }
}
- #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." ] # [ inline ( always ) ]
pub fn du(&mut self) -> _DUW {
_DUW { w: self }
}
- #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." ] # [ inline ( always ) ]
pub fn ces(&mut self) -> _CESW {
_CESW { w: self }
}
- #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" ] # [ inline ( always ) ]
pub fn nis(&mut self) -> _NISW {
_NISW { w: self }
}
- #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" ] # [ inline ( always ) ]
pub fn ais(&mut self) -> _AISW {
_AISW { w: self }
}
@@ -45658,8 +43935,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." ] # [ inline ( always ) ]
pub fn hda(&self) -> HDAR {
let bits = {
const MASK: u32 = 4294967295;
@@ -45706,8 +43982,7 @@ pub mod sdmmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." ] # [ inline ( always ) ]
pub fn hba(&self) -> HBAR {
let bits = {
const MASK: u32 = 4294967295;
@@ -45736,126 +44011,7 @@ pub mod emc {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Controls operation of the memory controller."]
- pub control: CONTROL,
- #[doc = "0x04 - Provides EMC status information."] pub status: STATUS,
- #[doc = "0x08 - Configures operation of the memory controller."]
- pub config: CONFIG,
- _reserved0: [u8; 20usize],
- #[doc = "0x20 - Controls dynamic memory operation."]
- pub dynamiccontrol: DYNAMICCONTROL,
- #[doc = "0x24 - Configures dynamic memory refresh operation."]
- pub dynamicrefresh: DYNAMICREFRESH,
- #[doc = "0x28 - Configures the dynamic memory read strategy."]
- pub dynamicreadconfig: DYNAMICREADCONFIG,
- _reserved1: [u8; 4usize],
- #[doc = "0x30 - Selects the precharge command period."]
- pub dynamicrp: DYNAMICRP,
- #[doc = "0x34 - Selects the active to precharge command period."]
- pub dynamicras: DYNAMICRAS,
- #[doc = "0x38 - Selects the self-refresh exit time."]
- pub dynamicsrex: DYNAMICSREX,
- #[doc = "0x3c - Selects the last-data-out to active command time."]
- pub dynamicapr: DYNAMICAPR,
- #[doc = "0x40 - Selects the data-in to active command time."]
- pub dynamicdal: DYNAMICDAL,
- #[doc = "0x44 - Selects the write recovery time."]
- pub dynamicwr: DYNAMICWR,
- #[doc = "0x48 - Selects the active to active command period."]
- pub dynamicrc: DYNAMICRC,
- #[doc = "0x4c - Selects the auto-refresh period."]
- pub dynamicrfc: DYNAMICRFC,
- #[doc = "0x50 - Selects the exit self-refresh to active command time."]
- pub dynamicxsr: DYNAMICXSR,
- #[doc = "0x54 - Selects the active bank A to active bank B latency."]
- pub dynamicrrd: DYNAMICRRD,
- #[doc = "0x58 - Selects the load mode register to active command time."]
- pub dynamicmrd: DYNAMICMRD,
- _reserved2: [u8; 36usize],
- #[doc = "0x80 - Selects time for long static memory read and write transfers."]
- pub staticextendedwait: STATICEXTENDEDWAIT,
- _reserved3: [u8; 124usize],
- #[doc = "0x100 - Selects the configuration information for dynamic memory chip select 0."]
- pub dynamicconfig0: DYNAMICCONFIG,
- #[doc = "0x104 - Selects the RAS and CAS latencies for dynamic memory chip select 0."]
- pub dynamicrascas0: DYNAMICRASCAS,
- _reserved4: [u8; 24usize],
- #[doc = "0x120 - Selects the configuration information for dynamic memory chip select 0."]
- pub dynamicconfig1: DYNAMICCONFIG,
- #[doc = "0x124 - Selects the RAS and CAS latencies for dynamic memory chip select 0."]
- pub dynamicrascas1: DYNAMICRASCAS,
- _reserved5: [u8; 24usize],
- #[doc = "0x140 - Selects the configuration information for dynamic memory chip select 0."]
- pub dynamicconfig2: DYNAMICCONFIG,
- #[doc = "0x144 - Selects the RAS and CAS latencies for dynamic memory chip select 0."]
- pub dynamicrascas2: DYNAMICRASCAS,
- _reserved6: [u8; 24usize],
- #[doc = "0x160 - Selects the configuration information for dynamic memory chip select 0."]
- pub dynamicconfig3: DYNAMICCONFIG,
- #[doc = "0x164 - Selects the RAS and CAS latencies for dynamic memory chip select 0."]
- pub dynamicrascas3: DYNAMICRASCAS,
- _reserved7: [u8; 152usize],
- #[doc = "0x200 - Selects the memory configuration for static chip select 0."]
- pub staticconfig0: STATICCONFIG,
- #[doc = "0x204 - Selects the delay from chip select 0 to write enable."]
- pub staticwaitwen0: STATICWAITWEN,
- #[doc = "0x208 - Selects the delay from chip select 0 or address change, whichever is later, to output enable."]
- pub staticwaitoen0: STATICWAITOEN,
- #[doc = "0x20c - Selects the delay from chip select 0 to a read access."]
- pub staticwaitrd0: STATICWAITRD,
- #[doc = "0x210 - Selects the delay for asynchronous page mode sequential accesses for chip select 0."]
- pub staticwaitpage0: STATICWAITPAGE,
- #[doc = "0x214 - Selects the delay from chip select 0 to a write access."]
- pub staticwaitwr0: STATICWAITWR,
- #[doc = "0x218 - Selects the number of bus turnaround cycles for chip select 0."]
- pub staticwaitturn0: STATICWAITTURN,
- _reserved8: [u8; 4usize],
- #[doc = "0x220 - Selects the memory configuration for static chip select 0."]
- pub staticconfig1: STATICCONFIG,
- #[doc = "0x224 - Selects the delay from chip select 0 to write enable."]
- pub staticwaitwen1: STATICWAITWEN,
- #[doc = "0x228 - Selects the delay from chip select 0 or address change, whichever is later, to output enable."]
- pub staticwaitoen1: STATICWAITOEN,
- #[doc = "0x22c - Selects the delay from chip select 0 to a read access."]
- pub staticwaitrd1: STATICWAITRD,
- #[doc = "0x230 - Selects the delay for asynchronous page mode sequential accesses for chip select 0."]
- pub staticwaitpage1: STATICWAITPAGE,
- #[doc = "0x234 - Selects the delay from chip select 0 to a write access."]
- pub staticwaitwr1: STATICWAITWR,
- #[doc = "0x238 - Selects the number of bus turnaround cycles for chip select 0."]
- pub staticwaitturn1: STATICWAITTURN,
- _reserved9: [u8; 4usize],
- #[doc = "0x240 - Selects the memory configuration for static chip select 0."]
- pub staticconfig2: STATICCONFIG,
- #[doc = "0x244 - Selects the delay from chip select 0 to write enable."]
- pub staticwaitwen2: STATICWAITWEN,
- #[doc = "0x248 - Selects the delay from chip select 0 or address change, whichever is later, to output enable."]
- pub staticwaitoen2: STATICWAITOEN,
- #[doc = "0x24c - Selects the delay from chip select 0 to a read access."]
- pub staticwaitrd2: STATICWAITRD,
- #[doc = "0x250 - Selects the delay for asynchronous page mode sequential accesses for chip select 0."]
- pub staticwaitpage2: STATICWAITPAGE,
- #[doc = "0x254 - Selects the delay from chip select 0 to a write access."]
- pub staticwaitwr2: STATICWAITWR,
- #[doc = "0x258 - Selects the number of bus turnaround cycles for chip select 0."]
- pub staticwaitturn2: STATICWAITTURN,
- _reserved10: [u8; 4usize],
- #[doc = "0x260 - Selects the memory configuration for static chip select 0."]
- pub staticconfig3: STATICCONFIG,
- #[doc = "0x264 - Selects the delay from chip select 0 to write enable."]
- pub staticwaitwen3: STATICWAITWEN,
- #[doc = "0x268 - Selects the delay from chip select 0 or address change, whichever is later, to output enable."]
- pub staticwaitoen3: STATICWAITOEN,
- #[doc = "0x26c - Selects the delay from chip select 0 to a read access."]
- pub staticwaitrd3: STATICWAITRD,
- #[doc = "0x270 - Selects the delay for asynchronous page mode sequential accesses for chip select 0."]
- pub staticwaitpage3: STATICWAITPAGE,
- #[doc = "0x274 - Selects the delay from chip select 0 to a write access."]
- pub staticwaitwr3: STATICWAITWR,
- #[doc = "0x278 - Selects the number of bus turnaround cycles for chip select 0."]
- pub staticwaitturn3: STATICWAITTURN,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - Controls operation of the memory controller." ] pub control : CONTROL , # [ doc = "0x04 - Provides EMC status information." ] pub status : STATUS , # [ doc = "0x08 - Configures operation of the memory controller." ] pub config : CONFIG , _reserved0 : [ u8 ; 20usize ] , # [ doc = "0x20 - Controls dynamic memory operation." ] pub dynamiccontrol : DYNAMICCONTROL , # [ doc = "0x24 - Configures dynamic memory refresh operation." ] pub dynamicrefresh : DYNAMICREFRESH , # [ doc = "0x28 - Configures the dynamic memory read strategy." ] pub dynamicreadconfig : DYNAMICREADCONFIG , _reserved1 : [ u8 ; 4usize ] , # [ doc = "0x30 - Selects the precharge command period." ] pub dynamicrp : DYNAMICRP , # [ doc = "0x34 - Selects the active to precharge command period." ] pub dynamicras : DYNAMICRAS , # [ doc = "0x38 - Selects the self-refresh exit time." ] pub dynamicsrex : DYNAMICSREX , # [ doc = "0x3c - Selects the last-data-out to active command time." ] pub dynamicapr : DYNAMICAPR , # [ doc = "0x40 - Selects the data-in to active command time." ] pub dynamicdal : DYNAMICDAL , # [ doc = "0x44 - Selects the write recovery time." ] pub dynamicwr : DYNAMICWR , # [ doc = "0x48 - Selects the active to active command period." ] pub dynamicrc : DYNAMICRC , # [ doc = "0x4c - Selects the auto-refresh period." ] pub dynamicrfc : DYNAMICRFC , # [ doc = "0x50 - Selects the exit self-refresh to active command time." ] pub dynamicxsr : DYNAMICXSR , # [ doc = "0x54 - Selects the active bank A to active bank B latency." ] pub dynamicrrd : DYNAMICRRD , # [ doc = "0x58 - Selects the load mode register to active command time." ] pub dynamicmrd : DYNAMICMRD , _reserved2 : [ u8 ; 36usize ] , # [ doc = "0x80 - Selects time for long static memory read and write transfers." ] pub staticextendedwait : STATICEXTENDEDWAIT , _reserved3 : [ u8 ; 124usize ] , # [ doc = "0x100 - Selects the configuration information for dynamic memory chip select 0." ] pub dynamicconfig0 : DYNAMICCONFIG , # [ doc = "0x104 - Selects the RAS and CAS latencies for dynamic memory chip select 0." ] pub dynamicrascas0 : DYNAMICRASCAS , _reserved4 : [ u8 ; 24usize ] , # [ doc = "0x120 - Selects the configuration information for dynamic memory chip select 0." ] pub dynamicconfig1 : DYNAMICCONFIG , # [ doc = "0x124 - Selects the RAS and CAS latencies for dynamic memory chip select 0." ] pub dynamicrascas1 : DYNAMICRASCAS , _reserved5 : [ u8 ; 24usize ] , # [ doc = "0x140 - Selects the configuration information for dynamic memory chip select 0." ] pub dynamicconfig2 : DYNAMICCONFIG , # [ doc = "0x144 - Selects the RAS and CAS latencies for dynamic memory chip select 0." ] pub dynamicrascas2 : DYNAMICRASCAS , _reserved6 : [ u8 ; 24usize ] , # [ doc = "0x160 - Selects the configuration information for dynamic memory chip select 0." ] pub dynamicconfig3 : DYNAMICCONFIG , # [ doc = "0x164 - Selects the RAS and CAS latencies for dynamic memory chip select 0." ] pub dynamicrascas3 : DYNAMICRASCAS , _reserved7 : [ u8 ; 152usize ] , # [ doc = "0x200 - Selects the memory configuration for static chip select 0." ] pub staticconfig0 : STATICCONFIG , # [ doc = "0x204 - Selects the delay from chip select 0 to write enable." ] pub staticwaitwen0 : STATICWAITWEN , # [ doc = "0x208 - Selects the delay from chip select 0 or address change, whichever is later, to output enable." ] pub staticwaitoen0 : STATICWAITOEN , # [ doc = "0x20c - Selects the delay from chip select 0 to a read access." ] pub staticwaitrd0 : STATICWAITRD , # [ doc = "0x210 - Selects the delay for asynchronous page mode sequential accesses for chip select 0." ] pub staticwaitpage0 : STATICWAITPAGE , # [ doc = "0x214 - Selects the delay from chip select 0 to a write access." ] pub staticwaitwr0 : STATICWAITWR , # [ doc = "0x218 - Selects the number of bus turnaround cycles for chip select 0." ] pub staticwaitturn0 : STATICWAITTURN , _reserved8 : [ u8 ; 4usize ] , # [ doc = "0x220 - Selects the memory configuration for static chip select 0." ] pub staticconfig1 : STATICCONFIG , # [ doc = "0x224 - Selects the delay from chip select 0 to write enable." ] pub staticwaitwen1 : STATICWAITWEN , # [ doc = "0x228 - Selects the delay from chip select 0 or address change, whichever is later, to output enable." ] pub staticwaitoen1 : STATICWAITOEN , # [ doc = "0x22c - Selects the delay from chip select 0 to a read access." ] pub staticwaitrd1 : STATICWAITRD , # [ doc = "0x230 - Selects the delay for asynchronous page mode sequential accesses for chip select 0." ] pub staticwaitpage1 : STATICWAITPAGE , # [ doc = "0x234 - Selects the delay from chip select 0 to a write access." ] pub staticwaitwr1 : STATICWAITWR , # [ doc = "0x238 - Selects the number of bus turnaround cycles for chip select 0." ] pub staticwaitturn1 : STATICWAITTURN , _reserved9 : [ u8 ; 4usize ] , # [ doc = "0x240 - Selects the memory configuration for static chip select 0." ] pub staticconfig2 : STATICCONFIG , # [ doc = "0x244 - Selects the delay from chip select 0 to write enable." ] pub staticwaitwen2 : STATICWAITWEN , # [ doc = "0x248 - Selects the delay from chip select 0 or address change, whichever is later, to output enable." ] pub staticwaitoen2 : STATICWAITOEN , # [ doc = "0x24c - Selects the delay from chip select 0 to a read access." ] pub staticwaitrd2 : STATICWAITRD , # [ doc = "0x250 - Selects the delay for asynchronous page mode sequential accesses for chip select 0." ] pub staticwaitpage2 : STATICWAITPAGE , # [ doc = "0x254 - Selects the delay from chip select 0 to a write access." ] pub staticwaitwr2 : STATICWAITWR , # [ doc = "0x258 - Selects the number of bus turnaround cycles for chip select 0." ] pub staticwaitturn2 : STATICWAITTURN , _reserved10 : [ u8 ; 4usize ] , # [ doc = "0x260 - Selects the memory configuration for static chip select 0." ] pub staticconfig3 : STATICCONFIG , # [ doc = "0x264 - Selects the delay from chip select 0 to write enable." ] pub staticwaitwen3 : STATICWAITWEN , # [ doc = "0x268 - Selects the delay from chip select 0 or address change, whichever is later, to output enable." ] pub staticwaitoen3 : STATICWAITOEN , # [ doc = "0x26c - Selects the delay from chip select 0 to a read access." ] pub staticwaitrd3 : STATICWAITRD , # [ doc = "0x270 - Selects the delay for asynchronous page mode sequential accesses for chip select 0." ] pub staticwaitpage3 : STATICWAITPAGE , # [ doc = "0x274 - Selects the delay from chip select 0 to a write access." ] pub staticwaitwr3 : STATICWAITWR , # [ doc = "0x278 - Selects the number of bus turnaround cycles for chip select 0." ] pub staticwaitturn3 : STATICWAITTURN , }
#[doc = "Controls operation of the memory controller."]
pub struct CONTROL {
register: VolatileCell<u32>,
@@ -45953,11 +44109,7 @@ pub mod emc {
}
#[doc = "Possible values of the field `M`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MR {
- #[doc = "Normal. Normal memory map."] NORMAL,
- #[doc = "Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)."]
- RESET,
- }
+ pub enum MR {# [ doc = "Normal. Normal memory map." ] NORMAL , # [ doc = "Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." ] RESET}
impl MR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -46099,11 +44251,7 @@ pub mod emc {
}
}
#[doc = "Values that can be written to the field `M`"]
- pub enum MW {
- #[doc = "Normal. Normal memory map."] NORMAL,
- #[doc = "Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)."]
- RESET,
- }
+ pub enum MW {# [ doc = "Normal. Normal memory map." ] NORMAL , # [ doc = "Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." ] RESET}
impl MW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -46132,8 +44280,7 @@ pub mod emc {
pub fn normal(self) -> &'a mut W {
self.variant(MW::NORMAL)
}
- #[doc = "Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." ] # [ inline ( always ) ]
pub fn reset(self) -> &'a mut W {
self.variant(MW::RESET)
}
@@ -46217,8 +44364,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]"]
- #[inline(always)]
+ # [ doc = "Bit 0 - EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]" ] # [ inline ( always ) ]
pub fn e(&self) -> ER {
ER::_from({
const MASK: bool = true;
@@ -46226,8 +44372,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed." ] # [ inline ( always ) ]
pub fn m(&self) -> MR {
MR::_from({
const MASK: bool = true;
@@ -46235,8 +44380,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]" ] # [ inline ( always ) ]
pub fn l(&self) -> LR {
LR::_from({
const MASK: bool = true;
@@ -46257,18 +44401,15 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]"]
- #[inline(always)]
+ # [ doc = "Bit 0 - EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]" ] # [ inline ( always ) ]
pub fn e(&mut self) -> _EW {
_EW { w: self }
}
- #[doc = "Bit 1 - Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed." ] # [ inline ( always ) ]
pub fn m(&mut self) -> _MW {
_MW { w: self }
}
- #[doc = "Bit 2 - Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]" ] # [ inline ( always ) ]
pub fn l(&mut self) -> _LW {
_LW { w: self }
}
@@ -46295,11 +44436,7 @@ pub mod emc {
}
#[doc = "Possible values of the field `B`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BR {
- #[doc = "Idle. EMC is idle (warm reset value)."] IDLE,
- #[doc = "Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)."]
- BUSY,
- }
+ pub enum BR {# [ doc = "Idle. EMC is idle (warm reset value)." ] IDLE , # [ doc = "Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." ] BUSY}
impl BR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -46435,8 +44572,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:" ] # [ inline ( always ) ]
pub fn b(&self) -> BR {
BR::_from({
const MASK: bool = true;
@@ -46444,8 +44580,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:" ] # [ inline ( always ) ]
pub fn s(&self) -> SR {
SR::_from({
const MASK: bool = true;
@@ -46453,8 +44588,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Self-refresh acknowledge. This bit indicates the operating mode of the EMC:"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Self-refresh acknowledge. This bit indicates the operating mode of the EMC:" ] # [ inline ( always ) ]
pub fn sa(&self) -> SAR {
SAR::_from({
const MASK: bool = true;
@@ -46702,12 +44836,7 @@ pub mod emc {
}
#[doc = "Possible values of the field `CE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CER {
- #[doc = "Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)."]
- DISABLED,
- #[doc = "Enabled. All clock enables are driven HIGH continuously.[1]"]
- ENABLED,
- }
+ pub enum CER {# [ doc = "Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." ] DISABLED , # [ doc = "Enabled. All clock enables are driven HIGH continuously.[1]" ] ENABLED}
impl CER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -46797,8 +44926,7 @@ pub mod emc {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SRR {
#[doc = "Normal mode."] NORMAL_MODE,
- #[doc = "Self-refresh. Enter self-refresh mode (POR reset value)."]
- SELF_REFRESH,
+ #[doc = "Self-refresh. Enter self-refresh mode (POR reset value)."] SELF_REFRESH,
}
impl SRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -46887,8 +45015,7 @@ pub mod emc {
#[doc = "Possible values of the field `I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IR {
- #[doc = "Normal. Issue SDRAM NORMAL operation command (POR reset value)."]
- NORMAL,
+ #[doc = "Normal. Issue SDRAM NORMAL operation command (POR reset value)."] NORMAL,
#[doc = "Mode. Issue SDRAM MODE command."] MODE,
#[doc = "PALL. Issue SDRAM PALL (precharge all) command."] PALL,
#[doc = "NOP. Issue SDRAM NOP (no operation) command)"] NOP,
@@ -46938,12 +45065,7 @@ pub mod emc {
}
}
#[doc = "Values that can be written to the field `CE`"]
- pub enum CEW {
- #[doc = "Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)."]
- DISABLED,
- #[doc = "Enabled. All clock enables are driven HIGH continuously.[1]"]
- ENABLED,
- }
+ pub enum CEW {# [ doc = "Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." ] DISABLED , # [ doc = "Enabled. All clock enables are driven HIGH continuously.[1]" ] ENABLED}
impl CEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -46967,8 +45089,7 @@ pub mod emc {
self.bit(variant._bits())
}
}
- #[doc = "Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." ] # [ inline ( always ) ]
pub fn disabled(self) -> &'a mut W {
self.variant(CEW::DISABLED)
}
@@ -47055,8 +45176,7 @@ pub mod emc {
#[doc = "Values that can be written to the field `SR`"]
pub enum SRW {
#[doc = "Normal mode."] NORMAL_MODE,
- #[doc = "Self-refresh. Enter self-refresh mode (POR reset value)."]
- SELF_REFRESH,
+ #[doc = "Self-refresh. Enter self-refresh mode (POR reset value)."] SELF_REFRESH,
}
impl SRW {
#[allow(missing_docs)]
@@ -47167,8 +45287,7 @@ pub mod emc {
}
#[doc = "Values that can be written to the field `I`"]
pub enum IW {
- #[doc = "Normal. Issue SDRAM NORMAL operation command (POR reset value)."]
- NORMAL,
+ #[doc = "Normal. Issue SDRAM NORMAL operation command (POR reset value)."] NORMAL,
#[doc = "Mode. Issue SDRAM MODE command."] MODE,
#[doc = "PALL. Issue SDRAM PALL (precharge all) command."] PALL,
#[doc = "NOP. Issue SDRAM NOP (no operation) command)"] NOP,
@@ -47243,8 +45362,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode." ] # [ inline ( always ) ]
pub fn cs(&self) -> CSR {
CSR::_from({
const MASK: bool = true;
@@ -47252,8 +45370,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]" ] # [ inline ( always ) ]
pub fn sr(&self) -> SRR {
SRR::_from({
const MASK: bool = true;
@@ -47297,13 +45414,11 @@ pub mod emc {
pub fn ce(&mut self) -> _CEW {
_CEW { w: self }
}
- #[doc = "Bit 1 - Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode." ] # [ inline ( always ) ]
pub fn cs(&mut self) -> _CSW {
_CSW { w: self }
}
- #[doc = "Bit 2 - Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]" ] # [ inline ( always ) ]
pub fn sr(&mut self) -> _SRW {
_SRW { w: self }
}
@@ -47401,8 +45516,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:10 - Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles"]
- #[inline(always)]
+ # [ doc = "Bits 0:10 - Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" ] # [ inline ( always ) ]
pub fn refresh(&self) -> REFRESHR {
let bits = {
const MASK: u16 = 2047;
@@ -47424,8 +45538,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:10 - Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles"]
- #[inline(always)]
+ # [ doc = "Bits 0:10 - Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" ] # [ inline ( always ) ]
pub fn refresh(&mut self) -> _REFRESHW {
_REFRESHW { w: self }
}
@@ -47486,10 +45599,8 @@ pub mod emc {
pub enum RDR {
#[doc = "Do not use. POR reset value."] DO_NOT_USE,
#[doc = "Command delayed by 1/2 EMC_CCLK."] HALF,
- #[doc = "Command delayed by 1/2 EMC_CCLK plus one clock cycle."]
- HALFPLUSONE,
- #[doc = "Command delayed by1/2 EMC_CCLK plus two clock cycles,"]
- HALFPLUSTWO,
+ #[doc = "Command delayed by 1/2 EMC_CCLK plus one clock cycle."] HALFPLUSONE,
+ #[doc = "Command delayed by1/2 EMC_CCLK plus two clock cycles,"] HALFPLUSTWO,
}
impl RDR {
#[doc = r" Value of the field as raw bits"]
@@ -47539,10 +45650,8 @@ pub mod emc {
pub enum RDW {
#[doc = "Do not use. POR reset value."] DO_NOT_USE,
#[doc = "Command delayed by 1/2 EMC_CCLK."] HALF,
- #[doc = "Command delayed by 1/2 EMC_CCLK plus one clock cycle."]
- HALFPLUSONE,
- #[doc = "Command delayed by1/2 EMC_CCLK plus two clock cycles,"]
- HALFPLUSTWO,
+ #[doc = "Command delayed by 1/2 EMC_CCLK plus one clock cycle."] HALFPLUSONE,
+ #[doc = "Command delayed by1/2 EMC_CCLK plus two clock cycles,"] HALFPLUSTWO,
}
impl RDW {
#[allow(missing_docs)]
@@ -47716,8 +45825,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trp(&self) -> TRPR {
let bits = {
const MASK: u8 = 15;
@@ -47739,8 +45847,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trp(&mut self) -> _TRPW {
_TRPW { w: self }
}
@@ -47828,8 +45935,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tras(&self) -> TRASR {
let bits = {
const MASK: u8 = 15;
@@ -47851,8 +45957,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tras(&mut self) -> _TRASW {
_TRASW { w: self }
}
@@ -47940,8 +46045,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tsrex(&self) -> TSREXR {
let bits = {
const MASK: u8 = 15;
@@ -47963,8 +46067,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tsrex(&mut self) -> _TSREXW {
_TSREXW { w: self }
}
@@ -48052,8 +46155,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tapr(&self) -> TAPRR {
let bits = {
const MASK: u8 = 15;
@@ -48075,8 +46177,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tapr(&mut self) -> _TAPRW {
_TAPRW { w: self }
}
@@ -48164,8 +46265,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tdal(&self) -> TDALR {
let bits = {
const MASK: u8 = 15;
@@ -48187,8 +46287,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tdal(&mut self) -> _TDALW {
_TDALW { w: self }
}
@@ -48276,8 +46375,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn twr(&self) -> TWRR {
let bits = {
const MASK: u8 = 15;
@@ -48299,8 +46397,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn twr(&mut self) -> _TWRW {
_TWRW { w: self }
}
@@ -48388,8 +46485,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trc(&self) -> TRCR {
let bits = {
const MASK: u8 = 31;
@@ -48411,8 +46507,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trc(&mut self) -> _TRCW {
_TRCW { w: self }
}
@@ -48500,8 +46595,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trfc(&self) -> TRFCR {
let bits = {
const MASK: u8 = 31;
@@ -48523,8 +46617,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trfc(&mut self) -> _TRFCW {
_TRFCW { w: self }
}
@@ -48612,8 +46705,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn txsr(&self) -> TXSRR {
let bits = {
const MASK: u8 = 31;
@@ -48635,8 +46727,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn txsr(&mut self) -> _TXSRW {
_TXSRW { w: self }
}
@@ -48724,8 +46815,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trrd(&self) -> TRRDR {
let bits = {
const MASK: u8 = 15;
@@ -48747,8 +46837,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn trrd(&mut self) -> _TRRDW {
_TRRDW { w: self }
}
@@ -48836,8 +46925,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tmrd(&self) -> TMRDR {
let bits = {
const MASK: u8 = 15;
@@ -48859,8 +46947,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn tmrd(&mut self) -> _TMRDW {
_TMRDW { w: self }
}
@@ -48948,8 +47035,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:9 - Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles."]
- #[inline(always)]
+ # [ doc = "Bits 0:9 - Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." ] # [ inline ( always ) ]
pub fn extendedwait(&self) -> EXTENDEDWAITR {
let bits = {
const MASK: u16 = 1023;
@@ -48971,8 +47057,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:9 - Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles."]
- #[inline(always)]
+ # [ doc = "Bits 0:9 - Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." ] # [ inline ( always ) ]
pub fn extendedwait(&mut self) -> _EXTENDEDWAITW {
_EXTENDEDWAITW { w: self }
}
@@ -49090,12 +47175,7 @@ pub mod emc {
}
#[doc = "Possible values of the field `B`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BR {
- #[doc = "Disabled. Buffer disabled for accesses to this chip select (POR reset value)."]
- DISABLED,
- #[doc = "Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]"]
- ENABLED,
- }
+ pub enum BR {# [ doc = "Disabled. Buffer disabled for accesses to this chip select (POR reset value)." ] DISABLED , # [ doc = "Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" ] ENABLED}
impl BR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -49258,12 +47338,7 @@ pub mod emc {
}
}
#[doc = "Values that can be written to the field `B`"]
- pub enum BW {
- #[doc = "Disabled. Buffer disabled for accesses to this chip select (POR reset value)."]
- DISABLED,
- #[doc = "Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]"]
- ENABLED,
- }
+ pub enum BW {# [ doc = "Disabled. Buffer disabled for accesses to this chip select (POR reset value)." ] DISABLED , # [ doc = "Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" ] ENABLED}
impl BW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -49292,8 +47367,7 @@ pub mod emc {
pub fn disabled(self) -> &'a mut W {
self.variant(BW::DISABLED)
}
- #[doc = "Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]"]
- #[inline(always)]
+ # [ doc = "Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(BW::ENABLED)
}
@@ -49519,8 +47593,7 @@ pub mod emc {
pub enum RASR {
#[doc = "One EMC_CCLK cycle."] ONE_EMC_CCLK_CYCLE,
#[doc = "Two EMC_CCLK cycles."] TWO_EMC_CCLK_CYCLES,
- #[doc = "Three EMC_CCLK cycles (POR reset value)."]
- THREE_EMC_CCLK_CYCLE,
+ #[doc = "Three EMC_CCLK cycles (POR reset value)."] THREE_EMC_CCLK_CYCLE,
}
impl RASR {
#[doc = r" Value of the field as raw bits"]
@@ -49564,8 +47637,7 @@ pub mod emc {
pub enum CASR {
#[doc = "One EMC_CCLK cycle."] ONE_EMC_CCLK_CYCLE,
#[doc = "Two EMC_CCLK cycles."] TWO_EMC_CCLK_CYCLES,
- #[doc = "Three EMC_CCLK cycles (POR reset value)."]
- THREE_EMC_CCLK_CYCLE,
+ #[doc = "Three EMC_CCLK cycles (POR reset value)."] THREE_EMC_CCLK_CYCLE,
}
impl CASR {
#[doc = r" Value of the field as raw bits"]
@@ -49608,8 +47680,7 @@ pub mod emc {
pub enum RASW {
#[doc = "One EMC_CCLK cycle."] ONE_EMC_CCLK_CYCLE,
#[doc = "Two EMC_CCLK cycles."] TWO_EMC_CCLK_CYCLES,
- #[doc = "Three EMC_CCLK cycles (POR reset value)."]
- THREE_EMC_CCLK_CYCLE,
+ #[doc = "Three EMC_CCLK cycles (POR reset value)."] THREE_EMC_CCLK_CYCLE,
}
impl RASW {
#[allow(missing_docs)]
@@ -49662,8 +47733,7 @@ pub mod emc {
pub enum CASW {
#[doc = "One EMC_CCLK cycle."] ONE_EMC_CCLK_CYCLE,
#[doc = "Two EMC_CCLK cycles."] TWO_EMC_CCLK_CYCLES,
- #[doc = "Three EMC_CCLK cycles (POR reset value)."]
- THREE_EMC_CCLK_CYCLE,
+ #[doc = "Three EMC_CCLK cycles (POR reset value)."] THREE_EMC_CCLK_CYCLE,
}
impl CASW {
#[allow(missing_docs)]
@@ -49859,8 +47929,7 @@ pub mod emc {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PMR {
#[doc = "Disabled. (POR reset value.)"] DISABLED,
- #[doc = "Enabled. Async page mode enabled (page length four)."]
- ENABLED,
+ #[doc = "Enabled. Async page mode enabled (page length four)."] ENABLED,
}
impl PMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -49948,12 +48017,7 @@ pub mod emc {
}
#[doc = "Possible values of the field `PB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PBR {
- #[doc = "High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)."]
- HIGH,
- #[doc = "Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW."]
- LOW,
- }
+ pub enum PBR {# [ doc = "High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." ] HIGH , # [ doc = "Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." ] LOW}
impl PBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -49996,8 +48060,7 @@ pub mod emc {
#[doc = "Possible values of the field `EW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EWR {
- #[doc = "Disabled. Extended wait disabled (POR reset value)."]
- DISABLED,
+ #[doc = "Disabled. Extended wait disabled (POR reset value)."] DISABLED,
#[doc = "Enabled. Extended wait enabled."] ENABLED,
}
impl EWR {
@@ -50185,8 +48248,7 @@ pub mod emc {
#[doc = "Values that can be written to the field `PM`"]
pub enum PMW {
#[doc = "Disabled. (POR reset value.)"] DISABLED,
- #[doc = "Enabled. Async page mode enabled (page length four)."]
- ENABLED,
+ #[doc = "Enabled. Async page mode enabled (page length four)."] ENABLED,
}
impl PMW {
#[allow(missing_docs)]
@@ -50296,12 +48358,7 @@ pub mod emc {
}
}
#[doc = "Values that can be written to the field `PB`"]
- pub enum PBW {
- #[doc = "High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)."]
- HIGH,
- #[doc = "Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW."]
- LOW,
- }
+ pub enum PBW {# [ doc = "High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." ] HIGH , # [ doc = "Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." ] LOW}
impl PBW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -50325,13 +48382,11 @@ pub mod emc {
self.bit(variant._bits())
}
}
- #[doc = "High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)."]
- #[inline(always)]
+ # [ doc = "High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." ] # [ inline ( always ) ]
pub fn high(self) -> &'a mut W {
self.variant(PBW::HIGH)
}
- #[doc = "Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW."]
- #[inline(always)]
+ # [ doc = "Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." ] # [ inline ( always ) ]
pub fn low(self) -> &'a mut W {
self.variant(PBW::LOW)
}
@@ -50355,8 +48410,7 @@ pub mod emc {
}
#[doc = "Values that can be written to the field `EW`"]
pub enum EWW {
- #[doc = "Disabled. Extended wait disabled (POR reset value)."]
- DISABLED,
+ #[doc = "Disabled. Extended wait disabled (POR reset value)."] DISABLED,
#[doc = "Enabled. Extended wait enabled."] ENABLED,
}
impl EWW {
@@ -50537,8 +48591,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 3 - Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally." ] # [ inline ( always ) ]
pub fn pm(&self) -> PMR {
PMR::_from({
const MASK: bool = true;
@@ -50546,8 +48599,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Chip select polarity. The value of the chip select polarity on power-on reset is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Chip select polarity. The value of the chip select polarity on power-on reset is 0." ] # [ inline ( always ) ]
pub fn pc(&self) -> PCR {
PCR::_from({
const MASK: bool = true;
@@ -50555,8 +48607,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal." ] # [ inline ( always ) ]
pub fn pb(&self) -> PBR {
PBR::_from({
const MASK: bool = true;
@@ -50564,8 +48615,7 @@ pub mod emc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]" ] # [ inline ( always ) ]
pub fn ew(&self) -> EWR {
EWR::_from({
const MASK: bool = true;
@@ -50609,23 +48659,19 @@ pub mod emc {
pub fn mw(&mut self) -> _MWW {
_MWW { w: self }
}
- #[doc = "Bit 3 - Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally." ] # [ inline ( always ) ]
pub fn pm(&mut self) -> _PMW {
_PMW { w: self }
}
- #[doc = "Bit 6 - Chip select polarity. The value of the chip select polarity on power-on reset is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Chip select polarity. The value of the chip select polarity on power-on reset is 0." ] # [ inline ( always ) ]
pub fn pc(&mut self) -> _PCW {
_PCW { w: self }
}
- #[doc = "Bit 7 - Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal." ] # [ inline ( always ) ]
pub fn pb(&mut self) -> _PBW {
_PBW { w: self }
}
- #[doc = "Bit 8 - Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]" ] # [ inline ( always ) ]
pub fn ew(&mut self) -> _EWW {
_EWW { w: self }
}
@@ -50723,8 +48769,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." ] # [ inline ( always ) ]
pub fn waitwen(&self) -> WAITWENR {
let bits = {
const MASK: u8 = 15;
@@ -50746,18 +48791,17 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." ] # [ inline ( always ) ]
pub fn waitwen(&mut self) -> _WAITWENW {
_WAITWENW { w: self }
}
}
}
- #[doc = "Selects the delay from chip select 0 or address change, whichever is later, to output enable."]
+ # [ doc = "Selects the delay from chip select 0 or address change, whichever is later, to output enable." ]
pub struct STATICWAITOEN {
register: VolatileCell<u32>,
}
- #[doc = "Selects the delay from chip select 0 or address change, whichever is later, to output enable."]
+ # [ doc = "Selects the delay from chip select 0 or address change, whichever is later, to output enable." ]
pub mod staticwaitoen {
#[doc = r" Value read from the register"]
pub struct R {
@@ -50835,8 +48879,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." ] # [ inline ( always ) ]
pub fn waitoen(&self) -> WAITOENR {
let bits = {
const MASK: u8 = 15;
@@ -50858,8 +48901,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." ] # [ inline ( always ) ]
pub fn waitoen(&mut self) -> _WAITOENW {
_WAITOENW { w: self }
}
@@ -50947,8 +48989,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." ] # [ inline ( always ) ]
pub fn waitrd(&self) -> WAITRDR {
let bits = {
const MASK: u8 = 31;
@@ -50970,8 +49011,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." ] # [ inline ( always ) ]
pub fn waitrd(&mut self) -> _WAITRDW {
_WAITRDW { w: self }
}
@@ -51059,8 +49099,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." ] # [ inline ( always ) ]
pub fn waitpage(&self) -> WAITPAGER {
let bits = {
const MASK: u8 = 31;
@@ -51082,8 +49121,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." ] # [ inline ( always ) ]
pub fn waitpage(&mut self) -> _WAITPAGEW {
_WAITPAGEW { w: self }
}
@@ -51171,8 +49209,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." ] # [ inline ( always ) ]
pub fn waitwr(&self) -> WAITWRR {
let bits = {
const MASK: u8 = 31;
@@ -51194,8 +49231,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." ] # [ inline ( always ) ]
pub fn waitwr(&mut self) -> _WAITWRW {
_WAITWRW { w: self }
}
@@ -51283,8 +49319,7 @@ pub mod emc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn waitturn(&self) -> WAITTURNR {
let bits = {
const MASK: u8 = 15;
@@ -51306,8 +49341,7 @@ pub mod emc {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." ] # [ inline ( always ) ]
pub fn waitturn(&mut self) -> _WAITTURNW {
_WAITTURNW { w: self }
}
@@ -51331,7 +49365,48 @@ pub mod usb0 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock { _reserved0 : [ u8 ; 256usize ] , # [ doc = "0x100 - Capability register length" ] pub caplength : CAPLENGTH , # [ doc = "0x104 - Host controller structural parameters" ] pub hcsparams : HCSPARAMS , # [ doc = "0x108 - Host controller capability parameters" ] pub hccparams : HCCPARAMS , _reserved1 : [ u8 ; 20usize ] , # [ doc = "0x120 - Device interface version number" ] pub dciversion : DCIVERSION , _reserved2 : [ u8 ; 28usize ] , # [ doc = "0x140 - USB command (device mode)" ] pub usbcmd_d : USBCMD_D , # [ doc = "0x144 - USB status (device mode)" ] pub usbsts_d : USBSTS_D , # [ doc = "0x148 - USB interrupt enable (device mode)" ] pub usbintr_d : USBINTR_D , # [ doc = "0x14c - USB frame index (device mode)" ] pub frindex_d : FRINDEX_D , _reserved3 : [ u8 ; 4usize ] , # [ doc = "0x154 - USB device address (device mode)" ] pub deviceaddr : DEVICEADDR , # [ doc = "0x158 - Address of endpoint list in memory" ] pub endpointlistaddr : ENDPOINTLISTADDR , # [ doc = "0x15c - Asynchronous buffer status for embedded TT (host mode)" ] pub ttctrl : TTCTRL , # [ doc = "0x160 - Programmable burst size" ] pub burstsize : BURSTSIZE , # [ doc = "0x164 - Host transmit pre-buffer packet tuning (host mode)" ] pub txfilltuning : TXFILLTUNING , _reserved4 : [ u8 ; 12usize ] , # [ doc = "0x174 - Length of virtual frame" ] pub binterval : BINTERVAL , # [ doc = "0x178 - Endpoint NAK (device mode)" ] pub endptnak : ENDPTNAK , # [ doc = "0x17c - Endpoint NAK Enable (device mode)" ] pub endptnaken : ENDPTNAKEN , _reserved5 : [ u8 ; 4usize ] , # [ doc = "0x184 - Port 1 status/control (device mode)" ] pub portsc1_d : PORTSC1_D , _reserved6 : [ u8 ; 28usize ] , # [ doc = "0x1a4 - OTG status and control" ] pub otgsc : OTGSC , # [ doc = "0x1a8 - USB device mode (device mode)" ] pub usbmode_d : USBMODE_D , # [ doc = "0x1ac - Endpoint setup status" ] pub endptsetupstat : ENDPTSETUPSTAT , # [ doc = "0x1b0 - Endpoint initialization" ] pub endptprime : ENDPTPRIME , # [ doc = "0x1b4 - Endpoint de-initialization" ] pub endptflush : ENDPTFLUSH , # [ doc = "0x1b8 - Endpoint status" ] pub endptstat : ENDPTSTAT , # [ doc = "0x1bc - Endpoint complete" ] pub endptcomplete : ENDPTCOMPLETE , # [ doc = "0x1c0 - Endpoint control 0" ] pub endptctrl0 : ENDPTCTRL0 , # [ doc = "0x1c4 - Endpoint control" ] pub endptctrl1 : ENDPTCTRL , # [ doc = "0x1c8 - Endpoint control" ] pub endptctrl2 : ENDPTCTRL , # [ doc = "0x1cc - Endpoint control" ] pub endptctrl3 : ENDPTCTRL , # [ doc = "0x1d0 - Endpoint control" ] pub endptctrl4 : ENDPTCTRL , # [ doc = "0x1d4 - Endpoint control" ] pub endptctrl5 : ENDPTCTRL , }
+ pub struct RegisterBlock {
+ _reserved0: [u8; 256usize],
+ #[doc = "0x100 - Capability register length"] pub caplength: CAPLENGTH,
+ #[doc = "0x104 - Host controller structural parameters"] pub hcsparams: HCSPARAMS,
+ #[doc = "0x108 - Host controller capability parameters"] pub hccparams: HCCPARAMS,
+ _reserved1: [u8; 20usize],
+ #[doc = "0x120 - Device interface version number"] pub dciversion: DCIVERSION,
+ _reserved2: [u8; 28usize],
+ #[doc = "0x140 - USB command (device mode)"] pub usbcmd_d: USBCMD_D,
+ #[doc = "0x144 - USB status (device mode)"] pub usbsts_d: USBSTS_D,
+ #[doc = "0x148 - USB interrupt enable (device mode)"] pub usbintr_d: USBINTR_D,
+ #[doc = "0x14c - USB frame index (device mode)"] pub frindex_d: FRINDEX_D,
+ _reserved3: [u8; 4usize],
+ #[doc = "0x154 - USB device address (device mode)"] pub deviceaddr: DEVICEADDR,
+ #[doc = "0x158 - Address of endpoint list in memory"]
+ pub endpointlistaddr: ENDPOINTLISTADDR,
+ #[doc = "0x15c - Asynchronous buffer status for embedded TT (host mode)"]
+ pub ttctrl: TTCTRL,
+ #[doc = "0x160 - Programmable burst size"] pub burstsize: BURSTSIZE,
+ #[doc = "0x164 - Host transmit pre-buffer packet tuning (host mode)"]
+ pub txfilltuning: TXFILLTUNING,
+ _reserved4: [u8; 12usize],
+ #[doc = "0x174 - Length of virtual frame"] pub binterval: BINTERVAL,
+ #[doc = "0x178 - Endpoint NAK (device mode)"] pub endptnak: ENDPTNAK,
+ #[doc = "0x17c - Endpoint NAK Enable (device mode)"] pub endptnaken: ENDPTNAKEN,
+ _reserved5: [u8; 4usize],
+ #[doc = "0x184 - Port 1 status/control (device mode)"] pub portsc1_d: PORTSC1_D,
+ _reserved6: [u8; 28usize],
+ #[doc = "0x1a4 - OTG status and control"] pub otgsc: OTGSC,
+ #[doc = "0x1a8 - USB device mode (device mode)"] pub usbmode_d: USBMODE_D,
+ #[doc = "0x1ac - Endpoint setup status"] pub endptsetupstat: ENDPTSETUPSTAT,
+ #[doc = "0x1b0 - Endpoint initialization"] pub endptprime: ENDPTPRIME,
+ #[doc = "0x1b4 - Endpoint de-initialization"] pub endptflush: ENDPTFLUSH,
+ #[doc = "0x1b8 - Endpoint status"] pub endptstat: ENDPTSTAT,
+ #[doc = "0x1bc - Endpoint complete"] pub endptcomplete: ENDPTCOMPLETE,
+ #[doc = "0x1c0 - Endpoint control 0"] pub endptctrl0: ENDPTCTRL0,
+ #[doc = "0x1c4 - Endpoint control"] pub endptctrl1: ENDPTCTRL,
+ #[doc = "0x1c8 - Endpoint control"] pub endptctrl2: ENDPTCTRL,
+ #[doc = "0x1cc - Endpoint control"] pub endptctrl3: ENDPTCTRL,
+ #[doc = "0x1d0 - Endpoint control"] pub endptctrl4: ENDPTCTRL,
+ #[doc = "0x1d4 - Endpoint control"] pub endptctrl5: ENDPTCTRL,
+ }
#[doc = "Capability register length"]
pub struct CAPLENGTH {
register: VolatileCell<u32>,
@@ -51379,8 +49454,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Indicates offset to add to the register base address at the beginning of the Operational Register"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Indicates offset to add to the register base address at the beginning of the Operational Register" ] # [ inline ( always ) ]
pub fn caplength(&self) -> CAPLENGTHR {
let bits = {
const MASK: u8 = 255;
@@ -51389,8 +49463,7 @@ pub mod usb0 {
};
CAPLENGTHR { bits }
}
- #[doc = "Bits 8:23 - BCD encoding of the EHCI revision number supported by this host controller."]
- #[inline(always)]
+ # [ doc = "Bits 8:23 - BCD encoding of the EHCI revision number supported by this host controller." ] # [ inline ( always ) ]
pub fn hciversion(&self) -> HCIVERSIONR {
let bits = {
const MASK: u16 = 65535;
@@ -51523,8 +49596,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." ] # [ inline ( always ) ]
pub fn n_ports(&self) -> N_PORTSR {
let bits = {
const MASK: u8 = 15;
@@ -51533,8 +49605,7 @@ pub mod usb0 {
};
N_PORTSR { bits }
}
- #[doc = "Bit 4 - Port Power Control. This field indicates whether the host controller implementation includes port power control."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Port Power Control. This field indicates whether the host controller implementation includes port power control." ] # [ inline ( always ) ]
pub fn ppc(&self) -> PPCR {
let bits = {
const MASK: bool = true;
@@ -51543,8 +49614,7 @@ pub mod usb0 {
};
PPCR { bits }
}
- #[doc = "Bits 8:11 - Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller."]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." ] # [ inline ( always ) ]
pub fn n_pcc(&self) -> N_PCCR {
let bits = {
const MASK: u8 = 15;
@@ -51553,8 +49623,7 @@ pub mod usb0 {
};
N_PCCR { bits }
}
- #[doc = "Bits 12:15 - Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller."]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." ] # [ inline ( always ) ]
pub fn n_cc(&self) -> N_CCR {
let bits = {
const MASK: u8 = 15;
@@ -51563,8 +49632,7 @@ pub mod usb0 {
};
N_CCR { bits }
}
- #[doc = "Bit 16 - Port indicators. This bit indicates whether the ports support port indicator control."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Port indicators. This bit indicates whether the ports support port indicator control." ] # [ inline ( always ) ]
pub fn pi(&self) -> PIR {
let bits = {
const MASK: bool = true;
@@ -51573,8 +49641,7 @@ pub mod usb0 {
};
PIR { bits }
}
- #[doc = "Bits 20:23 - Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller."]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." ] # [ inline ( always ) ]
pub fn n_ptt(&self) -> N_PTTR {
let bits = {
const MASK: u8 = 15;
@@ -51583,8 +49650,7 @@ pub mod usb0 {
};
N_PTTR { bits }
}
- #[doc = "Bits 24:27 - Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller."]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." ] # [ inline ( always ) ]
pub fn n_tt(&self) -> N_TTR {
let bits = {
const MASK: u8 = 15;
@@ -51705,8 +49771,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported."]
- #[inline(always)]
+ # [ doc = "Bit 0 - 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." ] # [ inline ( always ) ]
pub fn adc(&self) -> ADCR {
let bits = {
const MASK: bool = true;
@@ -51715,8 +49780,7 @@ pub mod usb0 {
};
ADCR { bits }
}
- #[doc = "Bit 1 - Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." ] # [ inline ( always ) ]
pub fn pfl(&self) -> PFLR {
let bits = {
const MASK: bool = true;
@@ -51725,8 +49789,7 @@ pub mod usb0 {
};
PFLR { bits }
}
- #[doc = "Bit 2 - Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." ] # [ inline ( always ) ]
pub fn asp(&self) -> ASPR {
let bits = {
const MASK: bool = true;
@@ -51735,8 +49798,7 @@ pub mod usb0 {
};
ASPR { bits }
}
- #[doc = "Bits 4:7 - Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." ] # [ inline ( always ) ]
pub fn ist(&self) -> ISTR {
let bits = {
const MASK: u8 = 15;
@@ -51745,8 +49807,7 @@ pub mod usb0 {
};
ISTR { bits }
}
- #[doc = "Bits 8:15 - EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." ] # [ inline ( always ) ]
pub fn eecp(&self) -> EECPR {
let bits = {
const MASK: u8 = 255;
@@ -51793,8 +49854,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." ] # [ inline ( always ) ]
pub fn dciversion(&self) -> DCIVERSIONR {
let bits = {
const MASK: u16 = 65535;
@@ -51857,11 +49917,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `RS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSR {
- #[doc = "Writing a 0 to this bit will cause a detach event."] DETACH,
- #[doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized."]
- ATTACH,
- }
+ pub enum RSR {# [ doc = "Writing a 0 to this bit will cause a detach event." ] DETACH , # [ doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." ] ATTACH}
impl RSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -51903,12 +49959,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `RST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSTR {
- #[doc = "Set to 0 by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
- RESET,
- }
+ pub enum RSTR {# [ doc = "Set to 0 by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." ] RESET}
impl RSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -52002,11 +50053,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `RS`"]
- pub enum RSW {
- #[doc = "Writing a 0 to this bit will cause a detach event."] DETACH,
- #[doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized."]
- ATTACH,
- }
+ pub enum RSW {# [ doc = "Writing a 0 to this bit will cause a detach event." ] DETACH , # [ doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." ] ATTACH}
impl RSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -52035,8 +50082,7 @@ pub mod usb0 {
pub fn detach(self) -> &'a mut W {
self.variant(RSW::DETACH)
}
- #[doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized."]
- #[inline(always)]
+ # [ doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." ] # [ inline ( always ) ]
pub fn attach(self) -> &'a mut W {
self.variant(RSW::ATTACH)
}
@@ -52059,12 +50105,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `RST`"]
- pub enum RSTW {
- #[doc = "Set to 0 by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
- RESET,
- }
+ pub enum RSTW {# [ doc = "Set to 0 by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." ] RESET}
impl RSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -52093,8 +50134,7 @@ pub mod usb0 {
pub fn resetcomplete(self) -> &'a mut W {
self.variant(RSTW::RESETCOMPLETE)
}
- #[doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
- #[inline(always)]
+ # [ doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." ] # [ inline ( always ) ]
pub fn reset(self) -> &'a mut W {
self.variant(RSTW::RESET)
}
@@ -52192,8 +50232,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&self) -> RSTR {
RSTR::_from({
const MASK: bool = true;
@@ -52201,8 +50240,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." ] # [ inline ( always ) ]
pub fn sutw(&self) -> SUTWR {
let bits = {
const MASK: bool = true;
@@ -52211,8 +50249,7 @@ pub mod usb0 {
};
SUTWR { bits }
}
- #[doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." ] # [ inline ( always ) ]
pub fn atdtw(&self) -> ATDTWR {
let bits = {
const MASK: bool = true;
@@ -52221,8 +50258,7 @@ pub mod usb0 {
};
ATDTWR { bits }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&self) -> ITCR {
let bits = {
const MASK: u8 = 255;
@@ -52249,23 +50285,19 @@ pub mod usb0 {
pub fn rs(&mut self) -> _RSW {
_RSW { w: self }
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&mut self) -> _RSTW {
_RSTW { w: self }
}
- #[doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." ] # [ inline ( always ) ]
pub fn sutw(&mut self) -> _SUTWW {
_SUTWW { w: self }
}
- #[doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." ] # [ inline ( always ) ]
pub fn atdtw(&mut self) -> _ATDTWW {
_ATDTWW { w: self }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&mut self) -> _ITCW {
_ITCW { w: self }
}
@@ -52323,12 +50355,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `RS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSR {
- #[doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)."]
- HALT,
- #[doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one."]
- PROCEED,
- }
+ pub enum RSR {# [ doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." ] HALT , # [ doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." ] PROCEED}
impl RSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -52370,12 +50397,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `RST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSTR {
- #[doc = "This bit is set to zero by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
- RESET,
- }
+ pub enum RSTR {# [ doc = "This bit is set to zero by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." ] RESET}
impl RSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -52460,8 +50482,7 @@ pub mod usb0 {
#[doc = "Possible values of the field `PSE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PSER {
- #[doc = "Do not process the periodic schedule."]
- DO_NOT_PROCESS_THE_P,
+ #[doc = "Do not process the periodic schedule."] DO_NOT_PROCESS_THE_P,
#[doc = "Use the PERIODICLISTBASE register to access the periodic schedule."]
USE_THE_PERIODICLIST,
}
@@ -52507,8 +50528,7 @@ pub mod usb0 {
#[doc = "Possible values of the field `ASE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ASER {
- #[doc = "Do not process the asynchronous schedule."]
- DO_NOT_PROCESS_THE_A,
+ #[doc = "Do not process the asynchronous schedule."] DO_NOT_PROCESS_THE_A,
#[doc = "Use the ASYNCLISTADDR to access the asynchronous schedule."]
USE_THE_ASYNCLISTADD,
}
@@ -52553,12 +50573,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `IAA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum IAAR {
- #[doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one."]
- THE_HOST_CONTROLLER_,
- #[doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results."]
- SOFTWARE_MUST_WRITE_,
- }
+ pub enum IAAR {# [ doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." ] THE_HOST_CONTROLLER_ , # [ doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." ] SOFTWARE_MUST_WRITE_}
impl IAAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -52687,12 +50702,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `RS`"]
- pub enum RSW {
- #[doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)."]
- HALT,
- #[doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one."]
- PROCEED,
- }
+ pub enum RSW {# [ doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." ] HALT , # [ doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." ] PROCEED}
impl RSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -52716,13 +50726,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)."]
- #[inline(always)]
+ # [ doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." ] # [ inline ( always ) ]
pub fn halt(self) -> &'a mut W {
self.variant(RSW::HALT)
}
- #[doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one."]
- #[inline(always)]
+ # [ doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." ] # [ inline ( always ) ]
pub fn proceed(self) -> &'a mut W {
self.variant(RSW::PROCEED)
}
@@ -52745,12 +50753,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `RST`"]
- pub enum RSTW {
- #[doc = "This bit is set to zero by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
- RESET,
- }
+ pub enum RSTW {# [ doc = "This bit is set to zero by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." ] RESET}
impl RSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -52779,8 +50782,7 @@ pub mod usb0 {
pub fn resetcomplete(self) -> &'a mut W {
self.variant(RSTW::RESETCOMPLETE)
}
- #[doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
- #[inline(always)]
+ # [ doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." ] # [ inline ( always ) ]
pub fn reset(self) -> &'a mut W {
self.variant(RSTW::RESET)
}
@@ -52850,8 +50852,7 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `PSE`"]
pub enum PSEW {
- #[doc = "Do not process the periodic schedule."]
- DO_NOT_PROCESS_THE_P,
+ #[doc = "Do not process the periodic schedule."] DO_NOT_PROCESS_THE_P,
#[doc = "Use the PERIODICLISTBASE register to access the periodic schedule."]
USE_THE_PERIODICLIST,
}
@@ -52908,8 +50909,7 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `ASE`"]
pub enum ASEW {
- #[doc = "Do not process the asynchronous schedule."]
- DO_NOT_PROCESS_THE_A,
+ #[doc = "Do not process the asynchronous schedule."] DO_NOT_PROCESS_THE_A,
#[doc = "Use the ASYNCLISTADDR to access the asynchronous schedule."]
USE_THE_ASYNCLISTADD,
}
@@ -52965,12 +50965,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `IAA`"]
- pub enum IAAW {
- #[doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one."]
- THE_HOST_CONTROLLER_,
- #[doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results."]
- SOFTWARE_MUST_WRITE_,
- }
+ pub enum IAAW {# [ doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." ] THE_HOST_CONTROLLER_ , # [ doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." ] SOFTWARE_MUST_WRITE_}
impl IAAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -52994,13 +50989,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one."]
- #[inline(always)]
+ # [ doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." ] # [ inline ( always ) ]
pub fn the_host_controller_(self) -> &'a mut W {
self.variant(IAAW::THE_HOST_CONTROLLER_)
}
- #[doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results."]
- #[inline(always)]
+ # [ doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." ] # [ inline ( always ) ]
pub fn software_must_write_(self) -> &'a mut W {
self.variant(IAAW::SOFTWARE_MUST_WRITE_)
}
@@ -53146,8 +51139,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&self) -> RSTR {
RSTR::_from({
const MASK: bool = true;
@@ -53155,8 +51147,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." ] # [ inline ( always ) ]
pub fn fs0(&self) -> FS0R {
let bits = {
const MASK: bool = true;
@@ -53175,8 +51166,7 @@ pub mod usb0 {
};
FS1R { bits }
}
- #[doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule."]
- #[inline(always)]
+ # [ doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule." ] # [ inline ( always ) ]
pub fn pse(&self) -> PSER {
PSER::_from({
const MASK: bool = true;
@@ -53184,8 +51174,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule." ] # [ inline ( always ) ]
pub fn ase(&self) -> ASER {
ASER::_from({
const MASK: bool = true;
@@ -53193,8 +51182,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule." ] # [ inline ( always ) ]
pub fn iaa(&self) -> IAAR {
IAAR::_from({
const MASK: bool = true;
@@ -53202,8 +51190,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 8:9 - Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." ] # [ inline ( always ) ]
pub fn asp1_0(&self) -> ASP1_0R {
let bits = {
const MASK: u8 = 3;
@@ -53231,8 +51218,7 @@ pub mod usb0 {
};
FS2R { bits }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&self) -> ITCR {
let bits = {
const MASK: u8 = 255;
@@ -53259,13 +51245,11 @@ pub mod usb0 {
pub fn rs(&mut self) -> _RSW {
_RSW { w: self }
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&mut self) -> _RSTW {
_RSTW { w: self }
}
- #[doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." ] # [ inline ( always ) ]
pub fn fs0(&mut self) -> _FS0W {
_FS0W { w: self }
}
@@ -53274,23 +51258,19 @@ pub mod usb0 {
pub fn fs1(&mut self) -> _FS1W {
_FS1W { w: self }
}
- #[doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule."]
- #[inline(always)]
+ # [ doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule." ] # [ inline ( always ) ]
pub fn pse(&mut self) -> _PSEW {
_PSEW { w: self }
}
- #[doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule." ] # [ inline ( always ) ]
pub fn ase(&mut self) -> _ASEW {
_ASEW { w: self }
}
- #[doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule." ] # [ inline ( always ) ]
pub fn iaa(&mut self) -> _IAAW {
_IAAW { w: self }
}
- #[doc = "Bits 8:9 - Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." ] # [ inline ( always ) ]
pub fn asp1_0(&mut self) -> _ASP1_0W {
_ASP1_0W { w: self }
}
@@ -53304,8 +51284,7 @@ pub mod usb0 {
pub fn fs2(&mut self) -> _FS2W {
_FS2W { w: self }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&mut self) -> _ITCW {
_ITCW { w: self }
}
@@ -53363,11 +51342,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `UI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -53409,11 +51384,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `UEI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UEIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)."]
- CLEAR,
- }
+ pub enum UEIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." ] CLEAR}
impl UEIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -53455,11 +51426,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `PCI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PCIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively."]
- CLEAR,
- }
+ pub enum PCIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." ] CLEAR}
impl PCIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -53522,11 +51489,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `URI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum URIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum URIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." ] CLEAR}
impl URIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -53568,11 +51531,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `SRI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SRIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp."]
- CLEAR,
- }
+ pub enum SRIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." ] CLEAR}
impl SRIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -53614,12 +51573,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `SLI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SLIR {
- #[doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it."]
- ST,
- #[doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum SLIR {# [ doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." ] ST , # [ doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one." ] CLEAR}
impl SLIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -53661,12 +51615,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `NAKI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum NAKIR {
- #[doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared."]
- ST,
- #[doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set."]
- CLEAR,
- }
+ pub enum NAKIR {# [ doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." ] ST , # [ doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." ] CLEAR}
impl NAKIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -53707,11 +51656,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `UI`"]
- pub enum UIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -53740,8 +51685,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(UIW::ST)
}
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UIW::CLEAR)
}
@@ -53764,11 +51708,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `UEI`"]
- pub enum UEIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)."]
- CLEAR,
- }
+ pub enum UEIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." ] CLEAR}
impl UEIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -53797,8 +51737,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(UEIW::ST)
}
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)."]
- #[inline(always)]
+ # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UEIW::CLEAR)
}
@@ -53821,11 +51760,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `PCI`"]
- pub enum PCIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively."]
- CLEAR,
- }
+ pub enum PCIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." ] CLEAR}
impl PCIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -53854,8 +51789,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(PCIW::ST)
}
- #[doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively."]
- #[inline(always)]
+ # [ doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(PCIW::CLEAR)
}
@@ -53901,11 +51835,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `URI`"]
- pub enum URIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum URIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." ] CLEAR}
impl URIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -53934,8 +51864,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(URIW::ST)
}
- #[doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one."]
- #[inline(always)]
+ # [ doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(URIW::CLEAR)
}
@@ -53958,11 +51887,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `SRI`"]
- pub enum SRIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp."]
- CLEAR,
- }
+ pub enum SRIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." ] CLEAR}
impl SRIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -53991,8 +51916,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(SRIW::ST)
}
- #[doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp."]
- #[inline(always)]
+ # [ doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(SRIW::CLEAR)
}
@@ -54015,12 +51939,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `SLI`"]
- pub enum SLIW {
- #[doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it."]
- ST,
- #[doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum SLIW {# [ doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." ] ST , # [ doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one." ] CLEAR}
impl SLIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -54044,13 +51963,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it."]
- #[inline(always)]
+ # [ doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." ] # [ inline ( always ) ]
pub fn st(self) -> &'a mut W {
self.variant(SLIW::ST)
}
- #[doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one."]
- #[inline(always)]
+ # [ doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(SLIW::CLEAR)
}
@@ -54073,12 +51990,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `NAKI`"]
- pub enum NAKIW {
- #[doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared."]
- ST,
- #[doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set."]
- CLEAR,
- }
+ pub enum NAKIW {# [ doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." ] ST , # [ doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." ] CLEAR}
impl NAKIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -54102,13 +52014,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared."]
- #[inline(always)]
+ # [ doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." ] # [ inline ( always ) ]
pub fn st(self) -> &'a mut W {
self.variant(NAKIW::ST)
}
- #[doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set."]
- #[inline(always)]
+ # [ doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(NAKIW::CLEAR)
}
@@ -54316,11 +52226,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `UI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54362,11 +52268,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `UEI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UEIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
- CLEAR,
- }
+ pub enum UEIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." ] CLEAR}
impl UEIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54408,11 +52310,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `PCI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PCIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port."]
- CLEAR,
- }
+ pub enum PCIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." ] CLEAR}
impl PCIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54454,11 +52352,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `FRI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum FRIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)."]
- CLEAR,
- }
+ pub enum FRIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." ] CLEAR}
impl FRIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54500,11 +52394,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `AAI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum AAIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
- CLEAR,
- }
+ pub enum AAIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." ] CLEAR}
impl AAIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54546,11 +52436,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `SRI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SRIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base."]
- CLEAR,
- }
+ pub enum SRIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." ] CLEAR}
impl SRIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54592,12 +52478,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `HCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum HCHR {
- #[doc = "The RS bit in USBCMD is set to zero. Set by the host controller."]
- RS,
- #[doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)."]
- HALT,
- }
+ pub enum HCHR {# [ doc = "The RS bit in USBCMD is set to zero. Set by the host controller." ] RS , # [ doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." ] HALT}
impl HCHR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54640,8 +52521,7 @@ pub mod usb0 {
#[doc = "Possible values of the field `RCL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RCLR {
- #[doc = "No empty asynchronous schedule detected."]
- NO_EMPTY_ASYNCHRONOU,
+ #[doc = "No empty asynchronous schedule detected."] NO_EMPTY_ASYNCHRONOU,
#[doc = "An empty asynchronous schedule is detected. Set by the host controller."]
EMPTY_ASYNCHRONOU,
}
@@ -54776,11 +52656,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `UAI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UAIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UAIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UAIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54822,11 +52698,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `UPI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UPIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UPIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UPIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -54867,11 +52739,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `UI`"]
- pub enum UIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -54900,8 +52768,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(UIW::ST)
}
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UIW::CLEAR)
}
@@ -54924,11 +52791,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `UEI`"]
- pub enum UEIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
- CLEAR,
- }
+ pub enum UEIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." ] CLEAR}
impl UEIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -54957,8 +52820,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(UEIW::ST)
}
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
- #[inline(always)]
+ # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UEIW::CLEAR)
}
@@ -54981,11 +52843,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `PCI`"]
- pub enum PCIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port."]
- CLEAR,
- }
+ pub enum PCIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." ] CLEAR}
impl PCIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -55014,8 +52872,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(PCIW::ST)
}
- #[doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port."]
- #[inline(always)]
+ # [ doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(PCIW::CLEAR)
}
@@ -55038,11 +52895,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `FRI`"]
- pub enum FRIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)."]
- CLEAR,
- }
+ pub enum FRIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." ] CLEAR}
impl FRIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -55071,8 +52924,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(FRIW::ST)
}
- #[doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)."]
- #[inline(always)]
+ # [ doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(FRIW::CLEAR)
}
@@ -55095,11 +52947,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `AAI`"]
- pub enum AAIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
- CLEAR,
- }
+ pub enum AAIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." ] CLEAR}
impl AAIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -55128,8 +52976,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(AAIW::ST)
}
- #[doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
- #[inline(always)]
+ # [ doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(AAIW::CLEAR)
}
@@ -55152,11 +52999,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `SRI`"]
- pub enum SRIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base."]
- CLEAR,
- }
+ pub enum SRIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." ] CLEAR}
impl SRIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -55185,8 +53028,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(SRIW::ST)
}
- #[doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base."]
- #[inline(always)]
+ # [ doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(SRIW::CLEAR)
}
@@ -55209,12 +53051,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `HCH`"]
- pub enum HCHW {
- #[doc = "The RS bit in USBCMD is set to zero. Set by the host controller."]
- RS,
- #[doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)."]
- HALT,
- }
+ pub enum HCHW {# [ doc = "The RS bit in USBCMD is set to zero. Set by the host controller." ] RS , # [ doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." ] HALT}
impl HCHW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -55243,8 +53080,7 @@ pub mod usb0 {
pub fn rs(self) -> &'a mut W {
self.variant(HCHW::RS)
}
- #[doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)."]
- #[inline(always)]
+ # [ doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." ] # [ inline ( always ) ]
pub fn halt(self) -> &'a mut W {
self.variant(HCHW::HALT)
}
@@ -55268,8 +53104,7 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `RCL`"]
pub enum RCLW {
- #[doc = "No empty asynchronous schedule detected."]
- NO_EMPTY_ASYNCHRONOU,
+ #[doc = "No empty asynchronous schedule detected."] NO_EMPTY_ASYNCHRONOU,
#[doc = "An empty asynchronous schedule is detected. Set by the host controller."]
EMPTY_ASYNCHRONOU,
}
@@ -55437,11 +53272,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `UAI`"]
- pub enum UAIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UAIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UAIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -55470,8 +53301,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(UAIW::ST)
}
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UAIW::CLEAR)
}
@@ -55494,11 +53324,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `UPI`"]
- pub enum UPIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UPIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UPIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -55527,8 +53353,7 @@ pub mod usb0 {
pub fn st(self) -> &'a mut W {
self.variant(UPIW::ST)
}
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UPIW::CLEAR)
}
@@ -55628,8 +53453,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn ps(&self) -> PSR {
PSR::_from({
const MASK: bool = true;
@@ -55637,8 +53461,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn as_(&self) -> ASR {
ASR::_from({
const MASK: bool = true;
@@ -55717,13 +53540,11 @@ pub mod usb0 {
pub fn rcl(&mut self) -> _RCLW {
_RCLW { w: self }
}
- #[doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn ps(&mut self) -> _PSW {
_PSW { w: self }
}
- #[doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn as_(&mut self) -> _ASW {
_ASW { w: self }
}
@@ -56103,8 +53924,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&self) -> UER {
let bits = {
const MASK: bool = true;
@@ -56113,8 +53933,7 @@ pub mod usb0 {
};
UER { bits }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&self) -> UEER {
let bits = {
const MASK: bool = true;
@@ -56123,8 +53942,7 @@ pub mod usb0 {
};
UEER { bits }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&self) -> PCER {
let bits = {
const MASK: bool = true;
@@ -56133,8 +53951,7 @@ pub mod usb0 {
};
PCER { bits }
}
- #[doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." ] # [ inline ( always ) ]
pub fn ure(&self) -> URER {
let bits = {
const MASK: bool = true;
@@ -56143,8 +53960,7 @@ pub mod usb0 {
};
URER { bits }
}
- #[doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." ] # [ inline ( always ) ]
pub fn sre(&self) -> SRER {
let bits = {
const MASK: bool = true;
@@ -56153,8 +53969,7 @@ pub mod usb0 {
};
SRER { bits }
}
- #[doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." ] # [ inline ( always ) ]
pub fn sle(&self) -> SLER {
let bits = {
const MASK: bool = true;
@@ -56163,8 +53978,7 @@ pub mod usb0 {
};
SLER { bits }
}
- #[doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated."]
- #[inline(always)]
+ # [ doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." ] # [ inline ( always ) ]
pub fn nake(&self) -> NAKER {
let bits = {
const MASK: bool = true;
@@ -56186,38 +54000,31 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&mut self) -> _UEW {
_UEW { w: self }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&mut self) -> _UEEW {
_UEEW { w: self }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&mut self) -> _PCEW {
_PCEW { w: self }
}
- #[doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." ] # [ inline ( always ) ]
pub fn ure(&mut self) -> _UREW {
_UREW { w: self }
}
- #[doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." ] # [ inline ( always ) ]
pub fn sre(&mut self) -> _SREW {
_SREW { w: self }
}
- #[doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." ] # [ inline ( always ) ]
pub fn sle(&mut self) -> _SLEW {
_SLEW { w: self }
}
- #[doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated."]
- #[inline(always)]
+ # [ doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." ] # [ inline ( always ) ]
pub fn nake(&mut self) -> _NAKEW {
_NAKEW { w: self }
}
@@ -56631,8 +54438,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&self) -> UER {
let bits = {
const MASK: bool = true;
@@ -56641,8 +54447,7 @@ pub mod usb0 {
};
UER { bits }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&self) -> UEER {
let bits = {
const MASK: bool = true;
@@ -56651,8 +54456,7 @@ pub mod usb0 {
};
UEER { bits }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&self) -> PCER {
let bits = {
const MASK: bool = true;
@@ -56661,8 +54465,7 @@ pub mod usb0 {
};
PCER { bits }
}
- #[doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." ] # [ inline ( always ) ]
pub fn fre(&self) -> FRER {
let bits = {
const MASK: bool = true;
@@ -56671,8 +54474,7 @@ pub mod usb0 {
};
FRER { bits }
}
- #[doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." ] # [ inline ( always ) ]
pub fn aae(&self) -> AAER {
let bits = {
const MASK: bool = true;
@@ -56681,8 +54483,7 @@ pub mod usb0 {
};
AAER { bits }
}
- #[doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn sre(&self) -> SRER {
let bits = {
const MASK: bool = true;
@@ -56691,8 +54492,7 @@ pub mod usb0 {
};
SRER { bits }
}
- #[doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." ] # [ inline ( always ) ]
pub fn uaie(&self) -> UAIER {
let bits = {
const MASK: bool = true;
@@ -56701,8 +54501,7 @@ pub mod usb0 {
};
UAIER { bits }
}
- #[doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." ] # [ inline ( always ) ]
pub fn upia(&self) -> UPIAR {
let bits = {
const MASK: bool = true;
@@ -56724,43 +54523,35 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&mut self) -> _UEW {
_UEW { w: self }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&mut self) -> _UEEW {
_UEEW { w: self }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&mut self) -> _PCEW {
_PCEW { w: self }
}
- #[doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." ] # [ inline ( always ) ]
pub fn fre(&mut self) -> _FREW {
_FREW { w: self }
}
- #[doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." ] # [ inline ( always ) ]
pub fn aae(&mut self) -> _AAEW {
_AAEW { w: self }
}
- #[doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn sre(&mut self) -> _SREW {
_SREW { w: self }
}
- #[doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." ] # [ inline ( always ) ]
pub fn uaie(&mut self) -> _UAIEW {
_UAIEW { w: self }
}
- #[doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." ] # [ inline ( always ) ]
pub fn upia(&mut self) -> _UPIAW {
_UPIAW { w: self }
}
@@ -57124,11 +54915,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `USBADRA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum USBADRAR {
- #[doc = "Any write to USBADR are instantaneous."] INSTANTANEOUS,
- #[doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement."]
- DELAYED,
- }
+ pub enum USBADRAR {# [ doc = "Any write to USBADR are instantaneous." ] INSTANTANEOUS , # [ doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." ] DELAYED}
impl USBADRAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -57180,11 +54967,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `USBADRA`"]
- pub enum USBADRAW {
- #[doc = "Any write to USBADR are instantaneous."] INSTANTANEOUS,
- #[doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement."]
- DELAYED,
- }
+ pub enum USBADRAW {# [ doc = "Any write to USBADR are instantaneous." ] INSTANTANEOUS , # [ doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." ] DELAYED}
impl USBADRAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -57213,8 +54996,7 @@ pub mod usb0 {
pub fn instantaneous(self) -> &'a mut W {
self.variant(USBADRAW::INSTANTANEOUS)
}
- #[doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement."]
- #[inline(always)]
+ # [ doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." ] # [ inline ( always ) ]
pub fn delayed(self) -> &'a mut W {
self.variant(USBADRAW::DELAYED)
}
@@ -57383,8 +55165,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals 31:12."]
- #[inline(always)]
+ # [ doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals 31:12." ] # [ inline ( always ) ]
pub fn perbase31_12(&self) -> PERBASE31_12R {
let bits = {
const MASK: u32 = 1048575;
@@ -57406,8 +55187,7 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals 31:12."]
- #[inline(always)]
+ # [ doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals 31:12." ] # [ inline ( always ) ]
pub fn perbase31_12(&mut self) -> _PERBASE31_12W {
_PERBASE31_12W { w: self }
}
@@ -57495,8 +55275,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)"]
- #[inline(always)]
+ # [ doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" ] # [ inline ( always ) ]
pub fn epbase31_11(&self) -> EPBASE31_11R {
let bits = {
const MASK: u32 = 2097151;
@@ -57518,8 +55297,7 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)"]
- #[inline(always)]
+ # [ doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" ] # [ inline ( always ) ]
pub fn epbase31_11(&mut self) -> _EPBASE31_11W {
_EPBASE31_11W { w: self }
}
@@ -57607,8 +55385,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)."]
- #[inline(always)]
+ # [ doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." ] # [ inline ( always ) ]
pub fn asybase31_5(&self) -> ASYBASE31_5R {
let bits = {
const MASK: u32 = 134217727;
@@ -57630,8 +55407,7 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)."]
- #[inline(always)]
+ # [ doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." ] # [ inline ( always ) ]
pub fn asybase31_5(&mut self) -> _ASYBASE31_5W {
_ASYBASE31_5W { w: self }
}
@@ -57857,8 +55633,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." ] # [ inline ( always ) ]
pub fn rxpburst(&self) -> RXPBURSTR {
let bits = {
const MASK: u8 = 255;
@@ -57867,8 +55642,7 @@ pub mod usb0 {
};
RXPBURSTR { bits }
}
- #[doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." ] # [ inline ( always ) ]
pub fn txpburst(&self) -> TXPBURSTR {
let bits = {
const MASK: u8 = 255;
@@ -57890,13 +55664,11 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." ] # [ inline ( always ) ]
pub fn rxpburst(&mut self) -> _RXPBURSTW {
_RXPBURSTW { w: self }
}
- #[doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." ] # [ inline ( always ) ]
pub fn txpburst(&mut self) -> _TXPBURSTW {
_TXPBURSTW { w: self }
}
@@ -58036,8 +55808,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." ] # [ inline ( always ) ]
pub fn txschoh(&self) -> TXSCHOHR {
let bits = {
const MASK: u8 = 255;
@@ -58046,8 +55817,7 @@ pub mod usb0 {
};
TXSCHOHR { bits }
}
- #[doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." ] # [ inline ( always ) ]
pub fn txscheatlth(&self) -> TXSCHEATLTHR {
let bits = {
const MASK: u8 = 31;
@@ -58056,8 +55826,7 @@ pub mod usb0 {
};
TXSCHEATLTHR { bits }
}
- #[doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode for OTG and SPH."]
- #[inline(always)]
+ # [ doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode for OTG and SPH." ] # [ inline ( always ) ]
pub fn txfifothres(&self) -> TXFIFOTHRESR {
let bits = {
const MASK: u8 = 63;
@@ -58079,18 +55848,15 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." ] # [ inline ( always ) ]
pub fn txschoh(&mut self) -> _TXSCHOHW {
_TXSCHOHW { w: self }
}
- #[doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." ] # [ inline ( always ) ]
pub fn txscheatlth(&mut self) -> _TXSCHEATLTHW {
_TXSCHEATLTHW { w: self }
}
- #[doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode for OTG and SPH."]
- #[inline(always)]
+ # [ doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode for OTG and SPH." ] # [ inline ( always ) ]
pub fn txfifothres(&mut self) -> _TXFIFOTHRESW {
_TXFIFOTHRESW { w: self }
}
@@ -58792,8 +56558,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn0(&self) -> EPRN0R {
let bits = {
const MASK: bool = true;
@@ -58802,8 +56567,7 @@ pub mod usb0 {
};
EPRN0R { bits }
}
- #[doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn1(&self) -> EPRN1R {
let bits = {
const MASK: bool = true;
@@ -58812,8 +56576,7 @@ pub mod usb0 {
};
EPRN1R { bits }
}
- #[doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn2(&self) -> EPRN2R {
let bits = {
const MASK: bool = true;
@@ -58822,8 +56585,7 @@ pub mod usb0 {
};
EPRN2R { bits }
}
- #[doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn3(&self) -> EPRN3R {
let bits = {
const MASK: bool = true;
@@ -58832,8 +56594,7 @@ pub mod usb0 {
};
EPRN3R { bits }
}
- #[doc = "Bit 4 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn4(&self) -> EPRN4R {
let bits = {
const MASK: bool = true;
@@ -58842,8 +56603,7 @@ pub mod usb0 {
};
EPRN4R { bits }
}
- #[doc = "Bit 5 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn5(&self) -> EPRN5R {
let bits = {
const MASK: bool = true;
@@ -58852,8 +56612,7 @@ pub mod usb0 {
};
EPRN5R { bits }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn0(&self) -> EPTN0R {
let bits = {
const MASK: bool = true;
@@ -58862,8 +56621,7 @@ pub mod usb0 {
};
EPTN0R { bits }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn1(&self) -> EPTN1R {
let bits = {
const MASK: bool = true;
@@ -58872,8 +56630,7 @@ pub mod usb0 {
};
EPTN1R { bits }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn2(&self) -> EPTN2R {
let bits = {
const MASK: bool = true;
@@ -58882,8 +56639,7 @@ pub mod usb0 {
};
EPTN2R { bits }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn3(&self) -> EPTN3R {
let bits = {
const MASK: bool = true;
@@ -58892,8 +56648,7 @@ pub mod usb0 {
};
EPTN3R { bits }
}
- #[doc = "Bit 20 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn4(&self) -> EPTN4R {
let bits = {
const MASK: bool = true;
@@ -58902,8 +56657,7 @@ pub mod usb0 {
};
EPTN4R { bits }
}
- #[doc = "Bit 21 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn5(&self) -> EPTN5R {
let bits = {
const MASK: bool = true;
@@ -58925,63 +56679,51 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn0(&mut self) -> _EPRN0W {
_EPRN0W { w: self }
}
- #[doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn1(&mut self) -> _EPRN1W {
_EPRN1W { w: self }
}
- #[doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn2(&mut self) -> _EPRN2W {
_EPRN2W { w: self }
}
- #[doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn3(&mut self) -> _EPRN3W {
_EPRN3W { w: self }
}
- #[doc = "Bit 4 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn4(&mut self) -> _EPRN4W {
_EPRN4W { w: self }
}
- #[doc = "Bit 5 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn5(&mut self) -> _EPRN5W {
_EPRN5W { w: self }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn0(&mut self) -> _EPTN0W {
_EPTN0W { w: self }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn1(&mut self) -> _EPTN1W {
_EPTN1W { w: self }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn2(&mut self) -> _EPTN2W {
_EPTN2W { w: self }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn3(&mut self) -> _EPTN3W {
_EPTN3W { w: self }
}
- #[doc = "Bit 20 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn4(&mut self) -> _EPTN4W {
_EPTN4W { w: self }
}
- #[doc = "Bit 21 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn5(&mut self) -> _EPTN5W {
_EPTN5W { w: self }
}
@@ -59571,8 +57313,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne0(&self) -> EPRNE0R {
let bits = {
const MASK: bool = true;
@@ -59581,8 +57322,7 @@ pub mod usb0 {
};
EPRNE0R { bits }
}
- #[doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne1(&self) -> EPRNE1R {
let bits = {
const MASK: bool = true;
@@ -59591,8 +57331,7 @@ pub mod usb0 {
};
EPRNE1R { bits }
}
- #[doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne2(&self) -> EPRNE2R {
let bits = {
const MASK: bool = true;
@@ -59601,8 +57340,7 @@ pub mod usb0 {
};
EPRNE2R { bits }
}
- #[doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne3(&self) -> EPRNE3R {
let bits = {
const MASK: bool = true;
@@ -59611,8 +57349,7 @@ pub mod usb0 {
};
EPRNE3R { bits }
}
- #[doc = "Bit 4 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne4(&self) -> EPRNE4R {
let bits = {
const MASK: bool = true;
@@ -59621,8 +57358,7 @@ pub mod usb0 {
};
EPRNE4R { bits }
}
- #[doc = "Bit 5 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne5(&self) -> EPRNE5R {
let bits = {
const MASK: bool = true;
@@ -59631,8 +57367,7 @@ pub mod usb0 {
};
EPRNE5R { bits }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne0(&self) -> EPTNE0R {
let bits = {
const MASK: bool = true;
@@ -59641,8 +57376,7 @@ pub mod usb0 {
};
EPTNE0R { bits }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne1(&self) -> EPTNE1R {
let bits = {
const MASK: bool = true;
@@ -59651,8 +57385,7 @@ pub mod usb0 {
};
EPTNE1R { bits }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne2(&self) -> EPTNE2R {
let bits = {
const MASK: bool = true;
@@ -59661,8 +57394,7 @@ pub mod usb0 {
};
EPTNE2R { bits }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne3(&self) -> EPTNE3R {
let bits = {
const MASK: bool = true;
@@ -59671,8 +57403,7 @@ pub mod usb0 {
};
EPTNE3R { bits }
}
- #[doc = "Bit 20 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne4(&self) -> EPTNE4R {
let bits = {
const MASK: bool = true;
@@ -59681,8 +57412,7 @@ pub mod usb0 {
};
EPTNE4R { bits }
}
- #[doc = "Bit 21 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne5(&self) -> EPTNE5R {
let bits = {
const MASK: bool = true;
@@ -59704,63 +57434,51 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne0(&mut self) -> _EPRNE0W {
_EPRNE0W { w: self }
}
- #[doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne1(&mut self) -> _EPRNE1W {
_EPRNE1W { w: self }
}
- #[doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne2(&mut self) -> _EPRNE2W {
_EPRNE2W { w: self }
}
- #[doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne3(&mut self) -> _EPRNE3W {
_EPRNE3W { w: self }
}
- #[doc = "Bit 4 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne4(&mut self) -> _EPRNE4W {
_EPRNE4W { w: self }
}
- #[doc = "Bit 5 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne5(&mut self) -> _EPRNE5W {
_EPRNE5W { w: self }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne0(&mut self) -> _EPTNE0W {
_EPTNE0W { w: self }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne1(&mut self) -> _EPTNE1W {
_EPTNE1W { w: self }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne2(&mut self) -> _EPTNE2W {
_EPTNE2W { w: self }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne3(&mut self) -> _EPTNE3W {
_EPTNE3W { w: self }
}
- #[doc = "Bit 20 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne4(&mut self) -> _EPTNE4W {
_EPTNE4W { w: self }
}
- #[doc = "Bit 21 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne5(&mut self) -> _EPTNE5W {
_EPTNE5W { w: self }
}
@@ -59818,12 +57536,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `CCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CCSR {
- #[doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended."]
- DEVICE_NOT_ATTACHED_,
- #[doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register."]
- DEVICE_ATTACHED__A_,
- }
+ pub enum CCSR {# [ doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." ] DEVICE_NOT_ATTACHED_ , # [ doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." ] DEVICE_ATTACHED__A_}
impl CCSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -60043,10 +57756,8 @@ pub mod usb0 {
#[doc = "Possible values of the field `HSP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HSPR {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NOT_HIGHSSPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HIGHSPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NOT_HIGHSSPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HIGHSPEED,
}
impl HSPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -60219,12 +57930,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `PHCD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PHCDR {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- ENABLE,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- DISABLE,
- }
+ pub enum PHCDR {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] ENABLE , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] DISABLE}
impl PHCDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -60266,11 +57972,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `PFSC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PFSCR {
- #[doc = "Port connects at any speed."] ANYSPEED,
- #[doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device."]
- FULLSPEED,
- }
+ pub enum PFSCR {# [ doc = "Port connects at any speed." ] ANYSPEED , # [ doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." ] FULLSPEED}
impl PFSCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -60357,12 +58059,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `CCS`"]
- pub enum CCSW {
- #[doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended."]
- DEVICE_NOT_ATTACHED_,
- #[doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register."]
- DEVICE_ATTACHED__A_,
- }
+ pub enum CCSW {# [ doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." ] DEVICE_NOT_ATTACHED_ , # [ doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." ] DEVICE_ATTACHED__A_}
impl CCSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -60386,13 +58083,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended."]
- #[inline(always)]
+ # [ doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." ] # [ inline ( always ) ]
pub fn device_not_attached_(self) -> &'a mut W {
self.variant(CCSW::DEVICE_NOT_ATTACHED_)
}
- #[doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register."]
- #[inline(always)]
+ # [ doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." ] # [ inline ( always ) ]
pub fn device_attached__a_(self) -> &'a mut W {
self.variant(CCSW::DEVICE_ATTACHED__A_)
}
@@ -60630,10 +58325,8 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `HSP`"]
pub enum HSPW {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NOT_HIGHSSPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HIGHSPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NOT_HIGHSSPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HIGHSPEED,
}
impl HSPW {
#[allow(missing_docs)]
@@ -60830,12 +58523,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `PHCD`"]
- pub enum PHCDW {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- ENABLE,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- DISABLE,
- }
+ pub enum PHCDW {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] ENABLE , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] DISABLE}
impl PHCDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -60859,13 +58547,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] # [ inline ( always ) ]
pub fn enable(self) -> &'a mut W {
self.variant(PHCDW::ENABLE)
}
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] # [ inline ( always ) ]
pub fn disable(self) -> &'a mut W {
self.variant(PHCDW::DISABLE)
}
@@ -60888,11 +58574,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `PFSC`"]
- pub enum PFSCW {
- #[doc = "Port connects at any speed."] ANYSPEED,
- #[doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device."]
- FULLSPEED,
- }
+ pub enum PFSCW {# [ doc = "Port connects at any speed." ] ANYSPEED , # [ doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." ] FULLSPEED}
impl PFSCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -60921,8 +58603,7 @@ pub mod usb0 {
pub fn anyspeed(self) -> &'a mut W {
self.variant(PFSCW::ANYSPEED)
}
- #[doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." ] # [ inline ( always ) ]
pub fn fullspeed(self) -> &'a mut W {
self.variant(PFSCW::FULLSPEED)
}
@@ -61022,8 +58703,7 @@ pub mod usb0 {
};
PER { bits }
}
- #[doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled." ] # [ inline ( always ) ]
pub fn pec(&self) -> PECR {
let bits = {
const MASK: bool = true;
@@ -61032,8 +58712,7 @@ pub mod usb0 {
};
PECR { bits }
}
- #[doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well." ] # [ inline ( always ) ]
pub fn fpr(&self) -> FPRR {
FPRR::_from({
const MASK: bool = true;
@@ -61050,8 +58729,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register." ] # [ inline ( always ) ]
pub fn pr(&self) -> PRR {
PRR::_from({
const MASK: bool = true;
@@ -61059,8 +58737,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons."]
- #[inline(always)]
+ # [ doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons." ] # [ inline ( always ) ]
pub fn hsp(&self) -> HSPR {
HSPR::_from({
const MASK: bool = true;
@@ -61068,8 +58745,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins." ] # [ inline ( always ) ]
pub fn pic1_0(&self) -> PIC1_0R {
PIC1_0R::_from({
const MASK: u8 = 3;
@@ -61077,8 +58753,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid." ] # [ inline ( always ) ]
pub fn ptc3_0(&self) -> PTC3_0R {
PTC3_0R::_from({
const MASK: u8 = 15;
@@ -61086,8 +58761,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit." ] # [ inline ( always ) ]
pub fn phcd(&self) -> PHCDR {
PHCDR::_from({
const MASK: bool = true;
@@ -61104,8 +58778,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating." ] # [ inline ( always ) ]
pub fn pspd(&self) -> PSPDR {
PSPDR::_from({
const MASK: u8 = 3;
@@ -61136,13 +58809,11 @@ pub mod usb0 {
pub fn pe(&mut self) -> _PEW {
_PEW { w: self }
}
- #[doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled." ] # [ inline ( always ) ]
pub fn pec(&mut self) -> _PECW {
_PECW { w: self }
}
- #[doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well." ] # [ inline ( always ) ]
pub fn fpr(&mut self) -> _FPRW {
_FPRW { w: self }
}
@@ -61151,28 +58822,23 @@ pub mod usb0 {
pub fn susp(&mut self) -> _SUSPW {
_SUSPW { w: self }
}
- #[doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register." ] # [ inline ( always ) ]
pub fn pr(&mut self) -> _PRW {
_PRW { w: self }
}
- #[doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons."]
- #[inline(always)]
+ # [ doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons." ] # [ inline ( always ) ]
pub fn hsp(&mut self) -> _HSPW {
_HSPW { w: self }
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins." ] # [ inline ( always ) ]
pub fn pic1_0(&mut self) -> _PIC1_0W {
_PIC1_0W { w: self }
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid." ] # [ inline ( always ) ]
pub fn ptc3_0(&mut self) -> _PTC3_0W {
_PTC3_0W { w: self }
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit." ] # [ inline ( always ) ]
pub fn phcd(&mut self) -> _PHCDW {
_PHCDW { w: self }
}
@@ -61181,8 +58847,7 @@ pub mod usb0 {
pub fn pfsc(&mut self) -> _PFSCW {
_PFSCW { w: self }
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating." ] # [ inline ( always ) ]
pub fn pspd(&mut self) -> _PSPDW {
_PSPDW { w: self }
}
@@ -61421,10 +59086,8 @@ pub mod usb0 {
#[doc = "Possible values of the field `OCA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OCAR {
- #[doc = "The port does not have an over-current condition."]
- THE_PORT_DOES_NOT_HA,
- #[doc = "The port has currently an over-current condition."]
- THE_PORT_HAS_CURRENT,
+ #[doc = "The port does not have an over-current condition."] THE_PORT_DOES_NOT_HA,
+ #[doc = "The port has currently an over-current condition."] THE_PORT_HAS_CURRENT,
}
impl OCAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -61533,11 +59196,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `SUSP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SUSPR {
- #[doc = "Port not in suspend state"] PORT_NOT_IN_SUSPEND_,
- #[doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB."]
- PORT_IN_SUSPEND_STAT,
- }
+ pub enum SUSPR {# [ doc = "Port not in suspend state" ] PORT_NOT_IN_SUSPEND_ , # [ doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." ] PORT_IN_SUSPEND_STAT}
impl SUSPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -61625,10 +59284,8 @@ pub mod usb0 {
#[doc = "Possible values of the field `HSP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HSPR {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NO_HISPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HISPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NO_HISPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HISPEED,
}
impl HSPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -61906,12 +59563,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `WKCN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WKCNR {
- #[doc = "Disables the port to wake up on device connects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events."]
- WRITING_THIS_BIT_TO_,
- }
+ pub enum WKCNR {# [ doc = "Disables the port to wake up on device connects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." ] WRITING_THIS_BIT_TO_}
impl WKCNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -61953,12 +59605,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `WKDC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WKDCR {
- #[doc = "Disables the port to wake up on device disconnects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events."]
- WRITING_THIS_BIT_TO_,
- }
+ pub enum WKDCR {# [ doc = "Disables the port to wake up on device disconnects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." ] WRITING_THIS_BIT_TO_}
impl WKDCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -62000,12 +59647,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `WKOC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WKOCR {
- #[doc = "Disables the port to wake up on over-current events."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events."]
- WRITING_A_ONE_TO_THI,
- }
+ pub enum WKOCR {# [ doc = "Disables the port to wake up on over-current events." ] DISABLES_THE_PORT_TO , # [ doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." ] WRITING_A_ONE_TO_THI}
impl WKOCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -62047,12 +59689,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `PHCD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PHCDR {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- WRITING_A_0_ENABLES_,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- WRITING_A_1_DISABLES,
- }
+ pub enum PHCDR {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] WRITING_A_0_ENABLES_ , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] WRITING_A_1_DISABLES}
impl PHCDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -62094,11 +59731,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `PFSC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PFSCR {
- #[doc = "Port connects at any speed."] PORT_CONNECTS_AT_ANY,
- #[doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device."]
- WRITING_THIS_BIT_TO_,
- }
+ pub enum PFSCR {# [ doc = "Port connects at any speed." ] PORT_CONNECTS_AT_ANY , # [ doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." ] WRITING_THIS_BIT_TO_}
impl PFSCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -62410,10 +60043,8 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `OCA`"]
pub enum OCAW {
- #[doc = "The port does not have an over-current condition."]
- THE_PORT_DOES_NOT_HA,
- #[doc = "The port has currently an over-current condition."]
- THE_PORT_HAS_CURRENT,
+ #[doc = "The port does not have an over-current condition."] THE_PORT_DOES_NOT_HA,
+ #[doc = "The port has currently an over-current condition."] THE_PORT_HAS_CURRENT,
}
impl OCAW {
#[allow(missing_docs)]
@@ -62546,11 +60177,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `SUSP`"]
- pub enum SUSPW {
- #[doc = "Port not in suspend state"] PORT_NOT_IN_SUSPEND_,
- #[doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB."]
- PORT_IN_SUSPEND_STAT,
- }
+ pub enum SUSPW {# [ doc = "Port not in suspend state" ] PORT_NOT_IN_SUSPEND_ , # [ doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." ] PORT_IN_SUSPEND_STAT}
impl SUSPW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -62579,8 +60206,7 @@ pub mod usb0 {
pub fn port_not_in_suspend_(self) -> &'a mut W {
self.variant(SUSPW::PORT_NOT_IN_SUSPEND_)
}
- #[doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB."]
- #[inline(always)]
+ # [ doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." ] # [ inline ( always ) ]
pub fn port_in_suspend_stat(self) -> &'a mut W {
self.variant(SUSPW::PORT_IN_SUSPEND_STAT)
}
@@ -62660,10 +60286,8 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `HSP`"]
pub enum HSPW {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NO_HISPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HISPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NO_HISPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HISPEED,
}
impl HSPW {
#[allow(missing_docs)]
@@ -62985,12 +60609,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `WKCN`"]
- pub enum WKCNW {
- #[doc = "Disables the port to wake up on device connects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events."]
- WRITING_THIS_BIT_TO_,
- }
+ pub enum WKCNW {# [ doc = "Disables the port to wake up on device connects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." ] WRITING_THIS_BIT_TO_}
impl WKCNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -63019,8 +60638,7 @@ pub mod usb0 {
pub fn disables_the_port_to(self) -> &'a mut W {
self.variant(WKCNW::DISABLES_THE_PORT_TO)
}
- #[doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." ] # [ inline ( always ) ]
pub fn writing_this_bit_to_(self) -> &'a mut W {
self.variant(WKCNW::WRITING_THIS_BIT_TO_)
}
@@ -63043,12 +60661,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `WKDC`"]
- pub enum WKDCW {
- #[doc = "Disables the port to wake up on device disconnects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events."]
- WRITING_THIS_BIT_TO_,
- }
+ pub enum WKDCW {# [ doc = "Disables the port to wake up on device disconnects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." ] WRITING_THIS_BIT_TO_}
impl WKDCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -63077,8 +60690,7 @@ pub mod usb0 {
pub fn disables_the_port_to(self) -> &'a mut W {
self.variant(WKDCW::DISABLES_THE_PORT_TO)
}
- #[doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." ] # [ inline ( always ) ]
pub fn writing_this_bit_to_(self) -> &'a mut W {
self.variant(WKDCW::WRITING_THIS_BIT_TO_)
}
@@ -63101,12 +60713,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `WKOC`"]
- pub enum WKOCW {
- #[doc = "Disables the port to wake up on over-current events."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events."]
- WRITING_A_ONE_TO_THI,
- }
+ pub enum WKOCW {# [ doc = "Disables the port to wake up on over-current events." ] DISABLES_THE_PORT_TO , # [ doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." ] WRITING_A_ONE_TO_THI}
impl WKOCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -63135,8 +60742,7 @@ pub mod usb0 {
pub fn disables_the_port_to(self) -> &'a mut W {
self.variant(WKOCW::DISABLES_THE_PORT_TO)
}
- #[doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events."]
- #[inline(always)]
+ # [ doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." ] # [ inline ( always ) ]
pub fn writing_a_one_to_thi(self) -> &'a mut W {
self.variant(WKOCW::WRITING_A_ONE_TO_THI)
}
@@ -63159,12 +60765,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `PHCD`"]
- pub enum PHCDW {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- WRITING_A_0_ENABLES_,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- WRITING_A_1_DISABLES,
- }
+ pub enum PHCDW {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] WRITING_A_0_ENABLES_ , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] WRITING_A_1_DISABLES}
impl PHCDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -63188,13 +60789,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] # [ inline ( always ) ]
pub fn writing_a_0_enables_(self) -> &'a mut W {
self.variant(PHCDW::WRITING_A_0_ENABLES_)
}
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] # [ inline ( always ) ]
pub fn writing_a_1_disables(self) -> &'a mut W {
self.variant(PHCDW::WRITING_A_1_DISABLES)
}
@@ -63217,11 +60816,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `PFSC`"]
- pub enum PFSCW {
- #[doc = "Port connects at any speed."] PORT_CONNECTS_AT_ANY,
- #[doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device."]
- WRITING_THIS_BIT_TO_,
- }
+ pub enum PFSCW {# [ doc = "Port connects at any speed." ] PORT_CONNECTS_AT_ANY , # [ doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." ] WRITING_THIS_BIT_TO_}
impl PFSCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -63250,8 +60845,7 @@ pub mod usb0 {
pub fn port_connects_at_any(self) -> &'a mut W {
self.variant(PFSCW::PORT_CONNECTS_AT_ANY)
}
- #[doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." ] # [ inline ( always ) ]
pub fn writing_this_bit_to_(self) -> &'a mut W {
self.variant(PFSCW::WRITING_THIS_BIT_TO_)
}
@@ -63332,8 +60926,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it." ] # [ inline ( always ) ]
pub fn ccs(&self) -> CCSR {
CCSR::_from({
const MASK: bool = true;
@@ -63341,8 +60934,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn csc(&self) -> CSCR {
CSCR::_from({
const MASK: bool = true;
@@ -63350,8 +60942,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
@@ -63359,8 +60950,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0," ] # [ inline ( always ) ]
pub fn pec(&self) -> PECR {
PECR::_from({
const MASK: bool = true;
@@ -63368,8 +60958,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed." ] # [ inline ( always ) ]
pub fn oca(&self) -> OCAR {
OCAR::_from({
const MASK: bool = true;
@@ -63377,8 +60966,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." ] # [ inline ( always ) ]
pub fn occ(&self) -> OCCR {
let bits = {
const MASK: bool = true;
@@ -63387,8 +60975,7 @@ pub mod usb0 {
};
OCCR { bits }
}
- #[doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn fpr(&self) -> FPRR {
FPRR::_from({
const MASK: bool = true;
@@ -63396,8 +60983,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn susp(&self) -> SUSPR {
SUSPR::_from({
const MASK: bool = true;
@@ -63405,8 +60991,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pr(&self) -> PRR {
PRR::_from({
const MASK: bool = true;
@@ -63423,8 +61008,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS." ] # [ inline ( always ) ]
pub fn ls(&self) -> LSR {
LSR::_from({
const MASK: u8 = 3;
@@ -63432,8 +61016,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 12 - Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)." ] # [ inline ( always ) ]
pub fn pp(&self) -> PPR {
PPR::_from({
const MASK: bool = true;
@@ -63441,8 +61024,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0." ] # [ inline ( always ) ]
pub fn pic1_0(&self) -> PIC1_0R {
PIC1_0R::_from({
const MASK: u8 = 3;
@@ -63450,8 +61032,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved." ] # [ inline ( always ) ]
pub fn ptc3_0(&self) -> PTC3_0R {
PTC3_0R::_from({
const MASK: u8 = 15;
@@ -63459,8 +61040,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn wkcn(&self) -> WKCNR {
WKCNR::_from({
const MASK: bool = true;
@@ -63468,8 +61048,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn wkdc(&self) -> WKDCR {
WKDCR::_from({
const MASK: bool = true;
@@ -63486,8 +61065,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software." ] # [ inline ( always ) ]
pub fn phcd(&self) -> PHCDR {
PHCDR::_from({
const MASK: bool = true;
@@ -63504,8 +61082,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator." ] # [ inline ( always ) ]
pub fn pspd(&self) -> PSPDR {
PSPDR::_from({
const MASK: u8 = 3;
@@ -63526,48 +61103,39 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it." ] # [ inline ( always ) ]
pub fn ccs(&mut self) -> _CCSW {
_CCSW { w: self }
}
- #[doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn csc(&mut self) -> _CSCW {
_CSCW { w: self }
}
- #[doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pe(&mut self) -> _PEW {
_PEW { w: self }
}
- #[doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0," ] # [ inline ( always ) ]
pub fn pec(&mut self) -> _PECW {
_PECW { w: self }
}
- #[doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed." ] # [ inline ( always ) ]
pub fn oca(&mut self) -> _OCAW {
_OCAW { w: self }
}
- #[doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." ] # [ inline ( always ) ]
pub fn occ(&mut self) -> _OCCW {
_OCCW { w: self }
}
- #[doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn fpr(&mut self) -> _FPRW {
_FPRW { w: self }
}
- #[doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn susp(&mut self) -> _SUSPW {
_SUSPW { w: self }
}
- #[doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pr(&mut self) -> _PRW {
_PRW { w: self }
}
@@ -63576,33 +61144,27 @@ pub mod usb0 {
pub fn hsp(&mut self) -> _HSPW {
_HSPW { w: self }
}
- #[doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS." ] # [ inline ( always ) ]
pub fn ls(&mut self) -> _LSW {
_LSW { w: self }
}
- #[doc = "Bit 12 - Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)." ] # [ inline ( always ) ]
pub fn pp(&mut self) -> _PPW {
_PPW { w: self }
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0." ] # [ inline ( always ) ]
pub fn pic1_0(&mut self) -> _PIC1_0W {
_PIC1_0W { w: self }
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved." ] # [ inline ( always ) ]
pub fn ptc3_0(&mut self) -> _PTC3_0W {
_PTC3_0W { w: self }
}
- #[doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn wkcn(&mut self) -> _WKCNW {
_WKCNW { w: self }
}
- #[doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn wkdc(&mut self) -> _WKDCW {
_WKDCW { w: self }
}
@@ -63611,8 +61173,7 @@ pub mod usb0 {
pub fn wkoc(&mut self) -> _WKOCW {
_WKOCW { w: self }
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software." ] # [ inline ( always ) ]
pub fn phcd(&mut self) -> _PHCDW {
_PHCDW { w: self }
}
@@ -63621,8 +61182,7 @@ pub mod usb0 {
pub fn pfsc(&mut self) -> _PFSCW {
_PFSCW { w: self }
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator." ] # [ inline ( always ) ]
pub fn pspd(&mut self) -> _PSPDW {
_PSPDW { w: self }
}
@@ -63724,8 +61284,7 @@ pub mod usb0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HAARR {
#[doc = "Disabled"] DISABLED,
- #[doc = "Enable automatic reset after connect on host port."]
- ENABLE_AUTOMATIC_RES,
+ #[doc = "Enable automatic reset after connect on host port."] ENABLE_AUTOMATIC_RES,
}
impl HAARR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -63811,8 +61370,7 @@ pub mod usb0 {
#[doc = "Possible values of the field `IDPU`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDPUR {
- #[doc = "Pull-up off. The ID bit will not be sampled."]
- PULL_UP_OFF_THE_ID_,
+ #[doc = "Pull-up off. The ID bit will not be sampled."] PULL_UP_OFF_THE_ID_,
#[doc = "Pull-up on."] PULL_UP_ON_,
}
impl IDPUR {
@@ -63879,8 +61437,7 @@ pub mod usb0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HABAR {
#[doc = "Disabled."] DISABLED_,
- #[doc = "Enable automatic B-disconnect to A-connect sequence."]
- ENABLE_AUTOMATIC_B_D,
+ #[doc = "Enable automatic B-disconnect to A-connect sequence."] ENABLE_AUTOMATIC_B_D,
}
impl HABAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -64435,8 +61992,7 @@ pub mod usb0 {
#[doc = "Values that can be written to the field `HAAR`"]
pub enum HAARW {
#[doc = "Disabled"] DISABLED,
- #[doc = "Enable automatic reset after connect on host port."]
- ENABLE_AUTOMATIC_RES,
+ #[doc = "Enable automatic reset after connect on host port."] ENABLE_AUTOMATIC_RES,
}
impl HAARW {
#[allow(missing_docs)]
@@ -64537,8 +62093,7 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `IDPU`"]
pub enum IDPUW {
- #[doc = "Pull-up off. The ID bit will not be sampled."]
- PULL_UP_OFF_THE_ID_,
+ #[doc = "Pull-up off. The ID bit will not be sampled."] PULL_UP_OFF_THE_ID_,
#[doc = "Pull-up on."] PULL_UP_ON_,
}
impl IDPUW {
@@ -64618,8 +62173,7 @@ pub mod usb0 {
#[doc = "Values that can be written to the field `HABA`"]
pub enum HABAW {
#[doc = "Disabled."] DISABLED_,
- #[doc = "Enable automatic B-disconnect to A-connect sequence."]
- ENABLE_AUTOMATIC_B_D,
+ #[doc = "Enable automatic B-disconnect to A-connect sequence."] ENABLE_AUTOMATIC_B_D,
}
impl HABAW {
#[allow(missing_docs)]
@@ -65194,8 +62748,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor."]
- #[inline(always)]
+ # [ doc = "Bit 0 - VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." ] # [ inline ( always ) ]
pub fn vd(&self) -> VDR {
let bits = {
const MASK: bool = true;
@@ -65204,8 +62757,7 @@ pub mod usb0 {
};
VDR { bits }
}
- #[doc = "Bit 1 - VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP."]
- #[inline(always)]
+ # [ doc = "Bit 1 - VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." ] # [ inline ( always ) ]
pub fn vc(&self) -> VCR {
let bits = {
const MASK: bool = true;
@@ -65223,8 +62775,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM."]
- #[inline(always)]
+ # [ doc = "Bit 3 - OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." ] # [ inline ( always ) ]
pub fn ot(&self) -> OTR {
let bits = {
const MASK: bool = true;
@@ -65233,8 +62784,7 @@ pub mod usb0 {
};
OTR { bits }
}
- #[doc = "Bit 4 - Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." ] # [ inline ( always ) ]
pub fn dp(&self) -> DPR {
let bits = {
const MASK: bool = true;
@@ -65280,8 +62830,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 9 - A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." ] # [ inline ( always ) ]
pub fn avv(&self) -> AVVR {
let bits = {
const MASK: bool = true;
@@ -65290,8 +62839,7 @@ pub mod usb0 {
};
AVVR { bits }
}
- #[doc = "Bit 10 - A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." ] # [ inline ( always ) ]
pub fn asv(&self) -> ASVR {
let bits = {
const MASK: bool = true;
@@ -65300,8 +62848,7 @@ pub mod usb0 {
};
ASVR { bits }
}
- #[doc = "Bit 11 - B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold."]
- #[inline(always)]
+ # [ doc = "Bit 11 - B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." ] # [ inline ( always ) ]
pub fn bsv(&self) -> BSVR {
let bits = {
const MASK: bool = true;
@@ -65310,8 +62857,7 @@ pub mod usb0 {
};
BSVR { bits }
}
- #[doc = "Bit 12 - B-session end Reading 1 indicates that VBUS is below the B-session end threshold."]
- #[inline(always)]
+ # [ doc = "Bit 12 - B-session end Reading 1 indicates that VBUS is below the B-session end threshold." ] # [ inline ( always ) ]
pub fn bse(&self) -> BSER {
let bits = {
const MASK: bool = true;
@@ -65330,8 +62876,7 @@ pub mod usb0 {
};
MS1TR { bits }
}
- #[doc = "Bit 14 - Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." ] # [ inline ( always ) ]
pub fn dps(&self) -> DPSR {
let bits = {
const MASK: bool = true;
@@ -65340,8 +62885,7 @@ pub mod usb0 {
};
DPSR { bits }
}
- #[doc = "Bit 16 - USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 16 - USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn idis(&self) -> IDISR {
let bits = {
const MASK: bool = true;
@@ -65350,8 +62894,7 @@ pub mod usb0 {
};
IDISR { bits }
}
- #[doc = "Bit 17 - A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 17 - A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn avvis(&self) -> AVVISR {
let bits = {
const MASK: bool = true;
@@ -65360,8 +62903,7 @@ pub mod usb0 {
};
AVVISR { bits }
}
- #[doc = "Bit 18 - A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 18 - A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn asvis(&self) -> ASVISR {
let bits = {
const MASK: bool = true;
@@ -65370,8 +62912,7 @@ pub mod usb0 {
};
ASVISR { bits }
}
- #[doc = "Bit 19 - B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 19 - B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn bsvis(&self) -> BSVISR {
let bits = {
const MASK: bool = true;
@@ -65380,8 +62921,7 @@ pub mod usb0 {
};
BSVISR { bits }
}
- #[doc = "Bit 20 - B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 20 - B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn bseis(&self) -> BSEISR {
let bits = {
const MASK: bool = true;
@@ -65390,8 +62930,7 @@ pub mod usb0 {
};
BSEISR { bits }
}
- #[doc = "Bit 21 - 1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 21 - 1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn ms1s(&self) -> MS1SR {
let bits = {
const MASK: bool = true;
@@ -65400,8 +62939,7 @@ pub mod usb0 {
};
MS1SR { bits }
}
- #[doc = "Bit 22 - Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn dpis(&self) -> DPISR {
let bits = {
const MASK: bool = true;
@@ -65410,8 +62948,7 @@ pub mod usb0 {
};
DPISR { bits }
}
- #[doc = "Bit 24 - USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 24 - USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn idie(&self) -> IDIER {
let bits = {
const MASK: bool = true;
@@ -65420,8 +62957,7 @@ pub mod usb0 {
};
IDIER { bits }
}
- #[doc = "Bit 25 - A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 25 - A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn avvie(&self) -> AVVIER {
let bits = {
const MASK: bool = true;
@@ -65430,8 +62966,7 @@ pub mod usb0 {
};
AVVIER { bits }
}
- #[doc = "Bit 26 - A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 26 - A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" ] # [ inline ( always ) ]
pub fn asvie(&self) -> ASVIER {
let bits = {
const MASK: bool = true;
@@ -65440,8 +62975,7 @@ pub mod usb0 {
};
ASVIER { bits }
}
- #[doc = "Bit 27 - B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 27 - B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn bsvie(&self) -> BSVIER {
let bits = {
const MASK: bool = true;
@@ -65450,8 +62984,7 @@ pub mod usb0 {
};
BSVIER { bits }
}
- #[doc = "Bit 28 - B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 28 - B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn bseie(&self) -> BSEIER {
let bits = {
const MASK: bool = true;
@@ -65460,8 +62993,7 @@ pub mod usb0 {
};
BSEIER { bits }
}
- #[doc = "Bit 29 - 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 29 - 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn ms1e(&self) -> MS1ER {
let bits = {
const MASK: bool = true;
@@ -65470,8 +63002,7 @@ pub mod usb0 {
};
MS1ER { bits }
}
- #[doc = "Bit 30 - Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 30 - Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" ] # [ inline ( always ) ]
pub fn dpie(&self) -> DPIER {
let bits = {
const MASK: bool = true;
@@ -65493,13 +63024,11 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor."]
- #[inline(always)]
+ # [ doc = "Bit 0 - VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." ] # [ inline ( always ) ]
pub fn vd(&mut self) -> _VDW {
_VDW { w: self }
}
- #[doc = "Bit 1 - VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP."]
- #[inline(always)]
+ # [ doc = "Bit 1 - VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." ] # [ inline ( always ) ]
pub fn vc(&mut self) -> _VCW {
_VCW { w: self }
}
@@ -65508,13 +63037,11 @@ pub mod usb0 {
pub fn haar(&mut self) -> _HAARW {
_HAARW { w: self }
}
- #[doc = "Bit 3 - OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM."]
- #[inline(always)]
+ # [ doc = "Bit 3 - OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." ] # [ inline ( always ) ]
pub fn ot(&mut self) -> _OTW {
_OTW { w: self }
}
- #[doc = "Bit 4 - Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." ] # [ inline ( always ) ]
pub fn dp(&mut self) -> _DPW {
_DPW { w: self }
}
@@ -65538,23 +63065,19 @@ pub mod usb0 {
pub fn id(&mut self) -> _IDW {
_IDW { w: self }
}
- #[doc = "Bit 9 - A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." ] # [ inline ( always ) ]
pub fn avv(&mut self) -> _AVVW {
_AVVW { w: self }
}
- #[doc = "Bit 10 - A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." ] # [ inline ( always ) ]
pub fn asv(&mut self) -> _ASVW {
_ASVW { w: self }
}
- #[doc = "Bit 11 - B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold."]
- #[inline(always)]
+ # [ doc = "Bit 11 - B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." ] # [ inline ( always ) ]
pub fn bsv(&mut self) -> _BSVW {
_BSVW { w: self }
}
- #[doc = "Bit 12 - B-session end Reading 1 indicates that VBUS is below the B-session end threshold."]
- #[inline(always)]
+ # [ doc = "Bit 12 - B-session end Reading 1 indicates that VBUS is below the B-session end threshold." ] # [ inline ( always ) ]
pub fn bse(&mut self) -> _BSEW {
_BSEW { w: self }
}
@@ -65563,78 +63086,63 @@ pub mod usb0 {
pub fn ms1t(&mut self) -> _MS1TW {
_MS1TW { w: self }
}
- #[doc = "Bit 14 - Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." ] # [ inline ( always ) ]
pub fn dps(&mut self) -> _DPSW {
_DPSW { w: self }
}
- #[doc = "Bit 16 - USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 16 - USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn idis(&mut self) -> _IDISW {
_IDISW { w: self }
}
- #[doc = "Bit 17 - A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 17 - A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn avvis(&mut self) -> _AVVISW {
_AVVISW { w: self }
}
- #[doc = "Bit 18 - A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 18 - A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn asvis(&mut self) -> _ASVISW {
_ASVISW { w: self }
}
- #[doc = "Bit 19 - B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 19 - B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn bsvis(&mut self) -> _BSVISW {
_BSVISW { w: self }
}
- #[doc = "Bit 20 - B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 20 - B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn bseis(&mut self) -> _BSEISW {
_BSEISW { w: self }
}
- #[doc = "Bit 21 - 1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 21 - 1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn ms1s(&mut self) -> _MS1SW {
_MS1SW { w: self }
}
- #[doc = "Bit 22 - Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." ] # [ inline ( always ) ]
pub fn dpis(&mut self) -> _DPISW {
_DPISW { w: self }
}
- #[doc = "Bit 24 - USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 24 - USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn idie(&mut self) -> _IDIEW {
_IDIEW { w: self }
}
- #[doc = "Bit 25 - A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 25 - A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn avvie(&mut self) -> _AVVIEW {
_AVVIEW { w: self }
}
- #[doc = "Bit 26 - A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 26 - A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" ] # [ inline ( always ) ]
pub fn asvie(&mut self) -> _ASVIEW {
_ASVIEW { w: self }
}
- #[doc = "Bit 27 - B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 27 - B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn bsvie(&mut self) -> _BSVIEW {
_BSVIEW { w: self }
}
- #[doc = "Bit 28 - B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 28 - B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn bseie(&mut self) -> _BSEIEW {
_BSEIEW { w: self }
}
- #[doc = "Bit 29 - 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 29 - 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." ] # [ inline ( always ) ]
pub fn ms1e(&mut self) -> _MS1EW {
_MS1EW { w: self }
}
- #[doc = "Bit 30 - Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 30 - Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" ] # [ inline ( always ) ]
pub fn dpie(&mut self) -> _DPIEW {
_DPIEW { w: self }
}
@@ -65736,12 +63244,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `ES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ESR {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESR {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -65829,11 +63332,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `SDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SDISR {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active."]
- DISABLED_SETTING_TH,
- }
+ pub enum SDISR {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." ] DISABLED_SETTING_TH}
impl SDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -65927,12 +63426,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `ES`"]
- pub enum ESW {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESW {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -66042,11 +63536,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `SDIS`"]
- pub enum SDISW {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active."]
- DISABLED_SETTING_TH,
- }
+ pub enum SDISW {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." ] DISABLED_SETTING_TH}
impl SDISW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -66075,8 +63565,7 @@ pub mod usb0 {
pub fn not_disabled(self) -> &'a mut W {
self.variant(SDISW::NOT_DISABLED)
}
- #[doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active."]
- #[inline(always)]
+ # [ doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." ] # [ inline ( always ) ]
pub fn disabled_setting_th(self) -> &'a mut W {
self.variant(SDISW::DISABLED_SETTING_TH)
}
@@ -66104,8 +63593,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm1_0(&self) -> CM1_0R {
CM1_0R::_from({
const MASK: u8 = 3;
@@ -66113,8 +63601,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&self) -> ESR {
ESR::_from({
const MASK: bool = true;
@@ -66122,8 +63609,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8." ] # [ inline ( always ) ]
pub fn slom(&self) -> SLOMR {
SLOMR::_from({
const MASK: bool = true;
@@ -66131,8 +63617,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&self) -> SDISR {
SDISR::_from({
const MASK: bool = true;
@@ -66153,23 +63638,19 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm1_0(&mut self) -> _CM1_0W {
_CM1_0W { w: self }
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&mut self) -> _ESW {
_ESW { w: self }
}
- #[doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8." ] # [ inline ( always ) ]
pub fn slom(&mut self) -> _SLOMW {
_SLOMW { w: self }
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&mut self) -> _SDISW {
_SDISW { w: self }
}
@@ -66271,12 +63752,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `ES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ESR {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESR {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -66318,11 +63794,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `SDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SDISR {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature."]
- DISABLED_SETTING_TO,
- }
+ pub enum SDISR {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." ] DISABLED_SETTING_TO}
impl SDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -66461,12 +63933,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `ES`"]
- pub enum ESW {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESW {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -66519,11 +63986,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `SDIS`"]
- pub enum SDISW {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature."]
- DISABLED_SETTING_TO,
- }
+ pub enum SDISW {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." ] DISABLED_SETTING_TO}
impl SDISW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -66552,8 +64015,7 @@ pub mod usb0 {
pub fn not_disabled(self) -> &'a mut W {
self.variant(SDISW::NOT_DISABLED)
}
- #[doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature."]
- #[inline(always)]
+ # [ doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." ] # [ inline ( always ) ]
pub fn disabled_setting_to(self) -> &'a mut W {
self.variant(SDISW::DISABLED_SETTING_TO)
}
@@ -66637,8 +64099,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm(&self) -> CMR {
CMR::_from({
const MASK: u8 = 3;
@@ -66646,8 +64107,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&self) -> ESR {
ESR::_from({
const MASK: bool = true;
@@ -66655,8 +64115,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&self) -> SDISR {
SDISR::_from({
const MASK: bool = true;
@@ -66686,18 +64145,15 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm(&mut self) -> _CMW {
_CMW { w: self }
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&mut self) -> _ESW {
_ESW { w: self }
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&mut self) -> _SDISW {
_SDISW { w: self }
}
@@ -67028,8 +64484,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat0(&self) -> ENDPTSETUPSTAT0R {
let bits = {
const MASK: bool = true;
@@ -67038,8 +64493,7 @@ pub mod usb0 {
};
ENDPTSETUPSTAT0R { bits }
}
- #[doc = "Bit 1 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat1(&self) -> ENDPTSETUPSTAT1R {
let bits = {
const MASK: bool = true;
@@ -67048,8 +64502,7 @@ pub mod usb0 {
};
ENDPTSETUPSTAT1R { bits }
}
- #[doc = "Bit 2 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat2(&self) -> ENDPTSETUPSTAT2R {
let bits = {
const MASK: bool = true;
@@ -67058,8 +64511,7 @@ pub mod usb0 {
};
ENDPTSETUPSTAT2R { bits }
}
- #[doc = "Bit 3 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat3(&self) -> ENDPTSETUPSTAT3R {
let bits = {
const MASK: bool = true;
@@ -67068,8 +64520,7 @@ pub mod usb0 {
};
ENDPTSETUPSTAT3R { bits }
}
- #[doc = "Bit 4 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat4(&self) -> ENDPTSETUPSTAT4R {
let bits = {
const MASK: bool = true;
@@ -67078,8 +64529,7 @@ pub mod usb0 {
};
ENDPTSETUPSTAT4R { bits }
}
- #[doc = "Bit 5 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat5(&self) -> ENDPTSETUPSTAT5R {
let bits = {
const MASK: bool = true;
@@ -67101,33 +64551,27 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat0(&mut self) -> _ENDPTSETUPSTAT0W {
_ENDPTSETUPSTAT0W { w: self }
}
- #[doc = "Bit 1 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat1(&mut self) -> _ENDPTSETUPSTAT1W {
_ENDPTSETUPSTAT1W { w: self }
}
- #[doc = "Bit 2 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat2(&mut self) -> _ENDPTSETUPSTAT2W {
_ENDPTSETUPSTAT2W { w: self }
}
- #[doc = "Bit 3 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat3(&mut self) -> _ENDPTSETUPSTAT3W {
_ENDPTSETUPSTAT3W { w: self }
}
- #[doc = "Bit 4 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat4(&mut self) -> _ENDPTSETUPSTAT4W {
_ENDPTSETUPSTAT4W { w: self }
}
- #[doc = "Bit 5 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat5(&mut self) -> _ENDPTSETUPSTAT5W {
_ENDPTSETUPSTAT5W { w: self }
}
@@ -67717,8 +65161,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb0(&self) -> PERB0R {
let bits = {
const MASK: bool = true;
@@ -67727,8 +65170,7 @@ pub mod usb0 {
};
PERB0R { bits }
}
- #[doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb1(&self) -> PERB1R {
let bits = {
const MASK: bool = true;
@@ -67737,8 +65179,7 @@ pub mod usb0 {
};
PERB1R { bits }
}
- #[doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb2(&self) -> PERB2R {
let bits = {
const MASK: bool = true;
@@ -67747,8 +65188,7 @@ pub mod usb0 {
};
PERB2R { bits }
}
- #[doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb3(&self) -> PERB3R {
let bits = {
const MASK: bool = true;
@@ -67757,8 +65197,7 @@ pub mod usb0 {
};
PERB3R { bits }
}
- #[doc = "Bit 4 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb4(&self) -> PERB4R {
let bits = {
const MASK: bool = true;
@@ -67767,8 +65206,7 @@ pub mod usb0 {
};
PERB4R { bits }
}
- #[doc = "Bit 5 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb5(&self) -> PERB5R {
let bits = {
const MASK: bool = true;
@@ -67777,8 +65215,7 @@ pub mod usb0 {
};
PERB5R { bits }
}
- #[doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb0(&self) -> PETB0R {
let bits = {
const MASK: bool = true;
@@ -67787,8 +65224,7 @@ pub mod usb0 {
};
PETB0R { bits }
}
- #[doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb1(&self) -> PETB1R {
let bits = {
const MASK: bool = true;
@@ -67797,8 +65233,7 @@ pub mod usb0 {
};
PETB1R { bits }
}
- #[doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb2(&self) -> PETB2R {
let bits = {
const MASK: bool = true;
@@ -67807,8 +65242,7 @@ pub mod usb0 {
};
PETB2R { bits }
}
- #[doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb3(&self) -> PETB3R {
let bits = {
const MASK: bool = true;
@@ -67817,8 +65251,7 @@ pub mod usb0 {
};
PETB3R { bits }
}
- #[doc = "Bit 20 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb4(&self) -> PETB4R {
let bits = {
const MASK: bool = true;
@@ -67827,8 +65260,7 @@ pub mod usb0 {
};
PETB4R { bits }
}
- #[doc = "Bit 21 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb5(&self) -> PETB5R {
let bits = {
const MASK: bool = true;
@@ -67850,63 +65282,51 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb0(&mut self) -> _PERB0W {
_PERB0W { w: self }
}
- #[doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb1(&mut self) -> _PERB1W {
_PERB1W { w: self }
}
- #[doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb2(&mut self) -> _PERB2W {
_PERB2W { w: self }
}
- #[doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb3(&mut self) -> _PERB3W {
_PERB3W { w: self }
}
- #[doc = "Bit 4 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb4(&mut self) -> _PERB4W {
_PERB4W { w: self }
}
- #[doc = "Bit 5 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn perb5(&mut self) -> _PERB5W {
_PERB5W { w: self }
}
- #[doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb0(&mut self) -> _PETB0W {
_PETB0W { w: self }
}
- #[doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb1(&mut self) -> _PETB1W {
_PETB1W { w: self }
}
- #[doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb2(&mut self) -> _PETB2W {
_PETB2W { w: self }
}
- #[doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb3(&mut self) -> _PETB3W {
_PETB3W { w: self }
}
- #[doc = "Bit 20 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb4(&mut self) -> _PETB4W {
_PETB4W { w: self }
}
- #[doc = "Bit 21 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn petb5(&mut self) -> _PETB5W {
_PETB5W { w: self }
}
@@ -68496,8 +65916,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb0(&self) -> FERB0R {
let bits = {
const MASK: bool = true;
@@ -68506,8 +65925,7 @@ pub mod usb0 {
};
FERB0R { bits }
}
- #[doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb1(&self) -> FERB1R {
let bits = {
const MASK: bool = true;
@@ -68516,8 +65934,7 @@ pub mod usb0 {
};
FERB1R { bits }
}
- #[doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb2(&self) -> FERB2R {
let bits = {
const MASK: bool = true;
@@ -68526,8 +65943,7 @@ pub mod usb0 {
};
FERB2R { bits }
}
- #[doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb3(&self) -> FERB3R {
let bits = {
const MASK: bool = true;
@@ -68536,8 +65952,7 @@ pub mod usb0 {
};
FERB3R { bits }
}
- #[doc = "Bit 4 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb4(&self) -> FERB4R {
let bits = {
const MASK: bool = true;
@@ -68546,8 +65961,7 @@ pub mod usb0 {
};
FERB4R { bits }
}
- #[doc = "Bit 5 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb5(&self) -> FERB5R {
let bits = {
const MASK: bool = true;
@@ -68556,8 +65970,7 @@ pub mod usb0 {
};
FERB5R { bits }
}
- #[doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb0(&self) -> FETB0R {
let bits = {
const MASK: bool = true;
@@ -68566,8 +65979,7 @@ pub mod usb0 {
};
FETB0R { bits }
}
- #[doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb1(&self) -> FETB1R {
let bits = {
const MASK: bool = true;
@@ -68576,8 +65988,7 @@ pub mod usb0 {
};
FETB1R { bits }
}
- #[doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb2(&self) -> FETB2R {
let bits = {
const MASK: bool = true;
@@ -68586,8 +65997,7 @@ pub mod usb0 {
};
FETB2R { bits }
}
- #[doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb3(&self) -> FETB3R {
let bits = {
const MASK: bool = true;
@@ -68596,8 +66006,7 @@ pub mod usb0 {
};
FETB3R { bits }
}
- #[doc = "Bit 20 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb4(&self) -> FETB4R {
let bits = {
const MASK: bool = true;
@@ -68606,8 +66015,7 @@ pub mod usb0 {
};
FETB4R { bits }
}
- #[doc = "Bit 21 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb5(&self) -> FETB5R {
let bits = {
const MASK: bool = true;
@@ -68629,63 +66037,51 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb0(&mut self) -> _FERB0W {
_FERB0W { w: self }
}
- #[doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb1(&mut self) -> _FERB1W {
_FERB1W { w: self }
}
- #[doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb2(&mut self) -> _FERB2W {
_FERB2W { w: self }
}
- #[doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb3(&mut self) -> _FERB3W {
_FERB3W { w: self }
}
- #[doc = "Bit 4 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb4(&mut self) -> _FERB4W {
_FERB4W { w: self }
}
- #[doc = "Bit 5 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn ferb5(&mut self) -> _FERB5W {
_FERB5W { w: self }
}
- #[doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb0(&mut self) -> _FETB0W {
_FETB0W { w: self }
}
- #[doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb1(&mut self) -> _FETB1W {
_FETB1W { w: self }
}
- #[doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb2(&mut self) -> _FETB2W {
_FETB2W { w: self }
}
- #[doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb3(&mut self) -> _FETB3W {
_FETB3W { w: self }
}
- #[doc = "Bit 20 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb4(&mut self) -> _FETB4W {
_FETB4W { w: self }
}
- #[doc = "Bit 21 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5" ] # [ inline ( always ) ]
pub fn fetb5(&mut self) -> _FETB5W {
_FETB5W { w: self }
}
@@ -68968,8 +66364,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erbr0(&self) -> ERBR0R {
let bits = {
const MASK: bool = true;
@@ -68978,8 +66373,7 @@ pub mod usb0 {
};
ERBR0R { bits }
}
- #[doc = "Bit 1 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erbr1(&self) -> ERBR1R {
let bits = {
const MASK: bool = true;
@@ -68988,8 +66382,7 @@ pub mod usb0 {
};
ERBR1R { bits }
}
- #[doc = "Bit 2 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erbr2(&self) -> ERBR2R {
let bits = {
const MASK: bool = true;
@@ -68998,8 +66391,7 @@ pub mod usb0 {
};
ERBR2R { bits }
}
- #[doc = "Bit 3 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erbr3(&self) -> ERBR3R {
let bits = {
const MASK: bool = true;
@@ -69008,8 +66400,7 @@ pub mod usb0 {
};
ERBR3R { bits }
}
- #[doc = "Bit 4 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erbr4(&self) -> ERBR4R {
let bits = {
const MASK: bool = true;
@@ -69018,8 +66409,7 @@ pub mod usb0 {
};
ERBR4R { bits }
}
- #[doc = "Bit 5 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erbr5(&self) -> ERBR5R {
let bits = {
const MASK: bool = true;
@@ -69028,8 +66418,7 @@ pub mod usb0 {
};
ERBR5R { bits }
}
- #[doc = "Bit 16 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etbr0(&self) -> ETBR0R {
let bits = {
const MASK: bool = true;
@@ -69038,8 +66427,7 @@ pub mod usb0 {
};
ETBR0R { bits }
}
- #[doc = "Bit 17 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etbr1(&self) -> ETBR1R {
let bits = {
const MASK: bool = true;
@@ -69048,8 +66436,7 @@ pub mod usb0 {
};
ETBR1R { bits }
}
- #[doc = "Bit 18 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etbr2(&self) -> ETBR2R {
let bits = {
const MASK: bool = true;
@@ -69058,8 +66445,7 @@ pub mod usb0 {
};
ETBR2R { bits }
}
- #[doc = "Bit 19 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etbr3(&self) -> ETBR3R {
let bits = {
const MASK: bool = true;
@@ -69068,8 +66454,7 @@ pub mod usb0 {
};
ETBR3R { bits }
}
- #[doc = "Bit 20 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etbr4(&self) -> ETBR4R {
let bits = {
const MASK: bool = true;
@@ -69078,8 +66463,7 @@ pub mod usb0 {
};
ETBR4R { bits }
}
- #[doc = "Bit 21 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etbr5(&self) -> ETBR5R {
let bits = {
const MASK: bool = true;
@@ -69674,8 +67058,7 @@ pub mod usb0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce0(&self) -> ERCE0R {
let bits = {
const MASK: bool = true;
@@ -69684,8 +67067,7 @@ pub mod usb0 {
};
ERCE0R { bits }
}
- #[doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce1(&self) -> ERCE1R {
let bits = {
const MASK: bool = true;
@@ -69694,8 +67076,7 @@ pub mod usb0 {
};
ERCE1R { bits }
}
- #[doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce2(&self) -> ERCE2R {
let bits = {
const MASK: bool = true;
@@ -69704,8 +67085,7 @@ pub mod usb0 {
};
ERCE2R { bits }
}
- #[doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce3(&self) -> ERCE3R {
let bits = {
const MASK: bool = true;
@@ -69714,8 +67094,7 @@ pub mod usb0 {
};
ERCE3R { bits }
}
- #[doc = "Bit 4 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce4(&self) -> ERCE4R {
let bits = {
const MASK: bool = true;
@@ -69724,8 +67103,7 @@ pub mod usb0 {
};
ERCE4R { bits }
}
- #[doc = "Bit 5 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce5(&self) -> ERCE5R {
let bits = {
const MASK: bool = true;
@@ -69734,8 +67112,7 @@ pub mod usb0 {
};
ERCE5R { bits }
}
- #[doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce0(&self) -> ETCE0R {
let bits = {
const MASK: bool = true;
@@ -69744,8 +67121,7 @@ pub mod usb0 {
};
ETCE0R { bits }
}
- #[doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce1(&self) -> ETCE1R {
let bits = {
const MASK: bool = true;
@@ -69754,8 +67130,7 @@ pub mod usb0 {
};
ETCE1R { bits }
}
- #[doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce2(&self) -> ETCE2R {
let bits = {
const MASK: bool = true;
@@ -69764,8 +67139,7 @@ pub mod usb0 {
};
ETCE2R { bits }
}
- #[doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce3(&self) -> ETCE3R {
let bits = {
const MASK: bool = true;
@@ -69774,8 +67148,7 @@ pub mod usb0 {
};
ETCE3R { bits }
}
- #[doc = "Bit 20 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce4(&self) -> ETCE4R {
let bits = {
const MASK: bool = true;
@@ -69784,8 +67157,7 @@ pub mod usb0 {
};
ETCE4R { bits }
}
- #[doc = "Bit 21 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce5(&self) -> ETCE5R {
let bits = {
const MASK: bool = true;
@@ -69807,63 +67179,51 @@ pub mod usb0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce0(&mut self) -> _ERCE0W {
_ERCE0W { w: self }
}
- #[doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce1(&mut self) -> _ERCE1W {
_ERCE1W { w: self }
}
- #[doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce2(&mut self) -> _ERCE2W {
_ERCE2W { w: self }
}
- #[doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce3(&mut self) -> _ERCE3W {
_ERCE3W { w: self }
}
- #[doc = "Bit 4 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce4(&mut self) -> _ERCE4W {
_ERCE4W { w: self }
}
- #[doc = "Bit 5 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn erce5(&mut self) -> _ERCE5W {
_ERCE5W { w: self }
}
- #[doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce0(&mut self) -> _ETCE0W {
_ETCE0W { w: self }
}
- #[doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce1(&mut self) -> _ETCE1W {
_ETCE1W { w: self }
}
- #[doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce2(&mut self) -> _ETCE2W {
_ETCE2W { w: self }
}
- #[doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce3(&mut self) -> _ETCE3W {
_ETCE3W { w: self }
}
- #[doc = "Bit 20 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce4(&mut self) -> _ETCE4W {
_ETCE4W { w: self }
}
- #[doc = "Bit 21 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" ] # [ inline ( always ) ]
pub fn etce5(&mut self) -> _ETCE5W {
_ETCE5W { w: self }
}
@@ -69921,11 +67281,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `RXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RXSR {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSR {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl RXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -69999,11 +67355,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `TXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TXSR {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSR {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl TXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -70076,11 +67428,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `RXS`"]
- pub enum RXSW {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSW {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl RXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -70109,8 +67457,7 @@ pub mod usb0 {
pub fn endpoint_ok_(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_OK_)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_STALLED_SOF)
}
@@ -70171,11 +67518,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `TXS`"]
- pub enum TXSW {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSW {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl TXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -70204,8 +67547,7 @@ pub mod usb0 {
pub fn endpoint_ok_(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_OK_)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_STALLED_SOF)
}
@@ -70290,8 +67632,7 @@ pub mod usb0 {
};
RXT1_0R { bits }
}
- #[doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn rxe(&self) -> RXER {
let bits = {
const MASK: bool = true;
@@ -70319,8 +67660,7 @@ pub mod usb0 {
};
TXT1_0R { bits }
}
- #[doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn txe(&self) -> TXER {
let bits = {
const MASK: bool = true;
@@ -70352,8 +67692,7 @@ pub mod usb0 {
pub fn rxt1_0(&mut self) -> _RXT1_0W {
_RXT1_0W { w: self }
}
- #[doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn rxe(&mut self) -> _RXEW {
_RXEW { w: self }
}
@@ -70367,8 +67706,7 @@ pub mod usb0 {
pub fn txt1_0(&mut self) -> _TXT1_0W {
_TXT1_0W { w: self }
}
- #[doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn txe(&mut self) -> _TXEW {
_TXEW { w: self }
}
@@ -70426,12 +67764,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `RXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RXSR {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request."]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSR {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." ] ENDPOINT_STALLED_SOF}
impl RXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -70628,12 +67961,7 @@ pub mod usb0 {
}
#[doc = "Possible values of the field `TXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TXSR {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request."]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSR {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." ] ENDPOINT_STALLED_SOF}
impl TXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -70837,12 +68165,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `RXS`"]
- pub enum RXSW {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request."]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSW {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." ] ENDPOINT_STALLED_SOF}
impl RXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -70866,13 +68189,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- #[inline(always)]
+ # [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] # [ inline ( always ) ]
pub fn endpoint_ok_this_bi(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_OK_THIS_BI)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request."]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_STALLED_SOF)
}
@@ -71083,12 +68404,7 @@ pub mod usb0 {
}
}
#[doc = "Values that can be written to the field `TXS`"]
- pub enum TXSW {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request."]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSW {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." ] ENDPOINT_STALLED_SOF}
impl TXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -71112,13 +68428,11 @@ pub mod usb0 {
self.bit(variant._bits())
}
}
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- #[inline(always)]
+ # [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] # [ inline ( always ) ]
pub fn endpoint_ok_this_bi(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_OK_THIS_BI)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request."]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_STALLED_SOF)
}
@@ -71361,8 +68675,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn rxi(&self) -> RXIR {
RXIR::_from({
const MASK: bool = true;
@@ -71370,8 +68683,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn rxr(&self) -> RXRR {
let bits = {
const MASK: bool = true;
@@ -71380,8 +68692,7 @@ pub mod usb0 {
};
RXRR { bits }
}
- #[doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured." ] # [ inline ( always ) ]
pub fn rxe(&self) -> RXER {
RXER::_from({
const MASK: bool = true;
@@ -71407,8 +68718,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn txi(&self) -> TXIR {
TXIR::_from({
const MASK: bool = true;
@@ -71416,8 +68726,7 @@ pub mod usb0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn txr(&self) -> TXRR {
let bits = {
const MASK: bool = true;
@@ -71426,8 +68735,7 @@ pub mod usb0 {
};
TXRR { bits }
}
- #[doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured"]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured" ] # [ inline ( always ) ]
pub fn txe(&self) -> TXER {
TXER::_from({
const MASK: bool = true;
@@ -71458,18 +68766,15 @@ pub mod usb0 {
pub fn rxt(&mut self) -> _RXTW {
_RXTW { w: self }
}
- #[doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn rxi(&mut self) -> _RXIW {
_RXIW { w: self }
}
- #[doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn rxr(&mut self) -> _RXRW {
_RXRW { w: self }
}
- #[doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured." ] # [ inline ( always ) ]
pub fn rxe(&mut self) -> _RXEW {
_RXEW { w: self }
}
@@ -71483,18 +68788,15 @@ pub mod usb0 {
pub fn txt1_0(&mut self) -> _TXT1_0W {
_TXT1_0W { w: self }
}
- #[doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn txi(&mut self) -> _TXIW {
_TXIW { w: self }
}
- #[doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn txr(&mut self) -> _TXRW {
_TXRW { w: self }
}
- #[doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured"]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured" ] # [ inline ( always ) ]
pub fn txe(&mut self) -> _TXEW {
_TXEW { w: self }
}
@@ -71518,7 +68820,46 @@ pub mod usb1 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock { _reserved0 : [ u8 ; 256usize ] , # [ doc = "0x100 - Capability register length" ] pub caplength : CAPLENGTH , # [ doc = "0x104 - Host controller structural parameters" ] pub hcsparams : HCSPARAMS , # [ doc = "0x108 - Host controller capability parameters" ] pub hccparams : HCCPARAMS , _reserved1 : [ u8 ; 20usize ] , # [ doc = "0x120 - Device interface version number" ] pub dciversion : DCIVERSION , _reserved2 : [ u8 ; 28usize ] , # [ doc = "0x140 - USB command (device mode)" ] pub usbcmd_d : USBCMD_D , # [ doc = "0x144 - USB status (device mode)" ] pub usbsts_d : USBSTS_D , # [ doc = "0x148 - USB interrupt enable (device mode)" ] pub usbintr_d : USBINTR_D , # [ doc = "0x14c - USB frame index (device mode)" ] pub frindex_d : FRINDEX_D , _reserved3 : [ u8 ; 4usize ] , # [ doc = "0x154 - USB device address" ] pub deviceaddr : DEVICEADDR , # [ doc = "0x158 - Address of endpoint list in memory (device mode)" ] pub endpointlistaddr : ENDPOINTLISTADDR , # [ doc = "0x15c - Asynchronous buffer status for embedded TT (host mode)" ] pub ttctrl : TTCTRL , # [ doc = "0x160 - Programmable burst size" ] pub burstsize : BURSTSIZE , # [ doc = "0x164 - Host transmit pre-buffer packet tuning (host mode)" ] pub txfilltuning : TXFILLTUNING , _reserved4 : [ u8 ; 8usize ] , # [ doc = "0x170 - ULPI viewport" ] pub ulpiviewport : ULPIVIEWPORT , # [ doc = "0x174 - Length of virtual frame" ] pub binterval : BINTERVAL , # [ doc = "0x178 - Endpoint NAK (device mode)" ] pub endptnak : ENDPTNAK , # [ doc = "0x17c - Endpoint NAK Enable (device mode)" ] pub endptnaken : ENDPTNAKEN , _reserved5 : [ u8 ; 4usize ] , # [ doc = "0x184 - Port 1 status/control (device mode)" ] pub portsc1_d : PORTSC1_D , _reserved6 : [ u8 ; 32usize ] , # [ doc = "0x1a8 - USB mode (device mode)" ] pub usbmode_d : USBMODE_D , # [ doc = "0x1ac - Endpoint setup status" ] pub endptsetupstat : ENDPTSETUPSTAT , # [ doc = "0x1b0 - Endpoint initialization" ] pub endptprime : ENDPTPRIME , # [ doc = "0x1b4 - Endpoint de-initialization" ] pub endptflush : ENDPTFLUSH , # [ doc = "0x1b8 - Endpoint status" ] pub endptstat : ENDPTSTAT , # [ doc = "0x1bc - Endpoint complete" ] pub endptcomplete : ENDPTCOMPLETE , # [ doc = "0x1c0 - Endpoint control 0" ] pub endptctrl0 : ENDPTCTRL0 , # [ doc = "0x1c4 - Endpoint control" ] pub endptctrl1 : ENDPTCTRL , # [ doc = "0x1c8 - Endpoint control" ] pub endptctrl2 : ENDPTCTRL , # [ doc = "0x1cc - Endpoint control" ] pub endptctrl3 : ENDPTCTRL , }
+ pub struct RegisterBlock {
+ _reserved0: [u8; 256usize],
+ #[doc = "0x100 - Capability register length"] pub caplength: CAPLENGTH,
+ #[doc = "0x104 - Host controller structural parameters"] pub hcsparams: HCSPARAMS,
+ #[doc = "0x108 - Host controller capability parameters"] pub hccparams: HCCPARAMS,
+ _reserved1: [u8; 20usize],
+ #[doc = "0x120 - Device interface version number"] pub dciversion: DCIVERSION,
+ _reserved2: [u8; 28usize],
+ #[doc = "0x140 - USB command (device mode)"] pub usbcmd_d: USBCMD_D,
+ #[doc = "0x144 - USB status (device mode)"] pub usbsts_d: USBSTS_D,
+ #[doc = "0x148 - USB interrupt enable (device mode)"] pub usbintr_d: USBINTR_D,
+ #[doc = "0x14c - USB frame index (device mode)"] pub frindex_d: FRINDEX_D,
+ _reserved3: [u8; 4usize],
+ #[doc = "0x154 - USB device address"] pub deviceaddr: DEVICEADDR,
+ #[doc = "0x158 - Address of endpoint list in memory (device mode)"]
+ pub endpointlistaddr: ENDPOINTLISTADDR,
+ #[doc = "0x15c - Asynchronous buffer status for embedded TT (host mode)"]
+ pub ttctrl: TTCTRL,
+ #[doc = "0x160 - Programmable burst size"] pub burstsize: BURSTSIZE,
+ #[doc = "0x164 - Host transmit pre-buffer packet tuning (host mode)"]
+ pub txfilltuning: TXFILLTUNING,
+ _reserved4: [u8; 8usize],
+ #[doc = "0x170 - ULPI viewport"] pub ulpiviewport: ULPIVIEWPORT,
+ #[doc = "0x174 - Length of virtual frame"] pub binterval: BINTERVAL,
+ #[doc = "0x178 - Endpoint NAK (device mode)"] pub endptnak: ENDPTNAK,
+ #[doc = "0x17c - Endpoint NAK Enable (device mode)"] pub endptnaken: ENDPTNAKEN,
+ _reserved5: [u8; 4usize],
+ #[doc = "0x184 - Port 1 status/control (device mode)"] pub portsc1_d: PORTSC1_D,
+ _reserved6: [u8; 32usize],
+ #[doc = "0x1a8 - USB mode (device mode)"] pub usbmode_d: USBMODE_D,
+ #[doc = "0x1ac - Endpoint setup status"] pub endptsetupstat: ENDPTSETUPSTAT,
+ #[doc = "0x1b0 - Endpoint initialization"] pub endptprime: ENDPTPRIME,
+ #[doc = "0x1b4 - Endpoint de-initialization"] pub endptflush: ENDPTFLUSH,
+ #[doc = "0x1b8 - Endpoint status"] pub endptstat: ENDPTSTAT,
+ #[doc = "0x1bc - Endpoint complete"] pub endptcomplete: ENDPTCOMPLETE,
+ #[doc = "0x1c0 - Endpoint control 0"] pub endptctrl0: ENDPTCTRL0,
+ #[doc = "0x1c4 - Endpoint control"] pub endptctrl1: ENDPTCTRL,
+ #[doc = "0x1c8 - Endpoint control"] pub endptctrl2: ENDPTCTRL,
+ #[doc = "0x1cc - Endpoint control"] pub endptctrl3: ENDPTCTRL,
+ }
#[doc = "Capability register length"]
pub struct CAPLENGTH {
register: VolatileCell<u32>,
@@ -71566,8 +68907,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Indicates offset to add to the register base address at the beginning of the Operational Register"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Indicates offset to add to the register base address at the beginning of the Operational Register" ] # [ inline ( always ) ]
pub fn caplength(&self) -> CAPLENGTHR {
let bits = {
const MASK: u8 = 255;
@@ -71576,8 +68916,7 @@ pub mod usb1 {
};
CAPLENGTHR { bits }
}
- #[doc = "Bits 8:23 - BCD encoding of the EHCI revision number supported by this host controller."]
- #[inline(always)]
+ # [ doc = "Bits 8:23 - BCD encoding of the EHCI revision number supported by this host controller." ] # [ inline ( always ) ]
pub fn hciversion(&self) -> HCIVERSIONR {
let bits = {
const MASK: u16 = 65535;
@@ -71710,8 +69049,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." ] # [ inline ( always ) ]
pub fn n_ports(&self) -> N_PORTSR {
let bits = {
const MASK: u8 = 15;
@@ -71720,8 +69058,7 @@ pub mod usb1 {
};
N_PORTSR { bits }
}
- #[doc = "Bit 4 - Port Power Control. This field indicates whether the host controller implementation includes port power control."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Port Power Control. This field indicates whether the host controller implementation includes port power control." ] # [ inline ( always ) ]
pub fn ppc(&self) -> PPCR {
let bits = {
const MASK: bool = true;
@@ -71730,8 +69067,7 @@ pub mod usb1 {
};
PPCR { bits }
}
- #[doc = "Bits 8:11 - Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller."]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." ] # [ inline ( always ) ]
pub fn n_pcc(&self) -> N_PCCR {
let bits = {
const MASK: u8 = 15;
@@ -71740,8 +69076,7 @@ pub mod usb1 {
};
N_PCCR { bits }
}
- #[doc = "Bits 12:15 - Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller."]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." ] # [ inline ( always ) ]
pub fn n_cc(&self) -> N_CCR {
let bits = {
const MASK: u8 = 15;
@@ -71750,8 +69085,7 @@ pub mod usb1 {
};
N_CCR { bits }
}
- #[doc = "Bit 16 - Port indicators. This bit indicates whether the ports support port indicator control."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Port indicators. This bit indicates whether the ports support port indicator control." ] # [ inline ( always ) ]
pub fn pi(&self) -> PIR {
let bits = {
const MASK: bool = true;
@@ -71760,8 +69094,7 @@ pub mod usb1 {
};
PIR { bits }
}
- #[doc = "Bits 20:23 - Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller."]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." ] # [ inline ( always ) ]
pub fn n_ptt(&self) -> N_PTTR {
let bits = {
const MASK: u8 = 15;
@@ -71770,8 +69103,7 @@ pub mod usb1 {
};
N_PTTR { bits }
}
- #[doc = "Bits 24:27 - Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller."]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." ] # [ inline ( always ) ]
pub fn n_tt(&self) -> N_TTR {
let bits = {
const MASK: u8 = 15;
@@ -71892,8 +69224,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported."]
- #[inline(always)]
+ # [ doc = "Bit 0 - 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." ] # [ inline ( always ) ]
pub fn adc(&self) -> ADCR {
let bits = {
const MASK: bool = true;
@@ -71902,8 +69233,7 @@ pub mod usb1 {
};
ADCR { bits }
}
- #[doc = "Bit 1 - Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." ] # [ inline ( always ) ]
pub fn pfl(&self) -> PFLR {
let bits = {
const MASK: bool = true;
@@ -71912,8 +69242,7 @@ pub mod usb1 {
};
PFLR { bits }
}
- #[doc = "Bit 2 - Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." ] # [ inline ( always ) ]
pub fn asp(&self) -> ASPR {
let bits = {
const MASK: bool = true;
@@ -71922,8 +69251,7 @@ pub mod usb1 {
};
ASPR { bits }
}
- #[doc = "Bits 4:7 - Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." ] # [ inline ( always ) ]
pub fn ist(&self) -> ISTR {
let bits = {
const MASK: u8 = 15;
@@ -71932,8 +69260,7 @@ pub mod usb1 {
};
ISTR { bits }
}
- #[doc = "Bits 8:15 - EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." ] # [ inline ( always ) ]
pub fn eecp(&self) -> EECPR {
let bits = {
const MASK: u8 = 255;
@@ -71980,8 +69307,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." ] # [ inline ( always ) ]
pub fn dciversion(&self) -> DCIVERSIONR {
let bits = {
const MASK: u16 = 65535;
@@ -72044,11 +69370,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `RS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSR {
- #[doc = "Writing a 0 to this bit will cause a detach event."] DETACH,
- #[doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized."]
- ATACH,
- }
+ pub enum RSR {# [ doc = "Writing a 0 to this bit will cause a detach event." ] DETACH , # [ doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." ] ATACH}
impl RSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -72090,12 +69412,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `RST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSTR {
- #[doc = "Set to 0 by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
- RESET,
- }
+ pub enum RSTR {# [ doc = "Set to 0 by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." ] RESET}
impl RSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -72210,11 +69527,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `RS`"]
- pub enum RSW {
- #[doc = "Writing a 0 to this bit will cause a detach event."] DETACH,
- #[doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized."]
- ATACH,
- }
+ pub enum RSW {# [ doc = "Writing a 0 to this bit will cause a detach event." ] DETACH , # [ doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." ] ATACH}
impl RSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -72243,8 +69556,7 @@ pub mod usb1 {
pub fn detach(self) -> &'a mut W {
self.variant(RSW::DETACH)
}
- #[doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized."]
- #[inline(always)]
+ # [ doc = "Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." ] # [ inline ( always ) ]
pub fn atach(self) -> &'a mut W {
self.variant(RSW::ATACH)
}
@@ -72267,12 +69579,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `RST`"]
- pub enum RSTW {
- #[doc = "Set to 0 by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
- RESET,
- }
+ pub enum RSTW {# [ doc = "Set to 0 by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." ] RESET}
impl RSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -72301,8 +69608,7 @@ pub mod usb1 {
pub fn resetcomplete(self) -> &'a mut W {
self.variant(RSTW::RESETCOMPLETE)
}
- #[doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
- #[inline(always)]
+ # [ doc = "When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." ] # [ inline ( always ) ]
pub fn reset(self) -> &'a mut W {
self.variant(RSTW::RESET)
}
@@ -72423,8 +69729,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&self) -> RSTR {
RSTR::_from({
const MASK: bool = true;
@@ -72432,8 +69737,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." ] # [ inline ( always ) ]
pub fn sutw(&self) -> SUTWR {
let bits = {
const MASK: bool = true;
@@ -72442,8 +69746,7 @@ pub mod usb1 {
};
SUTWR { bits }
}
- #[doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." ] # [ inline ( always ) ]
pub fn atdtw(&self) -> ATDTWR {
let bits = {
const MASK: bool = true;
@@ -72462,8 +69765,7 @@ pub mod usb1 {
};
FS2R { bits }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&self) -> ITCR {
let bits = {
const MASK: u8 = 255;
@@ -72490,18 +69792,15 @@ pub mod usb1 {
pub fn rs(&mut self) -> _RSW {
_RSW { w: self }
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&mut self) -> _RSTW {
_RSTW { w: self }
}
- #[doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." ] # [ inline ( always ) ]
pub fn sutw(&mut self) -> _SUTWW {
_SUTWW { w: self }
}
- #[doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." ] # [ inline ( always ) ]
pub fn atdtw(&mut self) -> _ATDTWW {
_ATDTWW { w: self }
}
@@ -72510,8 +69809,7 @@ pub mod usb1 {
pub fn fs2(&mut self) -> _FS2W {
_FS2W { w: self }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&mut self) -> _ITCW {
_ITCW { w: self }
}
@@ -72569,12 +69867,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `RS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSR {
- #[doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)."]
- HALT,
- #[doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one."]
- PROCEED,
- }
+ pub enum RSR {# [ doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." ] HALT , # [ doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." ] PROCEED}
impl RSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -72616,12 +69909,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `RST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RSTR {
- #[doc = "This bit is set to zero by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
- RESET,
- }
+ pub enum RSTR {# [ doc = "This bit is set to zero by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." ] RESET}
impl RSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -72706,8 +69994,7 @@ pub mod usb1 {
#[doc = "Possible values of the field `PSE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PSER {
- #[doc = "Do not process the periodic schedule."]
- DO_NOT_PROCESS_THE_P,
+ #[doc = "Do not process the periodic schedule."] DO_NOT_PROCESS_THE_P,
#[doc = "Use the PERIODICLISTBASE register to access the periodic schedule."]
USE_THE_PERIODICLIST,
}
@@ -72753,8 +70040,7 @@ pub mod usb1 {
#[doc = "Possible values of the field `ASE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ASER {
- #[doc = "Do not process the asynchronous schedule."]
- DO_NOT_PROCESS_THE_A,
+ #[doc = "Do not process the asynchronous schedule."] DO_NOT_PROCESS_THE_A,
#[doc = "Use the ASYNCLISTADDR to access the asynchronous schedule."]
USE_THE_ASYNCLISTADD,
}
@@ -72799,12 +70085,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `IAA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum IAAR {
- #[doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one."]
- ST,
- #[doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results."]
- DOORBELL,
- }
+ pub enum IAAR {# [ doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." ] ST , # [ doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." ] DOORBELL}
impl IAAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -72933,12 +70214,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `RS`"]
- pub enum RSW {
- #[doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)."]
- HALT,
- #[doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one."]
- PROCEED,
- }
+ pub enum RSW {# [ doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." ] HALT , # [ doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." ] PROCEED}
impl RSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -72962,13 +70238,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)."]
- #[inline(always)]
+ # [ doc = "When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." ] # [ inline ( always ) ]
pub fn halt(self) -> &'a mut W {
self.variant(RSW::HALT)
}
- #[doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one."]
- #[inline(always)]
+ # [ doc = "When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." ] # [ inline ( always ) ]
pub fn proceed(self) -> &'a mut W {
self.variant(RSW::PROCEED)
}
@@ -72991,12 +70265,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `RST`"]
- pub enum RSTW {
- #[doc = "This bit is set to zero by hardware when the reset process is complete."]
- RESETCOMPLETE,
- #[doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
- RESET,
- }
+ pub enum RSTW {# [ doc = "This bit is set to zero by hardware when the reset process is complete." ] RESETCOMPLETE , # [ doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." ] RESET}
impl RSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -73025,8 +70294,7 @@ pub mod usb1 {
pub fn resetcomplete(self) -> &'a mut W {
self.variant(RSTW::RESETCOMPLETE)
}
- #[doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior."]
- #[inline(always)]
+ # [ doc = "When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." ] # [ inline ( always ) ]
pub fn reset(self) -> &'a mut W {
self.variant(RSTW::RESET)
}
@@ -73096,8 +70364,7 @@ pub mod usb1 {
}
#[doc = "Values that can be written to the field `PSE`"]
pub enum PSEW {
- #[doc = "Do not process the periodic schedule."]
- DO_NOT_PROCESS_THE_P,
+ #[doc = "Do not process the periodic schedule."] DO_NOT_PROCESS_THE_P,
#[doc = "Use the PERIODICLISTBASE register to access the periodic schedule."]
USE_THE_PERIODICLIST,
}
@@ -73154,8 +70421,7 @@ pub mod usb1 {
}
#[doc = "Values that can be written to the field `ASE`"]
pub enum ASEW {
- #[doc = "Do not process the asynchronous schedule."]
- DO_NOT_PROCESS_THE_A,
+ #[doc = "Do not process the asynchronous schedule."] DO_NOT_PROCESS_THE_A,
#[doc = "Use the ASYNCLISTADDR to access the asynchronous schedule."]
USE_THE_ASYNCLISTADD,
}
@@ -73211,12 +70477,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `IAA`"]
- pub enum IAAW {
- #[doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one."]
- ST,
- #[doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results."]
- DOORBELL,
- }
+ pub enum IAAW {# [ doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." ] ST , # [ doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." ] DOORBELL}
impl IAAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -73240,13 +70501,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one."]
- #[inline(always)]
+ # [ doc = "The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." ] # [ inline ( always ) ]
pub fn st(self) -> &'a mut W {
self.variant(IAAW::ST)
}
- #[doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results."]
- #[inline(always)]
+ # [ doc = "Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." ] # [ inline ( always ) ]
pub fn doorbell(self) -> &'a mut W {
self.variant(IAAW::DOORBELL)
}
@@ -73392,8 +70651,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&self) -> RSTR {
RSTR::_from({
const MASK: bool = true;
@@ -73401,8 +70659,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." ] # [ inline ( always ) ]
pub fn fs0(&self) -> FS0R {
let bits = {
const MASK: bool = true;
@@ -73421,8 +70678,7 @@ pub mod usb1 {
};
FS1R { bits }
}
- #[doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule."]
- #[inline(always)]
+ # [ doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule." ] # [ inline ( always ) ]
pub fn pse(&self) -> PSER {
PSER::_from({
const MASK: bool = true;
@@ -73430,8 +70686,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule." ] # [ inline ( always ) ]
pub fn ase(&self) -> ASER {
ASER::_from({
const MASK: bool = true;
@@ -73439,8 +70694,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule." ] # [ inline ( always ) ]
pub fn iaa(&self) -> IAAR {
IAAR::_from({
const MASK: bool = true;
@@ -73448,8 +70702,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 8:9 - Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." ] # [ inline ( always ) ]
pub fn asp1_0(&self) -> ASP1_0R {
let bits = {
const MASK: u8 = 3;
@@ -73477,8 +70730,7 @@ pub mod usb1 {
};
FS2R { bits }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&self) -> ITCR {
let bits = {
const MASK: u8 = 255;
@@ -73505,13 +70757,11 @@ pub mod usb1 {
pub fn rs(&mut self) -> _RSW {
_RSW { w: self }
}
- #[doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register." ] # [ inline ( always ) ]
pub fn rst(&mut self) -> _RSTW {
_RSTW { w: self }
}
- #[doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." ] # [ inline ( always ) ]
pub fn fs0(&mut self) -> _FS0W {
_FS0W { w: self }
}
@@ -73520,23 +70770,19 @@ pub mod usb1 {
pub fn fs1(&mut self) -> _FS1W {
_FS1W { w: self }
}
- #[doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule."]
- #[inline(always)]
+ # [ doc = "Bit 4 - This bit controls whether the host controller skips processing the periodic schedule." ] # [ inline ( always ) ]
pub fn pse(&mut self) -> _PSEW {
_PSEW { w: self }
}
- #[doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 5 - This bit controls whether the host controller skips processing the asynchronous schedule." ] # [ inline ( always ) ]
pub fn ase(&mut self) -> _ASEW {
_ASEW { w: self }
}
- #[doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule."]
- #[inline(always)]
+ # [ doc = "Bit 6 - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule." ] # [ inline ( always ) ]
pub fn iaa(&mut self) -> _IAAW {
_IAAW { w: self }
}
- #[doc = "Bits 8:9 - Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." ] # [ inline ( always ) ]
pub fn asp1_0(&mut self) -> _ASP1_0W {
_ASP1_0W { w: self }
}
@@ -73550,8 +70796,7 @@ pub mod usb1 {
pub fn fs2(&mut self) -> _FS2W {
_FS2W { w: self }
}
- #[doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." ] # [ inline ( always ) ]
pub fn itc(&mut self) -> _ITCW {
_ITCW { w: self }
}
@@ -73609,11 +70854,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `UI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -73655,11 +70896,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `UEI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UEIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)."]
- CLEAR,
- }
+ pub enum UEIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." ] CLEAR}
impl UEIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -73701,11 +70938,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `PCI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PCIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively."]
- CLEAR,
- }
+ pub enum PCIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." ] CLEAR}
impl PCIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -73747,11 +70980,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `URI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum URIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum URIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." ] CLEAR}
impl URIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -73793,11 +71022,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `SRI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SRIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp."]
- CLEAR,
- }
+ pub enum SRIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." ] CLEAR}
impl SRIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -73839,12 +71064,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `SLI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SLIR {
- #[doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it."]
- ST,
- #[doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum SLIR {# [ doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." ] ST , # [ doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one." ] CLEAR}
impl SLIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -73886,12 +71106,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `NAKI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum NAKIR {
- #[doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared."]
- ENDPCLEAR,
- #[doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set."]
- SET,
- }
+ pub enum NAKIR {# [ doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." ] ENDPCLEAR , # [ doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." ] SET}
impl NAKIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -73932,11 +71147,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `UI`"]
- pub enum UIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -73965,8 +71176,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(UIW::ST)
}
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UIW::CLEAR)
}
@@ -73989,11 +71199,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `UEI`"]
- pub enum UEIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)."]
- CLEAR,
- }
+ pub enum UEIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." ] CLEAR}
impl UEIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -74022,8 +71228,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(UEIW::ST)
}
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)."]
- #[inline(always)]
+ # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UEIW::CLEAR)
}
@@ -74046,11 +71251,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `PCI`"]
- pub enum PCIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively."]
- CLEAR,
- }
+ pub enum PCIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." ] CLEAR}
impl PCIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -74079,8 +71280,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(PCIW::ST)
}
- #[doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively."]
- #[inline(always)]
+ # [ doc = "The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(PCIW::CLEAR)
}
@@ -74103,11 +71303,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `URI`"]
- pub enum URIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum URIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." ] CLEAR}
impl URIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -74136,8 +71332,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(URIW::ST)
}
- #[doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one."]
- #[inline(always)]
+ # [ doc = "When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(URIW::CLEAR)
}
@@ -74160,11 +71355,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `SRI`"]
- pub enum SRIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp."]
- CLEAR,
- }
+ pub enum SRIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." ] CLEAR}
impl SRIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -74193,8 +71384,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(SRIW::ST)
}
- #[doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp."]
- #[inline(always)]
+ # [ doc = "When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(SRIW::CLEAR)
}
@@ -74217,12 +71407,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `SLI`"]
- pub enum SLIW {
- #[doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it."]
- ST,
- #[doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one."]
- CLEAR,
- }
+ pub enum SLIW {# [ doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." ] ST , # [ doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one." ] CLEAR}
impl SLIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -74246,13 +71431,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it."]
- #[inline(always)]
+ # [ doc = "The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." ] # [ inline ( always ) ]
pub fn st(self) -> &'a mut W {
self.variant(SLIW::ST)
}
- #[doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one."]
- #[inline(always)]
+ # [ doc = "When a device controller enters a suspend state from an active state, this bit will be set to a one." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(SLIW::CLEAR)
}
@@ -74275,12 +71458,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `NAKI`"]
- pub enum NAKIW {
- #[doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared."]
- ENDPCLEAR,
- #[doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set."]
- SET,
- }
+ pub enum NAKIW {# [ doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." ] ENDPCLEAR , # [ doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." ] SET}
impl NAKIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -74304,13 +71482,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared."]
- #[inline(always)]
+ # [ doc = "This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." ] # [ inline ( always ) ]
pub fn endpclear(self) -> &'a mut W {
self.variant(NAKIW::ENDPCLEAR)
}
- #[doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set."]
- #[inline(always)]
+ # [ doc = "It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." ] # [ inline ( always ) ]
pub fn set(self) -> &'a mut W {
self.variant(NAKIW::SET)
}
@@ -74503,11 +71679,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `UI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -74549,11 +71721,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `UEI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UEIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
- CLEAR,
- }
+ pub enum UEIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." ] CLEAR}
impl UEIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -74595,11 +71763,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `PCI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PCIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port."]
- CLEAR,
- }
+ pub enum PCIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." ] CLEAR}
impl PCIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -74641,11 +71805,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `FRI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum FRIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)."]
- CLEAR,
- }
+ pub enum FRIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." ] CLEAR}
impl FRIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -74687,11 +71847,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `AAI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum AAIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
- CLEAR,
- }
+ pub enum AAIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." ] CLEAR}
impl AAIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -74733,11 +71889,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `SRI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SRIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base."]
- CLEAR,
- }
+ pub enum SRIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." ] CLEAR}
impl SRIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -74800,12 +71952,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `HCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum HCHR {
- #[doc = "The RS bit in USBCMD is set to zero. Set by the host controller."]
- RS,
- #[doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)."]
- STOP,
- }
+ pub enum HCHR {# [ doc = "The RS bit in USBCMD is set to zero. Set by the host controller." ] RS , # [ doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." ] STOP}
impl HCHR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -74848,8 +71995,7 @@ pub mod usb1 {
#[doc = "Possible values of the field `RCL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RCLR {
- #[doc = "No empty asynchronous schedule detected."]
- NO_EMPTY_ASYNCHRONOU,
+ #[doc = "No empty asynchronous schedule detected."] NO_EMPTY_ASYNCHRONOU,
#[doc = "An empty asynchronous schedule is detected. Set by the host controller."]
EMPTY_ASYNCHRONOU,
}
@@ -74984,11 +72130,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `UAI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UAIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UAIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UAIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -75030,11 +72172,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `UPI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum UPIR {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UPIR {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UPIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -75075,11 +72213,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `UI`"]
- pub enum UIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75108,8 +72242,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(UIW::ST)
}
- #[doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UIW::CLEAR)
}
@@ -75132,11 +72265,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `UEI`"]
- pub enum UEIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
- CLEAR,
- }
+ pub enum UEIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." ] CLEAR}
impl UEIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75165,8 +72294,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(UEIW::ST)
}
- #[doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
- #[inline(always)]
+ # [ doc = "When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UEIW::CLEAR)
}
@@ -75189,11 +72317,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `PCI`"]
- pub enum PCIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port."]
- CLEAR,
- }
+ pub enum PCIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." ] CLEAR}
impl PCIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75222,8 +72346,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(PCIW::ST)
}
- #[doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port."]
- #[inline(always)]
+ # [ doc = "The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(PCIW::CLEAR)
}
@@ -75246,11 +72369,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `FRI`"]
- pub enum FRIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)."]
- CLEAR,
- }
+ pub enum FRIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." ] CLEAR}
impl FRIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75279,8 +72398,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(FRIW::ST)
}
- #[doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)."]
- #[inline(always)]
+ # [ doc = "The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(FRIW::CLEAR)
}
@@ -75303,11 +72421,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `AAI`"]
- pub enum AAIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
- CLEAR,
- }
+ pub enum AAIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." ] CLEAR}
impl AAIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75336,8 +72450,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(AAIW::ST)
}
- #[doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source."]
- #[inline(always)]
+ # [ doc = "System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(AAIW::CLEAR)
}
@@ -75360,11 +72473,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `SRI`"]
- pub enum SRIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base."]
- CLEAR,
- }
+ pub enum SRIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." ] CLEAR}
impl SRIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75393,8 +72502,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(SRIW::ST)
}
- #[doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base."]
- #[inline(always)]
+ # [ doc = "In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(SRIW::CLEAR)
}
@@ -75440,12 +72548,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `HCH`"]
- pub enum HCHW {
- #[doc = "The RS bit in USBCMD is set to zero. Set by the host controller."]
- RS,
- #[doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)."]
- STOP,
- }
+ pub enum HCHW {# [ doc = "The RS bit in USBCMD is set to zero. Set by the host controller." ] RS , # [ doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." ] STOP}
impl HCHW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75474,8 +72577,7 @@ pub mod usb1 {
pub fn rs(self) -> &'a mut W {
self.variant(HCHW::RS)
}
- #[doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)."]
- #[inline(always)]
+ # [ doc = "The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." ] # [ inline ( always ) ]
pub fn stop(self) -> &'a mut W {
self.variant(HCHW::STOP)
}
@@ -75499,8 +72601,7 @@ pub mod usb1 {
}
#[doc = "Values that can be written to the field `RCL`"]
pub enum RCLW {
- #[doc = "No empty asynchronous schedule detected."]
- NO_EMPTY_ASYNCHRONOU,
+ #[doc = "No empty asynchronous schedule detected."] NO_EMPTY_ASYNCHRONOU,
#[doc = "An empty asynchronous schedule is detected. Set by the host controller."]
EMPTY_ASYNCHRONOU,
}
@@ -75668,11 +72769,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `UAI`"]
- pub enum UAIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UAIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UAIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75701,8 +72798,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(UAIW::ST)
}
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UAIW::CLEAR)
}
@@ -75725,11 +72821,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `UPI`"]
- pub enum UPIW {
- #[doc = "This bit is cleared by software writing a one to it."] ST,
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- CLEAR,
- }
+ pub enum UPIW {# [ doc = "This bit is cleared by software writing a one to it." ] ST , # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] CLEAR}
impl UPIW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -75758,8 +72850,7 @@ pub mod usb1 {
pub fn st(self) -> &'a mut W {
self.variant(UPIW::ST)
}
- #[doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
- #[inline(always)]
+ # [ doc = "This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(UPIW::CLEAR)
}
@@ -75869,8 +72960,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn ps(&self) -> PSR {
PSR::_from({
const MASK: bool = true;
@@ -75878,8 +72968,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn as_(&self) -> ASR {
ASR::_from({
const MASK: bool = true;
@@ -75963,13 +73052,11 @@ pub mod usb1 {
pub fn rcl(&mut self) -> _RCLW {
_RCLW { w: self }
}
- #[doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn ps(&mut self) -> _PSW {
_PSW { w: self }
}
- #[doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0)." ] # [ inline ( always ) ]
pub fn as_(&mut self) -> _ASW {
_ASW { w: self }
}
@@ -76437,8 +73524,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&self) -> UER {
let bits = {
const MASK: bool = true;
@@ -76447,8 +73533,7 @@ pub mod usb1 {
};
UER { bits }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&self) -> UEER {
let bits = {
const MASK: bool = true;
@@ -76457,8 +73542,7 @@ pub mod usb1 {
};
UEER { bits }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&self) -> PCER {
let bits = {
const MASK: bool = true;
@@ -76467,8 +73551,7 @@ pub mod usb1 {
};
PCER { bits }
}
- #[doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." ] # [ inline ( always ) ]
pub fn ure(&self) -> URER {
let bits = {
const MASK: bool = true;
@@ -76477,8 +73560,7 @@ pub mod usb1 {
};
URER { bits }
}
- #[doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." ] # [ inline ( always ) ]
pub fn sre(&self) -> SRER {
let bits = {
const MASK: bool = true;
@@ -76487,8 +73569,7 @@ pub mod usb1 {
};
SRER { bits }
}
- #[doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." ] # [ inline ( always ) ]
pub fn sle(&self) -> SLER {
let bits = {
const MASK: bool = true;
@@ -76497,8 +73578,7 @@ pub mod usb1 {
};
SLER { bits }
}
- #[doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated."]
- #[inline(always)]
+ # [ doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." ] # [ inline ( always ) ]
pub fn nake(&self) -> NAKER {
let bits = {
const MASK: bool = true;
@@ -76540,38 +73620,31 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&mut self) -> _UEW {
_UEW { w: self }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&mut self) -> _UEEW {
_UEEW { w: self }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&mut self) -> _PCEW {
_PCEW { w: self }
}
- #[doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." ] # [ inline ( always ) ]
pub fn ure(&mut self) -> _UREW {
_UREW { w: self }
}
- #[doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." ] # [ inline ( always ) ]
pub fn sre(&mut self) -> _SREW {
_SREW { w: self }
}
- #[doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." ] # [ inline ( always ) ]
pub fn sle(&mut self) -> _SLEW {
_SLEW { w: self }
}
- #[doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated."]
- #[inline(always)]
+ # [ doc = "Bit 16 - NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." ] # [ inline ( always ) ]
pub fn nake(&mut self) -> _NAKEW {
_NAKEW { w: self }
}
@@ -76995,8 +74068,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&self) -> UER {
let bits = {
const MASK: bool = true;
@@ -77005,8 +74077,7 @@ pub mod usb1 {
};
UER { bits }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&self) -> UEER {
let bits = {
const MASK: bool = true;
@@ -77015,8 +74086,7 @@ pub mod usb1 {
};
UEER { bits }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&self) -> PCER {
let bits = {
const MASK: bool = true;
@@ -77025,8 +74095,7 @@ pub mod usb1 {
};
PCER { bits }
}
- #[doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." ] # [ inline ( always ) ]
pub fn fre(&self) -> FRER {
let bits = {
const MASK: bool = true;
@@ -77035,8 +74104,7 @@ pub mod usb1 {
};
FRER { bits }
}
- #[doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." ] # [ inline ( always ) ]
pub fn aae(&self) -> AAER {
let bits = {
const MASK: bool = true;
@@ -77045,8 +74113,7 @@ pub mod usb1 {
};
AAER { bits }
}
- #[doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn sre(&self) -> SRER {
let bits = {
const MASK: bool = true;
@@ -77055,8 +74122,7 @@ pub mod usb1 {
};
SRER { bits }
}
- #[doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." ] # [ inline ( always ) ]
pub fn uaie(&self) -> UAIER {
let bits = {
const MASK: bool = true;
@@ -77065,8 +74131,7 @@ pub mod usb1 {
};
UAIER { bits }
}
- #[doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." ] # [ inline ( always ) ]
pub fn upia(&self) -> UPIAR {
let bits = {
const MASK: bool = true;
@@ -77088,43 +74153,35 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 0 - USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." ] # [ inline ( always ) ]
pub fn ue(&mut self) -> _UEW {
_UEW { w: self }
}
- #[doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn uee(&mut self) -> _UEEW {
_UEEW { w: self }
}
- #[doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." ] # [ inline ( always ) ]
pub fn pce(&mut self) -> _PCEW {
_PCEW { w: self }
}
- #[doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." ] # [ inline ( always ) ]
pub fn fre(&mut self) -> _FREW {
_FREW { w: self }
}
- #[doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." ] # [ inline ( always ) ]
pub fn aae(&mut self) -> _AAEW {
_AAEW { w: self }
}
- #[doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." ] # [ inline ( always ) ]
pub fn sre(&mut self) -> _SREW {
_SREW { w: self }
}
- #[doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." ] # [ inline ( always ) ]
pub fn uaie(&mut self) -> _UAIEW {
_UAIEW { w: self }
}
- #[doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." ] # [ inline ( always ) ]
pub fn upia(&mut self) -> _UPIAW {
_UPIAW { w: self }
}
@@ -77404,11 +74461,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `USBADRA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum USBADRAR {
- #[doc = "Any write to USBADR are instantaneous."] ADVANCE,
- #[doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement."]
- HOLD,
- }
+ pub enum USBADRAR {# [ doc = "Any write to USBADR are instantaneous." ] ADVANCE , # [ doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." ] HOLD}
impl USBADRAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -77460,11 +74513,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `USBADRA`"]
- pub enum USBADRAW {
- #[doc = "Any write to USBADR are instantaneous."] ADVANCE,
- #[doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement."]
- HOLD,
- }
+ pub enum USBADRAW {# [ doc = "Any write to USBADR are instantaneous." ] ADVANCE , # [ doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." ] HOLD}
impl USBADRAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -77493,8 +74542,7 @@ pub mod usb1 {
pub fn advance(self) -> &'a mut W {
self.variant(USBADRAW::ADVANCE)
}
- #[doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement."]
- #[inline(always)]
+ # [ doc = "When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." ] # [ inline ( always ) ]
pub fn hold(self) -> &'a mut W {
self.variant(USBADRAW::HOLD)
}
@@ -77663,8 +74711,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals[31:12]."]
- #[inline(always)]
+ # [ doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals[31:12]." ] # [ inline ( always ) ]
pub fn perbase31_12(&self) -> PERBASE31_12R {
let bits = {
const MASK: u32 = 1048575;
@@ -77686,8 +74733,7 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals[31:12]."]
- #[inline(always)]
+ # [ doc = "Bits 12:31 - Base Address (Low) These bits correspond to the memory address signals[31:12]." ] # [ inline ( always ) ]
pub fn perbase31_12(&mut self) -> _PERBASE31_12W {
_PERBASE31_12W { w: self }
}
@@ -77775,8 +74821,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)"]
- #[inline(always)]
+ # [ doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" ] # [ inline ( always ) ]
pub fn epbase31_11(&self) -> EPBASE31_11R {
let bits = {
const MASK: u32 = 2097151;
@@ -77798,8 +74843,7 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)"]
- #[inline(always)]
+ # [ doc = "Bits 11:31 - Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" ] # [ inline ( always ) ]
pub fn epbase31_11(&mut self) -> _EPBASE31_11W {
_EPBASE31_11W { w: self }
}
@@ -77887,8 +74931,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)."]
- #[inline(always)]
+ # [ doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." ] # [ inline ( always ) ]
pub fn asybase31_5(&self) -> ASYBASE31_5R {
let bits = {
const MASK: u32 = 134217727;
@@ -77910,8 +74953,7 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)."]
- #[inline(always)]
+ # [ doc = "Bits 5:31 - Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." ] # [ inline ( always ) ]
pub fn asybase31_5(&mut self) -> _ASYBASE31_5W {
_ASYBASE31_5W { w: self }
}
@@ -78137,8 +75179,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." ] # [ inline ( always ) ]
pub fn rxpburst(&self) -> RXPBURSTR {
let bits = {
const MASK: u8 = 255;
@@ -78147,8 +75188,7 @@ pub mod usb1 {
};
RXPBURSTR { bits }
}
- #[doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." ] # [ inline ( always ) ]
pub fn txpburst(&self) -> TXPBURSTR {
let bits = {
const MASK: u8 = 255;
@@ -78170,13 +75210,11 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." ] # [ inline ( always ) ]
pub fn rxpburst(&mut self) -> _RXPBURSTW {
_RXPBURSTW { w: self }
}
- #[doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." ] # [ inline ( always ) ]
pub fn txpburst(&mut self) -> _TXPBURSTW {
_TXPBURSTW { w: self }
}
@@ -78316,8 +75354,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." ] # [ inline ( always ) ]
pub fn txschoh(&self) -> TXSCHOHR {
let bits = {
const MASK: u8 = 255;
@@ -78326,8 +75363,7 @@ pub mod usb1 {
};
TXSCHOHR { bits }
}
- #[doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." ] # [ inline ( always ) ]
pub fn txscheatlth(&self) -> TXSCHEATLTHR {
let bits = {
const MASK: u8 = 31;
@@ -78336,8 +75372,7 @@ pub mod usb1 {
};
TXSCHEATLTHR { bits }
}
- #[doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode."]
- #[inline(always)]
+ # [ doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode." ] # [ inline ( always ) ]
pub fn txfifothres(&self) -> TXFIFOTHRESR {
let bits = {
const MASK: u8 = 63;
@@ -78359,18 +75394,15 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." ] # [ inline ( always ) ]
pub fn txschoh(&mut self) -> _TXSCHOHW {
_TXSCHOHW { w: self }
}
- #[doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." ] # [ inline ( always ) ]
pub fn txscheatlth(&mut self) -> _TXSCHEATLTHW {
_TXSCHEATLTHW { w: self }
}
- #[doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode."]
- #[inline(always)]
+ # [ doc = "Bits 16:21 - Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode." ] # [ inline ( always ) ]
pub fn txfifothres(&mut self) -> _TXFIFOTHRESW {
_TXFIFOTHRESW { w: self }
}
@@ -78473,8 +75505,7 @@ pub mod usb1 {
#[doc = "Possible values of the field `ULPISS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ULPISSR {
- #[doc = "In another state (ie. carkit, serial, low power)"]
- IN_ANOTHER_STATE,
+ #[doc = "In another state (ie. carkit, serial, low power)"] IN_ANOTHER_STATE,
#[doc = "Normal Sync. State."] NORMAL_SYNC_STATE_,
}
impl ULPISSR {
@@ -78665,8 +75696,7 @@ pub mod usb1 {
}
#[doc = "Values that can be written to the field `ULPISS`"]
pub enum ULPISSW {
- #[doc = "In another state (ie. carkit, serial, low power)"]
- IN_ANOTHER_STATE,
+ #[doc = "In another state (ie. carkit, serial, low power)"] IN_ANOTHER_STATE,
#[doc = "Normal Sync. State."] NORMAL_SYNC_STATE_,
}
impl ULPISSW {
@@ -78828,8 +75858,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - When a write operation is commanded, the data to be sent is written to this field."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - When a write operation is commanded, the data to be sent is written to this field." ] # [ inline ( always ) ]
pub fn ulpidatwr(&self) -> ULPIDATWRR {
let bits = {
const MASK: u8 = 255;
@@ -78838,8 +75867,7 @@ pub mod usb1 {
};
ULPIDATWRR { bits }
}
- #[doc = "Bits 8:15 - After a read operation completes, the result is placed in this field."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - After a read operation completes, the result is placed in this field." ] # [ inline ( always ) ]
pub fn ulpidatrd(&self) -> ULPIDATRDR {
let bits = {
const MASK: u8 = 255;
@@ -78848,8 +75876,7 @@ pub mod usb1 {
};
ULPIDATRDR { bits }
}
- #[doc = "Bits 16:23 - When a read or write operation is commanded, the address of the operation is written to this field."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - When a read or write operation is commanded, the address of the operation is written to this field." ] # [ inline ( always ) ]
pub fn ulpiaddr(&self) -> ULPIADDRR {
let bits = {
const MASK: u8 = 255;
@@ -78858,8 +75885,7 @@ pub mod usb1 {
};
ULPIADDRR { bits }
}
- #[doc = "Bits 24:26 - For the wakeup or read/write operation to be executed, this value must be written as 0."]
- #[inline(always)]
+ # [ doc = "Bits 24:26 - For the wakeup or read/write operation to be executed, this value must be written as 0." ] # [ inline ( always ) ]
pub fn ulpiport(&self) -> ULPIPORTR {
let bits = {
const MASK: u8 = 7;
@@ -78877,8 +75903,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 29 - ULPI Read/Write control. This bit selects between running a read or write operation."]
- #[inline(always)]
+ # [ doc = "Bit 29 - ULPI Read/Write control. This bit selects between running a read or write operation." ] # [ inline ( always ) ]
pub fn ulpirw(&self) -> ULPIRWR {
ULPIRWR::_from({
const MASK: bool = true;
@@ -78886,8 +75911,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 30 - ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time."]
- #[inline(always)]
+ # [ doc = "Bit 30 - ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time." ] # [ inline ( always ) ]
pub fn ulpirun(&self) -> ULPIRUNR {
let bits = {
const MASK: bool = true;
@@ -78896,8 +75920,7 @@ pub mod usb1 {
};
ULPIRUNR { bits }
}
- #[doc = "Bit 31 - ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time."]
- #[inline(always)]
+ # [ doc = "Bit 31 - ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time." ] # [ inline ( always ) ]
pub fn ulpiwu(&self) -> ULPIWUR {
let bits = {
const MASK: bool = true;
@@ -78919,23 +75942,19 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - When a write operation is commanded, the data to be sent is written to this field."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - When a write operation is commanded, the data to be sent is written to this field." ] # [ inline ( always ) ]
pub fn ulpidatwr(&mut self) -> _ULPIDATWRW {
_ULPIDATWRW { w: self }
}
- #[doc = "Bits 8:15 - After a read operation completes, the result is placed in this field."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - After a read operation completes, the result is placed in this field." ] # [ inline ( always ) ]
pub fn ulpidatrd(&mut self) -> _ULPIDATRDW {
_ULPIDATRDW { w: self }
}
- #[doc = "Bits 16:23 - When a read or write operation is commanded, the address of the operation is written to this field."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - When a read or write operation is commanded, the address of the operation is written to this field." ] # [ inline ( always ) ]
pub fn ulpiaddr(&mut self) -> _ULPIADDRW {
_ULPIADDRW { w: self }
}
- #[doc = "Bits 24:26 - For the wakeup or read/write operation to be executed, this value must be written as 0."]
- #[inline(always)]
+ # [ doc = "Bits 24:26 - For the wakeup or read/write operation to be executed, this value must be written as 0." ] # [ inline ( always ) ]
pub fn ulpiport(&mut self) -> _ULPIPORTW {
_ULPIPORTW { w: self }
}
@@ -78944,18 +75963,15 @@ pub mod usb1 {
pub fn ulpiss(&mut self) -> _ULPISSW {
_ULPISSW { w: self }
}
- #[doc = "Bit 29 - ULPI Read/Write control. This bit selects between running a read or write operation."]
- #[inline(always)]
+ # [ doc = "Bit 29 - ULPI Read/Write control. This bit selects between running a read or write operation." ] # [ inline ( always ) ]
pub fn ulpirw(&mut self) -> _ULPIRWW {
_ULPIRWW { w: self }
}
- #[doc = "Bit 30 - ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time."]
- #[inline(always)]
+ # [ doc = "Bit 30 - ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time." ] # [ inline ( always ) ]
pub fn ulpirun(&mut self) -> _ULPIRUNW {
_ULPIRUNW { w: self }
}
- #[doc = "Bit 31 - ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time."]
- #[inline(always)]
+ # [ doc = "Bit 31 - ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time." ] # [ inline ( always ) ]
pub fn ulpiwu(&mut self) -> _ULPIWUW {
_ULPIWUW { w: self }
}
@@ -79481,8 +76497,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn0(&self) -> EPRN0R {
let bits = {
const MASK: bool = true;
@@ -79491,8 +76506,7 @@ pub mod usb1 {
};
EPRN0R { bits }
}
- #[doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn1(&self) -> EPRN1R {
let bits = {
const MASK: bool = true;
@@ -79501,8 +76515,7 @@ pub mod usb1 {
};
EPRN1R { bits }
}
- #[doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn2(&self) -> EPRN2R {
let bits = {
const MASK: bool = true;
@@ -79511,8 +76524,7 @@ pub mod usb1 {
};
EPRN2R { bits }
}
- #[doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn3(&self) -> EPRN3R {
let bits = {
const MASK: bool = true;
@@ -79521,8 +76533,7 @@ pub mod usb1 {
};
EPRN3R { bits }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn16(&self) -> EPTN16R {
let bits = {
const MASK: bool = true;
@@ -79531,8 +76542,7 @@ pub mod usb1 {
};
EPTN16R { bits }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn17(&self) -> EPTN17R {
let bits = {
const MASK: bool = true;
@@ -79541,8 +76551,7 @@ pub mod usb1 {
};
EPTN17R { bits }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn18(&self) -> EPTN18R {
let bits = {
const MASK: bool = true;
@@ -79551,8 +76560,7 @@ pub mod usb1 {
};
EPTN18R { bits }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn19(&self) -> EPTN19R {
let bits = {
const MASK: bool = true;
@@ -79574,43 +76582,35 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn0(&mut self) -> _EPRN0W {
_EPRN0W { w: self }
}
- #[doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn1(&mut self) -> _EPRN1W {
_EPRN1W { w: self }
}
- #[doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn2(&mut self) -> _EPRN2W {
_EPRN2W { w: self }
}
- #[doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprn3(&mut self) -> _EPRN3W {
_EPRN3W { w: self }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn16(&mut self) -> _EPTN16W {
_EPTN16W { w: self }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn17(&mut self) -> _EPTN17W {
_EPTN17W { w: self }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn18(&mut self) -> _EPTN18W {
_EPTN18W { w: self }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptn19(&mut self) -> _EPTN19W {
_EPTN19W { w: self }
}
@@ -80024,8 +77024,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne0(&self) -> EPRNE0R {
let bits = {
const MASK: bool = true;
@@ -80034,8 +77033,7 @@ pub mod usb1 {
};
EPRNE0R { bits }
}
- #[doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne1(&self) -> EPRNE1R {
let bits = {
const MASK: bool = true;
@@ -80044,8 +77042,7 @@ pub mod usb1 {
};
EPRNE1R { bits }
}
- #[doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne2(&self) -> EPRNE2R {
let bits = {
const MASK: bool = true;
@@ -80054,8 +77051,7 @@ pub mod usb1 {
};
EPRNE2R { bits }
}
- #[doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne3(&self) -> EPRNE3R {
let bits = {
const MASK: bool = true;
@@ -80064,8 +77060,7 @@ pub mod usb1 {
};
EPRNE3R { bits }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne16(&self) -> EPTNE16R {
let bits = {
const MASK: bool = true;
@@ -80074,8 +77069,7 @@ pub mod usb1 {
};
EPTNE16R { bits }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne17(&self) -> EPTNE17R {
let bits = {
const MASK: bool = true;
@@ -80084,8 +77078,7 @@ pub mod usb1 {
};
EPTNE17R { bits }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne18(&self) -> EPTNE18R {
let bits = {
const MASK: bool = true;
@@ -80094,8 +77087,7 @@ pub mod usb1 {
};
EPTNE18R { bits }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne19(&self) -> EPTNE19R {
let bits = {
const MASK: bool = true;
@@ -80117,43 +77109,35 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne0(&mut self) -> _EPRNE0W {
_EPRNE0W { w: self }
}
- #[doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne1(&mut self) -> _EPRNE1W {
_EPRNE1W { w: self }
}
- #[doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne2(&mut self) -> _EPRNE2W {
_EPRNE2W { w: self }
}
- #[doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eprne3(&mut self) -> _EPRNE3W {
_EPRNE3W { w: self }
}
- #[doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne16(&mut self) -> _EPTNE16W {
_EPTNE16W { w: self }
}
- #[doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne17(&mut self) -> _EPTNE17W {
_EPTNE17W { w: self }
}
- #[doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne18(&mut self) -> _EPTNE18W {
_EPTNE18W { w: self }
}
- #[doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." ] # [ inline ( always ) ]
pub fn eptne19(&mut self) -> _EPTNE19W {
_EPTNE19W { w: self }
}
@@ -80211,12 +77195,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `CCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CCSR {
- #[doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended."]
- DEVICE_NOT_ATTACHED_,
- #[doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register."]
- DEVICE_ATTACHED__A_,
- }
+ pub enum CCSR {# [ doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." ] DEVICE_NOT_ATTACHED_ , # [ doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." ] DEVICE_ATTACHED__A_}
impl CCSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -80457,10 +77436,8 @@ pub mod usb1 {
#[doc = "Possible values of the field `HSP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HSPR {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NOHISPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HISPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NOHISPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HISPEED,
}
impl HSPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -80665,12 +77642,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `PHCD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PHCDR {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- ENABLED,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- DISABLED,
- }
+ pub enum PHCDR {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] ENABLED , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] DISABLED}
impl PHCDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -80712,11 +77684,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `PFSC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PFSCR {
- #[doc = "Port connects at any speed."] ANYSPEED,
- #[doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device."]
- FULLSPEED,
- }
+ pub enum PFSCR {# [ doc = "Port connects at any speed." ] ANYSPEED , # [ doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." ] FULLSPEED}
impl PFSCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -80841,12 +77809,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `CCS`"]
- pub enum CCSW {
- #[doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended."]
- DEVICE_NOT_ATTACHED_,
- #[doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register."]
- DEVICE_ATTACHED__A_,
- }
+ pub enum CCSW {# [ doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." ] DEVICE_NOT_ATTACHED_ , # [ doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." ] DEVICE_ATTACHED__A_}
impl CCSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -80870,13 +77833,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended."]
- #[inline(always)]
+ # [ doc = "Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." ] # [ inline ( always ) ]
pub fn device_not_attached_(self) -> &'a mut W {
self.variant(CCSW::DEVICE_NOT_ATTACHED_)
}
- #[doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register."]
- #[inline(always)]
+ # [ doc = "Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." ] # [ inline ( always ) ]
pub fn device_attached__a_(self) -> &'a mut W {
self.variant(CCSW::DEVICE_ATTACHED__A_)
}
@@ -81137,10 +78098,8 @@ pub mod usb1 {
}
#[doc = "Values that can be written to the field `HSP`"]
pub enum HSPW {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NOHISPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HISPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NOHISPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HISPEED,
}
impl HSPW {
#[allow(missing_docs)]
@@ -81375,12 +78334,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `PHCD`"]
- pub enum PHCDW {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- ENABLED,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- DISABLED,
- }
+ pub enum PHCDW {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] ENABLED , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] DISABLED}
impl PHCDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -81404,13 +78358,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(PHCDW::ENABLED)
}
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] # [ inline ( always ) ]
pub fn disabled(self) -> &'a mut W {
self.variant(PHCDW::DISABLED)
}
@@ -81433,11 +78385,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `PFSC`"]
- pub enum PFSCW {
- #[doc = "Port connects at any speed."] ANYSPEED,
- #[doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device."]
- FULLSPEED,
- }
+ pub enum PFSCW {# [ doc = "Port connects at any speed." ] ANYSPEED , # [ doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." ] FULLSPEED}
impl PFSCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -81466,8 +78414,7 @@ pub mod usb1 {
pub fn anyspeed(self) -> &'a mut W {
self.variant(PFSCW::ANYSPEED)
}
- #[doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." ] # [ inline ( always ) ]
pub fn fullspeed(self) -> &'a mut W {
self.variant(PFSCW::FULLSPEED)
}
@@ -81623,8 +78570,7 @@ pub mod usb1 {
};
PER { bits }
}
- #[doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled." ] # [ inline ( always ) ]
pub fn pec(&self) -> PECR {
let bits = {
const MASK: bool = true;
@@ -81633,8 +78579,7 @@ pub mod usb1 {
};
PECR { bits }
}
- #[doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well." ] # [ inline ( always ) ]
pub fn fpr(&self) -> FPRR {
FPRR::_from({
const MASK: bool = true;
@@ -81651,8 +78596,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register." ] # [ inline ( always ) ]
pub fn pr(&self) -> PRR {
PRR::_from({
const MASK: bool = true;
@@ -81660,8 +78604,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons."]
- #[inline(always)]
+ # [ doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons." ] # [ inline ( always ) ]
pub fn hsp(&self) -> HSPR {
HSPR::_from({
const MASK: bool = true;
@@ -81689,8 +78632,7 @@ pub mod usb1 {
};
PPR { bits }
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins." ] # [ inline ( always ) ]
pub fn pic1_0(&self) -> PIC1_0R {
PIC1_0R::_from({
const MASK: u8 = 3;
@@ -81698,8 +78640,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved." ] # [ inline ( always ) ]
pub fn ptc3_0(&self) -> PTC3_0R {
PTC3_0R::_from({
const MASK: u8 = 15;
@@ -81707,8 +78648,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit." ] # [ inline ( always ) ]
pub fn phcd(&self) -> PHCDR {
PHCDR::_from({
const MASK: bool = true;
@@ -81725,8 +78665,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating." ] # [ inline ( always ) ]
pub fn pspd(&self) -> PSPDR {
PSPDR::_from({
const MASK: u8 = 3;
@@ -81771,13 +78710,11 @@ pub mod usb1 {
pub fn pe(&mut self) -> _PEW {
_PEW { w: self }
}
- #[doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port enable/disable change This bit is always 0. The device port is always enabled." ] # [ inline ( always ) ]
pub fn pec(&mut self) -> _PECW {
_PECW { w: self }
}
- #[doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well." ] # [ inline ( always ) ]
pub fn fpr(&mut self) -> _FPRW {
_FPRW { w: self }
}
@@ -81786,13 +78723,11 @@ pub mod usb1 {
pub fn susp(&mut self) -> _SUSPW {
_SUSPW { w: self }
}
- #[doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register." ] # [ inline ( always ) ]
pub fn pr(&mut self) -> _PRW {
_PRW { w: self }
}
- #[doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons."]
- #[inline(always)]
+ # [ doc = "Bit 9 - High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons." ] # [ inline ( always ) ]
pub fn hsp(&mut self) -> _HSPW {
_HSPW { w: self }
}
@@ -81806,18 +78741,15 @@ pub mod usb1 {
pub fn pp(&mut self) -> _PPW {
_PPW { w: self }
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins." ] # [ inline ( always ) ]
pub fn pic1_0(&mut self) -> _PIC1_0W {
_PIC1_0W { w: self }
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved." ] # [ inline ( always ) ]
pub fn ptc3_0(&mut self) -> _PTC3_0W {
_PTC3_0W { w: self }
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit." ] # [ inline ( always ) ]
pub fn phcd(&mut self) -> _PHCDW {
_PHCDW { w: self }
}
@@ -81826,8 +78758,7 @@ pub mod usb1 {
pub fn pfsc(&mut self) -> _PFSCW {
_PFSCW { w: self }
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating." ] # [ inline ( always ) ]
pub fn pspd(&mut self) -> _PSPDW {
_PSPDW { w: self }
}
@@ -82071,10 +79002,8 @@ pub mod usb1 {
#[doc = "Possible values of the field `OCA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OCAR {
- #[doc = "The port does not have an over-current condition."]
- THE_PORT_DOES_NOT_HA,
- #[doc = "The port has currently an over-current condition."]
- THE_PORT_HAS_CURRENT,
+ #[doc = "The port does not have an over-current condition."] THE_PORT_DOES_NOT_HA,
+ #[doc = "The port has currently an over-current condition."] THE_PORT_HAS_CURRENT,
}
impl OCAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -82183,11 +79112,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `SUSP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SUSPR {
- #[doc = "Port not in suspend state"] PORT_NOT_IN_SUSPEND_,
- #[doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB."]
- PORT_IN_SUSPEND_STAT,
- }
+ pub enum SUSPR {# [ doc = "Port not in suspend state" ] PORT_NOT_IN_SUSPEND_ , # [ doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." ] PORT_IN_SUSPEND_STAT}
impl SUSPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -82275,10 +79200,8 @@ pub mod usb1 {
#[doc = "Possible values of the field `HSP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HSPR {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NOHIGHSPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HIGHSPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NOHIGHSPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HIGHSPEED,
}
impl HSPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -82556,12 +79479,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `WKCN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WKCNR {
- #[doc = "Disables the port to wake up on device connects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events."]
- ENABLE_DEVICE_CON,
- }
+ pub enum WKCNR {# [ doc = "Disables the port to wake up on device connects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." ] ENABLE_DEVICE_CON}
impl WKCNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -82603,12 +79521,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `WKDC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WKDCR {
- #[doc = "Disables the port to wake up on device disconnects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events."]
- ENABLE_DEVICE_CON,
- }
+ pub enum WKDCR {# [ doc = "Disables the port to wake up on device disconnects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." ] ENABLE_DEVICE_CON}
impl WKDCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -82650,12 +79563,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `WKOC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WKOCR {
- #[doc = "Disables the port to wake up on over-current events."]
- DISABLES_OVERCURRENT,
- #[doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events."]
- ENABLE_OVERCURRENT,
- }
+ pub enum WKOCR {# [ doc = "Disables the port to wake up on over-current events." ] DISABLES_OVERCURRENT , # [ doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." ] ENABLE_OVERCURRENT}
impl WKOCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -82697,12 +79605,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `PHCD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PHCDR {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- ENABLE_PHY_CLK,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- DISABLE_PHY_CLK,
- }
+ pub enum PHCDR {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] ENABLE_PHY_CLK , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] DISABLE_PHY_CLK}
impl PHCDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -82744,11 +79647,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `PFSC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PFSCR {
- #[doc = "Port connects at any speed."] ANYSPEED,
- #[doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device."]
- FULLSPEED,
- }
+ pub enum PFSCR {# [ doc = "Port connects at any speed." ] ANYSPEED , # [ doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." ] FULLSPEED}
impl PFSCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -83098,10 +79997,8 @@ pub mod usb1 {
}
#[doc = "Values that can be written to the field `OCA`"]
pub enum OCAW {
- #[doc = "The port does not have an over-current condition."]
- THE_PORT_DOES_NOT_HA,
- #[doc = "The port has currently an over-current condition."]
- THE_PORT_HAS_CURRENT,
+ #[doc = "The port does not have an over-current condition."] THE_PORT_DOES_NOT_HA,
+ #[doc = "The port has currently an over-current condition."] THE_PORT_HAS_CURRENT,
}
impl OCAW {
#[allow(missing_docs)]
@@ -83234,11 +80131,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `SUSP`"]
- pub enum SUSPW {
- #[doc = "Port not in suspend state"] PORT_NOT_IN_SUSPEND_,
- #[doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB."]
- PORT_IN_SUSPEND_STAT,
- }
+ pub enum SUSPW {# [ doc = "Port not in suspend state" ] PORT_NOT_IN_SUSPEND_ , # [ doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." ] PORT_IN_SUSPEND_STAT}
impl SUSPW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -83267,8 +80160,7 @@ pub mod usb1 {
pub fn port_not_in_suspend_(self) -> &'a mut W {
self.variant(SUSPW::PORT_NOT_IN_SUSPEND_)
}
- #[doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB."]
- #[inline(always)]
+ # [ doc = "Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." ] # [ inline ( always ) ]
pub fn port_in_suspend_stat(self) -> &'a mut W {
self.variant(SUSPW::PORT_IN_SUSPEND_STAT)
}
@@ -83348,10 +80240,8 @@ pub mod usb1 {
}
#[doc = "Values that can be written to the field `HSP`"]
pub enum HSPW {
- #[doc = "Host/device connected to the port is not in High-speed mode."]
- NOHIGHSPEED,
- #[doc = "Host/device connected to the port is in High-speed mode."]
- HIGHSPEED,
+ #[doc = "Host/device connected to the port is not in High-speed mode."] NOHIGHSPEED,
+ #[doc = "Host/device connected to the port is in High-speed mode."] HIGHSPEED,
}
impl HSPW {
#[allow(missing_docs)]
@@ -83673,12 +80563,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `WKCN`"]
- pub enum WKCNW {
- #[doc = "Disables the port to wake up on device connects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events."]
- ENABLE_DEVICE_CON,
- }
+ pub enum WKCNW {# [ doc = "Disables the port to wake up on device connects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." ] ENABLE_DEVICE_CON}
impl WKCNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -83707,8 +80592,7 @@ pub mod usb1 {
pub fn disables_the_port_to(self) -> &'a mut W {
self.variant(WKCNW::DISABLES_THE_PORT_TO)
}
- #[doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." ] # [ inline ( always ) ]
pub fn enable_device_con(self) -> &'a mut W {
self.variant(WKCNW::ENABLE_DEVICE_CON)
}
@@ -83731,12 +80615,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `WKDC`"]
- pub enum WKDCW {
- #[doc = "Disables the port to wake up on device disconnects."]
- DISABLES_THE_PORT_TO,
- #[doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events."]
- ENABLE_DEVICE_CON,
- }
+ pub enum WKDCW {# [ doc = "Disables the port to wake up on device disconnects." ] DISABLES_THE_PORT_TO , # [ doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." ] ENABLE_DEVICE_CON}
impl WKDCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -83765,8 +80644,7 @@ pub mod usb1 {
pub fn disables_the_port_to(self) -> &'a mut W {
self.variant(WKDCW::DISABLES_THE_PORT_TO)
}
- #[doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." ] # [ inline ( always ) ]
pub fn enable_device_con(self) -> &'a mut W {
self.variant(WKDCW::ENABLE_DEVICE_CON)
}
@@ -83789,12 +80667,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `WKOC`"]
- pub enum WKOCW {
- #[doc = "Disables the port to wake up on over-current events."]
- DISABLES_OVERCURRENT,
- #[doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events."]
- ENABLE_OVERCURRENT,
- }
+ pub enum WKOCW {# [ doc = "Disables the port to wake up on over-current events." ] DISABLES_OVERCURRENT , # [ doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." ] ENABLE_OVERCURRENT}
impl WKOCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -83823,8 +80696,7 @@ pub mod usb1 {
pub fn disables_overcurrent(self) -> &'a mut W {
self.variant(WKOCW::DISABLES_OVERCURRENT)
}
- #[doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events."]
- #[inline(always)]
+ # [ doc = "Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." ] # [ inline ( always ) ]
pub fn enable_overcurrent(self) -> &'a mut W {
self.variant(WKOCW::ENABLE_OVERCURRENT)
}
@@ -83847,12 +80719,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `PHCD`"]
- pub enum PHCDW {
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- ENABLE_PHY_CLK,
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- DISABLE_PHY_CLK,
- }
+ pub enum PHCDW {# [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] ENABLE_PHY_CLK , # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] DISABLE_PHY_CLK}
impl PHCDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -83876,13 +80743,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." ] # [ inline ( always ) ]
pub fn enable_phy_clk(self) -> &'a mut W {
self.variant(PHCDW::ENABLE_PHY_CLK)
}
- #[doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)."]
- #[inline(always)]
+ # [ doc = "Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." ] # [ inline ( always ) ]
pub fn disable_phy_clk(self) -> &'a mut W {
self.variant(PHCDW::DISABLE_PHY_CLK)
}
@@ -83905,11 +80770,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `PFSC`"]
- pub enum PFSCW {
- #[doc = "Port connects at any speed."] ANYSPEED,
- #[doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device."]
- FULLSPEED,
- }
+ pub enum PFSCW {# [ doc = "Port connects at any speed." ] ANYSPEED , # [ doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." ] FULLSPEED}
impl PFSCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -83938,8 +80799,7 @@ pub mod usb1 {
pub fn anyspeed(self) -> &'a mut W {
self.variant(PFSCW::ANYSPEED)
}
- #[doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device."]
- #[inline(always)]
+ # [ doc = "Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." ] # [ inline ( always ) ]
pub fn fullspeed(self) -> &'a mut W {
self.variant(PFSCW::FULLSPEED)
}
@@ -84066,8 +80926,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it." ] # [ inline ( always ) ]
pub fn ccs(&self) -> CCSR {
CCSR::_from({
const MASK: bool = true;
@@ -84075,8 +80934,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn csc(&self) -> CSCR {
CSCR::_from({
const MASK: bool = true;
@@ -84084,8 +80942,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
@@ -84093,8 +80950,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0," ] # [ inline ( always ) ]
pub fn pec(&self) -> PECR {
PECR::_from({
const MASK: bool = true;
@@ -84102,8 +80958,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed." ] # [ inline ( always ) ]
pub fn oca(&self) -> OCAR {
OCAR::_from({
const MASK: bool = true;
@@ -84111,8 +80966,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." ] # [ inline ( always ) ]
pub fn occ(&self) -> OCCR {
let bits = {
const MASK: bool = true;
@@ -84121,8 +80975,7 @@ pub mod usb1 {
};
OCCR { bits }
}
- #[doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn fpr(&self) -> FPRR {
FPRR::_from({
const MASK: bool = true;
@@ -84130,8 +80983,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn susp(&self) -> SUSPR {
SUSPR::_from({
const MASK: bool = true;
@@ -84139,8 +80991,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pr(&self) -> PRR {
PRR::_from({
const MASK: bool = true;
@@ -84157,8 +81008,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS." ] # [ inline ( always ) ]
pub fn ls(&self) -> LSR {
LSR::_from({
const MASK: u8 = 3;
@@ -84166,8 +81016,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 12 - Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)." ] # [ inline ( always ) ]
pub fn pp(&self) -> PPR {
PPR::_from({
const MASK: bool = true;
@@ -84175,8 +81024,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0." ] # [ inline ( always ) ]
pub fn pic1_0(&self) -> PIC1_0R {
PIC1_0R::_from({
const MASK: u8 = 3;
@@ -84184,8 +81032,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved." ] # [ inline ( always ) ]
pub fn ptc3_0(&self) -> PTC3_0R {
PTC3_0R::_from({
const MASK: u8 = 15;
@@ -84193,8 +81040,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn wkcn(&self) -> WKCNR {
WKCNR::_from({
const MASK: bool = true;
@@ -84202,8 +81048,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn wkdc(&self) -> WKDCR {
WKDCR::_from({
const MASK: bool = true;
@@ -84220,8 +81065,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software." ] # [ inline ( always ) ]
pub fn phcd(&self) -> PHCDR {
PHCDR::_from({
const MASK: bool = true;
@@ -84238,8 +81082,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator." ] # [ inline ( always ) ]
pub fn pspd(&self) -> PSPDR {
PSPDR::_from({
const MASK: u8 = 3;
@@ -84269,48 +81112,39 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it." ] # [ inline ( always ) ]
pub fn ccs(&mut self) -> _CCSW {
_CCSW { w: self }
}
- #[doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn csc(&mut self) -> _CSCW {
_CSCW { w: self }
}
- #[doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pe(&mut self) -> _PEW {
_PEW { w: self }
}
- #[doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0," ] # [ inline ( always ) ]
pub fn pec(&mut self) -> _PECW {
_PECW { w: self }
}
- #[doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed." ] # [ inline ( always ) ]
pub fn oca(&mut self) -> _OCAW {
_OCAW { w: self }
}
- #[doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." ] # [ inline ( always ) ]
pub fn occ(&mut self) -> _OCCW {
_OCCW { w: self }
}
- #[doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn fpr(&mut self) -> _FPRW {
_FPRW { w: self }
}
- #[doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn susp(&mut self) -> _SUSPW {
_SUSPW { w: self }
}
- #[doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn pr(&mut self) -> _PRW {
_PRW { w: self }
}
@@ -84319,33 +81153,27 @@ pub mod usb1 {
pub fn hsp(&mut self) -> _HSPW {
_HSPW { w: self }
}
- #[doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS." ] # [ inline ( always ) ]
pub fn ls(&mut self) -> _LSW {
_LSW { w: self }
}
- #[doc = "Bit 12 - Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port)." ] # [ inline ( always ) ]
pub fn pp(&mut self) -> _PPW {
_PPW { w: self }
}
- #[doc = "Bits 14:15 - Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0."]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0." ] # [ inline ( always ) ]
pub fn pic1_0(&mut self) -> _PIC1_0W {
_PIC1_0W { w: self }
}
- #[doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved." ] # [ inline ( always ) ]
pub fn ptc3_0(&mut self) -> _PTC3_0W {
_PTC3_0W { w: self }
}
- #[doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0" ] # [ inline ( always ) ]
pub fn wkcn(&mut self) -> _WKCNW {
_WKCNW { w: self }
}
- #[doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0." ] # [ inline ( always ) ]
pub fn wkdc(&mut self) -> _WKDCW {
_WKDCW { w: self }
}
@@ -84354,8 +81182,7 @@ pub mod usb1 {
pub fn wkoc(&mut self) -> _WKOCW {
_WKOCW { w: self }
}
- #[doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software."]
- #[inline(always)]
+ # [ doc = "Bit 23 - PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software." ] # [ inline ( always ) ]
pub fn phcd(&mut self) -> _PHCDW {
_PHCDW { w: self }
}
@@ -84364,8 +81191,7 @@ pub mod usb1 {
pub fn pfsc(&mut self) -> _PFSCW {
_PFSCW { w: self }
}
- #[doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator."]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator." ] # [ inline ( always ) ]
pub fn pspd(&mut self) -> _PSPDW {
_PSPDW { w: self }
}
@@ -84472,12 +81298,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `ES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ESR {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESR {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -84565,11 +81386,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `SDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SDISR {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active."]
- DISABLED_SETTING_TH,
- }
+ pub enum SDISR {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." ] DISABLED_SETTING_TH}
impl SDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -84663,12 +81480,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `ES`"]
- pub enum ESW {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESW {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -84778,11 +81590,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `SDIS`"]
- pub enum SDISW {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active."]
- DISABLED_SETTING_TH,
- }
+ pub enum SDISW {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." ] DISABLED_SETTING_TH}
impl SDISW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -84811,8 +81619,7 @@ pub mod usb1 {
pub fn not_disabled(self) -> &'a mut W {
self.variant(SDISW::NOT_DISABLED)
}
- #[doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active."]
- #[inline(always)]
+ # [ doc = "Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." ] # [ inline ( always ) ]
pub fn disabled_setting_th(self) -> &'a mut W {
self.variant(SDISW::DISABLED_SETTING_TH)
}
@@ -84840,8 +81647,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm1_0(&self) -> CM1_0R {
CM1_0R::_from({
const MASK: u8 = 3;
@@ -84849,8 +81655,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&self) -> ESR {
ESR::_from({
const MASK: bool = true;
@@ -84858,8 +81663,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8." ] # [ inline ( always ) ]
pub fn slom(&self) -> SLOMR {
SLOMR::_from({
const MASK: bool = true;
@@ -84867,8 +81671,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&self) -> SDISR {
SDISR::_from({
const MASK: bool = true;
@@ -84889,23 +81692,19 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm1_0(&mut self) -> _CM1_0W {
_CM1_0W { w: self }
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&mut self) -> _ESW {
_ESW { w: self }
}
- #[doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8." ] # [ inline ( always ) ]
pub fn slom(&mut self) -> _SLOMW {
_SLOMW { w: self }
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&mut self) -> _SDISW {
_SDISW { w: self }
}
@@ -85007,12 +81806,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `ES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ESR {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESR {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -85054,11 +81848,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `SDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SDISR {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature."]
- DISABLED_SETTING_TO,
- }
+ pub enum SDISR {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." ] DISABLED_SETTING_TO}
impl SDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -85197,12 +81987,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `ES`"]
- pub enum ESW {
- #[doc = "Little endian: first byte referenced in least significant byte of 32-bit word."]
- LITTLE_ENDIAN_FIRST,
- #[doc = "Big endian: first byte referenced in most significant byte of 32-bit word."]
- BIG_ENDIAN_FIRST_BY,
- }
+ pub enum ESW {# [ doc = "Little endian: first byte referenced in least significant byte of 32-bit word." ] LITTLE_ENDIAN_FIRST , # [ doc = "Big endian: first byte referenced in most significant byte of 32-bit word." ] BIG_ENDIAN_FIRST_BY}
impl ESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -85255,11 +82040,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `SDIS`"]
- pub enum SDISW {
- #[doc = "Not disabled"] NOT_DISABLED,
- #[doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature."]
- DISABLED_SETTING_TO,
- }
+ pub enum SDISW {# [ doc = "Not disabled" ] NOT_DISABLED , # [ doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." ] DISABLED_SETTING_TO}
impl SDISW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -85288,8 +82069,7 @@ pub mod usb1 {
pub fn not_disabled(self) -> &'a mut W {
self.variant(SDISW::NOT_DISABLED)
}
- #[doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature."]
- #[inline(always)]
+ # [ doc = "Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." ] # [ inline ( always ) ]
pub fn disabled_setting_to(self) -> &'a mut W {
self.variant(SDISW::DISABLED_SETTING_TO)
}
@@ -85373,8 +82153,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm1_0(&self) -> CM1_0R {
CM1_0R::_from({
const MASK: u8 = 3;
@@ -85382,8 +82161,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&self) -> ESR {
ESR::_from({
const MASK: bool = true;
@@ -85391,8 +82169,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&self) -> SDISR {
SDISR::_from({
const MASK: bool = true;
@@ -85422,18 +82199,15 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register." ] # [ inline ( always ) ]
pub fn cm1_0(&mut self) -> _CM1_0W {
_CM1_0W { w: self }
}
- #[doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words." ] # [ inline ( always ) ]
pub fn es(&mut self) -> _ESW {
_ESW { w: self }
}
- #[doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved." ] # [ inline ( always ) ]
pub fn sdis(&mut self) -> _SDISW {
_SDISW { w: self }
}
@@ -85676,8 +82450,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat0(&self) -> ENDPTSETUPSTAT0R {
let bits = {
const MASK: bool = true;
@@ -85686,8 +82459,7 @@ pub mod usb1 {
};
ENDPTSETUPSTAT0R { bits }
}
- #[doc = "Bit 1 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat1(&self) -> ENDPTSETUPSTAT1R {
let bits = {
const MASK: bool = true;
@@ -85696,8 +82468,7 @@ pub mod usb1 {
};
ENDPTSETUPSTAT1R { bits }
}
- #[doc = "Bit 2 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat2(&self) -> ENDPTSETUPSTAT2R {
let bits = {
const MASK: bool = true;
@@ -85706,8 +82477,7 @@ pub mod usb1 {
};
ENDPTSETUPSTAT2R { bits }
}
- #[doc = "Bit 3 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat3(&self) -> ENDPTSETUPSTAT3R {
let bits = {
const MASK: bool = true;
@@ -85729,23 +82499,19 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat0(&mut self) -> _ENDPTSETUPSTAT0W {
_ENDPTSETUPSTAT0W { w: self }
}
- #[doc = "Bit 1 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat1(&mut self) -> _ENDPTSETUPSTAT1W {
_ENDPTSETUPSTAT1W { w: self }
}
- #[doc = "Bit 2 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat2(&mut self) -> _ENDPTSETUPSTAT2W {
_ENDPTSETUPSTAT2W { w: self }
}
- #[doc = "Bit 3 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." ] # [ inline ( always ) ]
pub fn endptsetupstat3(&mut self) -> _ENDPTSETUPSTAT3W {
_ENDPTSETUPSTAT3W { w: self }
}
@@ -86159,8 +82925,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb0(&self) -> PERB0R {
let bits = {
const MASK: bool = true;
@@ -86169,8 +82934,7 @@ pub mod usb1 {
};
PERB0R { bits }
}
- #[doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb1(&self) -> PERB1R {
let bits = {
const MASK: bool = true;
@@ -86179,8 +82943,7 @@ pub mod usb1 {
};
PERB1R { bits }
}
- #[doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb2(&self) -> PERB2R {
let bits = {
const MASK: bool = true;
@@ -86189,8 +82952,7 @@ pub mod usb1 {
};
PERB2R { bits }
}
- #[doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb3(&self) -> PERB3R {
let bits = {
const MASK: bool = true;
@@ -86199,8 +82961,7 @@ pub mod usb1 {
};
PERB3R { bits }
}
- #[doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb0(&self) -> PETB0R {
let bits = {
const MASK: bool = true;
@@ -86209,8 +82970,7 @@ pub mod usb1 {
};
PETB0R { bits }
}
- #[doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb1(&self) -> PETB1R {
let bits = {
const MASK: bool = true;
@@ -86219,8 +82979,7 @@ pub mod usb1 {
};
PETB1R { bits }
}
- #[doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb2(&self) -> PETB2R {
let bits = {
const MASK: bool = true;
@@ -86229,8 +82988,7 @@ pub mod usb1 {
};
PETB2R { bits }
}
- #[doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb3(&self) -> PETB3R {
let bits = {
const MASK: bool = true;
@@ -86252,43 +83010,35 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb0(&mut self) -> _PERB0W {
_PERB0W { w: self }
}
- #[doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb1(&mut self) -> _PERB1W {
_PERB1W { w: self }
}
- #[doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb2(&mut self) -> _PERB2W {
_PERB2W { w: self }
}
- #[doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn perb3(&mut self) -> _PERB3W {
_PERB3W { w: self }
}
- #[doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb0(&mut self) -> _PETB0W {
_PETB0W { w: self }
}
- #[doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb1(&mut self) -> _PETB1W {
_PETB1W { w: self }
}
- #[doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb2(&mut self) -> _PETB2W {
_PETB2W { w: self }
}
- #[doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn petb3(&mut self) -> _PETB3W {
_PETB3W { w: self }
}
@@ -86702,8 +83452,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb0(&self) -> FERB0R {
let bits = {
const MASK: bool = true;
@@ -86712,8 +83461,7 @@ pub mod usb1 {
};
FERB0R { bits }
}
- #[doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb1(&self) -> FERB1R {
let bits = {
const MASK: bool = true;
@@ -86722,8 +83470,7 @@ pub mod usb1 {
};
FERB1R { bits }
}
- #[doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb2(&self) -> FERB2R {
let bits = {
const MASK: bool = true;
@@ -86732,8 +83479,7 @@ pub mod usb1 {
};
FERB2R { bits }
}
- #[doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb3(&self) -> FERB3R {
let bits = {
const MASK: bool = true;
@@ -86742,8 +83488,7 @@ pub mod usb1 {
};
FERB3R { bits }
}
- #[doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb0(&self) -> FETB0R {
let bits = {
const MASK: bool = true;
@@ -86752,8 +83497,7 @@ pub mod usb1 {
};
FETB0R { bits }
}
- #[doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb1(&self) -> FETB1R {
let bits = {
const MASK: bool = true;
@@ -86762,8 +83506,7 @@ pub mod usb1 {
};
FETB1R { bits }
}
- #[doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb2(&self) -> FETB2R {
let bits = {
const MASK: bool = true;
@@ -86772,8 +83515,7 @@ pub mod usb1 {
};
FETB2R { bits }
}
- #[doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb3(&self) -> FETB3R {
let bits = {
const MASK: bool = true;
@@ -86795,43 +83537,35 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb0(&mut self) -> _FERB0W {
_FERB0W { w: self }
}
- #[doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb1(&mut self) -> _FERB1W {
_FERB1W { w: self }
}
- #[doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb2(&mut self) -> _FERB2W {
_FERB2W { w: self }
}
- #[doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn ferb3(&mut self) -> _FERB3W {
_FERB3W { w: self }
}
- #[doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb0(&mut self) -> _FETB0W {
_FETB0W { w: self }
}
- #[doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb1(&mut self) -> _FETB1W {
_FETB1W { w: self }
}
- #[doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb2(&mut self) -> _FETB2W {
_FETB2W { w: self }
}
- #[doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3" ] # [ inline ( always ) ]
pub fn fetb3(&mut self) -> _FETB3W {
_FETB3W { w: self }
}
@@ -87030,8 +83764,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erbr0(&self) -> ERBR0R {
let bits = {
const MASK: bool = true;
@@ -87040,8 +83773,7 @@ pub mod usb1 {
};
ERBR0R { bits }
}
- #[doc = "Bit 1 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erbr1(&self) -> ERBR1R {
let bits = {
const MASK: bool = true;
@@ -87050,8 +83782,7 @@ pub mod usb1 {
};
ERBR1R { bits }
}
- #[doc = "Bit 2 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erbr2(&self) -> ERBR2R {
let bits = {
const MASK: bool = true;
@@ -87060,8 +83791,7 @@ pub mod usb1 {
};
ERBR2R { bits }
}
- #[doc = "Bit 3 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erbr3(&self) -> ERBR3R {
let bits = {
const MASK: bool = true;
@@ -87070,8 +83800,7 @@ pub mod usb1 {
};
ERBR3R { bits }
}
- #[doc = "Bit 16 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etbr0(&self) -> ETBR0R {
let bits = {
const MASK: bool = true;
@@ -87080,8 +83809,7 @@ pub mod usb1 {
};
ETBR0R { bits }
}
- #[doc = "Bit 17 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etbr1(&self) -> ETBR1R {
let bits = {
const MASK: bool = true;
@@ -87090,8 +83818,7 @@ pub mod usb1 {
};
ETBR1R { bits }
}
- #[doc = "Bit 18 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etbr2(&self) -> ETBR2R {
let bits = {
const MASK: bool = true;
@@ -87100,8 +83827,7 @@ pub mod usb1 {
};
ETBR2R { bits }
}
- #[doc = "Bit 19 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etbr3(&self) -> ETBR3R {
let bits = {
const MASK: bool = true;
@@ -87520,8 +84246,7 @@ pub mod usb1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce0(&self) -> ERCE0R {
let bits = {
const MASK: bool = true;
@@ -87530,8 +84255,7 @@ pub mod usb1 {
};
ERCE0R { bits }
}
- #[doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce1(&self) -> ERCE1R {
let bits = {
const MASK: bool = true;
@@ -87540,8 +84264,7 @@ pub mod usb1 {
};
ERCE1R { bits }
}
- #[doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce2(&self) -> ERCE2R {
let bits = {
const MASK: bool = true;
@@ -87550,8 +84273,7 @@ pub mod usb1 {
};
ERCE2R { bits }
}
- #[doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce3(&self) -> ERCE3R {
let bits = {
const MASK: bool = true;
@@ -87560,8 +84282,7 @@ pub mod usb1 {
};
ERCE3R { bits }
}
- #[doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce0(&self) -> ETCE0R {
let bits = {
const MASK: bool = true;
@@ -87570,8 +84291,7 @@ pub mod usb1 {
};
ETCE0R { bits }
}
- #[doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce1(&self) -> ETCE1R {
let bits = {
const MASK: bool = true;
@@ -87580,8 +84300,7 @@ pub mod usb1 {
};
ETCE1R { bits }
}
- #[doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce2(&self) -> ETCE2R {
let bits = {
const MASK: bool = true;
@@ -87590,8 +84309,7 @@ pub mod usb1 {
};
ETCE2R { bits }
}
- #[doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce3(&self) -> ETCE3R {
let bits = {
const MASK: bool = true;
@@ -87613,43 +84331,35 @@ pub mod usb1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce0(&mut self) -> _ERCE0W {
_ERCE0W { w: self }
}
- #[doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce1(&mut self) -> _ERCE1W {
_ERCE1W { w: self }
}
- #[doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce2(&mut self) -> _ERCE2W {
_ERCE2W { w: self }
}
- #[doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn erce3(&mut self) -> _ERCE3W {
_ERCE3W { w: self }
}
- #[doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce0(&mut self) -> _ETCE0W {
_ETCE0W { w: self }
}
- #[doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce1(&mut self) -> _ETCE1W {
_ETCE1W { w: self }
}
- #[doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce2(&mut self) -> _ETCE2W {
_ETCE2W { w: self }
}
- #[doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" ] # [ inline ( always ) ]
pub fn etce3(&mut self) -> _ETCE3W {
_ETCE3W { w: self }
}
@@ -87707,11 +84417,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `RXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RXSR {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSR {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl RXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -87785,11 +84491,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `TXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TXSR {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSR {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl TXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -87862,11 +84564,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `RXS`"]
- pub enum RXSW {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSW {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl RXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -87895,8 +84593,7 @@ pub mod usb1 {
pub fn endpoint_ok_(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_OK_)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_STALLED_SOF)
}
@@ -87957,11 +84654,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `TXS`"]
- pub enum TXSW {
- #[doc = "Endpoint ok."] ENDPOINT_OK_,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSW {# [ doc = "Endpoint ok." ] ENDPOINT_OK_ , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] ENDPOINT_STALLED_SOF}
impl TXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -87990,8 +84683,7 @@ pub mod usb1 {
pub fn endpoint_ok_(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_OK_)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]"]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_STALLED_SOF)
}
@@ -88076,8 +84768,7 @@ pub mod usb1 {
};
RXTR { bits }
}
- #[doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn rxe(&self) -> RXER {
let bits = {
const MASK: bool = true;
@@ -88105,8 +84796,7 @@ pub mod usb1 {
};
TXTR { bits }
}
- #[doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn txe(&self) -> TXER {
let bits = {
const MASK: bool = true;
@@ -88138,8 +84828,7 @@ pub mod usb1 {
pub fn rxt(&mut self) -> _RXTW {
_RXTW { w: self }
}
- #[doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn rxe(&mut self) -> _RXEW {
_RXEW { w: self }
}
@@ -88153,8 +84842,7 @@ pub mod usb1 {
pub fn txt(&mut self) -> _TXTW {
_TXTW { w: self }
}
- #[doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." ] # [ inline ( always ) ]
pub fn txe(&mut self) -> _TXEW {
_TXEW { w: self }
}
@@ -88212,12 +84900,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `RXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RXSR {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSR {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" ] ENDPOINT_STALLED_SOF}
impl RXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -88414,12 +85097,7 @@ pub mod usb1 {
}
#[doc = "Possible values of the field `TXS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TXSR {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSR {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" ] ENDPOINT_STALLED_SOF}
impl TXSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -88623,12 +85301,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `RXS`"]
- pub enum RXSW {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum RXSW {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" ] ENDPOINT_STALLED_SOF}
impl RXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -88652,13 +85325,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- #[inline(always)]
+ # [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] # [ inline ( always ) ]
pub fn endpoint_ok_this_bi(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_OK_THIS_BI)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]"]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(RXSW::ENDPOINT_STALLED_SOF)
}
@@ -88869,12 +85540,7 @@ pub mod usb1 {
}
}
#[doc = "Values that can be written to the field `TXS`"]
- pub enum TXSW {
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- ENDPOINT_OK_THIS_BI,
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]"]
- ENDPOINT_STALLED_SOF,
- }
+ pub enum TXSW {# [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] ENDPOINT_OK_THIS_BI , # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" ] ENDPOINT_STALLED_SOF}
impl TXSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -88898,13 +85564,11 @@ pub mod usb1 {
self.bit(variant._bits())
}
}
- #[doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared."]
- #[inline(always)]
+ # [ doc = "Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." ] # [ inline ( always ) ]
pub fn endpoint_ok_this_bi(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_OK_THIS_BI)
}
- #[doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]"]
- #[inline(always)]
+ # [ doc = "Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" ] # [ inline ( always ) ]
pub fn endpoint_stalled_sof(self) -> &'a mut W {
self.variant(TXSW::ENDPOINT_STALLED_SOF)
}
@@ -89147,8 +85811,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn rxi(&self) -> RXIR {
RXIR::_from({
const MASK: bool = true;
@@ -89156,8 +85819,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn rxr(&self) -> RXRR {
let bits = {
const MASK: bool = true;
@@ -89166,8 +85828,7 @@ pub mod usb1 {
};
RXRR { bits }
}
- #[doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured." ] # [ inline ( always ) ]
pub fn rxe(&self) -> RXER {
RXER::_from({
const MASK: bool = true;
@@ -89193,8 +85854,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn txi(&self) -> TXIR {
TXIR::_from({
const MASK: bool = true;
@@ -89202,8 +85862,7 @@ pub mod usb1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn txr(&self) -> TXRR {
let bits = {
const MASK: bool = true;
@@ -89212,8 +85871,7 @@ pub mod usb1 {
};
TXRR { bits }
}
- #[doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured"]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured" ] # [ inline ( always ) ]
pub fn txe(&self) -> TXER {
TXER::_from({
const MASK: bool = true;
@@ -89244,18 +85902,15 @@ pub mod usb1 {
pub fn rxt(&mut self) -> _RXTW {
_RXTW { w: self }
}
- #[doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn rxi(&mut self) -> _RXIW {
_RXIW { w: self }
}
- #[doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn rxr(&mut self) -> _RXRW {
_RXRW { w: self }
}
- #[doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rx endpoint enable An endpoint should be enabled only after it has been configured." ] # [ inline ( always ) ]
pub fn rxe(&mut self) -> _RXEW {
_RXEW { w: self }
}
@@ -89269,18 +85924,15 @@ pub mod usb1 {
pub fn txt(&mut self) -> _TXTW {
_TXTW { w: self }
}
- #[doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID." ] # [ inline ( always ) ]
pub fn txi(&mut self) -> _TXIW {
_TXIW { w: self }
}
- #[doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." ] # [ inline ( always ) ]
pub fn txr(&mut self) -> _TXRW {
_TXRW { w: self }
}
- #[doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured"]
- #[inline(always)]
+ # [ doc = "Bit 23 - Tx endpoint enable An endpoint should be enabled only after it has been configured" ] # [ inline ( always ) ]
pub fn txe(&mut self) -> _TXEW {
_TXEW { w: self }
}
@@ -89307,22 +85959,17 @@ pub mod lcd {
pub struct RegisterBlock {
#[doc = "0x00 - Horizontal Timing Control register"] pub timh: TIMH,
#[doc = "0x04 - Vertical Timing Control register"] pub timv: TIMV,
- #[doc = "0x08 - Clock and Signal Polarity Control register"]
- pub pol: POL,
+ #[doc = "0x08 - Clock and Signal Polarity Control register"] pub pol: POL,
#[doc = "0x0c - Line End Control register"] pub le: LE,
- #[doc = "0x10 - Upper Panel Frame Base Address register"]
- pub upbase: UPBASE,
- #[doc = "0x14 - Lower Panel Frame Base Address register"]
- pub lpbase: LPBASE,
+ #[doc = "0x10 - Upper Panel Frame Base Address register"] pub upbase: UPBASE,
+ #[doc = "0x14 - Lower Panel Frame Base Address register"] pub lpbase: LPBASE,
#[doc = "0x18 - LCD Control register"] pub ctrl: CTRL,
#[doc = "0x1c - Interrupt Mask register"] pub intmsk: INTMSK,
#[doc = "0x20 - Raw Interrupt Status register"] pub intraw: INTRAW,
#[doc = "0x24 - Masked Interrupt Status register"] pub intstat: INTSTAT,
#[doc = "0x28 - Interrupt Clear register"] pub intclr: INTCLR,
- #[doc = "0x2c - Upper Panel Current Address Value register"]
- pub upcurr: UPCURR,
- #[doc = "0x30 - Lower Panel Current Address Value register"]
- pub lpcurr: LPCURR,
+ #[doc = "0x2c - Upper Panel Current Address Value register"] pub upcurr: UPCURR,
+ #[doc = "0x30 - Lower Panel Current Address Value register"] pub lpcurr: LPCURR,
_reserved0: [u8; 460usize],
#[doc = "0x200 - 256x16-bit Color Palette registers"] pub pal0: PAL,
#[doc = "0x204 - 256x16-bit Color Palette registers"] pub pal1: PAL,
@@ -89842,17 +86489,12 @@ pub mod lcd {
#[doc = "0xc08 - Cursor Palette register 0"] pub crsr_pal0: CRSR_PAL0,
#[doc = "0xc0c - Cursor Palette register 1"] pub crsr_pal1: CRSR_PAL1,
#[doc = "0xc10 - Cursor XY Position register"] pub crsr_xy: CRSR_XY,
- #[doc = "0xc14 - Cursor Clip Position register"]
- pub crsr_clip: CRSR_CLIP,
+ #[doc = "0xc14 - Cursor Clip Position register"] pub crsr_clip: CRSR_CLIP,
_reserved2: [u8; 8usize],
- #[doc = "0xc20 - Cursor Interrupt Mask register"]
- pub crsr_intmsk: CRSR_INTMSK,
- #[doc = "0xc24 - Cursor Interrupt Clear register"]
- pub crsr_intclr: CRSR_INTCLR,
- #[doc = "0xc28 - Cursor Raw Interrupt Status register"]
- pub crsr_intraw: CRSR_INTRAW,
- #[doc = "0xc2c - Cursor Masked Interrupt Status register"]
- pub crsr_intstat: CRSR_INTSTAT,
+ #[doc = "0xc20 - Cursor Interrupt Mask register"] pub crsr_intmsk: CRSR_INTMSK,
+ #[doc = "0xc24 - Cursor Interrupt Clear register"] pub crsr_intclr: CRSR_INTCLR,
+ #[doc = "0xc28 - Cursor Raw Interrupt Status register"] pub crsr_intraw: CRSR_INTRAW,
+ #[doc = "0xc2c - Cursor Masked Interrupt Status register"] pub crsr_intstat: CRSR_INTSTAT,
}
#[doc = "Horizontal Timing Control register"]
pub struct TIMH {
@@ -90014,8 +86656,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 2:7 - Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19."]
- #[inline(always)]
+ # [ doc = "Bits 2:7 - Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." ] # [ inline ( always ) ]
pub fn ppl(&self) -> PPLR {
let bits = {
const MASK: u8 = 63;
@@ -90024,8 +86665,7 @@ pub mod lcd {
};
PPLR { bits }
}
- #[doc = "Bits 8:15 - Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." ] # [ inline ( always ) ]
pub fn hsw(&self) -> HSWR {
let bits = {
const MASK: u8 = 255;
@@ -90034,8 +86674,7 @@ pub mod lcd {
};
HSWR { bits }
}
- #[doc = "Bits 16:23 - Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." ] # [ inline ( always ) ]
pub fn hfp(&self) -> HFPR {
let bits = {
const MASK: u8 = 255;
@@ -90044,8 +86683,7 @@ pub mod lcd {
};
HFPR { bits }
}
- #[doc = "Bits 24:31 - Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 24:31 - Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." ] # [ inline ( always ) ]
pub fn hbp(&self) -> HBPR {
let bits = {
const MASK: u8 = 255;
@@ -90067,23 +86705,19 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 2:7 - Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19."]
- #[inline(always)]
+ # [ doc = "Bits 2:7 - Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." ] # [ inline ( always ) ]
pub fn ppl(&mut self) -> _PPLW {
_PPLW { w: self }
}
- #[doc = "Bits 8:15 - Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." ] # [ inline ( always ) ]
pub fn hsw(&mut self) -> _HSWW {
_HSWW { w: self }
}
- #[doc = "Bits 16:23 - Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." ] # [ inline ( always ) ]
pub fn hfp(&mut self) -> _HFPW {
_HFPW { w: self }
}
- #[doc = "Bits 24:31 - Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 24:31 - Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." ] # [ inline ( always ) ]
pub fn hbp(&mut self) -> _HBPW {
_HBPW { w: self }
}
@@ -90249,8 +86883,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:9 - Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels."]
- #[inline(always)]
+ # [ doc = "Bits 0:9 - Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." ] # [ inline ( always ) ]
pub fn lpp(&self) -> LPPR {
let bits = {
const MASK: u16 = 1023;
@@ -90259,8 +86892,7 @@ pub mod lcd {
};
LPPR { bits }
}
- #[doc = "Bits 10:15 - Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs."]
- #[inline(always)]
+ # [ doc = "Bits 10:15 - Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." ] # [ inline ( always ) ]
pub fn vsw(&self) -> VSWR {
let bits = {
const MASK: u8 = 63;
@@ -90269,8 +86901,7 @@ pub mod lcd {
};
VSWR { bits }
}
- #[doc = "Bits 16:23 - Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." ] # [ inline ( always ) ]
pub fn vfp(&self) -> VFPR {
let bits = {
const MASK: u8 = 255;
@@ -90279,8 +86910,7 @@ pub mod lcd {
};
VFPR { bits }
}
- #[doc = "Bits 24:31 - Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast."]
- #[inline(always)]
+ # [ doc = "Bits 24:31 - Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." ] # [ inline ( always ) ]
pub fn vbp(&self) -> VBPR {
let bits = {
const MASK: u8 = 255;
@@ -90302,23 +86932,19 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 0:9 - Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels."]
- #[inline(always)]
+ # [ doc = "Bits 0:9 - Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." ] # [ inline ( always ) ]
pub fn lpp(&mut self) -> _LPPW {
_LPPW { w: self }
}
- #[doc = "Bits 10:15 - Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs."]
- #[inline(always)]
+ # [ doc = "Bits 10:15 - Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." ] # [ inline ( always ) ]
pub fn vsw(&mut self) -> _VSWW {
_VSWW { w: self }
}
- #[doc = "Bits 16:23 - Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." ] # [ inline ( always ) ]
pub fn vfp(&mut self) -> _VFPW {
_VFPW { w: self }
}
- #[doc = "Bits 24:31 - Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast."]
- #[inline(always)]
+ # [ doc = "Bits 24:31 - Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." ] # [ inline ( always ) ]
pub fn vbp(&mut self) -> _VBPW {
_VBPW { w: self }
}
@@ -90748,8 +87374,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." ] # [ inline ( always ) ]
pub fn pcd_lo(&self) -> PCD_LOR {
let bits = {
const MASK: u8 = 31;
@@ -90758,8 +87383,7 @@ pub mod lcd {
};
PCD_LOR { bits }
}
- #[doc = "Bit 5 - Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." ] # [ inline ( always ) ]
pub fn clksel(&self) -> CLKSELR {
let bits = {
const MASK: bool = true;
@@ -90768,8 +87392,7 @@ pub mod lcd {
};
CLKSELR { bits }
}
- #[doc = "Bits 6:10 - AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal."]
- #[inline(always)]
+ # [ doc = "Bits 6:10 - AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." ] # [ inline ( always ) ]
pub fn acb(&self) -> ACBR {
let bits = {
const MASK: u8 = 31;
@@ -90778,8 +87401,7 @@ pub mod lcd {
};
ACBR { bits }
}
- #[doc = "Bit 11 - Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." ] # [ inline ( always ) ]
pub fn ivs(&self) -> IVSR {
let bits = {
const MASK: bool = true;
@@ -90788,8 +87410,7 @@ pub mod lcd {
};
IVSR { bits }
}
- #[doc = "Bit 12 - Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." ] # [ inline ( always ) ]
pub fn ihs(&self) -> IHSR {
let bits = {
const MASK: bool = true;
@@ -90798,8 +87419,7 @@ pub mod lcd {
};
IHSR { bits }
}
- #[doc = "Bit 13 - Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." ] # [ inline ( always ) ]
pub fn ipc(&self) -> IPCR {
let bits = {
const MASK: bool = true;
@@ -90808,8 +87428,7 @@ pub mod lcd {
};
IPCR { bits }
}
- #[doc = "Bit 14 - Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." ] # [ inline ( always ) ]
pub fn ioe(&self) -> IOER {
let bits = {
const MASK: bool = true;
@@ -90818,8 +87437,7 @@ pub mod lcd {
};
IOER { bits }
}
- #[doc = "Bits 16:25 - Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly."]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." ] # [ inline ( always ) ]
pub fn cpl(&self) -> CPLR {
let bits = {
const MASK: u16 = 1023;
@@ -90828,8 +87446,7 @@ pub mod lcd {
};
CPLR { bits }
}
- #[doc = "Bit 26 - Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." ] # [ inline ( always ) ]
pub fn bcd(&self) -> BCDR {
let bits = {
const MASK: bool = true;
@@ -90838,8 +87455,7 @@ pub mod lcd {
};
BCDR { bits }
}
- #[doc = "Bits 27:31 - Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register."]
- #[inline(always)]
+ # [ doc = "Bits 27:31 - Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." ] # [ inline ( always ) ]
pub fn pcd_hi(&self) -> PCD_HIR {
let bits = {
const MASK: u8 = 31;
@@ -90861,53 +87477,43 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." ] # [ inline ( always ) ]
pub fn pcd_lo(&mut self) -> _PCD_LOW {
_PCD_LOW { w: self }
}
- #[doc = "Bit 5 - Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." ] # [ inline ( always ) ]
pub fn clksel(&mut self) -> _CLKSELW {
_CLKSELW { w: self }
}
- #[doc = "Bits 6:10 - AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal."]
- #[inline(always)]
+ # [ doc = "Bits 6:10 - AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." ] # [ inline ( always ) ]
pub fn acb(&mut self) -> _ACBW {
_ACBW { w: self }
}
- #[doc = "Bit 11 - Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." ] # [ inline ( always ) ]
pub fn ivs(&mut self) -> _IVSW {
_IVSW { w: self }
}
- #[doc = "Bit 12 - Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." ] # [ inline ( always ) ]
pub fn ihs(&mut self) -> _IHSW {
_IHSW { w: self }
}
- #[doc = "Bit 13 - Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." ] # [ inline ( always ) ]
pub fn ipc(&mut self) -> _IPCW {
_IPCW { w: self }
}
- #[doc = "Bit 14 - Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." ] # [ inline ( always ) ]
pub fn ioe(&mut self) -> _IOEW {
_IOEW { w: self }
}
- #[doc = "Bits 16:25 - Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly."]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." ] # [ inline ( always ) ]
pub fn cpl(&mut self) -> _CPLW {
_CPLW { w: self }
}
- #[doc = "Bit 26 - Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." ] # [ inline ( always ) ]
pub fn bcd(&mut self) -> _BCDW {
_BCDW { w: self }
}
- #[doc = "Bits 27:31 - Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register."]
- #[inline(always)]
+ # [ doc = "Bits 27:31 - Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." ] # [ inline ( always ) ]
pub fn pcd_hi(&mut self) -> _PCD_HIW {
_PCD_HIW { w: self }
}
@@ -91039,8 +87645,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:6 - Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 0:6 - Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." ] # [ inline ( always ) ]
pub fn led(&self) -> LEDR {
let bits = {
const MASK: u8 = 127;
@@ -91049,8 +87654,7 @@ pub mod lcd {
};
LEDR { bits }
}
- #[doc = "Bit 16 - LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active."]
- #[inline(always)]
+ # [ doc = "Bit 16 - LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." ] # [ inline ( always ) ]
pub fn lee(&self) -> LEER {
let bits = {
const MASK: bool = true;
@@ -91072,13 +87676,11 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 0:6 - Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1."]
- #[inline(always)]
+ # [ doc = "Bits 0:6 - Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." ] # [ inline ( always ) ]
pub fn led(&mut self) -> _LEDW {
_LEDW { w: self }
}
- #[doc = "Bit 16 - LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active."]
- #[inline(always)]
+ # [ doc = "Bit 16 - LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." ] # [ inline ( always ) ]
pub fn lee(&mut self) -> _LEEW {
_LEEW { w: self }
}
@@ -91166,8 +87768,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 3:31 - LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned."]
- #[inline(always)]
+ # [ doc = "Bits 3:31 - LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." ] # [ inline ( always ) ]
pub fn lcdupbase(&self) -> LCDUPBASER {
let bits = {
const MASK: u32 = 536870911;
@@ -91189,8 +87790,7 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 3:31 - LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned."]
- #[inline(always)]
+ # [ doc = "Bits 3:31 - LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." ] # [ inline ( always ) ]
pub fn lcdupbase(&mut self) -> _LCDUPBASEW {
_LCDUPBASEW { w: self }
}
@@ -91278,8 +87878,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 3:31 - LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned."]
- #[inline(always)]
+ # [ doc = "Bits 3:31 - LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." ] # [ inline ( always ) ]
pub fn lcdlpbase(&self) -> LCDLPBASER {
let bits = {
const MASK: u32 = 536870911;
@@ -91301,8 +87900,7 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 3:31 - LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned."]
- #[inline(always)]
+ # [ doc = "Bits 3:31 - LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." ] # [ inline ( always ) ]
pub fn lcdlpbase(&mut self) -> _LCDLPBASEW {
_LCDLPBASEW { w: self }
}
@@ -91856,8 +88454,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing."]
- #[inline(always)]
+ # [ doc = "Bit 0 - LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." ] # [ inline ( always ) ]
pub fn lcden(&self) -> LCDENR {
let bits = {
const MASK: bool = true;
@@ -91866,8 +88463,7 @@ pub mod lcd {
};
LCDENR { bits }
}
- #[doc = "Bits 1:3 - LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode."]
- #[inline(always)]
+ # [ doc = "Bits 1:3 - LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." ] # [ inline ( always ) ]
pub fn lcdbpp(&self) -> LCDBPPR {
let bits = {
const MASK: u8 = 7;
@@ -91876,8 +88472,7 @@ pub mod lcd {
};
LCDBPPR { bits }
}
- #[doc = "Bit 4 - STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode."]
- #[inline(always)]
+ # [ doc = "Bit 4 - STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." ] # [ inline ( always ) ]
pub fn lcdbw(&self) -> LCDBWR {
let bits = {
const MASK: bool = true;
@@ -91886,8 +88481,7 @@ pub mod lcd {
};
LCDBWR { bits }
}
- #[doc = "Bit 5 - LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler."]
- #[inline(always)]
+ # [ doc = "Bit 5 - LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." ] # [ inline ( always ) ]
pub fn lcdtft(&self) -> LCDTFTR {
let bits = {
const MASK: bool = true;
@@ -91896,8 +88490,7 @@ pub mod lcd {
};
LCDTFTR { bits }
}
- #[doc = "Bit 6 - Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." ] # [ inline ( always ) ]
pub fn lcdmono8(&self) -> LCDMONO8R {
let bits = {
const MASK: bool = true;
@@ -91906,8 +88499,7 @@ pub mod lcd {
};
LCDMONO8R { bits }
}
- #[doc = "Bit 7 - Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." ] # [ inline ( always ) ]
pub fn lcddual(&self) -> LCDDUALR {
let bits = {
const MASK: bool = true;
@@ -91916,8 +88508,7 @@ pub mod lcd {
};
LCDDUALR { bits }
}
- #[doc = "Bit 8 - Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." ] # [ inline ( always ) ]
pub fn bgr(&self) -> BGRR {
let bits = {
const MASK: bool = true;
@@ -91926,8 +88517,7 @@ pub mod lcd {
};
BGRR { bits }
}
- #[doc = "Bit 9 - Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." ] # [ inline ( always ) ]
pub fn bebo(&self) -> BEBOR {
let bits = {
const MASK: bool = true;
@@ -91936,8 +88526,7 @@ pub mod lcd {
};
BEBOR { bits }
}
- #[doc = "Bit 10 - Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format." ] # [ inline ( always ) ]
pub fn bepo(&self) -> BEPOR {
let bits = {
const MASK: bool = true;
@@ -91946,8 +88535,7 @@ pub mod lcd {
};
BEPOR { bits }
}
- #[doc = "Bit 11 - LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing."]
- #[inline(always)]
+ # [ doc = "Bit 11 - LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing." ] # [ inline ( always ) ]
pub fn lcdpwr(&self) -> LCDPWRR {
let bits = {
const MASK: bool = true;
@@ -91956,8 +88544,7 @@ pub mod lcd {
};
LCDPWRR { bits }
}
- #[doc = "Bits 12:13 - LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch."]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." ] # [ inline ( always ) ]
pub fn lcdvcomp(&self) -> LCDVCOMPR {
let bits = {
const MASK: u8 = 3;
@@ -91966,8 +88553,7 @@ pub mod lcd {
};
LCDVCOMPR { bits }
}
- #[doc = "Bit 16 - LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations."]
- #[inline(always)]
+ # [ doc = "Bit 16 - LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." ] # [ inline ( always ) ]
pub fn watermark(&self) -> WATERMARKR {
let bits = {
const MASK: bool = true;
@@ -91989,63 +88575,51 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bit 0 - LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing."]
- #[inline(always)]
+ # [ doc = "Bit 0 - LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." ] # [ inline ( always ) ]
pub fn lcden(&mut self) -> _LCDENW {
_LCDENW { w: self }
}
- #[doc = "Bits 1:3 - LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode."]
- #[inline(always)]
+ # [ doc = "Bits 1:3 - LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." ] # [ inline ( always ) ]
pub fn lcdbpp(&mut self) -> _LCDBPPW {
_LCDBPPW { w: self }
}
- #[doc = "Bit 4 - STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode."]
- #[inline(always)]
+ # [ doc = "Bit 4 - STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." ] # [ inline ( always ) ]
pub fn lcdbw(&mut self) -> _LCDBWW {
_LCDBWW { w: self }
}
- #[doc = "Bit 5 - LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler."]
- #[inline(always)]
+ # [ doc = "Bit 5 - LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." ] # [ inline ( always ) ]
pub fn lcdtft(&mut self) -> _LCDTFTW {
_LCDTFTW { w: self }
}
- #[doc = "Bit 6 - Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." ] # [ inline ( always ) ]
pub fn lcdmono8(&mut self) -> _LCDMONO8W {
_LCDMONO8W { w: self }
}
- #[doc = "Bit 7 - Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." ] # [ inline ( always ) ]
pub fn lcddual(&mut self) -> _LCDDUALW {
_LCDDUALW { w: self }
}
- #[doc = "Bit 8 - Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." ] # [ inline ( always ) ]
pub fn bgr(&mut self) -> _BGRW {
_BGRW { w: self }
}
- #[doc = "Bit 9 - Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." ] # [ inline ( always ) ]
pub fn bebo(&mut self) -> _BEBOW {
_BEBOW { w: self }
}
- #[doc = "Bit 10 - Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format." ] # [ inline ( always ) ]
pub fn bepo(&mut self) -> _BEPOW {
_BEPOW { w: self }
}
- #[doc = "Bit 11 - LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing."]
- #[inline(always)]
+ # [ doc = "Bit 11 - LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing." ] # [ inline ( always ) ]
pub fn lcdpwr(&mut self) -> _LCDPWRW {
_LCDPWRW { w: self }
}
- #[doc = "Bits 12:13 - LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch."]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." ] # [ inline ( always ) ]
pub fn lcdvcomp(&mut self) -> _LCDVCOMPW {
_LCDVCOMPW { w: self }
}
- #[doc = "Bit 16 - LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations."]
- #[inline(always)]
+ # [ doc = "Bit 16 - LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." ] # [ inline ( always ) ]
pub fn watermark(&mut self) -> _WATERMARKW {
_WATERMARKW { w: self }
}
@@ -92283,8 +88857,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 1 - FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows."]
- #[inline(always)]
+ # [ doc = "Bit 1 - FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." ] # [ inline ( always ) ]
pub fn fufim(&self) -> FUFIMR {
let bits = {
const MASK: bool = true;
@@ -92293,8 +88866,7 @@ pub mod lcd {
};
FUFIMR { bits }
}
- #[doc = "Bit 2 - LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers."]
- #[inline(always)]
+ # [ doc = "Bit 2 - LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." ] # [ inline ( always ) ]
pub fn lnbuim(&self) -> LNBUIMR {
let bits = {
const MASK: bool = true;
@@ -92303,8 +88875,7 @@ pub mod lcd {
};
LNBUIMR { bits }
}
- #[doc = "Bit 3 - Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." ] # [ inline ( always ) ]
pub fn vcompim(&self) -> VCOMPIMR {
let bits = {
const MASK: bool = true;
@@ -92313,8 +88884,7 @@ pub mod lcd {
};
VCOMPIMR { bits }
}
- #[doc = "Bit 4 - AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs."]
- #[inline(always)]
+ # [ doc = "Bit 4 - AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." ] # [ inline ( always ) ]
pub fn berim(&self) -> BERIMR {
let bits = {
const MASK: bool = true;
@@ -92336,23 +88906,19 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bit 1 - FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows."]
- #[inline(always)]
+ # [ doc = "Bit 1 - FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." ] # [ inline ( always ) ]
pub fn fufim(&mut self) -> _FUFIMW {
_FUFIMW { w: self }
}
- #[doc = "Bit 2 - LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers."]
- #[inline(always)]
+ # [ doc = "Bit 2 - LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." ] # [ inline ( always ) ]
pub fn lnbuim(&mut self) -> _LNBUIMW {
_LNBUIMW { w: self }
}
- #[doc = "Bit 3 - Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." ] # [ inline ( always ) ]
pub fn vcompim(&mut self) -> _VCOMPIMW {
_VCOMPIMW { w: self }
}
- #[doc = "Bit 4 - AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs."]
- #[inline(always)]
+ # [ doc = "Bit 4 - AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." ] # [ inline ( always ) ]
pub fn berim(&mut self) -> _BERIMW {
_BERIMW { w: self }
}
@@ -92467,8 +89033,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 1 - FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set."]
- #[inline(always)]
+ # [ doc = "Bit 1 - FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." ] # [ inline ( always ) ]
pub fn fufris(&self) -> FUFRISR {
let bits = {
const MASK: bool = true;
@@ -92477,8 +89042,7 @@ pub mod lcd {
};
FUFRISR { bits }
}
- #[doc = "Bit 2 - LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set."]
- #[inline(always)]
+ # [ doc = "Bit 2 - LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." ] # [ inline ( always ) ]
pub fn lnburis(&self) -> LNBURISR {
let bits = {
const MASK: bool = true;
@@ -92487,8 +89051,7 @@ pub mod lcd {
};
LNBURISR { bits }
}
- #[doc = "Bit 3 - Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." ] # [ inline ( always ) ]
pub fn vcompris(&self) -> VCOMPRISR {
let bits = {
const MASK: bool = true;
@@ -92497,8 +89060,7 @@ pub mod lcd {
};
VCOMPRISR { bits }
}
- #[doc = "Bit 4 - AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set."]
- #[inline(always)]
+ # [ doc = "Bit 4 - AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." ] # [ inline ( always ) ]
pub fn berraw(&self) -> BERRAWR {
let bits = {
const MASK: bool = true;
@@ -92618,8 +89180,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 1 - FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set."]
- #[inline(always)]
+ # [ doc = "Bit 1 - FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." ] # [ inline ( always ) ]
pub fn fufmis(&self) -> FUFMISR {
let bits = {
const MASK: bool = true;
@@ -92628,8 +89189,7 @@ pub mod lcd {
};
FUFMISR { bits }
}
- #[doc = "Bit 2 - LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set."]
- #[inline(always)]
+ # [ doc = "Bit 2 - LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." ] # [ inline ( always ) ]
pub fn lnbumis(&self) -> LNBUMISR {
let bits = {
const MASK: bool = true;
@@ -92638,8 +89198,7 @@ pub mod lcd {
};
LNBUMISR { bits }
}
- #[doc = "Bit 3 - Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." ] # [ inline ( always ) ]
pub fn vcompmis(&self) -> VCOMPMISR {
let bits = {
const MASK: bool = true;
@@ -92648,8 +89207,7 @@ pub mod lcd {
};
VCOMPMISR { bits }
}
- #[doc = "Bit 4 - AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set."]
- #[inline(always)]
+ # [ doc = "Bit 4 - AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." ] # [ inline ( always ) ]
pub fn bermis(&self) -> BERMISR {
let bits = {
const MASK: bool = true;
@@ -92786,23 +89344,19 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bit 1 - FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." ] # [ inline ( always ) ]
pub fn fufic(&mut self) -> _FUFICW {
_FUFICW { w: self }
}
- #[doc = "Bit 2 - LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." ] # [ inline ( always ) ]
pub fn lnbuic(&mut self) -> _LNBUICW {
_LNBUICW { w: self }
}
- #[doc = "Bit 3 - Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." ] # [ inline ( always ) ]
pub fn vcompic(&mut self) -> _VCOMPICW {
_VCOMPICW { w: self }
}
- #[doc = "Bit 4 - AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." ] # [ inline ( always ) ]
pub fn beric(&mut self) -> _BERICW {
_BERICW { w: self }
}
@@ -92844,8 +89398,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." ] # [ inline ( always ) ]
pub fn lcdupcurr(&self) -> LCDUPCURRR {
let bits = {
const MASK: u32 = 4294967295;
@@ -92892,8 +89445,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." ] # [ inline ( always ) ]
pub fn lcdlpcurr(&self) -> LCDLPCURRR {
let bits = {
const MASK: u32 = 4294967295;
@@ -93204,8 +89756,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." ] # [ inline ( always ) ]
pub fn r04_0(&self) -> R04_0R {
let bits = {
const MASK: u8 = 31;
@@ -93234,8 +89785,7 @@ pub mod lcd {
};
B04_0R { bits }
}
- #[doc = "Bit 15 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." ] # [ inline ( always ) ]
pub fn i0(&self) -> I0R {
let bits = {
const MASK: bool = true;
@@ -93244,8 +89794,7 @@ pub mod lcd {
};
I0R { bits }
}
- #[doc = "Bits 16:20 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields."]
- #[inline(always)]
+ # [ doc = "Bits 16:20 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." ] # [ inline ( always ) ]
pub fn r14_0(&self) -> R14_0R {
let bits = {
const MASK: u8 = 31;
@@ -93274,8 +89823,7 @@ pub mod lcd {
};
B14_0R { bits }
}
- #[doc = "Bit 31 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." ] # [ inline ( always ) ]
pub fn i1(&self) -> I1R {
let bits = {
const MASK: bool = true;
@@ -93297,8 +89845,7 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." ] # [ inline ( always ) ]
pub fn r04_0(&mut self) -> _R04_0W {
_R04_0W { w: self }
}
@@ -93312,13 +89859,11 @@ pub mod lcd {
pub fn b04_0(&mut self) -> _B04_0W {
_B04_0W { w: self }
}
- #[doc = "Bit 15 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." ] # [ inline ( always ) ]
pub fn i0(&mut self) -> _I0W {
_I0W { w: self }
}
- #[doc = "Bits 16:20 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields."]
- #[inline(always)]
+ # [ doc = "Bits 16:20 - Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." ] # [ inline ( always ) ]
pub fn r14_0(&mut self) -> _R14_0W {
_R14_0W { w: self }
}
@@ -93332,8 +89877,7 @@ pub mod lcd {
pub fn b14_0(&mut self) -> _B14_0W {
_B14_0W { w: self }
}
- #[doc = "Bit 31 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." ] # [ inline ( always ) ]
pub fn i1(&mut self) -> _I1W {
_I1W { w: self }
}
@@ -93421,8 +89965,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." ] # [ inline ( always ) ]
pub fn crsr_img(&self) -> CRSR_IMGR {
let bits = {
const MASK: u32 = 4294967295;
@@ -93444,8 +89987,7 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." ] # [ inline ( always ) ]
pub fn crsr_img(&mut self) -> _CRSR_IMGW {
_CRSR_IMGW { w: self }
}
@@ -93587,8 +90129,7 @@ pub mod lcd {
};
CRSRONR { bits }
}
- #[doc = "Bits 4:5 - Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." ] # [ inline ( always ) ]
pub fn crsrnum1_0(&self) -> CRSRNUM1_0R {
let bits = {
const MASK: u8 = 3;
@@ -93615,8 +90156,7 @@ pub mod lcd {
pub fn crsr_on(&mut self) -> _CRSRONW {
_CRSRONW { w: self }
}
- #[doc = "Bits 4:5 - Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." ] # [ inline ( always ) ]
pub fn crsrnum1_0(&mut self) -> _CRSRNUM1_0W {
_CRSRNUM1_0W { w: self }
}
@@ -93766,8 +90306,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." ] # [ inline ( always ) ]
pub fn crsr_size(&self) -> CRSRSIZER {
let bits = {
const MASK: bool = true;
@@ -93776,8 +90315,7 @@ pub mod lcd {
};
CRSRSIZER { bits }
}
- #[doc = "Bit 1 - Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." ] # [ inline ( always ) ]
pub fn framesync(&self) -> FRAMESYNCR {
let bits = {
const MASK: bool = true;
@@ -93799,13 +90337,11 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." ] # [ inline ( always ) ]
pub fn crsr_size(&mut self) -> _CRSRSIZEW {
_CRSRSIZEW { w: self }
}
- #[doc = "Bit 1 - Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." ] # [ inline ( always ) ]
pub fn framesync(&mut self) -> _FRAMESYNCW {
_FRAMESYNCW { w: self }
}
@@ -94307,8 +90843,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:9 - X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display."]
- #[inline(always)]
+ # [ doc = "Bits 0:9 - X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." ] # [ inline ( always ) ]
pub fn crsrx(&self) -> CRSRXR {
let bits = {
const MASK: u16 = 1023;
@@ -94317,8 +90852,7 @@ pub mod lcd {
};
CRSRXR { bits }
}
- #[doc = "Bits 16:25 - Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display."]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." ] # [ inline ( always ) ]
pub fn crsry(&self) -> CRSRYR {
let bits = {
const MASK: u16 = 1023;
@@ -94340,13 +90874,11 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 0:9 - X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display."]
- #[inline(always)]
+ # [ doc = "Bits 0:9 - X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." ] # [ inline ( always ) ]
pub fn crsrx(&mut self) -> _CRSRXW {
_CRSRXW { w: self }
}
- #[doc = "Bits 16:25 - Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display."]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." ] # [ inline ( always ) ]
pub fn crsry(&mut self) -> _CRSRYW {
_CRSRYW { w: self }
}
@@ -94460,8 +90992,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." ] # [ inline ( always ) ]
pub fn crsrclipx(&self) -> CRSRCLIPXR {
let bits = {
const MASK: u8 = 63;
@@ -94470,8 +91001,7 @@ pub mod lcd {
};
CRSRCLIPXR { bits }
}
- #[doc = "Bits 8:13 - Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image."]
- #[inline(always)]
+ # [ doc = "Bits 8:13 - Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." ] # [ inline ( always ) ]
pub fn crsrclipy(&self) -> CRSRCLIPYR {
let bits = {
const MASK: u8 = 63;
@@ -94493,13 +91023,11 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." ] # [ inline ( always ) ]
pub fn crsrclipx(&mut self) -> _CRSRCLIPXW {
_CRSRCLIPXW { w: self }
}
- #[doc = "Bits 8:13 - Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image."]
- #[inline(always)]
+ # [ doc = "Bits 8:13 - Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." ] # [ inline ( always ) ]
pub fn crsrclipy(&mut self) -> _CRSRCLIPYW {
_CRSRCLIPYW { w: self }
}
@@ -94605,8 +91133,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." ] # [ inline ( always ) ]
pub fn crsrim(&self) -> CRSRIMR {
let bits = {
const MASK: bool = true;
@@ -94628,8 +91155,7 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." ] # [ inline ( always ) ]
pub fn crsrim(&mut self) -> _CRSRIMW {
_CRSRIMW { w: self }
}
@@ -94692,8 +91218,7 @@ pub mod lcd {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." ] # [ inline ( always ) ]
pub fn crsric(&mut self) -> _CRSRICW {
_CRSRICW { w: self }
}
@@ -94745,8 +91270,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." ] # [ inline ( always ) ]
pub fn crsrris(&self) -> CRSRRISR {
let bits = {
const MASK: bool = true;
@@ -94803,8 +91327,7 @@ pub mod lcd {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." ] # [ inline ( always ) ]
pub fn crsrmis(&self) -> CRSRMISR {
let bits = {
const MASK: bool = true;
@@ -94837,8 +91360,7 @@ pub mod eeprom {
#[doc = "0x00 - EEPROM command register"] pub cmd: CMD,
_reserved0: [u8; 4usize],
#[doc = "0x08 - EEPROM read wait state register"] pub rwstate: RWSTATE,
- #[doc = "0x0c - EEPROM auto programming register"]
- pub autoprog: AUTOPROG,
+ #[doc = "0x0c - EEPROM auto programming register"] pub autoprog: AUTOPROG,
#[doc = "0x10 - EEPROM wait state register"] pub wstate: WSTATE,
#[doc = "0x14 - EEPROM clock divider register"] pub clkdiv: CLKDIV,
#[doc = "0x18 - EEPROM power-down register"] pub pwrdwn: PWRDWN,
@@ -94847,8 +91369,7 @@ pub mod eeprom {
#[doc = "0xfdc - EEPROM interrupt enable set"] pub intenset: INTENSET,
#[doc = "0xfe0 - EEPROM interrupt status"] pub intstat: INTSTAT,
#[doc = "0xfe4 - EEPROM interrupt enable"] pub inten: INTEN,
- #[doc = "0xfe8 - EEPROM interrupt status clear"]
- pub intstatclr: INTSTATCLR,
+ #[doc = "0xfe8 - EEPROM interrupt status clear"] pub intstatclr: INTSTATCLR,
}
#[doc = "EEPROM command register"]
pub struct CMD {
@@ -94932,8 +91453,7 @@ pub mod eeprom {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:2 - Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." ] # [ inline ( always ) ]
pub fn cmd(&self) -> CMDR {
let bits = {
const MASK: u8 = 7;
@@ -94955,8 +91475,7 @@ pub mod eeprom {
self.bits = bits;
self
}
- #[doc = "Bits 0:2 - Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." ] # [ inline ( always ) ]
pub fn cmd(&mut self) -> _CMDW {
_CMDW { w: self }
}
@@ -95070,8 +91589,7 @@ pub mod eeprom {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." ] # [ inline ( always ) ]
pub fn rphase2(&self) -> RPHASE2R {
let bits = {
const MASK: u8 = 255;
@@ -95080,8 +91598,7 @@ pub mod eeprom {
};
RPHASE2R { bits }
}
- #[doc = "Bits 8:15 - Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." ] # [ inline ( always ) ]
pub fn rphase1(&self) -> RPHASE1R {
let bits = {
const MASK: u8 = 255;
@@ -95103,13 +91620,11 @@ pub mod eeprom {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." ] # [ inline ( always ) ]
pub fn rphase2(&mut self) -> _RPHASE2W {
_RPHASE2W { w: self }
}
- #[doc = "Bits 8:15 - Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." ] # [ inline ( always ) ]
pub fn rphase1(&mut self) -> _RPHASE1W {
_RPHASE1W { w: self }
}
@@ -95197,8 +91712,7 @@ pub mod eeprom {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with ......1111100 (last word of a page)"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with ......1111100 (last word of a page)" ] # [ inline ( always ) ]
pub fn autoprog(&self) -> AUTOPROGR {
let bits = {
const MASK: u8 = 3;
@@ -95220,8 +91734,7 @@ pub mod eeprom {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with ......1111100 (last word of a page)"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with ......1111100 (last word of a page)" ] # [ inline ( always ) ]
pub fn autoprog(&mut self) -> _AUTOPROGW {
_AUTOPROGW { w: self }
}
@@ -95405,8 +91918,7 @@ pub mod eeprom {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." ] # [ inline ( always ) ]
pub fn phase3(&self) -> PHASE3R {
let bits = {
const MASK: u8 = 255;
@@ -95415,8 +91927,7 @@ pub mod eeprom {
};
PHASE3R { bits }
}
- #[doc = "Bits 8:15 - Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." ] # [ inline ( always ) ]
pub fn phase2(&self) -> PHASE2R {
let bits = {
const MASK: u8 = 255;
@@ -95425,8 +91936,7 @@ pub mod eeprom {
};
PHASE2R { bits }
}
- #[doc = "Bits 16:23 - Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." ] # [ inline ( always ) ]
pub fn phase1(&self) -> PHASE1R {
let bits = {
const MASK: u8 = 255;
@@ -95435,8 +91945,7 @@ pub mod eeprom {
};
PHASE1R { bits }
}
- #[doc = "Bit 31 - Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access"]
- #[inline(always)]
+ # [ doc = "Bit 31 - Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access" ] # [ inline ( always ) ]
pub fn lck_parwep(&self) -> LCK_PARWEPR {
let bits = {
const MASK: bool = true;
@@ -95458,23 +91967,19 @@ pub mod eeprom {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." ] # [ inline ( always ) ]
pub fn phase3(&mut self) -> _PHASE3W {
_PHASE3W { w: self }
}
- #[doc = "Bits 8:15 - Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." ] # [ inline ( always ) ]
pub fn phase2(&mut self) -> _PHASE2W {
_PHASE2W { w: self }
}
- #[doc = "Bits 16:23 - Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1."]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." ] # [ inline ( always ) ]
pub fn phase1(&mut self) -> _PHASE1W {
_PHASE1W { w: self }
}
- #[doc = "Bit 31 - Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access"]
- #[inline(always)]
+ # [ doc = "Bit 31 - Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access" ] # [ inline ( always ) ]
pub fn lck_parwep(&mut self) -> _LCK_PARWEPW {
_LCK_PARWEPW { w: self }
}
@@ -95779,8 +92284,7 @@ pub mod eeprom {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." ] # [ inline ( always ) ]
pub fn prog_clr_en(&mut self) -> _PROG_CLR_ENW {
_PROG_CLR_ENW { w: self }
}
@@ -95843,8 +92347,7 @@ pub mod eeprom {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." ] # [ inline ( always ) ]
pub fn prog_set_en(&mut self) -> _PROG_SET_ENW {
_PROG_SET_ENW { w: self }
}
@@ -95896,8 +92399,7 @@ pub mod eeprom {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." ] # [ inline ( always ) ]
pub fn end_of_prog(&self) -> END_OF_PROGR {
let bits = {
const MASK: bool = true;
@@ -95954,8 +92456,7 @@ pub mod eeprom {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." ] # [ inline ( always ) ]
pub fn ee_prog_done(&self) -> EE_PROG_DONER {
let bits = {
const MASK: bool = true;
@@ -96023,8 +92524,7 @@ pub mod eeprom {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." ] # [ inline ( always ) ]
pub fn prog_clr_st(&mut self) -> _PROG_CLR_STW {
_PROG_CLR_STW { w: self }
}
@@ -96042,8 +92542,7 @@ impl Deref for EEPROM {
}
}
#[doc = "Ethernet"]
-pub const ETHERNET: Peripheral<ETHERNET> =
- unsafe { Peripheral::new(1073807360) };
+pub const ETHERNET: Peripheral<ETHERNET> = unsafe { Peripheral::new(1073807360) };
#[doc = "Ethernet"]
pub mod ethernet {
use vcell::VolatileCell;
@@ -96051,52 +92550,36 @@ pub mod ethernet {
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - MAC configuration register"] pub mac_config: MAC_CONFIG,
- #[doc = "0x04 - MAC frame filter"]
- pub mac_frame_filter: MAC_FRAME_FILTER,
- #[doc = "0x08 - Hash table high register"]
- pub mac_hashtable_high: MAC_HASHTABLE_HIGH,
- #[doc = "0x0c - Hash table low register"]
- pub mac_hashtable_low: MAC_HASHTABLE_LOW,
+ #[doc = "0x04 - MAC frame filter"] pub mac_frame_filter: MAC_FRAME_FILTER,
+ #[doc = "0x08 - Hash table high register"] pub mac_hashtable_high: MAC_HASHTABLE_HIGH,
+ #[doc = "0x0c - Hash table low register"] pub mac_hashtable_low: MAC_HASHTABLE_LOW,
#[doc = "0x10 - MII address register"] pub mac_mii_addr: MAC_MII_ADDR,
#[doc = "0x14 - MII data register"] pub mac_mii_data: MAC_MII_DATA,
- #[doc = "0x18 - Flow control register"]
- pub mac_flow_ctrl: MAC_FLOW_CTRL,
+ #[doc = "0x18 - Flow control register"] pub mac_flow_ctrl: MAC_FLOW_CTRL,
#[doc = "0x1c - VLAN tag register"] pub mac_vlan_tag: MAC_VLAN_TAG,
_reserved0: [u8; 4usize],
#[doc = "0x24 - Debug register"] pub mac_debug: MAC_DEBUG,
- #[doc = "0x28 - Remote wake-up frame filter"]
- pub mac_rwake_frflt: MAC_RWAKE_FRFLT,
- #[doc = "0x2c - PMT control and status"]
- pub mac_pmt_ctrl_stat: MAC_PMT_CTRL_STAT,
+ #[doc = "0x28 - Remote wake-up frame filter"] pub mac_rwake_frflt: MAC_RWAKE_FRFLT,
+ #[doc = "0x2c - PMT control and status"] pub mac_pmt_ctrl_stat: MAC_PMT_CTRL_STAT,
_reserved1: [u8; 8usize],
#[doc = "0x38 - Interrupt status register"] pub mac_intr: MAC_INTR,
- #[doc = "0x3c - Interrupt mask register"]
- pub mac_intr_mask: MAC_INTR_MASK,
- #[doc = "0x40 - MAC address 0 high register"]
- pub mac_addr0_high: MAC_ADDR0_HIGH,
- #[doc = "0x44 - MAC address 0 low register"]
- pub mac_addr0_low: MAC_ADDR0_LOW,
+ #[doc = "0x3c - Interrupt mask register"] pub mac_intr_mask: MAC_INTR_MASK,
+ #[doc = "0x40 - MAC address 0 high register"] pub mac_addr0_high: MAC_ADDR0_HIGH,
+ #[doc = "0x44 - MAC address 0 low register"] pub mac_addr0_low: MAC_ADDR0_LOW,
_reserved2: [u8; 1720usize],
- #[doc = "0x700 - Time stamp control register"]
- pub mac_timestp_ctrl: MAC_TIMESTP_CTRL,
- #[doc = "0x704 - Sub-second increment register"]
- pub subsecond_incr: SUBSECOND_INCR,
+ #[doc = "0x700 - Time stamp control register"] pub mac_timestp_ctrl: MAC_TIMESTP_CTRL,
+ #[doc = "0x704 - Sub-second increment register"] pub subsecond_incr: SUBSECOND_INCR,
#[doc = "0x708 - System time seconds register"] pub seconds: SECONDS,
- #[doc = "0x70c - System time nanoseconds register"]
- pub nanoseconds: NANOSECONDS,
- #[doc = "0x710 - System time seconds update register"]
- pub secondsupdate: SECONDSUPDATE,
+ #[doc = "0x70c - System time nanoseconds register"] pub nanoseconds: NANOSECONDS,
+ #[doc = "0x710 - System time seconds update register"] pub secondsupdate: SECONDSUPDATE,
#[doc = "0x714 - System time nanoseconds update register"]
pub nanosecondsupdate: NANOSECONDSUPDATE,
#[doc = "0x718 - Time stamp addend register"] pub addend: ADDEND,
- #[doc = "0x71c - Target time seconds register"]
- pub targetseconds: TARGETSECONDS,
+ #[doc = "0x71c - Target time seconds register"] pub targetseconds: TARGETSECONDS,
#[doc = "0x720 - Target time nanoseconds register"]
pub targetnanoseconds: TARGETNANOSECONDS,
- #[doc = "0x724 - System time higher word seconds register"]
- pub highword: HIGHWORD,
- #[doc = "0x728 - Time stamp status register"]
- pub timestampstat: TIMESTAMPSTAT,
+ #[doc = "0x724 - System time higher word seconds register"] pub highword: HIGHWORD,
+ #[doc = "0x728 - Time stamp status register"] pub timestampstat: TIMESTAMPSTAT,
_reserved3: [u8; 2260usize],
#[doc = "0x1000 - Bus Mode Register"] pub dma_bus_mode: DMA_BUS_MODE,
#[doc = "0x1004 - Transmit poll demand register"]
@@ -96108,10 +92591,8 @@ pub mod ethernet {
#[doc = "0x1010 - Transmit descriptor list address register"]
pub dma_trans_des_addr: DMA_TRANS_DES_ADDR,
#[doc = "0x1014 - Status register"] pub dma_stat: DMA_STAT,
- #[doc = "0x1018 - Operation mode register"]
- pub dma_op_mode: DMA_OP_MODE,
- #[doc = "0x101c - Interrupt enable register"]
- pub dma_int_en: DMA_INT_EN,
+ #[doc = "0x1018 - Operation mode register"] pub dma_op_mode: DMA_OP_MODE,
+ #[doc = "0x101c - Interrupt enable register"] pub dma_int_en: DMA_INT_EN,
#[doc = "0x1020 - Missed frame and buffer overflow register"]
pub dma_mfrm_bufof: DMA_MFRM_BUFOF,
#[doc = "0x1024 - Receive interrupt watchdog timer register"]
@@ -96850,8 +93331,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." ] # [ inline ( always ) ]
pub fn re(&self) -> RER {
let bits = {
const MASK: bool = true;
@@ -96860,8 +93340,7 @@ pub mod ethernet {
};
RER { bits }
}
- #[doc = "Bit 3 - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." ] # [ inline ( always ) ]
pub fn te(&self) -> TER {
let bits = {
const MASK: bool = true;
@@ -96870,8 +93349,7 @@ pub mod ethernet {
};
TER { bits }
}
- #[doc = "Bit 4 - Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." ] # [ inline ( always ) ]
pub fn df(&self) -> DFR {
let bits = {
const MASK: bool = true;
@@ -96880,8 +93358,7 @@ pub mod ethernet {
};
DFR { bits }
}
- #[doc = "Bits 5:6 - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 00: k = min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 <= r <= 2k."]
- #[inline(always)]
+ # [ doc = "Bits 5:6 - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 00: k = min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 <= r <= 2k." ] # [ inline ( always ) ]
pub fn bl(&self) -> BLR {
let bits = {
const MASK: u8 = 3;
@@ -96890,8 +93367,7 @@ pub mod ethernet {
};
BLR { bits }
}
- #[doc = "Bit 7 - Automatic Pad/CRC Stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field. When this bit is reset, the MAC will pass all incoming frames to the Host unmodified."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Automatic Pad/CRC Stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field. When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." ] # [ inline ( always ) ]
pub fn acs(&self) -> ACSR {
let bits = {
const MASK: bool = true;
@@ -96900,8 +93376,7 @@ pub mod ethernet {
};
ACSR { bits }
}
- #[doc = "Bit 9 - Disable Retry When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Disable Retry When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." ] # [ inline ( always ) ]
pub fn dr(&self) -> DRR {
let bits = {
const MASK: bool = true;
@@ -96910,8 +93385,7 @@ pub mod ethernet {
};
DRR { bits }
}
- #[doc = "Bit 11 - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." ] # [ inline ( always ) ]
pub fn dm(&self) -> DMR {
let bits = {
const MASK: bool = true;
@@ -96920,8 +93394,7 @@ pub mod ethernet {
};
DMR { bits }
}
- #[doc = "Bit 12 - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." ] # [ inline ( always ) ]
pub fn lm(&self) -> LMR {
let bits = {
const MASK: bool = true;
@@ -96930,8 +93403,7 @@ pub mod ethernet {
};
LMR { bits }
}
- #[doc = "Bit 13 - Disable Receive Own When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in Full-Duplex mode."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Disable Receive Own When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in Full-Duplex mode." ] # [ inline ( always ) ]
pub fn do_(&self) -> DOR {
let bits = {
const MASK: bool = true;
@@ -96940,8 +93412,7 @@ pub mod ethernet {
};
DOR { bits }
}
- #[doc = "Bit 14 - Speed Indicates the speed in Fast Ethernet (MII) mode: 0 = 10 Mbps 1 = 100 Mbps"]
- #[inline(always)]
+ # [ doc = "Bit 14 - Speed Indicates the speed in Fast Ethernet (MII) mode: 0 = 10 Mbps 1 = 100 Mbps" ] # [ inline ( always ) ]
pub fn fes(&self) -> FESR {
let bits = {
const MASK: bool = true;
@@ -96960,8 +93431,7 @@ pub mod ethernet {
};
PSR { bits }
}
- #[doc = "Bit 16 - Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." ] # [ inline ( always ) ]
pub fn dcrs(&self) -> DCRSR {
let bits = {
const MASK: bool = true;
@@ -96970,8 +93440,7 @@ pub mod ethernet {
};
DCRSR { bits }
}
- #[doc = "Bits 17:19 - Inter-frame gap These bits control the minimum IFG between frames during transmission. 000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered"]
- #[inline(always)]
+ # [ doc = "Bits 17:19 - Inter-frame gap These bits control the minimum IFG between frames during transmission. 000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" ] # [ inline ( always ) ]
pub fn ifg(&self) -> IFGR {
let bits = {
const MASK: u8 = 7;
@@ -96980,8 +93449,7 @@ pub mod ethernet {
};
IFGR { bits }
}
- #[doc = "Bit 20 - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." ] # [ inline ( always ) ]
pub fn je(&self) -> JER {
let bits = {
const MASK: bool = true;
@@ -96990,8 +93458,7 @@ pub mod ethernet {
};
JER { bits }
}
- #[doc = "Bit 22 - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." ] # [ inline ( always ) ]
pub fn jd(&self) -> JDR {
let bits = {
const MASK: bool = true;
@@ -97000,8 +93467,7 @@ pub mod ethernet {
};
JDR { bits }
}
- #[doc = "Bit 23 - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." ] # [ inline ( always ) ]
pub fn wd(&self) -> WDR {
let bits = {
const MASK: bool = true;
@@ -97023,53 +93489,43 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." ] # [ inline ( always ) ]
pub fn re(&mut self) -> _REW {
_REW { w: self }
}
- #[doc = "Bit 3 - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." ] # [ inline ( always ) ]
pub fn te(&mut self) -> _TEW {
_TEW { w: self }
}
- #[doc = "Bit 4 - Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." ] # [ inline ( always ) ]
pub fn df(&mut self) -> _DFW {
_DFW { w: self }
}
- #[doc = "Bits 5:6 - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 00: k = min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 <= r <= 2k."]
- #[inline(always)]
+ # [ doc = "Bits 5:6 - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 00: k = min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 <= r <= 2k." ] # [ inline ( always ) ]
pub fn bl(&mut self) -> _BLW {
_BLW { w: self }
}
- #[doc = "Bit 7 - Automatic Pad/CRC Stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field. When this bit is reset, the MAC will pass all incoming frames to the Host unmodified."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Automatic Pad/CRC Stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field. When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." ] # [ inline ( always ) ]
pub fn acs(&mut self) -> _ACSW {
_ACSW { w: self }
}
- #[doc = "Bit 9 - Disable Retry When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Disable Retry When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." ] # [ inline ( always ) ]
pub fn dr(&mut self) -> _DRW {
_DRW { w: self }
}
- #[doc = "Bit 11 - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." ] # [ inline ( always ) ]
pub fn dm(&mut self) -> _DMW {
_DMW { w: self }
}
- #[doc = "Bit 12 - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." ] # [ inline ( always ) ]
pub fn lm(&mut self) -> _LMW {
_LMW { w: self }
}
- #[doc = "Bit 13 - Disable Receive Own When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in Full-Duplex mode."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Disable Receive Own When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in Full-Duplex mode." ] # [ inline ( always ) ]
pub fn do_(&mut self) -> _DOW {
_DOW { w: self }
}
- #[doc = "Bit 14 - Speed Indicates the speed in Fast Ethernet (MII) mode: 0 = 10 Mbps 1 = 100 Mbps"]
- #[inline(always)]
+ # [ doc = "Bit 14 - Speed Indicates the speed in Fast Ethernet (MII) mode: 0 = 10 Mbps 1 = 100 Mbps" ] # [ inline ( always ) ]
pub fn fes(&mut self) -> _FESW {
_FESW { w: self }
}
@@ -97078,28 +93534,23 @@ pub mod ethernet {
pub fn ps(&mut self) -> _PSW {
_PSW { w: self }
}
- #[doc = "Bit 16 - Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." ] # [ inline ( always ) ]
pub fn dcrs(&mut self) -> _DCRSW {
_DCRSW { w: self }
}
- #[doc = "Bits 17:19 - Inter-frame gap These bits control the minimum IFG between frames during transmission. 000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered"]
- #[inline(always)]
+ # [ doc = "Bits 17:19 - Inter-frame gap These bits control the minimum IFG between frames during transmission. 000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" ] # [ inline ( always ) ]
pub fn ifg(&mut self) -> _IFGW {
_IFGW { w: self }
}
- #[doc = "Bit 20 - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." ] # [ inline ( always ) ]
pub fn je(&mut self) -> _JEW {
_JEW { w: self }
}
- #[doc = "Bit 22 - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." ] # [ inline ( always ) ]
pub fn jd(&mut self) -> _JDW {
_JDW { w: self }
}
- #[doc = "Bit 23 - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." ] # [ inline ( always ) ]
pub fn wd(&mut self) -> _WDW {
_WDW { w: self }
}
@@ -97539,8 +93990,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." ] # [ inline ( always ) ]
pub fn pr(&self) -> PRR {
let bits = {
const MASK: bool = true;
@@ -97549,8 +93999,7 @@ pub mod ethernet {
};
PRR { bits }
}
- #[doc = "Bit 1 - Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." ] # [ inline ( always ) ]
pub fn huc(&self) -> HUCR {
let bits = {
const MASK: bool = true;
@@ -97559,8 +94008,7 @@ pub mod ethernet {
};
HUCR { bits }
}
- #[doc = "Bit 2 - Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." ] # [ inline ( always ) ]
pub fn hmc(&self) -> HMCR {
let bits = {
const MASK: bool = true;
@@ -97569,8 +94017,7 @@ pub mod ethernet {
};
HMCR { bits }
}
- #[doc = "Bit 3 - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed."]
- #[inline(always)]
+ # [ doc = "Bit 3 - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed." ] # [ inline ( always ) ]
pub fn daif(&self) -> DAIFR {
let bits = {
const MASK: bool = true;
@@ -97579,8 +94026,7 @@ pub mod ethernet {
};
DAIFR { bits }
}
- #[doc = "Bit 4 - Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit." ] # [ inline ( always ) ]
pub fn pm(&self) -> PMR {
let bits = {
const MASK: bool = true;
@@ -97589,8 +94035,7 @@ pub mod ethernet {
};
PMR { bits }
}
- #[doc = "Bit 5 - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. When this bit is reset, the AFM module passes all received broadcast frames."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. When this bit is reset, the AFM module passes all received broadcast frames." ] # [ inline ( always ) ]
pub fn dbf(&self) -> DBFR {
let bits = {
const MASK: bool = true;
@@ -97599,8 +94044,7 @@ pub mod ethernet {
};
DBFR { bits }
}
- #[doc = "Bits 6:7 - Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register. 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register. 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter." ] # [ inline ( always ) ]
pub fn pcf(&self) -> PCFR {
let bits = {
const MASK: u8 = 3;
@@ -97609,8 +94053,7 @@ pub mod ethernet {
};
PCFR { bits }
}
- #[doc = "Bit 10 - Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." ] # [ inline ( always ) ]
pub fn hpf(&self) -> HPFR {
let bits = {
const MASK: bool = true;
@@ -97619,8 +94062,7 @@ pub mod ethernet {
};
HPFR { bits }
}
- #[doc = "Bit 31 - Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." ] # [ inline ( always ) ]
pub fn ra(&self) -> RAR {
let bits = {
const MASK: bool = true;
@@ -97642,48 +94084,39 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." ] # [ inline ( always ) ]
pub fn pr(&mut self) -> _PRW {
_PRW { w: self }
}
- #[doc = "Bit 1 - Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." ] # [ inline ( always ) ]
pub fn huc(&mut self) -> _HUCW {
_HUCW { w: self }
}
- #[doc = "Bit 2 - Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." ] # [ inline ( always ) ]
pub fn hmc(&mut self) -> _HMCW {
_HMCW { w: self }
}
- #[doc = "Bit 3 - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed."]
- #[inline(always)]
+ # [ doc = "Bit 3 - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed." ] # [ inline ( always ) ]
pub fn daif(&mut self) -> _DAIFW {
_DAIFW { w: self }
}
- #[doc = "Bit 4 - Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit." ] # [ inline ( always ) ]
pub fn pm(&mut self) -> _PMW {
_PMW { w: self }
}
- #[doc = "Bit 5 - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. When this bit is reset, the AFM module passes all received broadcast frames."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. When this bit is reset, the AFM module passes all received broadcast frames." ] # [ inline ( always ) ]
pub fn dbf(&mut self) -> _DBFW {
_DBFW { w: self }
}
- #[doc = "Bits 6:7 - Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register. 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register. 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter." ] # [ inline ( always ) ]
pub fn pcf(&mut self) -> _PCFW {
_PCFW { w: self }
}
- #[doc = "Bit 10 - Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." ] # [ inline ( always ) ]
pub fn hpf(&mut self) -> _HPFW {
_HPFW { w: self }
}
- #[doc = "Bit 31 - Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." ] # [ inline ( always ) ]
pub fn ra(&mut self) -> _RAW {
_RAW { w: self }
}
@@ -97771,8 +94204,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Hash table high This field contains the upper 32 bits of Hash table."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Hash table high This field contains the upper 32 bits of Hash table." ] # [ inline ( always ) ]
pub fn hth(&self) -> HTHR {
let bits = {
const MASK: u32 = 4294967295;
@@ -97794,8 +94226,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Hash table high This field contains the upper 32 bits of Hash table."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Hash table high This field contains the upper 32 bits of Hash table." ] # [ inline ( always ) ]
pub fn hth(&mut self) -> _HTHW {
_HTHW { w: self }
}
@@ -97883,8 +94314,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Hash table low This field contains the upper 32 bits of Hash table."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Hash table low This field contains the upper 32 bits of Hash table." ] # [ inline ( always ) ]
pub fn htl(&self) -> HTLR {
let bits = {
const MASK: u32 = 4294967295;
@@ -97906,8 +94336,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Hash table low This field contains the upper 32 bits of Hash table."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Hash table low This field contains the upper 32 bits of Hash table." ] # [ inline ( always ) ]
pub fn htl(&mut self) -> _HTLW {
_HTLW { w: self }
}
@@ -98135,8 +94564,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 0 - MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." ] # [ inline ( always ) ]
pub fn gb(&self) -> GBR {
let bits = {
const MASK: bool = true;
@@ -98145,8 +94573,7 @@ pub mod ethernet {
};
GBR { bits }
}
- #[doc = "Bit 1 - MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." ] # [ inline ( always ) ]
pub fn w(&self) -> WR {
let bits = {
const MASK: bool = true;
@@ -98155,8 +94582,7 @@ pub mod ethernet {
};
WR { bits }
}
- #[doc = "Bits 2:5 - CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values."]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values." ] # [ inline ( always ) ]
pub fn cr(&self) -> CRR {
let bits = {
const MASK: u8 = 15;
@@ -98165,8 +94591,7 @@ pub mod ethernet {
};
CRR { bits }
}
- #[doc = "Bits 6:10 - MII register These bits select the desired MII register in the selected PHY device."]
- #[inline(always)]
+ # [ doc = "Bits 6:10 - MII register These bits select the desired MII register in the selected PHY device." ] # [ inline ( always ) ]
pub fn gr(&self) -> GRR {
let bits = {
const MASK: u8 = 31;
@@ -98175,8 +94600,7 @@ pub mod ethernet {
};
GRR { bits }
}
- #[doc = "Bits 11:15 - Physical layer address This field tells which of the 32 possible PHY devices are being accessed."]
- #[inline(always)]
+ # [ doc = "Bits 11:15 - Physical layer address This field tells which of the 32 possible PHY devices are being accessed." ] # [ inline ( always ) ]
pub fn pa(&self) -> PAR {
let bits = {
const MASK: u8 = 31;
@@ -98198,28 +94622,23 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 0 - MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." ] # [ inline ( always ) ]
pub fn gb(&mut self) -> _GBW {
_GBW { w: self }
}
- #[doc = "Bit 1 - MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." ] # [ inline ( always ) ]
pub fn w(&mut self) -> _WW {
_WW { w: self }
}
- #[doc = "Bits 2:5 - CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values."]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values." ] # [ inline ( always ) ]
pub fn cr(&mut self) -> _CRW {
_CRW { w: self }
}
- #[doc = "Bits 6:10 - MII register These bits select the desired MII register in the selected PHY device."]
- #[inline(always)]
+ # [ doc = "Bits 6:10 - MII register These bits select the desired MII register in the selected PHY device." ] # [ inline ( always ) ]
pub fn gr(&mut self) -> _GRW {
_GRW { w: self }
}
- #[doc = "Bits 11:15 - Physical layer address This field tells which of the 32 possible PHY devices are being accessed."]
- #[inline(always)]
+ # [ doc = "Bits 11:15 - Physical layer address This field tells which of the 32 possible PHY devices are being accessed." ] # [ inline ( always ) ]
pub fn pa(&mut self) -> _PAW {
_PAW { w: self }
}
@@ -98307,8 +94726,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." ] # [ inline ( always ) ]
pub fn gd(&self) -> GDR {
let bits = {
const MASK: u16 = 65535;
@@ -98330,8 +94748,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." ] # [ inline ( always ) ]
pub fn gd(&mut self) -> _GDW {
_GDW { w: self }
}
@@ -98665,8 +95082,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." ] # [ inline ( always ) ]
pub fn fcb(&self) -> FCBR {
let bits = {
const MASK: bool = true;
@@ -98675,8 +95091,7 @@ pub mod ethernet {
};
FCBR { bits }
}
- #[doc = "Bit 1 - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." ] # [ inline ( always ) ]
pub fn tfe(&self) -> TFER {
let bits = {
const MASK: bool = true;
@@ -98685,8 +95100,7 @@ pub mod ethernet {
};
TFER { bits }
}
- #[doc = "Bit 2 - Receive Flow Control Enable When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Receive Flow Control Enable When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." ] # [ inline ( always ) ]
pub fn rfe(&self) -> RFER {
let bits = {
const MASK: bool = true;
@@ -98695,8 +95109,7 @@ pub mod ethernet {
};
RFER { bits }
}
- #[doc = "Bit 3 - Unicast Pause Frame Detect When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Unicast Pause Frame Detect When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." ] # [ inline ( always ) ]
pub fn up(&self) -> UPR {
let bits = {
const MASK: bool = true;
@@ -98705,8 +95118,7 @@ pub mod ethernet {
};
UPR { bits }
}
- #[doc = "Bits 4:5 - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." ] # [ inline ( always ) ]
pub fn plt(&self) -> PLTR {
let bits = {
const MASK: u8 = 3;
@@ -98715,8 +95127,7 @@ pub mod ethernet {
};
PLTR { bits }
}
- #[doc = "Bit 7 - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." ] # [ inline ( always ) ]
pub fn dzpq(&self) -> DZPQR {
let bits = {
const MASK: bool = true;
@@ -98725,8 +95136,7 @@ pub mod ethernet {
};
DZPQR { bits }
}
- #[doc = "Bits 16:31 - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." ] # [ inline ( always ) ]
pub fn pt(&self) -> PTR {
let bits = {
const MASK: u16 = 65535;
@@ -98748,38 +95158,31 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." ] # [ inline ( always ) ]
pub fn fcb(&mut self) -> _FCBW {
_FCBW { w: self }
}
- #[doc = "Bit 1 - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." ] # [ inline ( always ) ]
pub fn tfe(&mut self) -> _TFEW {
_TFEW { w: self }
}
- #[doc = "Bit 2 - Receive Flow Control Enable When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Receive Flow Control Enable When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." ] # [ inline ( always ) ]
pub fn rfe(&mut self) -> _RFEW {
_RFEW { w: self }
}
- #[doc = "Bit 3 - Unicast Pause Frame Detect When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Unicast Pause Frame Detect When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." ] # [ inline ( always ) ]
pub fn up(&mut self) -> _UPW {
_UPW { w: self }
}
- #[doc = "Bits 4:5 - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." ] # [ inline ( always ) ]
pub fn plt(&mut self) -> _PLTW {
_PLTW { w: self }
}
- #[doc = "Bit 7 - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." ] # [ inline ( always ) ]
pub fn dzpq(&mut self) -> _DZPQW {
_DZPQW { w: self }
}
- #[doc = "Bits 16:31 - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain."]
- #[inline(always)]
+ # [ doc = "Bits 16:31 - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." ] # [ inline ( always ) ]
pub fn pt(&mut self) -> _PTW {
_PTW { w: self }
}
@@ -98911,8 +95314,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - VLAN Tag Identifier for Receive Frames This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - VLAN Tag Identifier for Receive Frames This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." ] # [ inline ( always ) ]
pub fn vl(&self) -> VLR {
let bits = {
const MASK: u16 = 65535;
@@ -98921,8 +95323,7 @@ pub mod ethernet {
};
VLR { bits }
}
- #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." ] # [ inline ( always ) ]
pub fn etv(&self) -> ETVR {
let bits = {
const MASK: bool = true;
@@ -98944,13 +95345,11 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - VLAN Tag Identifier for Receive Frames This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - VLAN Tag Identifier for Receive Frames This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." ] # [ inline ( always ) ]
pub fn vl(&mut self) -> _VLW {
_VLW { w: self }
}
- #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." ] # [ inline ( always ) ]
pub fn etv(&mut self) -> _ETVW {
_ETVW { w: self }
}
@@ -99183,8 +95582,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state."]
- #[inline(always)]
+ # [ doc = "Bit 0 - When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." ] # [ inline ( always ) ]
pub fn rxidlestat(&self) -> RXIDLESTATR {
let bits = {
const MASK: bool = true;
@@ -99193,8 +95591,7 @@ pub mod ethernet {
};
RXIDLESTATR { bits }
}
- #[doc = "Bits 1:2 - When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module."]
- #[inline(always)]
+ # [ doc = "Bits 1:2 - When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." ] # [ inline ( always ) ]
pub fn fifostat0(&self) -> FIFOSTAT0R {
let bits = {
const MASK: u8 = 3;
@@ -99203,8 +95600,7 @@ pub mod ethernet {
};
FIFOSTAT0R { bits }
}
- #[doc = "Bit 4 - When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 4 - When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." ] # [ inline ( always ) ]
pub fn rxfifostat1(&self) -> RXFIFOSTAT1R {
let bits = {
const MASK: bool = true;
@@ -99213,8 +95609,7 @@ pub mod ethernet {
};
RXFIFOSTAT1R { bits }
}
- #[doc = "Bits 5:6 - State of the RxFIFO read Controller: 00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status"]
- #[inline(always)]
+ # [ doc = "Bits 5:6 - State of the RxFIFO read Controller: 00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" ] # [ inline ( always ) ]
pub fn rxfifostat(&self) -> RXFIFOSTATR {
let bits = {
const MASK: u8 = 3;
@@ -99223,8 +95618,7 @@ pub mod ethernet {
};
RXFIFOSTATR { bits }
}
- #[doc = "Bits 8:9 - Status of the RxFIFO Fill-level 00 = RxFIFO Empty 01 = RxFIFO fill-level below flow-control de-activate threshold 10 = RxFIFO fill-level above flow-control activate threshold 11 = RxFIFO Full"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the RxFIFO Fill-level 00 = RxFIFO Empty 01 = RxFIFO fill-level below flow-control de-activate threshold 10 = RxFIFO fill-level above flow-control activate threshold 11 = RxFIFO Full" ] # [ inline ( always ) ]
pub fn rxfifolvl(&self) -> RXFIFOLVLR {
let bits = {
const MASK: u8 = 3;
@@ -99233,8 +95627,7 @@ pub mod ethernet {
};
RXFIFOLVLR { bits }
}
- #[doc = "Bit 16 - When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state."]
- #[inline(always)]
+ # [ doc = "Bit 16 - When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." ] # [ inline ( always ) ]
pub fn txidlestat(&self) -> TXIDLESTATR {
let bits = {
const MASK: bool = true;
@@ -99243,8 +95636,7 @@ pub mod ethernet {
};
TXIDLESTATR { bits }
}
- #[doc = "Bits 17:18 - State of the MAC Transmit Frame Controller module: 00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over 10 = Generating and transmitting a PAUSE control frame (in full duplex mode) 11 = Transferring input frame for transmission"]
- #[inline(always)]
+ # [ doc = "Bits 17:18 - State of the MAC Transmit Frame Controller module: 00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over 10 = Generating and transmitting a PAUSE control frame (in full duplex mode) 11 = Transferring input frame for transmission" ] # [ inline ( always ) ]
pub fn txstat(&self) -> TXSTATR {
let bits = {
const MASK: u8 = 3;
@@ -99253,8 +95645,7 @@ pub mod ethernet {
};
TXSTATR { bits }
}
- #[doc = "Bit 19 - When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission."]
- #[inline(always)]
+ # [ doc = "Bit 19 - When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." ] # [ inline ( always ) ]
pub fn pause(&self) -> PAUSER {
let bits = {
const MASK: bool = true;
@@ -99263,8 +95654,7 @@ pub mod ethernet {
};
PAUSER { bits }
}
- #[doc = "Bits 20:21 - State of the TxFIFO read Controller 00 = idle state 01 = READ state (transferring data to MAC transmitter) 10 = Waiting for TxStatus from MAC transmitter 11 = Writing the received TxStatus or flushing the TxFIFO"]
- #[inline(always)]
+ # [ doc = "Bits 20:21 - State of the TxFIFO read Controller 00 = idle state 01 = READ state (transferring data to MAC transmitter) 10 = Waiting for TxStatus from MAC transmitter 11 = Writing the received TxStatus or flushing the TxFIFO" ] # [ inline ( always ) ]
pub fn txfifostat(&self) -> TXFIFOSTATR {
let bits = {
const MASK: u8 = 3;
@@ -99273,8 +95663,7 @@ pub mod ethernet {
};
TXFIFOSTATR { bits }
}
- #[doc = "Bit 22 - When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO."]
- #[inline(always)]
+ # [ doc = "Bit 22 - When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." ] # [ inline ( always ) ]
pub fn txfifostat1(&self) -> TXFIFOSTAT1R {
let bits = {
const MASK: bool = true;
@@ -99283,8 +95672,7 @@ pub mod ethernet {
};
TXFIFOSTAT1R { bits }
}
- #[doc = "Bit 24 - When high, it indicates that the TxFIFO is not empty and has some data left for transmission."]
- #[inline(always)]
+ # [ doc = "Bit 24 - When high, it indicates that the TxFIFO is not empty and has some data left for transmission." ] # [ inline ( always ) ]
pub fn txfifolvl(&self) -> TXFIFOLVLR {
let bits = {
const MASK: bool = true;
@@ -99293,8 +95681,7 @@ pub mod ethernet {
};
TXFIFOLVLR { bits }
}
- #[doc = "Bit 25 - When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission."]
- #[inline(always)]
+ # [ doc = "Bit 25 - When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." ] # [ inline ( always ) ]
pub fn txfifofull(&self) -> TXFIFOFULLR {
let bits = {
const MASK: bool = true;
@@ -99781,8 +96168,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." ] # [ inline ( always ) ]
pub fn pd(&self) -> PDR {
let bits = {
const MASK: bool = true;
@@ -99791,8 +96177,7 @@ pub mod ethernet {
};
PDR { bits }
}
- #[doc = "Bit 1 - Magic packet enable When set, enables generation of a power management event due to Magic Packet reception."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." ] # [ inline ( always ) ]
pub fn mpe(&self) -> MPER {
let bits = {
const MASK: bool = true;
@@ -99801,8 +96186,7 @@ pub mod ethernet {
};
MPER { bits }
}
- #[doc = "Bit 2 - Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." ] # [ inline ( always ) ]
pub fn wfe(&self) -> WFER {
let bits = {
const MASK: bool = true;
@@ -99811,8 +96195,7 @@ pub mod ethernet {
};
WFER { bits }
}
- #[doc = "Bit 5 - Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." ] # [ inline ( always ) ]
pub fn mpr(&self) -> MPRR {
let bits = {
const MASK: bool = true;
@@ -99821,8 +96204,7 @@ pub mod ethernet {
};
MPRR { bits }
}
- #[doc = "Bit 6 - Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." ] # [ inline ( always ) ]
pub fn wfr(&self) -> WFRR {
let bits = {
const MASK: bool = true;
@@ -99831,8 +96213,7 @@ pub mod ethernet {
};
WFRR { bits }
}
- #[doc = "Bit 9 - Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." ] # [ inline ( always ) ]
pub fn gu(&self) -> GUR {
let bits = {
const MASK: bool = true;
@@ -99841,8 +96222,7 @@ pub mod ethernet {
};
GUR { bits }
}
- #[doc = "Bit 31 - Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." ] # [ inline ( always ) ]
pub fn wffrpr(&self) -> WFFRPRR {
let bits = {
const MASK: bool = true;
@@ -99864,38 +96244,31 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." ] # [ inline ( always ) ]
pub fn pd(&mut self) -> _PDW {
_PDW { w: self }
}
- #[doc = "Bit 1 - Magic packet enable When set, enables generation of a power management event due to Magic Packet reception."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." ] # [ inline ( always ) ]
pub fn mpe(&mut self) -> _MPEW {
_MPEW { w: self }
}
- #[doc = "Bit 2 - Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." ] # [ inline ( always ) ]
pub fn wfe(&mut self) -> _WFEW {
_WFEW { w: self }
}
- #[doc = "Bit 5 - Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." ] # [ inline ( always ) ]
pub fn mpr(&mut self) -> _MPRW {
_MPRW { w: self }
}
- #[doc = "Bit 6 - Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." ] # [ inline ( always ) ]
pub fn wfr(&mut self) -> _WFRW {
_WFRW { w: self }
}
- #[doc = "Bit 9 - Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." ] # [ inline ( always ) ]
pub fn gu(&mut self) -> _GUW {
_GUW { w: self }
}
- #[doc = "Bit 31 - Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." ] # [ inline ( always ) ]
pub fn wffrpr(&mut self) -> _WFFRPRW {
_WFFRPRW { w: self }
}
@@ -99968,8 +96341,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - PMT Interrupt Status This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register."]
- #[inline(always)]
+ # [ doc = "Bit 3 - PMT Interrupt Status This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." ] # [ inline ( always ) ]
pub fn pmt(&self) -> PMTR {
let bits = {
const MASK: bool = true;
@@ -99978,8 +96350,7 @@ pub mod ethernet {
};
PMTR { bits }
}
- #[doc = "Bit 9 - Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers - There is an overflow in the seconds register This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576). Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers - There is an overflow in the seconds register This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576). Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." ] # [ inline ( always ) ]
pub fn ts(&self) -> TSR {
let bits = {
const MASK: bool = true;
@@ -100134,8 +96505,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - PMT Interrupt Mask This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561."]
- #[inline(always)]
+ # [ doc = "Bit 3 - PMT Interrupt Mask This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." ] # [ inline ( always ) ]
pub fn pmtim(&self) -> PMTIMR {
let bits = {
const MASK: bool = true;
@@ -100144,8 +96514,7 @@ pub mod ethernet {
};
PMTIMR { bits }
}
- #[doc = "Bit 9 - Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" ] # [ inline ( always ) ]
pub fn tsim(&self) -> TSIMR {
let bits = {
const MASK: bool = true;
@@ -100167,13 +96536,11 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 3 - PMT Interrupt Mask This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561."]
- #[inline(always)]
+ # [ doc = "Bit 3 - PMT Interrupt Mask This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." ] # [ inline ( always ) ]
pub fn pmtim(&mut self) -> _PMTIMW {
_PMTIMW { w: self }
}
- #[doc = "Bit 9 - Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" ] # [ inline ( always ) ]
pub fn tsim(&mut self) -> _TSIMW {
_TSIMW { w: self }
}
@@ -100305,8 +96672,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." ] # [ inline ( always ) ]
pub fn a47_32(&self) -> A47_32R {
let bits = {
const MASK: u16 = 65535;
@@ -100338,8 +96704,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." ] # [ inline ( always ) ]
pub fn a47_32(&mut self) -> _A47_32W {
_A47_32W { w: self }
}
@@ -100432,8 +96797,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." ] # [ inline ( always ) ]
pub fn a31_0(&self) -> A31_0R {
let bits = {
const MASK: u32 = 4294967295;
@@ -100455,8 +96819,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." ] # [ inline ( always ) ]
pub fn a31_0(&mut self) -> _A31_0W {
_A31_0W { w: self }
}
@@ -101204,8 +97567,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." ] # [ inline ( always ) ]
pub fn tsena(&self) -> TSENAR {
let bits = {
const MASK: bool = true;
@@ -101214,8 +97576,7 @@ pub mod ethernet {
};
TSENAR { bits }
}
- #[doc = "Bit 1 - Time stamp Fine or Coarse Update When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Time stamp Fine or Coarse Update When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." ] # [ inline ( always ) ]
pub fn tscfupdt(&self) -> TSCFUPDTR {
let bits = {
const MASK: bool = true;
@@ -101224,8 +97585,7 @@ pub mod ethernet {
};
TSCFUPDTR { bits }
}
- #[doc = "Bit 2 - Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." ] # [ inline ( always ) ]
pub fn tsinit(&self) -> TSINITR {
let bits = {
const MASK: bool = true;
@@ -101234,8 +97594,7 @@ pub mod ethernet {
};
TSINITR { bits }
}
- #[doc = "Bit 3 - Time stamp Update This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Time stamp Update This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." ] # [ inline ( always ) ]
pub fn tsupdt(&self) -> TSUPDTR {
let bits = {
const MASK: bool = true;
@@ -101244,8 +97603,7 @@ pub mod ethernet {
};
TSUPDTR { bits }
}
- #[doc = "Bit 4 - Time stamp Interrupt Trigger Enable This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Time stamp Interrupt Trigger Enable This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." ] # [ inline ( always ) ]
pub fn tstrig(&self) -> TSTRIGR {
let bits = {
const MASK: bool = true;
@@ -101254,8 +97612,7 @@ pub mod ethernet {
};
TSTRIGR { bits }
}
- #[doc = "Bit 5 - Addend Reg Update When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Addend Reg Update When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." ] # [ inline ( always ) ]
pub fn tsaddreg(&self) -> TSADDREGR {
let bits = {
const MASK: bool = true;
@@ -101264,8 +97621,7 @@ pub mod ethernet {
};
TSADDREGR { bits }
}
- #[doc = "Bit 8 - Enable Time stamp for All Frames When set, the Time stamp snapshot is enabled for all frames received by the core."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Enable Time stamp for All Frames When set, the Time stamp snapshot is enabled for all frames received by the core." ] # [ inline ( always ) ]
pub fn tsenall(&self) -> TSENALLR {
let bits = {
const MASK: bool = true;
@@ -101274,8 +97630,7 @@ pub mod ethernet {
};
TSENALLR { bits }
}
- #[doc = "Bit 9 - Time stamp Digital or Binary rollover control When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Time stamp Digital or Binary rollover control When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." ] # [ inline ( always ) ]
pub fn tsctrlssr(&self) -> TSCTRLSSRR {
let bits = {
const MASK: bool = true;
@@ -101284,8 +97639,7 @@ pub mod ethernet {
};
TSCTRLSSRR { bits }
}
- #[doc = "Bit 10 - Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." ] # [ inline ( always ) ]
pub fn tsver2ena(&self) -> TSVER2ENAR {
let bits = {
const MASK: bool = true;
@@ -101294,8 +97648,7 @@ pub mod ethernet {
};
TSVER2ENAR { bits }
}
- #[doc = "Bit 11 - Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." ] # [ inline ( always ) ]
pub fn tsipena(&self) -> TSIPENAR {
let bits = {
const MASK: bool = true;
@@ -101304,8 +97657,7 @@ pub mod ethernet {
};
TSIPENAR { bits }
}
- #[doc = "Bit 12 - Enable Time stamp Snapshot for IPv6 frames When set, the Time stamp snapshot is taken for IPv6 frames."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Enable Time stamp Snapshot for IPv6 frames When set, the Time stamp snapshot is taken for IPv6 frames." ] # [ inline ( always ) ]
pub fn tsipv6ena(&self) -> TSIPV6ENAR {
let bits = {
const MASK: bool = true;
@@ -101314,8 +97666,7 @@ pub mod ethernet {
};
TSIPV6ENAR { bits }
}
- #[doc = "Bit 13 - Enable Time stamp Snapshot for IPv4 frames When set, the Time stamp snapshot is taken for IPv4 frames."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Enable Time stamp Snapshot for IPv4 frames When set, the Time stamp snapshot is taken for IPv4 frames." ] # [ inline ( always ) ]
pub fn tsipv4ena(&self) -> TSIPV4ENAR {
let bits = {
const MASK: bool = true;
@@ -101324,8 +97675,7 @@ pub mod ethernet {
};
TSIPV4ENAR { bits }
}
- #[doc = "Bit 14 - Enable Time stamp Snapshot for Event Messages When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Enable Time stamp Snapshot for Event Messages When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." ] # [ inline ( always ) ]
pub fn tsevntena(&self) -> TSEVNTENAR {
let bits = {
const MASK: bool = true;
@@ -101334,8 +97684,7 @@ pub mod ethernet {
};
TSEVNTENAR { bits }
}
- #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." ] # [ inline ( always ) ]
pub fn tsmstrena(&self) -> TSMSTRENAR {
let bits = {
const MASK: bool = true;
@@ -101344,8 +97693,7 @@ pub mod ethernet {
};
TSMSTRENAR { bits }
}
- #[doc = "Bits 16:17 - Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" ] # [ inline ( always ) ]
pub fn tsclktype(&self) -> TSCLKTYPER {
let bits = {
const MASK: u8 = 3;
@@ -101354,8 +97702,7 @@ pub mod ethernet {
};
TSCLKTYPER { bits }
}
- #[doc = "Bit 18 - Enable MAC address for PTP frame filtering When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Enable MAC address for PTP frame filtering When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." ] # [ inline ( always ) ]
pub fn tsenmacaddr(&self) -> TSENMACADDRR {
let bits = {
const MASK: bool = true;
@@ -101377,83 +97724,67 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." ] # [ inline ( always ) ]
pub fn tsena(&mut self) -> _TSENAW {
_TSENAW { w: self }
}
- #[doc = "Bit 1 - Time stamp Fine or Coarse Update When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Time stamp Fine or Coarse Update When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." ] # [ inline ( always ) ]
pub fn tscfupdt(&mut self) -> _TSCFUPDTW {
_TSCFUPDTW { w: self }
}
- #[doc = "Bit 2 - Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." ] # [ inline ( always ) ]
pub fn tsinit(&mut self) -> _TSINITW {
_TSINITW { w: self }
}
- #[doc = "Bit 3 - Time stamp Update This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Time stamp Update This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." ] # [ inline ( always ) ]
pub fn tsupdt(&mut self) -> _TSUPDTW {
_TSUPDTW { w: self }
}
- #[doc = "Bit 4 - Time stamp Interrupt Trigger Enable This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Time stamp Interrupt Trigger Enable This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." ] # [ inline ( always ) ]
pub fn tstrig(&mut self) -> _TSTRIGW {
_TSTRIGW { w: self }
}
- #[doc = "Bit 5 - Addend Reg Update When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Addend Reg Update When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." ] # [ inline ( always ) ]
pub fn tsaddreg(&mut self) -> _TSADDREGW {
_TSADDREGW { w: self }
}
- #[doc = "Bit 8 - Enable Time stamp for All Frames When set, the Time stamp snapshot is enabled for all frames received by the core."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Enable Time stamp for All Frames When set, the Time stamp snapshot is enabled for all frames received by the core." ] # [ inline ( always ) ]
pub fn tsenall(&mut self) -> _TSENALLW {
_TSENALLW { w: self }
}
- #[doc = "Bit 9 - Time stamp Digital or Binary rollover control When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Time stamp Digital or Binary rollover control When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." ] # [ inline ( always ) ]
pub fn tsctrlssr(&mut self) -> _TSCTRLSSRW {
_TSCTRLSSRW { w: self }
}
- #[doc = "Bit 10 - Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." ] # [ inline ( always ) ]
pub fn tsver2ena(&mut self) -> _TSVER2ENAW {
_TSVER2ENAW { w: self }
}
- #[doc = "Bit 11 - Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." ] # [ inline ( always ) ]
pub fn tsipena(&mut self) -> _TSIPENAW {
_TSIPENAW { w: self }
}
- #[doc = "Bit 12 - Enable Time stamp Snapshot for IPv6 frames When set, the Time stamp snapshot is taken for IPv6 frames."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Enable Time stamp Snapshot for IPv6 frames When set, the Time stamp snapshot is taken for IPv6 frames." ] # [ inline ( always ) ]
pub fn tsipv6ena(&mut self) -> _TSIPV6ENAW {
_TSIPV6ENAW { w: self }
}
- #[doc = "Bit 13 - Enable Time stamp Snapshot for IPv4 frames When set, the Time stamp snapshot is taken for IPv4 frames."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Enable Time stamp Snapshot for IPv4 frames When set, the Time stamp snapshot is taken for IPv4 frames." ] # [ inline ( always ) ]
pub fn tsipv4ena(&mut self) -> _TSIPV4ENAW {
_TSIPV4ENAW { w: self }
}
- #[doc = "Bit 14 - Enable Time stamp Snapshot for Event Messages When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Enable Time stamp Snapshot for Event Messages When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." ] # [ inline ( always ) ]
pub fn tsevntena(&mut self) -> _TSEVNTENAW {
_TSEVNTENAW { w: self }
}
- #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." ] # [ inline ( always ) ]
pub fn tsmstrena(&mut self) -> _TSMSTRENAW {
_TSMSTRENAW { w: self }
}
- #[doc = "Bits 16:17 - Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" ] # [ inline ( always ) ]
pub fn tsclktype(&mut self) -> _TSCLKTYPEW {
_TSCLKTYPEW { w: self }
}
- #[doc = "Bit 18 - Enable MAC address for PTP frame filtering When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Enable MAC address for PTP frame filtering When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." ] # [ inline ( always ) ]
pub fn tsenmacaddr(&mut self) -> _TSENMACADDRW {
_TSENMACADDRW { w: self }
}
@@ -101541,8 +97872,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" ] # [ inline ( always ) ]
pub fn ssinc(&self) -> SSINCR {
let bits = {
const MASK: u8 = 255;
@@ -101564,8 +97894,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" ] # [ inline ( always ) ]
pub fn ssinc(&mut self) -> _SSINCW {
_SSINCW { w: self }
}
@@ -101607,8 +97936,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." ] # [ inline ( always ) ]
pub fn tss(&self) -> TSSR {
let bits = {
const MASK: u32 = 4294967295;
@@ -101676,8 +98004,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:30 - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)."]
- #[inline(always)]
+ # [ doc = "Bits 0:30 - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." ] # [ inline ( always ) ]
pub fn tsss(&self) -> TSSSR {
let bits = {
const MASK: u32 = 2147483647;
@@ -101686,8 +98013,7 @@ pub mod ethernet {
};
TSSSR { bits }
}
- #[doc = "Bit 31 - Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." ] # [ inline ( always ) ]
pub fn psnt(&self) -> PSNTR {
let bits = {
const MASK: bool = true;
@@ -101780,8 +98106,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." ] # [ inline ( always ) ]
pub fn tss(&self) -> TSSR {
let bits = {
const MASK: u32 = 4294967295;
@@ -101803,8 +98128,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." ] # [ inline ( always ) ]
pub fn tss(&mut self) -> _TSSW {
_TSSW { w: self }
}
@@ -101936,8 +98260,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:30 - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)"]
- #[inline(always)]
+ # [ doc = "Bits 0:30 - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" ] # [ inline ( always ) ]
pub fn tsss(&self) -> TSSSR {
let bits = {
const MASK: u32 = 2147483647;
@@ -101946,8 +98269,7 @@ pub mod ethernet {
};
TSSSR { bits }
}
- #[doc = "Bit 31 - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." ] # [ inline ( always ) ]
pub fn addsub(&self) -> ADDSUBR {
let bits = {
const MASK: bool = true;
@@ -101969,13 +98291,11 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:30 - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)"]
- #[inline(always)]
+ # [ doc = "Bits 0:30 - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" ] # [ inline ( always ) ]
pub fn tsss(&mut self) -> _TSSSW {
_TSSSW { w: self }
}
- #[doc = "Bit 31 - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." ] # [ inline ( always ) ]
pub fn addsub(&mut self) -> _ADDSUBW {
_ADDSUBW { w: self }
}
@@ -102063,8 +98383,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." ] # [ inline ( always ) ]
pub fn tsar(&self) -> TSARR {
let bits = {
const MASK: u32 = 4294967295;
@@ -102086,8 +98405,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." ] # [ inline ( always ) ]
pub fn tsar(&mut self) -> _TSARW {
_TSARW { w: self }
}
@@ -102175,8 +98493,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." ] # [ inline ( always ) ]
pub fn tstr(&self) -> TSTRR {
let bits = {
const MASK: u32 = 4294967295;
@@ -102198,8 +98515,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." ] # [ inline ( always ) ]
pub fn tstr(&mut self) -> _TSTRW {
_TSTRW { w: self }
}
@@ -102287,8 +98603,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:30 - Target Time stamp low This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)"]
- #[inline(always)]
+ # [ doc = "Bits 0:30 - Target Time stamp low This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" ] # [ inline ( always ) ]
pub fn tstr(&self) -> TSTRR {
let bits = {
const MASK: u32 = 2147483647;
@@ -102310,8 +98625,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:30 - Target Time stamp low This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)"]
- #[inline(always)]
+ # [ doc = "Bits 0:30 - Target Time stamp low This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" ] # [ inline ( always ) ]
pub fn tstr(&mut self) -> _TSTRW {
_TSTRW { w: self }
}
@@ -102399,8 +98713,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." ] # [ inline ( always ) ]
pub fn tshwr(&self) -> TSHWRR {
let bits = {
const MASK: u16 = 65535;
@@ -102422,8 +98735,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." ] # [ inline ( always ) ]
pub fn tshwr(&mut self) -> _TSHWRW {
_TSHWRW { w: self }
}
@@ -102496,8 +98808,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." ] # [ inline ( always ) ]
pub fn tssovf(&self) -> TSSOVFR {
let bits = {
const MASK: bool = true;
@@ -102506,8 +98817,7 @@ pub mod ethernet {
};
TSSOVFR { bits }
}
- #[doc = "Bit 1 - Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" ] # [ inline ( always ) ]
pub fn tstargt(&self) -> TSTARGTR {
let bits = {
const MASK: bool = true;
@@ -103074,8 +99384,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." ] # [ inline ( always ) ]
pub fn swr(&self) -> SWRR {
let bits = {
const MASK: bool = true;
@@ -103084,8 +99393,7 @@ pub mod ethernet {
};
SWRR { bits }
}
- #[doc = "Bit 1 - DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14] 1 = Rx has priority over Tx"]
- #[inline(always)]
+ # [ doc = "Bit 1 - DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14] 1 = Rx has priority over Tx" ] # [ inline ( always ) ]
pub fn da(&self) -> DAR {
let bits = {
const MASK: bool = true;
@@ -103094,8 +99402,7 @@ pub mod ethernet {
};
DAR { bits }
}
- #[doc = "Bits 2:6 - Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode."]
- #[inline(always)]
+ # [ doc = "Bits 2:6 - Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." ] # [ inline ( always ) ]
pub fn dsl(&self) -> DSLR {
let bits = {
const MASK: u8 = 31;
@@ -103104,8 +99411,7 @@ pub mod ethernet {
};
DSLR { bits }
}
- #[doc = "Bit 7 - Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." ] # [ inline ( always ) ]
pub fn atds(&self) -> ATDSR {
let bits = {
const MASK: bool = true;
@@ -103114,8 +99420,7 @@ pub mod ethernet {
};
ATDSR { bits }
}
- #[doc = "Bits 8:13 - Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only. The PBL values have the following limitations. The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly."]
- #[inline(always)]
+ # [ doc = "Bits 8:13 - Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only. The PBL values have the following limitations. The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." ] # [ inline ( always ) ]
pub fn pbl(&self) -> PBLR {
let bits = {
const MASK: u8 = 63;
@@ -103124,8 +99429,7 @@ pub mod ethernet {
};
PBLR { bits }
}
- #[doc = "Bits 14:15 - Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset. 00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1"]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset. 00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" ] # [ inline ( always ) ]
pub fn pr(&self) -> PRR {
let bits = {
const MASK: u8 = 3;
@@ -103134,8 +99438,7 @@ pub mod ethernet {
};
PRR { bits }
}
- #[doc = "Bit 16 - Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." ] # [ inline ( always ) ]
pub fn fb(&self) -> FBR {
let bits = {
const MASK: bool = true;
@@ -103144,8 +99447,7 @@ pub mod ethernet {
};
FBR { bits }
}
- #[doc = "Bits 17:22 - RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high."]
- #[inline(always)]
+ # [ doc = "Bits 17:22 - RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." ] # [ inline ( always ) ]
pub fn rpbl(&self) -> RPBLR {
let bits = {
const MASK: u8 = 63;
@@ -103154,8 +99456,7 @@ pub mod ethernet {
};
RPBLR { bits }
}
- #[doc = "Bit 23 - Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." ] # [ inline ( always ) ]
pub fn usp(&self) -> USPR {
let bits = {
const MASK: bool = true;
@@ -103164,8 +99465,7 @@ pub mod ethernet {
};
USPR { bits }
}
- #[doc = "Bit 24 - 8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL."]
- #[inline(always)]
+ # [ doc = "Bit 24 - 8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." ] # [ inline ( always ) ]
pub fn pbl8x(&self) -> PBL8XR {
let bits = {
const MASK: bool = true;
@@ -103174,8 +99474,7 @@ pub mod ethernet {
};
PBL8XR { bits }
}
- #[doc = "Bit 25 - Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." ] # [ inline ( always ) ]
pub fn aal(&self) -> AALR {
let bits = {
const MASK: bool = true;
@@ -103184,8 +99483,7 @@ pub mod ethernet {
};
AALR { bits }
}
- #[doc = "Bit 26 - Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." ] # [ inline ( always ) ]
pub fn mb(&self) -> MBR {
let bits = {
const MASK: bool = true;
@@ -103194,8 +99492,7 @@ pub mod ethernet {
};
MBR { bits }
}
- #[doc = "Bit 27 - When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus."]
- #[inline(always)]
+ # [ doc = "Bit 27 - When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." ] # [ inline ( always ) ]
pub fn txpr(&self) -> TXPRR {
let bits = {
const MASK: bool = true;
@@ -103217,68 +99514,55 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." ] # [ inline ( always ) ]
pub fn swr(&mut self) -> _SWRW {
_SWRW { w: self }
}
- #[doc = "Bit 1 - DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14] 1 = Rx has priority over Tx"]
- #[inline(always)]
+ # [ doc = "Bit 1 - DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14] 1 = Rx has priority over Tx" ] # [ inline ( always ) ]
pub fn da(&mut self) -> _DAW {
_DAW { w: self }
}
- #[doc = "Bits 2:6 - Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode."]
- #[inline(always)]
+ # [ doc = "Bits 2:6 - Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." ] # [ inline ( always ) ]
pub fn dsl(&mut self) -> _DSLW {
_DSLW { w: self }
}
- #[doc = "Bit 7 - Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." ] # [ inline ( always ) ]
pub fn atds(&mut self) -> _ATDSW {
_ATDSW { w: self }
}
- #[doc = "Bits 8:13 - Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only. The PBL values have the following limitations. The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly."]
- #[inline(always)]
+ # [ doc = "Bits 8:13 - Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only. The PBL values have the following limitations. The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." ] # [ inline ( always ) ]
pub fn pbl(&mut self) -> _PBLW {
_PBLW { w: self }
}
- #[doc = "Bits 14:15 - Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset. 00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1"]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset. 00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" ] # [ inline ( always ) ]
pub fn pr(&mut self) -> _PRW {
_PRW { w: self }
}
- #[doc = "Bit 16 - Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." ] # [ inline ( always ) ]
pub fn fb(&mut self) -> _FBW {
_FBW { w: self }
}
- #[doc = "Bits 17:22 - RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high."]
- #[inline(always)]
+ # [ doc = "Bits 17:22 - RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." ] # [ inline ( always ) ]
pub fn rpbl(&mut self) -> _RPBLW {
_RPBLW { w: self }
}
- #[doc = "Bit 23 - Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." ] # [ inline ( always ) ]
pub fn usp(&mut self) -> _USPW {
_USPW { w: self }
}
- #[doc = "Bit 24 - 8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL."]
- #[inline(always)]
+ # [ doc = "Bit 24 - 8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." ] # [ inline ( always ) ]
pub fn pbl8x(&mut self) -> _PBL8XW {
_PBL8XW { w: self }
}
- #[doc = "Bit 25 - Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." ] # [ inline ( always ) ]
pub fn aal(&mut self) -> _AALW {
_AALW { w: self }
}
- #[doc = "Bit 26 - Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." ] # [ inline ( always ) ]
pub fn mb(&mut self) -> _MBW {
_MBW { w: self }
}
- #[doc = "Bit 27 - When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus."]
- #[inline(always)]
+ # [ doc = "Bit 27 - When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." ] # [ inline ( always ) ]
pub fn txpr(&mut self) -> _TXPRW {
_TXPRW { w: self }
}
@@ -103366,8 +99650,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." ] # [ inline ( always ) ]
pub fn tpd(&self) -> TPDR {
let bits = {
const MASK: u32 = 4294967295;
@@ -103389,8 +99672,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." ] # [ inline ( always ) ]
pub fn tpd(&mut self) -> _TPDW {
_TPDW { w: self }
}
@@ -103478,8 +99760,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." ] # [ inline ( always ) ]
pub fn rpd(&self) -> RPDR {
let bits = {
const MASK: u32 = 4294967295;
@@ -103501,8 +99782,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." ] # [ inline ( always ) ]
pub fn rpd(&mut self) -> _RPDW {
_RPDW { w: self }
}
@@ -103590,8 +99870,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." ] # [ inline ( always ) ]
pub fn srl(&self) -> SRLR {
let bits = {
const MASK: u32 = 4294967295;
@@ -103613,8 +99892,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." ] # [ inline ( always ) ]
pub fn srl(&mut self) -> _SRLW {
_SRLW { w: self }
}
@@ -103702,8 +99980,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." ] # [ inline ( always ) ]
pub fn srl(&self) -> SRLR {
let bits = {
const MASK: u32 = 4294967295;
@@ -103725,8 +100002,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." ] # [ inline ( always ) ]
pub fn srl(&mut self) -> _SRLW {
_SRLW { w: self }
}
@@ -104632,8 +100908,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." ] # [ inline ( always ) ]
pub fn ti(&self) -> TIR {
let bits = {
const MASK: bool = true;
@@ -104642,8 +100917,7 @@ pub mod ethernet {
};
TIR { bits }
}
- #[doc = "Bit 1 - Transmit process stopped This bit is set when the transmission is stopped."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit process stopped This bit is set when the transmission is stopped." ] # [ inline ( always ) ]
pub fn tps(&self) -> TPSR {
let bits = {
const MASK: bool = true;
@@ -104652,8 +100926,7 @@ pub mod ethernet {
};
TPSR { bits }
}
- #[doc = "Bit 2 - Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." ] # [ inline ( always ) ]
pub fn tu(&self) -> TUR {
let bits = {
const MASK: bool = true;
@@ -104662,8 +100935,7 @@ pub mod ethernet {
};
TUR { bits }
}
- #[doc = "Bit 3 - Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." ] # [ inline ( always ) ]
pub fn tjt(&self) -> TJTR {
let bits = {
const MASK: bool = true;
@@ -104672,8 +100944,7 @@ pub mod ethernet {
};
TJTR { bits }
}
- #[doc = "Bit 4 - Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." ] # [ inline ( always ) ]
pub fn ovf(&self) -> OVFR {
let bits = {
const MASK: bool = true;
@@ -104682,8 +100953,7 @@ pub mod ethernet {
};
OVFR { bits }
}
- #[doc = "Bit 5 - Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." ] # [ inline ( always ) ]
pub fn unf(&self) -> UNFR {
let bits = {
const MASK: bool = true;
@@ -104692,8 +100962,7 @@ pub mod ethernet {
};
UNFR { bits }
}
- #[doc = "Bit 6 - Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." ] # [ inline ( always ) ]
pub fn ri(&self) -> RIR {
let bits = {
const MASK: bool = true;
@@ -104702,8 +100971,7 @@ pub mod ethernet {
};
RIR { bits }
}
- #[doc = "Bit 7 - Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." ] # [ inline ( always ) ]
pub fn ru(&self) -> RUR {
let bits = {
const MASK: bool = true;
@@ -104712,8 +100980,7 @@ pub mod ethernet {
};
RUR { bits }
}
- #[doc = "Bit 8 - Received process stopped This bit is asserted when the Receive Process enters the Stopped state."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Received process stopped This bit is asserted when the Receive Process enters the Stopped state." ] # [ inline ( always ) ]
pub fn rps(&self) -> RPSR {
let bits = {
const MASK: bool = true;
@@ -104722,8 +100989,7 @@ pub mod ethernet {
};
RPSR { bits }
}
- #[doc = "Bit 9 - Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." ] # [ inline ( always ) ]
pub fn rwt(&self) -> RWTR {
let bits = {
const MASK: bool = true;
@@ -104732,8 +100998,7 @@ pub mod ethernet {
};
RWTR { bits }
}
- #[doc = "Bit 10 - Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." ] # [ inline ( always ) ]
pub fn eti(&self) -> ETIR {
let bits = {
const MASK: bool = true;
@@ -104742,8 +101007,7 @@ pub mod ethernet {
};
ETIR { bits }
}
- #[doc = "Bit 13 - Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." ] # [ inline ( always ) ]
pub fn fbi(&self) -> FBIR {
let bits = {
const MASK: bool = true;
@@ -104752,8 +101016,7 @@ pub mod ethernet {
};
FBIR { bits }
}
- #[doc = "Bit 14 - Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." ] # [ inline ( always ) ]
pub fn eri(&self) -> ERIR {
let bits = {
const MASK: bool = true;
@@ -104762,8 +101025,7 @@ pub mod ethernet {
};
ERIR { bits }
}
- #[doc = "Bit 15 - Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." ] # [ inline ( always ) ]
pub fn aie(&self) -> AIER {
let bits = {
const MASK: bool = true;
@@ -104772,8 +101034,7 @@ pub mod ethernet {
};
AIER { bits }
}
- #[doc = "Bit 16 - Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." ] # [ inline ( always ) ]
pub fn nis(&self) -> NISR {
let bits = {
const MASK: bool = true;
@@ -104782,8 +101043,7 @@ pub mod ethernet {
};
NISR { bits }
}
- #[doc = "Bits 17:19 - Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory."]
- #[inline(always)]
+ # [ doc = "Bits 17:19 - Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory." ] # [ inline ( always ) ]
pub fn rs(&self) -> RSR {
let bits = {
const MASK: u8 = 7;
@@ -104792,8 +101052,7 @@ pub mod ethernet {
};
RSR { bits }
}
- #[doc = "Bits 20:22 - Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor."]
- #[inline(always)]
+ # [ doc = "Bits 20:22 - Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor." ] # [ inline ( always ) ]
pub fn ts(&self) -> TSR {
let bits = {
const MASK: u8 = 7;
@@ -104802,8 +101061,7 @@ pub mod ethernet {
};
TSR { bits }
}
- #[doc = "Bit 23 - Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." ] # [ inline ( always ) ]
pub fn eb1(&self) -> EB1R {
let bits = {
const MASK: bool = true;
@@ -104812,8 +101070,7 @@ pub mod ethernet {
};
EB1R { bits }
}
- #[doc = "Bit 24 - Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer." ] # [ inline ( always ) ]
pub fn eb2(&self) -> EB2R {
let bits = {
const MASK: bool = true;
@@ -104822,8 +101079,7 @@ pub mod ethernet {
};
EB2R { bits }
}
- #[doc = "Bit 25 - Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access." ] # [ inline ( always ) ]
pub fn eb3(&self) -> EB3R {
let bits = {
const MASK: bool = true;
@@ -104845,103 +101101,83 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." ] # [ inline ( always ) ]
pub fn ti(&mut self) -> _TIW {
_TIW { w: self }
}
- #[doc = "Bit 1 - Transmit process stopped This bit is set when the transmission is stopped."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit process stopped This bit is set when the transmission is stopped." ] # [ inline ( always ) ]
pub fn tps(&mut self) -> _TPSW {
_TPSW { w: self }
}
- #[doc = "Bit 2 - Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." ] # [ inline ( always ) ]
pub fn tu(&mut self) -> _TUW {
_TUW { w: self }
}
- #[doc = "Bit 3 - Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." ] # [ inline ( always ) ]
pub fn tjt(&mut self) -> _TJTW {
_TJTW { w: self }
}
- #[doc = "Bit 4 - Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." ] # [ inline ( always ) ]
pub fn ovf(&mut self) -> _OVFW {
_OVFW { w: self }
}
- #[doc = "Bit 5 - Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." ] # [ inline ( always ) ]
pub fn unf(&mut self) -> _UNFW {
_UNFW { w: self }
}
- #[doc = "Bit 6 - Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." ] # [ inline ( always ) ]
pub fn ri(&mut self) -> _RIW {
_RIW { w: self }
}
- #[doc = "Bit 7 - Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." ] # [ inline ( always ) ]
pub fn ru(&mut self) -> _RUW {
_RUW { w: self }
}
- #[doc = "Bit 8 - Received process stopped This bit is asserted when the Receive Process enters the Stopped state."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Received process stopped This bit is asserted when the Receive Process enters the Stopped state." ] # [ inline ( always ) ]
pub fn rps(&mut self) -> _RPSW {
_RPSW { w: self }
}
- #[doc = "Bit 9 - Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." ] # [ inline ( always ) ]
pub fn rwt(&mut self) -> _RWTW {
_RWTW { w: self }
}
- #[doc = "Bit 10 - Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." ] # [ inline ( always ) ]
pub fn eti(&mut self) -> _ETIW {
_ETIW { w: self }
}
- #[doc = "Bit 13 - Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." ] # [ inline ( always ) ]
pub fn fbi(&mut self) -> _FBIW {
_FBIW { w: self }
}
- #[doc = "Bit 14 - Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." ] # [ inline ( always ) ]
pub fn eri(&mut self) -> _ERIW {
_ERIW { w: self }
}
- #[doc = "Bit 15 - Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." ] # [ inline ( always ) ]
pub fn aie(&mut self) -> _AIEW {
_AIEW { w: self }
}
- #[doc = "Bit 16 - Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." ] # [ inline ( always ) ]
pub fn nis(&mut self) -> _NISW {
_NISW { w: self }
}
- #[doc = "Bits 17:19 - Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory."]
- #[inline(always)]
+ # [ doc = "Bits 17:19 - Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory." ] # [ inline ( always ) ]
pub fn rs(&mut self) -> _RSW {
_RSW { w: self }
}
- #[doc = "Bits 20:22 - Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor."]
- #[inline(always)]
+ # [ doc = "Bits 20:22 - Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor." ] # [ inline ( always ) ]
pub fn ts(&mut self) -> _TSW {
_TSW { w: self }
}
- #[doc = "Bit 23 - Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." ] # [ inline ( always ) ]
pub fn eb1(&mut self) -> _EB1W {
_EB1W { w: self }
}
- #[doc = "Bit 24 - Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer." ] # [ inline ( always ) ]
pub fn eb2(&mut self) -> _EB2W {
_EB2W { w: self }
}
- #[doc = "Bit 25 - Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access." ] # [ inline ( always ) ]
pub fn eb3(&mut self) -> _EB3W {
_EB3W { w: self }
}
@@ -105363,8 +101599,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 1 - Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." ] # [ inline ( always ) ]
pub fn sr(&self) -> SRR {
let bits = {
const MASK: bool = true;
@@ -105373,8 +101608,7 @@ pub mod ethernet {
};
SRR { bits }
}
- #[doc = "Bit 2 - Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." ] # [ inline ( always ) ]
pub fn osf(&self) -> OSFR {
let bits = {
const MASK: bool = true;
@@ -105383,8 +101617,7 @@ pub mod ethernet {
};
OSFR { bits }
}
- #[doc = "Bits 3:4 - Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128"]
- #[inline(always)]
+ # [ doc = "Bits 3:4 - Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128" ] # [ inline ( always ) ]
pub fn rtc(&self) -> RTCR {
let bits = {
const MASK: u8 = 3;
@@ -105393,8 +101626,7 @@ pub mod ethernet {
};
RTCR { bits }
}
- #[doc = "Bit 6 - Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC). When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC). When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." ] # [ inline ( always ) ]
pub fn fuf(&self) -> FUFR {
let bits = {
const MASK: bool = true;
@@ -105403,8 +101635,7 @@ pub mod ethernet {
};
FUFR { bits }
}
- #[doc = "Bit 7 - Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." ] # [ inline ( always ) ]
pub fn fef(&self) -> FEFR {
let bits = {
const MASK: bool = true;
@@ -105413,8 +101644,7 @@ pub mod ethernet {
};
FEFR { bits }
}
- #[doc = "Bit 13 - Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." ] # [ inline ( always ) ]
pub fn st(&self) -> STR {
let bits = {
const MASK: bool = true;
@@ -105423,8 +101653,7 @@ pub mod ethernet {
};
STR { bits }
}
- #[doc = "Bits 14:16 - Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 14:16 - Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" ] # [ inline ( always ) ]
pub fn ttc(&self) -> TTCR {
let bits = {
const MASK: u8 = 7;
@@ -105433,8 +101662,7 @@ pub mod ethernet {
};
TTCR { bits }
}
- #[doc = "Bit 20 - Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission. The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission. The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." ] # [ inline ( always ) ]
pub fn ftf(&self) -> FTFR {
let bits = {
const MASK: bool = true;
@@ -105443,8 +101671,7 @@ pub mod ethernet {
};
FTFR { bits }
}
- #[doc = "Bit 24 - Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." ] # [ inline ( always ) ]
pub fn dff(&self) -> DFFR {
let bits = {
const MASK: bool = true;
@@ -105466,48 +101693,39 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 1 - Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." ] # [ inline ( always ) ]
pub fn sr(&mut self) -> _SRW {
_SRW { w: self }
}
- #[doc = "Bit 2 - Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." ] # [ inline ( always ) ]
pub fn osf(&mut self) -> _OSFW {
_OSFW { w: self }
}
- #[doc = "Bits 3:4 - Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128"]
- #[inline(always)]
+ # [ doc = "Bits 3:4 - Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128" ] # [ inline ( always ) ]
pub fn rtc(&mut self) -> _RTCW {
_RTCW { w: self }
}
- #[doc = "Bit 6 - Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC). When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC). When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." ] # [ inline ( always ) ]
pub fn fuf(&mut self) -> _FUFW {
_FUFW { w: self }
}
- #[doc = "Bit 7 - Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." ] # [ inline ( always ) ]
pub fn fef(&mut self) -> _FEFW {
_FEFW { w: self }
}
- #[doc = "Bit 13 - Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." ] # [ inline ( always ) ]
pub fn st(&mut self) -> _STW {
_STW { w: self }
}
- #[doc = "Bits 14:16 - Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 14:16 - Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" ] # [ inline ( always ) ]
pub fn ttc(&mut self) -> _TTCW {
_TTCW { w: self }
}
- #[doc = "Bit 20 - Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission. The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission. The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." ] # [ inline ( always ) ]
pub fn ftf(&mut self) -> _FTFW {
_FTFW { w: self }
}
- #[doc = "Bit 24 - Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." ] # [ inline ( always ) ]
pub fn dff(&mut self) -> _DFFW {
_DFFW { w: self }
}
@@ -106229,8 +102447,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tie(&self) -> TIER {
let bits = {
const MASK: bool = true;
@@ -106239,8 +102456,7 @@ pub mod ethernet {
};
TIER { bits }
}
- #[doc = "Bit 1 - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tse(&self) -> TSER {
let bits = {
const MASK: bool = true;
@@ -106249,8 +102465,7 @@ pub mod ethernet {
};
TSER { bits }
}
- #[doc = "Bit 2 - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tue(&self) -> TUER {
let bits = {
const MASK: bool = true;
@@ -106259,8 +102474,7 @@ pub mod ethernet {
};
TUER { bits }
}
- #[doc = "Bit 3 - Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tje(&self) -> TJER {
let bits = {
const MASK: bool = true;
@@ -106269,8 +102483,7 @@ pub mod ethernet {
};
TJER { bits }
}
- #[doc = "Bit 4 - Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ove(&self) -> OVER {
let bits = {
const MASK: bool = true;
@@ -106279,8 +102492,7 @@ pub mod ethernet {
};
OVER { bits }
}
- #[doc = "Bit 5 - Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." ] # [ inline ( always ) ]
pub fn une(&self) -> UNER {
let bits = {
const MASK: bool = true;
@@ -106289,8 +102501,7 @@ pub mod ethernet {
};
UNER { bits }
}
- #[doc = "Bit 6 - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rie(&self) -> RIER {
let bits = {
const MASK: bool = true;
@@ -106299,8 +102510,7 @@ pub mod ethernet {
};
RIER { bits }
}
- #[doc = "Bit 7 - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rue(&self) -> RUER {
let bits = {
const MASK: bool = true;
@@ -106309,8 +102519,7 @@ pub mod ethernet {
};
RUER { bits }
}
- #[doc = "Bit 8 - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rse(&self) -> RSER {
let bits = {
const MASK: bool = true;
@@ -106319,8 +102528,7 @@ pub mod ethernet {
};
RSER { bits }
}
- #[doc = "Bit 9 - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rwe(&self) -> RWER {
let bits = {
const MASK: bool = true;
@@ -106329,8 +102537,7 @@ pub mod ethernet {
};
RWER { bits }
}
- #[doc = "Bit 10 - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ete(&self) -> ETER {
let bits = {
const MASK: bool = true;
@@ -106339,8 +102546,7 @@ pub mod ethernet {
};
ETER { bits }
}
- #[doc = "Bit 13 - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn fbe(&self) -> FBER {
let bits = {
const MASK: bool = true;
@@ -106349,8 +102555,7 @@ pub mod ethernet {
};
FBER { bits }
}
- #[doc = "Bit 14 - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ere(&self) -> ERER {
let bits = {
const MASK: bool = true;
@@ -106359,8 +102564,7 @@ pub mod ethernet {
};
ERER { bits }
}
- #[doc = "Bit 15 - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error"]
- #[inline(always)]
+ # [ doc = "Bit 15 - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" ] # [ inline ( always ) ]
pub fn aie(&self) -> AIER {
let bits = {
const MASK: bool = true;
@@ -106369,8 +102573,7 @@ pub mod ethernet {
};
AIER { bits }
}
- #[doc = "Bit 16 - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" ] # [ inline ( always ) ]
pub fn nie(&self) -> NIER {
let bits = {
const MASK: bool = true;
@@ -106392,78 +102595,63 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tie(&mut self) -> _TIEW {
_TIEW { w: self }
}
- #[doc = "Bit 1 - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tse(&mut self) -> _TSEW {
_TSEW { w: self }
}
- #[doc = "Bit 2 - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tue(&mut self) -> _TUEW {
_TUEW { w: self }
}
- #[doc = "Bit 3 - Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." ] # [ inline ( always ) ]
pub fn tje(&mut self) -> _TJEW {
_TJEW { w: self }
}
- #[doc = "Bit 4 - Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ove(&mut self) -> _OVEW {
_OVEW { w: self }
}
- #[doc = "Bit 5 - Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." ] # [ inline ( always ) ]
pub fn une(&mut self) -> _UNEW {
_UNEW { w: self }
}
- #[doc = "Bit 6 - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rie(&mut self) -> _RIEW {
_RIEW { w: self }
}
- #[doc = "Bit 7 - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rue(&mut self) -> _RUEW {
_RUEW { w: self }
}
- #[doc = "Bit 8 - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rse(&mut self) -> _RSEW {
_RSEW { w: self }
}
- #[doc = "Bit 9 - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." ] # [ inline ( always ) ]
pub fn rwe(&mut self) -> _RWEW {
_RWEW { w: self }
}
- #[doc = "Bit 10 - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ete(&mut self) -> _ETEW {
_ETEW { w: self }
}
- #[doc = "Bit 13 - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." ] # [ inline ( always ) ]
pub fn fbe(&mut self) -> _FBEW {
_FBEW { w: self }
}
- #[doc = "Bit 14 - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." ] # [ inline ( always ) ]
pub fn ere(&mut self) -> _EREW {
_EREW { w: self }
}
- #[doc = "Bit 15 - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error"]
- #[inline(always)]
+ # [ doc = "Bit 15 - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" ] # [ inline ( always ) ]
pub fn aie(&mut self) -> _AIEW {
_AIEW { w: self }
}
- #[doc = "Bit 16 - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" ] # [ inline ( always ) ]
pub fn nie(&mut self) -> _NIEW {
_NIEW { w: self }
}
@@ -106558,8 +102746,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." ] # [ inline ( always ) ]
pub fn fmc(&self) -> FMCR {
let bits = {
const MASK: u16 = 65535;
@@ -106568,8 +102755,7 @@ pub mod ethernet {
};
FMCR { bits }
}
- #[doc = "Bit 16 - Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." ] # [ inline ( always ) ]
pub fn oc(&self) -> OCR {
let bits = {
const MASK: bool = true;
@@ -106578,8 +102764,7 @@ pub mod ethernet {
};
OCR { bits }
}
- #[doc = "Bits 17:27 - Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ."]
- #[inline(always)]
+ # [ doc = "Bits 17:27 - Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." ] # [ inline ( always ) ]
pub fn fma(&self) -> FMAR {
let bits = {
const MASK: u16 = 2047;
@@ -106588,8 +102773,7 @@ pub mod ethernet {
};
FMAR { bits }
}
- #[doc = "Bit 28 - Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." ] # [ inline ( always ) ]
pub fn of(&self) -> OFR {
let bits = {
const MASK: bool = true;
@@ -106682,8 +102866,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." ] # [ inline ( always ) ]
pub fn riwt(&self) -> RIWTR {
let bits = {
const MASK: u8 = 255;
@@ -106705,8 +102888,7 @@ pub mod ethernet {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." ] # [ inline ( always ) ]
pub fn riwt(&mut self) -> _RIWTW {
_RIWTW { w: self }
}
@@ -106748,8 +102930,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation." ] # [ inline ( always ) ]
pub fn htd(&self) -> HTDR {
let bits = {
const MASK: u32 = 4294967295;
@@ -106796,8 +102977,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Host Receive Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Host Receive Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation." ] # [ inline ( always ) ]
pub fn hrd(&self) -> HRDR {
let bits = {
const MASK: u32 = 4294967295;
@@ -106844,8 +103024,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation." ] # [ inline ( always ) ]
pub fn htb(&self) -> HTBR {
let bits = {
const MASK: u32 = 4294967295;
@@ -106892,8 +103071,7 @@ pub mod ethernet {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Host Receive Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Host Receive Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation." ] # [ inline ( always ) ]
pub fn hrb(&self) -> HRBR {
let bits = {
const MASK: u32 = 4294967295;
@@ -107015,8 +103193,7 @@ pub mod atimer {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." ] # [ inline ( always ) ]
pub fn cval(&self) -> CVALR {
let bits = {
const MASK: u16 = 65535;
@@ -107038,8 +103215,7 @@ pub mod atimer {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." ] # [ inline ( always ) ]
pub fn cval(&mut self) -> _CVALW {
_CVALW { w: self }
}
@@ -107214,8 +103390,7 @@ pub mod atimer {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." ] # [ inline ( always ) ]
pub fn clr_en(&mut self) -> _CLR_ENW {
_CLR_ENW { w: self }
}
@@ -107278,8 +103453,7 @@ pub mod atimer {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." ] # [ inline ( always ) ]
pub fn set_en(&mut self) -> _SET_ENW {
_SET_ENW { w: self }
}
@@ -107389,8 +103563,7 @@ pub mod atimer {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn en(&self) -> ENR {
let bits = {
const MASK: bool = true;
@@ -107458,8 +103631,7 @@ pub mod atimer {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." ] # [ inline ( always ) ]
pub fn cstat(&mut self) -> _CSTATW {
_CSTATW { w: self }
}
@@ -107522,8 +103694,7 @@ pub mod atimer {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." ] # [ inline ( always ) ]
pub fn sstat(&mut self) -> _SSTATW {
_SSTATW { w: self }
}
@@ -107548,134 +103719,70 @@ pub mod regfile {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
- #[doc = "0x00 - General purpose storage register"]
- pub regfile0: REGFILE,
- #[doc = "0x04 - General purpose storage register"]
- pub regfile1: REGFILE,
- #[doc = "0x08 - General purpose storage register"]
- pub regfile2: REGFILE,
- #[doc = "0x0c - General purpose storage register"]
- pub regfile3: REGFILE,
- #[doc = "0x10 - General purpose storage register"]
- pub regfile4: REGFILE,
- #[doc = "0x14 - General purpose storage register"]
- pub regfile5: REGFILE,
- #[doc = "0x18 - General purpose storage register"]
- pub regfile6: REGFILE,
- #[doc = "0x1c - General purpose storage register"]
- pub regfile7: REGFILE,
- #[doc = "0x20 - General purpose storage register"]
- pub regfile8: REGFILE,
- #[doc = "0x24 - General purpose storage register"]
- pub regfile9: REGFILE,
- #[doc = "0x28 - General purpose storage register"]
- pub regfile10: REGFILE,
- #[doc = "0x2c - General purpose storage register"]
- pub regfile11: REGFILE,
- #[doc = "0x30 - General purpose storage register"]
- pub regfile12: REGFILE,
- #[doc = "0x34 - General purpose storage register"]
- pub regfile13: REGFILE,
- #[doc = "0x38 - General purpose storage register"]
- pub regfile14: REGFILE,
- #[doc = "0x3c - General purpose storage register"]
- pub regfile15: REGFILE,
- #[doc = "0x40 - General purpose storage register"]
- pub regfile16: REGFILE,
- #[doc = "0x44 - General purpose storage register"]
- pub regfile17: REGFILE,
- #[doc = "0x48 - General purpose storage register"]
- pub regfile18: REGFILE,
- #[doc = "0x4c - General purpose storage register"]
- pub regfile19: REGFILE,
- #[doc = "0x50 - General purpose storage register"]
- pub regfile20: REGFILE,
- #[doc = "0x54 - General purpose storage register"]
- pub regfile21: REGFILE,
- #[doc = "0x58 - General purpose storage register"]
- pub regfile22: REGFILE,
- #[doc = "0x5c - General purpose storage register"]
- pub regfile23: REGFILE,
- #[doc = "0x60 - General purpose storage register"]
- pub regfile24: REGFILE,
- #[doc = "0x64 - General purpose storage register"]
- pub regfile25: REGFILE,
- #[doc = "0x68 - General purpose storage register"]
- pub regfile26: REGFILE,
- #[doc = "0x6c - General purpose storage register"]
- pub regfile27: REGFILE,
- #[doc = "0x70 - General purpose storage register"]
- pub regfile28: REGFILE,
- #[doc = "0x74 - General purpose storage register"]
- pub regfile29: REGFILE,
- #[doc = "0x78 - General purpose storage register"]
- pub regfile30: REGFILE,
- #[doc = "0x7c - General purpose storage register"]
- pub regfile31: REGFILE,
- #[doc = "0x80 - General purpose storage register"]
- pub regfile32: REGFILE,
- #[doc = "0x84 - General purpose storage register"]
- pub regfile33: REGFILE,
- #[doc = "0x88 - General purpose storage register"]
- pub regfile34: REGFILE,
- #[doc = "0x8c - General purpose storage register"]
- pub regfile35: REGFILE,
- #[doc = "0x90 - General purpose storage register"]
- pub regfile36: REGFILE,
- #[doc = "0x94 - General purpose storage register"]
- pub regfile37: REGFILE,
- #[doc = "0x98 - General purpose storage register"]
- pub regfile38: REGFILE,
- #[doc = "0x9c - General purpose storage register"]
- pub regfile39: REGFILE,
- #[doc = "0xa0 - General purpose storage register"]
- pub regfile40: REGFILE,
- #[doc = "0xa4 - General purpose storage register"]
- pub regfile41: REGFILE,
- #[doc = "0xa8 - General purpose storage register"]
- pub regfile42: REGFILE,
- #[doc = "0xac - General purpose storage register"]
- pub regfile43: REGFILE,
- #[doc = "0xb0 - General purpose storage register"]
- pub regfile44: REGFILE,
- #[doc = "0xb4 - General purpose storage register"]
- pub regfile45: REGFILE,
- #[doc = "0xb8 - General purpose storage register"]
- pub regfile46: REGFILE,
- #[doc = "0xbc - General purpose storage register"]
- pub regfile47: REGFILE,
- #[doc = "0xc0 - General purpose storage register"]
- pub regfile48: REGFILE,
- #[doc = "0xc4 - General purpose storage register"]
- pub regfile49: REGFILE,
- #[doc = "0xc8 - General purpose storage register"]
- pub regfile50: REGFILE,
- #[doc = "0xcc - General purpose storage register"]
- pub regfile51: REGFILE,
- #[doc = "0xd0 - General purpose storage register"]
- pub regfile52: REGFILE,
- #[doc = "0xd4 - General purpose storage register"]
- pub regfile53: REGFILE,
- #[doc = "0xd8 - General purpose storage register"]
- pub regfile54: REGFILE,
- #[doc = "0xdc - General purpose storage register"]
- pub regfile55: REGFILE,
- #[doc = "0xe0 - General purpose storage register"]
- pub regfile56: REGFILE,
- #[doc = "0xe4 - General purpose storage register"]
- pub regfile57: REGFILE,
- #[doc = "0xe8 - General purpose storage register"]
- pub regfile58: REGFILE,
- #[doc = "0xec - General purpose storage register"]
- pub regfile59: REGFILE,
- #[doc = "0xf0 - General purpose storage register"]
- pub regfile60: REGFILE,
- #[doc = "0xf4 - General purpose storage register"]
- pub regfile61: REGFILE,
- #[doc = "0xf8 - General purpose storage register"]
- pub regfile62: REGFILE,
- #[doc = "0xfc - General purpose storage register"]
- pub regfile63: REGFILE,
+ #[doc = "0x00 - General purpose storage register"] pub regfile0: REGFILE,
+ #[doc = "0x04 - General purpose storage register"] pub regfile1: REGFILE,
+ #[doc = "0x08 - General purpose storage register"] pub regfile2: REGFILE,
+ #[doc = "0x0c - General purpose storage register"] pub regfile3: REGFILE,
+ #[doc = "0x10 - General purpose storage register"] pub regfile4: REGFILE,
+ #[doc = "0x14 - General purpose storage register"] pub regfile5: REGFILE,
+ #[doc = "0x18 - General purpose storage register"] pub regfile6: REGFILE,
+ #[doc = "0x1c - General purpose storage register"] pub regfile7: REGFILE,
+ #[doc = "0x20 - General purpose storage register"] pub regfile8: REGFILE,
+ #[doc = "0x24 - General purpose storage register"] pub regfile9: REGFILE,
+ #[doc = "0x28 - General purpose storage register"] pub regfile10: REGFILE,
+ #[doc = "0x2c - General purpose storage register"] pub regfile11: REGFILE,
+ #[doc = "0x30 - General purpose storage register"] pub regfile12: REGFILE,
+ #[doc = "0x34 - General purpose storage register"] pub regfile13: REGFILE,
+ #[doc = "0x38 - General purpose storage register"] pub regfile14: REGFILE,
+ #[doc = "0x3c - General purpose storage register"] pub regfile15: REGFILE,
+ #[doc = "0x40 - General purpose storage register"] pub regfile16: REGFILE,
+ #[doc = "0x44 - General purpose storage register"] pub regfile17: REGFILE,
+ #[doc = "0x48 - General purpose storage register"] pub regfile18: REGFILE,
+ #[doc = "0x4c - General purpose storage register"] pub regfile19: REGFILE,
+ #[doc = "0x50 - General purpose storage register"] pub regfile20: REGFILE,
+ #[doc = "0x54 - General purpose storage register"] pub regfile21: REGFILE,
+ #[doc = "0x58 - General purpose storage register"] pub regfile22: REGFILE,
+ #[doc = "0x5c - General purpose storage register"] pub regfile23: REGFILE,
+ #[doc = "0x60 - General purpose storage register"] pub regfile24: REGFILE,
+ #[doc = "0x64 - General purpose storage register"] pub regfile25: REGFILE,
+ #[doc = "0x68 - General purpose storage register"] pub regfile26: REGFILE,
+ #[doc = "0x6c - General purpose storage register"] pub regfile27: REGFILE,
+ #[doc = "0x70 - General purpose storage register"] pub regfile28: REGFILE,
+ #[doc = "0x74 - General purpose storage register"] pub regfile29: REGFILE,
+ #[doc = "0x78 - General purpose storage register"] pub regfile30: REGFILE,
+ #[doc = "0x7c - General purpose storage register"] pub regfile31: REGFILE,
+ #[doc = "0x80 - General purpose storage register"] pub regfile32: REGFILE,
+ #[doc = "0x84 - General purpose storage register"] pub regfile33: REGFILE,
+ #[doc = "0x88 - General purpose storage register"] pub regfile34: REGFILE,
+ #[doc = "0x8c - General purpose storage register"] pub regfile35: REGFILE,
+ #[doc = "0x90 - General purpose storage register"] pub regfile36: REGFILE,
+ #[doc = "0x94 - General purpose storage register"] pub regfile37: REGFILE,
+ #[doc = "0x98 - General purpose storage register"] pub regfile38: REGFILE,
+ #[doc = "0x9c - General purpose storage register"] pub regfile39: REGFILE,
+ #[doc = "0xa0 - General purpose storage register"] pub regfile40: REGFILE,
+ #[doc = "0xa4 - General purpose storage register"] pub regfile41: REGFILE,
+ #[doc = "0xa8 - General purpose storage register"] pub regfile42: REGFILE,
+ #[doc = "0xac - General purpose storage register"] pub regfile43: REGFILE,
+ #[doc = "0xb0 - General purpose storage register"] pub regfile44: REGFILE,
+ #[doc = "0xb4 - General purpose storage register"] pub regfile45: REGFILE,
+ #[doc = "0xb8 - General purpose storage register"] pub regfile46: REGFILE,
+ #[doc = "0xbc - General purpose storage register"] pub regfile47: REGFILE,
+ #[doc = "0xc0 - General purpose storage register"] pub regfile48: REGFILE,
+ #[doc = "0xc4 - General purpose storage register"] pub regfile49: REGFILE,
+ #[doc = "0xc8 - General purpose storage register"] pub regfile50: REGFILE,
+ #[doc = "0xcc - General purpose storage register"] pub regfile51: REGFILE,
+ #[doc = "0xd0 - General purpose storage register"] pub regfile52: REGFILE,
+ #[doc = "0xd4 - General purpose storage register"] pub regfile53: REGFILE,
+ #[doc = "0xd8 - General purpose storage register"] pub regfile54: REGFILE,
+ #[doc = "0xdc - General purpose storage register"] pub regfile55: REGFILE,
+ #[doc = "0xe0 - General purpose storage register"] pub regfile56: REGFILE,
+ #[doc = "0xe4 - General purpose storage register"] pub regfile57: REGFILE,
+ #[doc = "0xe8 - General purpose storage register"] pub regfile58: REGFILE,
+ #[doc = "0xec - General purpose storage register"] pub regfile59: REGFILE,
+ #[doc = "0xf0 - General purpose storage register"] pub regfile60: REGFILE,
+ #[doc = "0xf4 - General purpose storage register"] pub regfile61: REGFILE,
+ #[doc = "0xf8 - General purpose storage register"] pub regfile62: REGFILE,
+ #[doc = "0xfc - General purpose storage register"] pub regfile63: REGFILE,
}
#[doc = "General purpose storage register"]
pub struct REGFILE {
@@ -107811,8 +103918,7 @@ pub mod pmc {
#[doc = "0x00 - Hardware sleep event enable register"]
pub pd0_sleep0_hw_ena: PD0_SLEEP0_HW_ENA,
_reserved0: [u8; 24usize],
- #[doc = "0x1c - Sleep power mode register"]
- pub pd0_sleep0_mode: PD0_SLEEP0_MODE,
+ #[doc = "0x1c - Sleep power mode register"] pub pd0_sleep0_mode: PD0_SLEEP0_MODE,
}
#[doc = "Hardware sleep event enable register"]
pub struct PD0_SLEEP0_HW_ENA {
@@ -107958,8 +104064,7 @@ pub mod pmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Writing a 1 enables the Cortex-M4 core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 enables the Cortex-M4 core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register." ] # [ inline ( always ) ]
pub fn ena_event0(&self) -> ENA_EVENT0R {
let bits = {
const MASK: bool = true;
@@ -107968,8 +104073,7 @@ pub mod pmc {
};
ENA_EVENT0R { bits }
}
- #[doc = "Bit 1 - Writing a 1 enables the Cortex-M0 core and the Cortex-M0 subsystem core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 enables the Cortex-M0 core and the Cortex-M0 subsystem core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register." ] # [ inline ( always ) ]
pub fn ena_event1(&self) -> ENA_EVENT1R {
let bits = {
const MASK: bool = true;
@@ -107991,13 +104095,11 @@ pub mod pmc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 enables the Cortex-M4 core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 enables the Cortex-M4 core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register." ] # [ inline ( always ) ]
pub fn ena_event0(&mut self) -> _ENA_EVENT0W {
_ENA_EVENT0W { w: self }
}
- #[doc = "Bit 1 - Writing a 1 enables the Cortex-M0 core and the Cortex-M0 subsystem core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 enables the Cortex-M0 core and the Cortex-M0 subsystem core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register." ] # [ inline ( always ) ]
pub fn ena_event1(&mut self) -> _ENA_EVENT1W {
_ENA_EVENT1W { w: self }
}
@@ -108085,8 +104187,7 @@ pub mod pmc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Selects between Deep-sleep, Power-down, and Deep power-down modes. Only one of the following three values can be programmed in this register: 0x0030 00AA = Deep-sleep mode 0x0030 FCBA = Power-down mode 0x0030 3CBA = Power-down mode with M0SUB SRAM maintained 0x0030 FF7F = Deep power-down mode"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Selects between Deep-sleep, Power-down, and Deep power-down modes. Only one of the following three values can be programmed in this register: 0x0030 00AA = Deep-sleep mode 0x0030 FCBA = Power-down mode 0x0030 3CBA = Power-down mode with M0SUB SRAM maintained 0x0030 FF7F = Deep power-down mode" ] # [ inline ( always ) ]
pub fn pwr_state(&self) -> PWR_STATER {
let bits = {
const MASK: u32 = 4294967295;
@@ -108108,8 +104209,7 @@ pub mod pmc {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Selects between Deep-sleep, Power-down, and Deep power-down modes. Only one of the following three values can be programmed in this register: 0x0030 00AA = Deep-sleep mode 0x0030 FCBA = Power-down mode 0x0030 3CBA = Power-down mode with M0SUB SRAM maintained 0x0030 FF7F = Deep power-down mode"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Selects between Deep-sleep, Power-down, and Deep power-down modes. Only one of the following three values can be programmed in this register: 0x0030 00AA = Deep-sleep mode 0x0030 FCBA = Power-down mode 0x0030 3CBA = Power-down mode with M0SUB SRAM maintained 0x0030 FF7F = Deep power-down mode" ] # [ inline ( always ) ]
pub fn pwr_state(&mut self) -> _PWR_STATEW {
_PWR_STATEW { w: self }
}
@@ -108133,44 +104233,7 @@ pub mod creg {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- _reserved0: [u8; 4usize],
- #[doc = "0x04 - Chip configuration register 32 kHz oscillator output and BOD control register."]
- pub creg0: CREG0,
- _reserved1: [u8; 248usize],
- #[doc = "0x100 - ARM Cortex-M4 memory mapping"] pub m4memmap: M4MEMMAP,
- _reserved2: [u8; 20usize],
- #[doc = "0x118 - Chip configuration register 5. Controls JTAG access."]
- pub creg5: CREG5,
- #[doc = "0x11c - DMA mux control"] pub dmamux: DMAMUX,
- #[doc = "0x120 - Flash accelerator configuration register for flash bank A"]
- pub flashcfga: FLASHCFGA,
- #[doc = "0x124 - Flash accelerator configuration register for flash bank B"]
- pub flashcfgb: FLASHCFGB,
- #[doc = "0x128 - ETB RAM configuration"] pub etbcfg: ETBCFG,
- #[doc = "0x12c - Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock."]
- pub creg6: CREG6,
- #[doc = "0x130 - Cortex-M4 TXEV event clear"] pub m4txevent: M4TXEVENT,
- _reserved3: [u8; 204usize],
- #[doc = "0x200 - Part ID"] pub chipid: CHIPID,
- _reserved4: [u8; 260usize],
- #[doc = "0x308 - ARM Cortex-M0SUB memory mapping"]
- pub m0submemmap: M0SUBMEMMAP,
- _reserved5: [u8; 8usize],
- #[doc = "0x314 - Cortex-M0SUB TXEV event clear"]
- pub m0subtxevent: M0SUBTXEVENT,
- _reserved6: [u8; 232usize],
- #[doc = "0x400 - Cortex-M0APP TXEV event clear"]
- pub m0apptxevent: M0APPTXEVENT,
- #[doc = "0x404 - ARM Cortex-M0APP memory mapping"]
- pub m0appmemmap: M0APPMEMMAP,
- _reserved7: [u8; 248usize],
- #[doc = "0x500 - USB0 frame length adjust register"]
- pub usb0fladj: USB0FLADJ,
- _reserved8: [u8; 252usize],
- #[doc = "0x600 - USB1 frame length adjust register"]
- pub usb1fladj: USB1FLADJ,
- }
+ pub struct RegisterBlock { _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x04 - Chip configuration register 32 kHz oscillator output and BOD control register." ] pub creg0 : CREG0 , _reserved1 : [ u8 ; 248usize ] , # [ doc = "0x100 - ARM Cortex-M4 memory mapping" ] pub m4memmap : M4MEMMAP , _reserved2 : [ u8 ; 20usize ] , # [ doc = "0x118 - Chip configuration register 5. Controls JTAG access." ] pub creg5 : CREG5 , # [ doc = "0x11c - DMA mux control" ] pub dmamux : DMAMUX , # [ doc = "0x120 - Flash accelerator configuration register for flash bank A" ] pub flashcfga : FLASHCFGA , # [ doc = "0x124 - Flash accelerator configuration register for flash bank B" ] pub flashcfgb : FLASHCFGB , # [ doc = "0x128 - ETB RAM configuration" ] pub etbcfg : ETBCFG , # [ doc = "0x12c - Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." ] pub creg6 : CREG6 , # [ doc = "0x130 - Cortex-M4 TXEV event clear" ] pub m4txevent : M4TXEVENT , _reserved3 : [ u8 ; 204usize ] , # [ doc = "0x200 - Part ID" ] pub chipid : CHIPID , _reserved4 : [ u8 ; 260usize ] , # [ doc = "0x308 - ARM Cortex-M0SUB memory mapping" ] pub m0submemmap : M0SUBMEMMAP , _reserved5 : [ u8 ; 8usize ] , # [ doc = "0x314 - Cortex-M0SUB TXEV event clear" ] pub m0subtxevent : M0SUBTXEVENT , _reserved6 : [ u8 ; 232usize ] , # [ doc = "0x400 - Cortex-M0APP TXEV event clear" ] pub m0apptxevent : M0APPTXEVENT , # [ doc = "0x404 - ARM Cortex-M0APP memory mapping" ] pub m0appmemmap : M0APPMEMMAP , _reserved7 : [ u8 ; 248usize ] , # [ doc = "0x500 - USB0 frame length adjust register" ] pub usb0fladj : USB0FLADJ , _reserved8 : [ u8 ; 252usize ] , # [ doc = "0x600 - USB1 frame length adjust register" ] pub usb1fladj : USB1FLADJ , }
#[doc = "Chip configuration register 32 kHz oscillator output and BOD control register."]
pub struct CREG0 {
register: VolatileCell<u32>,
@@ -108597,8 +104660,7 @@ pub mod creg {
#[doc = "Possible values of the field `SAMPLECTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAMPLECTRLR {
- #[doc = "Sample output from the event monitor/recorder."]
- SAMPLE_OUTPUT_FROM_T,
+ #[doc = "Sample output from the event monitor/recorder."] SAMPLE_OUTPUT_FROM_T,
#[doc = "Output from the event router."] OUTPUT_FROM_THE_EVEN,
}
impl SAMPLECTRLR {
@@ -109178,8 +105240,7 @@ pub mod creg {
}
#[doc = "Values that can be written to the field `SAMPLECTRL`"]
pub enum SAMPLECTRLW {
- #[doc = "Sample output from the event monitor/recorder."]
- SAMPLE_OUTPUT_FROM_T,
+ #[doc = "Sample output from the event monitor/recorder."] SAMPLE_OUTPUT_FROM_T,
#[doc = "Output from the event router."] OUTPUT_FROM_THE_EVEN,
}
impl SAMPLECTRLW {
@@ -109389,8 +105450,7 @@ pub mod creg {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 8:9 - BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values." ] # [ inline ( always ) ]
pub fn bodlvl1(&self) -> BODLVL1R {
BODLVL1R::_from({
const MASK: u8 = 3;
@@ -109398,8 +105458,7 @@ pub mod creg {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 10:11 - BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values." ] # [ inline ( always ) ]
pub fn bodlvl2(&self) -> BODLVL2R {
BODLVL2R::_from({
const MASK: u8 = 3;
@@ -109477,13 +105536,11 @@ pub mod creg {
pub fn alarmctrl(&mut self) -> _ALARMCTRLW {
_ALARMCTRLW { w: self }
}
- #[doc = "Bits 8:9 - BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values." ] # [ inline ( always ) ]
pub fn bodlvl1(&mut self) -> _BODLVL1W {
_BODLVL1W { w: self }
}
- #[doc = "Bits 10:11 - BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values." ] # [ inline ( always ) ]
pub fn bodlvl2(&mut self) -> _BODLVL2W {
_BODLVL2W { w: self }
}
@@ -109668,11 +105725,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `M0SUBTAPSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum M0SUBTAPSELR {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- DISABLE_JTAG_DEBUG,
- }
+ pub enum M0SUBTAPSELR {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] DISABLE_JTAG_DEBUG}
impl M0SUBTAPSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -109714,11 +105767,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `M4TAPSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum M4TAPSELR {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- DISABLE_JTAG_DEBUG,
- }
+ pub enum M4TAPSELR {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] DISABLE_JTAG_DEBUG}
impl M4TAPSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -109760,11 +105809,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `M0APPTAPSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum M0APPTAPSELR {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- DISABLE_JTAG_DEBUG,
- }
+ pub enum M0APPTAPSELR {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] DISABLE_JTAG_DEBUG}
impl M0APPTAPSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -109805,11 +105850,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `M0SUBTAPSEL`"]
- pub enum M0SUBTAPSELW {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- DISABLE_JTAG_DEBUG,
- }
+ pub enum M0SUBTAPSELW {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] DISABLE_JTAG_DEBUG}
impl M0SUBTAPSELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -109838,8 +105879,7 @@ pub mod creg {
pub fn no_effect(self) -> &'a mut W {
self.variant(M0SUBTAPSELW::NO_EFFECT)
}
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- #[inline(always)]
+ # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] # [ inline ( always ) ]
pub fn disable_jtag_debug(self) -> &'a mut W {
self.variant(M0SUBTAPSELW::DISABLE_JTAG_DEBUG)
}
@@ -109862,11 +105902,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `M4TAPSEL`"]
- pub enum M4TAPSELW {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- DISABLE_JTAG_DEBUG,
- }
+ pub enum M4TAPSELW {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] DISABLE_JTAG_DEBUG}
impl M4TAPSELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -109895,8 +105931,7 @@ pub mod creg {
pub fn no_effect(self) -> &'a mut W {
self.variant(M4TAPSELW::NO_EFFECT)
}
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- #[inline(always)]
+ # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] # [ inline ( always ) ]
pub fn disable_jtag_debug(self) -> &'a mut W {
self.variant(M4TAPSELW::DISABLE_JTAG_DEBUG)
}
@@ -109919,11 +105954,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `M0APPTAPSEL`"]
- pub enum M0APPTAPSELW {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- DISABLE_JTAG_DEBUG,
- }
+ pub enum M0APPTAPSELW {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] DISABLE_JTAG_DEBUG}
impl M0APPTAPSELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -109952,8 +105983,7 @@ pub mod creg {
pub fn no_effect(self) -> &'a mut W {
self.variant(M0APPTAPSELW::NO_EFFECT)
}
- #[doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source."]
- #[inline(always)]
+ # [ doc = "Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." ] # [ inline ( always ) ]
pub fn disable_jtag_debug(self) -> &'a mut W {
self.variant(M0APPTAPSELW::DISABLE_JTAG_DEBUG)
}
@@ -109981,8 +106011,7 @@ pub mod creg {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 10 - JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."]
- #[inline(always)]
+ # [ doc = "Bit 10 - JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset." ] # [ inline ( always ) ]
pub fn m0subtapsel(&self) -> M0SUBTAPSELR {
M0SUBTAPSELR::_from({
const MASK: bool = true;
@@ -109990,8 +106019,7 @@ pub mod creg {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 11 - JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."]
- #[inline(always)]
+ # [ doc = "Bit 11 - JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset." ] # [ inline ( always ) ]
pub fn m4tapsel(&self) -> M4TAPSELR {
M4TAPSELR::_from({
const MASK: bool = true;
@@ -109999,8 +106027,7 @@ pub mod creg {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 12 - JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."]
- #[inline(always)]
+ # [ doc = "Bit 12 - JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset." ] # [ inline ( always ) ]
pub fn m0apptapsel(&self) -> M0APPTAPSELR {
M0APPTAPSELR::_from({
const MASK: bool = true;
@@ -110021,18 +106048,15 @@ pub mod creg {
self.bits = bits;
self
}
- #[doc = "Bit 10 - JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."]
- #[inline(always)]
+ # [ doc = "Bit 10 - JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset." ] # [ inline ( always ) ]
pub fn m0subtapsel(&mut self) -> _M0SUBTAPSELW {
_M0SUBTAPSELW { w: self }
}
- #[doc = "Bit 11 - JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."]
- #[inline(always)]
+ # [ doc = "Bit 11 - JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset." ] # [ inline ( always ) ]
pub fn m4tapsel(&mut self) -> _M4TAPSELW {
_M4TAPSELW { w: self }
}
- #[doc = "Bit 12 - JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset."]
- #[inline(always)]
+ # [ doc = "Bit 12 - JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset." ] # [ inline ( always ) ]
pub fn m0apptapsel(&mut self) -> _M0APPTAPSELW {
_M0APPTAPSELW { w: self }
}
@@ -112043,29 +108067,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `FLASHTIM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum FLASHTIMR {
- #[doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz."]
- _1_BASE_M4_CLK_CLOCK,
- #[doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz."]
- _2_BASE_M4_CLK_CLOCKS,
- #[doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz."]
- _3_BASE_M4_CLK_CLOCKS,
- #[doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz."]
- _4_BASE_M4_CLK_CLOCKS,
- #[doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz."]
- _5_BASE_M4_CLK_CLOCKS,
- #[doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz."]
- _6_BASE_M4_CLK_CLOCKS,
- #[doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz."]
- _7_BASE_M4_CLK_CLOCKS,
- #[doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz."]
- _8_BASE_M4_CLK_CLOCKS,
- #[doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz."]
- _9_BASE_M4_CLK_CLOCKS,
- #[doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions."]
- _10_BASE_M4_CLK_CLOCK,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum FLASHTIMR {# [ doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." ] _1_BASE_M4_CLK_CLOCK , # [ doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." ] _2_BASE_M4_CLK_CLOCKS , # [ doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." ] _3_BASE_M4_CLK_CLOCKS , # [ doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." ] _4_BASE_M4_CLK_CLOCKS , # [ doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." ] _5_BASE_M4_CLK_CLOCKS , # [ doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." ] _6_BASE_M4_CLK_CLOCKS , # [ doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." ] _7_BASE_M4_CLK_CLOCKS , # [ doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." ] _8_BASE_M4_CLK_CLOCKS , # [ doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." ] _9_BASE_M4_CLK_CLOCKS , # [ doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." ] _10_BASE_M4_CLK_CLOCK , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl FLASHTIMR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -112199,28 +108201,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `FLASHTIM`"]
- pub enum FLASHTIMW {
- #[doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz."]
- _1_BASE_M4_CLK_CLOCK,
- #[doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz."]
- _2_BASE_M4_CLK_CLOCKS,
- #[doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz."]
- _3_BASE_M4_CLK_CLOCKS,
- #[doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz."]
- _4_BASE_M4_CLK_CLOCKS,
- #[doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz."]
- _5_BASE_M4_CLK_CLOCKS,
- #[doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz."]
- _6_BASE_M4_CLK_CLOCKS,
- #[doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz."]
- _7_BASE_M4_CLK_CLOCKS,
- #[doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz."]
- _8_BASE_M4_CLK_CLOCKS,
- #[doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz."]
- _9_BASE_M4_CLK_CLOCKS,
- #[doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions."]
- _10_BASE_M4_CLK_CLOCK,
- }
+ pub enum FLASHTIMW {# [ doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." ] _1_BASE_M4_CLK_CLOCK , # [ doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." ] _2_BASE_M4_CLK_CLOCKS , # [ doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." ] _3_BASE_M4_CLK_CLOCKS , # [ doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." ] _4_BASE_M4_CLK_CLOCKS , # [ doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." ] _5_BASE_M4_CLK_CLOCKS , # [ doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." ] _6_BASE_M4_CLK_CLOCKS , # [ doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." ] _7_BASE_M4_CLK_CLOCKS , # [ doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." ] _8_BASE_M4_CLK_CLOCKS , # [ doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." ] _9_BASE_M4_CLK_CLOCKS , # [ doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." ] _10_BASE_M4_CLK_CLOCK}
impl FLASHTIMW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -112295,8 +108276,7 @@ pub mod creg {
pub fn _9_base_m4_clk_clocks(self) -> &'a mut W {
self.variant(FLASHTIMW::_9_BASE_M4_CLK_CLOCKS)
}
- #[doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions."]
- #[inline(always)]
+ # [ doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." ] # [ inline ( always ) ]
pub fn _10_base_m4_clk_clock(self) -> &'a mut W {
self.variant(FLASHTIMW::_10_BASE_M4_CLK_CLOCK)
}
@@ -112372,8 +108352,7 @@ pub mod creg {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies." ] # [ inline ( always ) ]
pub fn flashtim(&self) -> FLASHTIMR {
FLASHTIMR::_from({
const MASK: u8 = 15;
@@ -112403,8 +108382,7 @@ pub mod creg {
self.bits = bits;
self
}
- #[doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies." ] # [ inline ( always ) ]
pub fn flashtim(&mut self) -> _FLASHTIMW {
_FLASHTIMW { w: self }
}
@@ -112467,29 +108445,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `FLASHTIM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum FLASHTIMR {
- #[doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz."]
- _1_BASE_M4_CLK_CLOCK,
- #[doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz."]
- _2_BASE_M4_CLK_CLOCKS,
- #[doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz."]
- _3_BASE_M4_CLK_CLOCKS,
- #[doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz."]
- _4_BASE_M4_CLK_CLOCKS,
- #[doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz."]
- _5_BASE_M4_CLK_CLOCKS,
- #[doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz."]
- _6_BASE_M4_CLK_CLOCKS,
- #[doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz."]
- _7_BASE_M4_CLK_CLOCKS,
- #[doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz."]
- _8_BASE_M4_CLK_CLOCKS,
- #[doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz."]
- _9_BASE_M4_CLK_CLOCKS,
- #[doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions."]
- _10_BASE_M4_CLK_CLOCK,
- #[doc = r" Reserved"] _Reserved(u8),
- }
+ pub enum FLASHTIMR {# [ doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." ] _1_BASE_M4_CLK_CLOCK , # [ doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." ] _2_BASE_M4_CLK_CLOCKS , # [ doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." ] _3_BASE_M4_CLK_CLOCKS , # [ doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." ] _4_BASE_M4_CLK_CLOCKS , # [ doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." ] _5_BASE_M4_CLK_CLOCKS , # [ doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." ] _6_BASE_M4_CLK_CLOCKS , # [ doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." ] _7_BASE_M4_CLK_CLOCKS , # [ doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." ] _8_BASE_M4_CLK_CLOCKS , # [ doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." ] _9_BASE_M4_CLK_CLOCKS , # [ doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." ] _10_BASE_M4_CLK_CLOCK , # [ doc = r" Reserved" ] _Reserved ( u8 )}
impl FLASHTIMR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -112623,28 +108579,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `FLASHTIM`"]
- pub enum FLASHTIMW {
- #[doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz."]
- _1_BASE_M4_CLK_CLOCK,
- #[doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz."]
- _2_BASE_M4_CLK_CLOCKS,
- #[doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz."]
- _3_BASE_M4_CLK_CLOCKS,
- #[doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz."]
- _4_BASE_M4_CLK_CLOCKS,
- #[doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz."]
- _5_BASE_M4_CLK_CLOCKS,
- #[doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz."]
- _6_BASE_M4_CLK_CLOCKS,
- #[doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz."]
- _7_BASE_M4_CLK_CLOCKS,
- #[doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz."]
- _8_BASE_M4_CLK_CLOCKS,
- #[doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz."]
- _9_BASE_M4_CLK_CLOCKS,
- #[doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions."]
- _10_BASE_M4_CLK_CLOCK,
- }
+ pub enum FLASHTIMW {# [ doc = "1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." ] _1_BASE_M4_CLK_CLOCK , # [ doc = "2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." ] _2_BASE_M4_CLK_CLOCKS , # [ doc = "3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." ] _3_BASE_M4_CLK_CLOCKS , # [ doc = "4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." ] _4_BASE_M4_CLK_CLOCKS , # [ doc = "5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." ] _5_BASE_M4_CLK_CLOCKS , # [ doc = "6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." ] _6_BASE_M4_CLK_CLOCKS , # [ doc = "7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." ] _7_BASE_M4_CLK_CLOCKS , # [ doc = "8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." ] _8_BASE_M4_CLK_CLOCKS , # [ doc = "9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." ] _9_BASE_M4_CLK_CLOCKS , # [ doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." ] _10_BASE_M4_CLK_CLOCK}
impl FLASHTIMW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -112719,8 +108654,7 @@ pub mod creg {
pub fn _9_base_m4_clk_clocks(self) -> &'a mut W {
self.variant(FLASHTIMW::_9_BASE_M4_CLK_CLOCKS)
}
- #[doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions."]
- #[inline(always)]
+ # [ doc = "10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." ] # [ inline ( always ) ]
pub fn _10_base_m4_clk_clock(self) -> &'a mut W {
self.variant(FLASHTIMW::_10_BASE_M4_CLK_CLOCK)
}
@@ -112796,8 +108730,7 @@ pub mod creg {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies." ] # [ inline ( always ) ]
pub fn flashtim(&self) -> FLASHTIMR {
FLASHTIMR::_from({
const MASK: u8 = 15;
@@ -112827,8 +108760,7 @@ pub mod creg {
self.bits = bits;
self
}
- #[doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies."]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies." ] # [ inline ( always ) ]
pub fn flashtim(&mut self) -> _FLASHTIMW {
_FLASHTIMW { w: self }
}
@@ -112892,10 +108824,8 @@ pub mod creg {
#[doc = "Possible values of the field `ETB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ETBR {
- #[doc = "ETB accesses SRAM at address 0x2000 C000."]
- ETB_ACCESSES_SRAM_AT,
- #[doc = "AHB accesses SRAM at address 0x2000 C000."]
- AHB_ACCESSES_SRAM_AT,
+ #[doc = "ETB accesses SRAM at address 0x2000 C000."] ETB_ACCESSES_SRAM_AT,
+ #[doc = "AHB accesses SRAM at address 0x2000 C000."] AHB_ACCESSES_SRAM_AT,
}
impl ETBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -112938,10 +108868,8 @@ pub mod creg {
}
#[doc = "Values that can be written to the field `ETB`"]
pub enum ETBW {
- #[doc = "ETB accesses SRAM at address 0x2000 C000."]
- ETB_ACCESSES_SRAM_AT,
- #[doc = "AHB accesses SRAM at address 0x2000 C000."]
- AHB_ACCESSES_SRAM_AT,
+ #[doc = "ETB accesses SRAM at address 0x2000 C000."] ETB_ACCESSES_SRAM_AT,
+ #[doc = "AHB accesses SRAM at address 0x2000 C000."] AHB_ACCESSES_SRAM_AT,
}
impl ETBW {
#[allow(missing_docs)]
@@ -113029,11 +108957,11 @@ pub mod creg {
}
}
}
- #[doc = "Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock."]
+ # [ doc = "Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." ]
pub struct CREG6 {
register: VolatileCell<u32>,
}
- #[doc = "Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock."]
+ # [ doc = "Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." ]
pub mod creg6 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -113166,12 +109094,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `I2S0_TX_SCK_IN_SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum I2S0_TX_SCK_IN_SELR {
- #[doc = "I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S0_TX_SCK_IN_SELR {# [ doc = "I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S0_TX_SCK_IN_SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -113213,12 +109136,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `I2S0_RX_SCK_IN_SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum I2S0_RX_SCK_IN_SELR {
- #[doc = "I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S0_RX_SCK_IN_SELR {# [ doc = "I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S0_RX_SCK_IN_SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -113260,12 +109178,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `I2S1_TX_SCK_IN_SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum I2S1_TX_SCK_IN_SELR {
- #[doc = "I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S1_TX_SCK_IN_SELR {# [ doc = "I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S1_TX_SCK_IN_SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -113307,12 +109220,7 @@ pub mod creg {
}
#[doc = "Possible values of the field `I2S1_RX_SCK_IN_SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum I2S1_RX_SCK_IN_SELR {
- #[doc = "I2S register. I2S clock selected as defined by the I2S receive mode register Table 961."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S1_RX_SCK_IN_SELR {# [ doc = "I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S1_RX_SCK_IN_SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -113502,12 +109410,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `I2S0_TX_SCK_IN_SEL`"]
- pub enum I2S0_TX_SCK_IN_SELW {
- #[doc = "I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S0_TX_SCK_IN_SELW {# [ doc = "I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S0_TX_SCK_IN_SELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -113531,13 +109434,11 @@ pub mod creg {
self.bit(variant._bits())
}
}
- #[doc = "I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960."]
- #[inline(always)]
+ # [ doc = "I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." ] # [ inline ( always ) ]
pub fn i2s_register(self) -> &'a mut W {
self.variant(I2S0_TX_SCK_IN_SELW::I2S_REGISTER)
}
- #[doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- #[inline(always)]
+ # [ doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] # [ inline ( always ) ]
pub fn base_audio_clk_for_i(self) -> &'a mut W {
self.variant(I2S0_TX_SCK_IN_SELW::BASE_AUDIO_CLK_FOR_I)
}
@@ -113560,12 +109461,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `I2S0_RX_SCK_IN_SEL`"]
- pub enum I2S0_RX_SCK_IN_SELW {
- #[doc = "I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S0_RX_SCK_IN_SELW {# [ doc = "I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S0_RX_SCK_IN_SELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -113589,13 +109485,11 @@ pub mod creg {
self.bit(variant._bits())
}
}
- #[doc = "I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961."]
- #[inline(always)]
+ # [ doc = "I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." ] # [ inline ( always ) ]
pub fn i2s_register(self) -> &'a mut W {
self.variant(I2S0_RX_SCK_IN_SELW::I2S_REGISTER)
}
- #[doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- #[inline(always)]
+ # [ doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] # [ inline ( always ) ]
pub fn base_audio_clk_for_i(self) -> &'a mut W {
self.variant(I2S0_RX_SCK_IN_SELW::BASE_AUDIO_CLK_FOR_I)
}
@@ -113618,12 +109512,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `I2S1_TX_SCK_IN_SEL`"]
- pub enum I2S1_TX_SCK_IN_SELW {
- #[doc = "I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S1_TX_SCK_IN_SELW {# [ doc = "I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S1_TX_SCK_IN_SELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -113647,13 +109536,11 @@ pub mod creg {
self.bit(variant._bits())
}
}
- #[doc = "I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960."]
- #[inline(always)]
+ # [ doc = "I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." ] # [ inline ( always ) ]
pub fn i2s_register(self) -> &'a mut W {
self.variant(I2S1_TX_SCK_IN_SELW::I2S_REGISTER)
}
- #[doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- #[inline(always)]
+ # [ doc = "BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] # [ inline ( always ) ]
pub fn base_audio_clk_for_i(self) -> &'a mut W {
self.variant(I2S1_TX_SCK_IN_SELW::BASE_AUDIO_CLK_FOR_I)
}
@@ -113676,12 +109563,7 @@ pub mod creg {
}
}
#[doc = "Values that can be written to the field `I2S1_RX_SCK_IN_SEL`"]
- pub enum I2S1_RX_SCK_IN_SELW {
- #[doc = "I2S register. I2S clock selected as defined by the I2S receive mode register Table 961."]
- I2S_REGISTER,
- #[doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- BASE_AUDIO_CLK_FOR_I,
- }
+ pub enum I2S1_RX_SCK_IN_SELW {# [ doc = "I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." ] I2S_REGISTER , # [ doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] BASE_AUDIO_CLK_FOR_I}
impl I2S1_RX_SCK_IN_SELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -113705,13 +109587,11 @@ pub mod creg {
self.bit(variant._bits())
}
}
- #[doc = "I2S register. I2S clock selected as defined by the I2S receive mode register Table 961."]
- #[inline(always)]
+ # [ doc = "I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." ] # [ inline ( always ) ]
pub fn i2s_register(self) -> &'a mut W {
self.variant(I2S1_RX_SCK_IN_SELW::I2S_REGISTER)
}
- #[doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode."]
- #[inline(always)]
+ # [ doc = "BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." ] # [ inline ( always ) ]
pub fn base_audio_clk_for_i(self) -> &'a mut W {
self.variant(I2S1_RX_SCK_IN_SELW::BASE_AUDIO_CLK_FOR_I)
}
@@ -113795,8 +109675,7 @@ pub mod creg {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:2 - Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved." ] # [ inline ( always ) ]
pub fn ethmode(&self) -> ETHMODER {
ETHMODER::_from({
const MASK: u8 = 7;
@@ -113871,8 +109750,7 @@ pub mod creg {
self.bits = bits;
self
}
- #[doc = "Bits 0:2 - Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved." ] # [ inline ( always ) ]
pub fn ethmode(&mut self) -> _ETHMODEW {
_ETHMODEW { w: self }
}
@@ -114130,8 +110008,7 @@ pub mod creg {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)" ] # [ inline ( always ) ]
pub fn id(&self) -> IDR {
let bits = {
const MASK: u32 = 4294967295;
@@ -114820,8 +110697,7 @@ pub mod creg {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" ] # [ inline ( always ) ]
pub fn fltv(&self) -> FLTVR {
let bits = {
const MASK: u8 = 63;
@@ -114843,8 +110719,7 @@ pub mod creg {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" ] # [ inline ( always ) ]
pub fn fltv(&mut self) -> _FLTVW {
_FLTVW { w: self }
}
@@ -114932,8 +110807,7 @@ pub mod creg {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" ] # [ inline ( always ) ]
pub fn fltv(&self) -> FLTVR {
let bits = {
const MASK: u8 = 63;
@@ -114955,8 +110829,7 @@ pub mod creg {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" ] # [ inline ( always ) ]
pub fn fltv(&mut self) -> _FLTVW {
_FLTVW { w: self }
}
@@ -114974,8 +110847,7 @@ impl Deref for CREG {
}
}
#[doc = "Event router"]
-pub const EVENTROUTER: Peripheral<EVENTROUTER> =
- unsafe { Peripheral::new(1074020352) };
+pub const EVENTROUTER: Peripheral<EVENTROUTER> = unsafe { Peripheral::new(1074020352) };
#[doc = "Event router"]
pub mod eventrouter {
use vcell::VolatileCell;
@@ -115044,12 +110916,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP0_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP0_LR {
- #[doc = "Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP0_LR {# [ doc = "Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP0_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115091,12 +110958,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP1_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP1_LR {
- #[doc = "Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP1_LR {# [ doc = "Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP1_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115138,12 +111000,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP2_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP2_LR {
- #[doc = "Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP2_LR {# [ doc = "Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP2_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115185,12 +111042,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP3_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP3_LR {
- #[doc = "Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP3_LR {# [ doc = "Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP3_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115232,12 +111084,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `ATIMER_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ATIMER_LR {
- #[doc = "Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum ATIMER_LR {# [ doc = "Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl ATIMER_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115279,12 +111126,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `RTC_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RTC_LR {
- #[doc = "Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum RTC_LR {# [ doc = "Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl RTC_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115326,12 +111168,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `BOD_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BOD_LR {
- #[doc = "Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum BOD_LR {# [ doc = "Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl BOD_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115373,12 +111210,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WWDT_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WWDT_LR {
- #[doc = "Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WWDT_LR {# [ doc = "Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WWDT_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115420,12 +111252,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `ETH_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ETH_LR {
- #[doc = "Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum ETH_LR {# [ doc = "Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl ETH_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115467,12 +111294,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `USB0_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum USB0_LR {
- #[doc = "Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum USB0_LR {# [ doc = "Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl USB0_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115514,12 +111336,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `USB1_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum USB1_LR {
- #[doc = "Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum USB1_LR {# [ doc = "Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl USB1_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115561,12 +111378,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `SDMMC_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SDMMC_LR {
- #[doc = "Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum SDMMC_LR {# [ doc = "Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl SDMMC_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115608,12 +111420,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `CAN_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAN_LR {
- #[doc = "Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum CAN_LR {# [ doc = "Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl CAN_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115655,12 +111462,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `TIM2_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TIM2_LR {
- #[doc = "Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum TIM2_LR {# [ doc = "Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl TIM2_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115702,12 +111504,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `TIM6_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TIM6_LR {
- #[doc = "Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum TIM6_LR {# [ doc = "Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl TIM6_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115749,12 +111546,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `QEI_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum QEI_LR {
- #[doc = "Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum QEI_LR {# [ doc = "Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl QEI_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115796,12 +111588,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `TIM14_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TIM14_LR {
- #[doc = "Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum TIM14_LR {# [ doc = "Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl TIM14_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115843,12 +111630,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `RESET_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RESET_LR {
- #[doc = "Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1."]
- DETECT_LOW_LEVEL_IF,
- #[doc = "Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL_IF,
- }
+ pub enum RESET_LR {# [ doc = "Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." ] DETECT_LOW_LEVEL_IF , # [ doc = "Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." ] DETECT_HIGH_LEVEL_IF}
impl RESET_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115890,12 +111672,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `BODRESET_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BODRESET_LR {
- #[doc = "Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1."]
- DETECT_LOW_LEVEL_IF,
- #[doc = "Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL_IF,
- }
+ pub enum BODRESET_LR {# [ doc = "Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." ] DETECT_LOW_LEVEL_IF , # [ doc = "Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." ] DETECT_HIGH_LEVEL_IF}
impl BODRESET_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115937,12 +111714,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `DPDRESET_L`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DPDRESET_LR {
- #[doc = "Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1."]
- DETECT_LOW_LEVEL_IF,
- #[doc = "Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL_IF,
- }
+ pub enum DPDRESET_LR {# [ doc = "Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." ] DETECT_LOW_LEVEL_IF , # [ doc = "Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." ] DETECT_HIGH_LEVEL_IF}
impl DPDRESET_LR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -115983,12 +111755,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP0_L`"]
- pub enum WAKEUP0_LW {
- #[doc = "Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP0_LW {# [ doc = "Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP0_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116012,13 +111779,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(WAKEUP0_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(WAKEUP0_LW::DETECT_HIGH_LEVEL)
}
@@ -116041,12 +111806,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP1_L`"]
- pub enum WAKEUP1_LW {
- #[doc = "Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP1_LW {# [ doc = "Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP1_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116075,8 +111835,7 @@ pub mod eventrouter {
pub fn detect_low_level(self) -> &'a mut W {
self.variant(WAKEUP1_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(WAKEUP1_LW::DETECT_HIGH_LEVEL)
}
@@ -116099,12 +111858,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP2_L`"]
- pub enum WAKEUP2_LW {
- #[doc = "Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP2_LW {# [ doc = "Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP2_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116128,13 +111882,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(WAKEUP2_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(WAKEUP2_LW::DETECT_HIGH_LEVEL)
}
@@ -116157,12 +111909,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP3_L`"]
- pub enum WAKEUP3_LW {
- #[doc = "Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WAKEUP3_LW {# [ doc = "Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WAKEUP3_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116186,13 +111933,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(WAKEUP3_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(WAKEUP3_LW::DETECT_HIGH_LEVEL)
}
@@ -116215,12 +111960,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `ATIMER_L`"]
- pub enum ATIMER_LW {
- #[doc = "Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum ATIMER_LW {# [ doc = "Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl ATIMER_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116244,13 +111984,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(ATIMER_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(ATIMER_LW::DETECT_HIGH_LEVEL)
}
@@ -116273,12 +112011,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `RTC_L`"]
- pub enum RTC_LW {
- #[doc = "Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum RTC_LW {# [ doc = "Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl RTC_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116302,13 +112035,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(RTC_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(RTC_LW::DETECT_HIGH_LEVEL)
}
@@ -116331,12 +112062,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `BOD_L`"]
- pub enum BOD_LW {
- #[doc = "Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum BOD_LW {# [ doc = "Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl BOD_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116360,13 +112086,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(BOD_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(BOD_LW::DETECT_HIGH_LEVEL)
}
@@ -116389,12 +112113,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WWDT_L`"]
- pub enum WWDT_LW {
- #[doc = "Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum WWDT_LW {# [ doc = "Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl WWDT_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116418,13 +112137,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(WWDT_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(WWDT_LW::DETECT_HIGH_LEVEL)
}
@@ -116447,12 +112164,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `ETH_L`"]
- pub enum ETH_LW {
- #[doc = "Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum ETH_LW {# [ doc = "Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl ETH_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116476,13 +112188,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(ETH_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(ETH_LW::DETECT_HIGH_LEVEL)
}
@@ -116505,12 +112215,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `USB0_L`"]
- pub enum USB0_LW {
- #[doc = "Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum USB0_LW {# [ doc = "Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl USB0_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116534,13 +112239,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(USB0_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(USB0_LW::DETECT_HIGH_LEVEL)
}
@@ -116563,12 +112266,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `USB1_L`"]
- pub enum USB1_LW {
- #[doc = "Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum USB1_LW {# [ doc = "Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl USB1_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116592,13 +112290,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(USB1_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(USB1_LW::DETECT_HIGH_LEVEL)
}
@@ -116621,12 +112317,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `SDMMC_L`"]
- pub enum SDMMC_LW {
- #[doc = "Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum SDMMC_LW {# [ doc = "Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl SDMMC_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116650,13 +112341,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(SDMMC_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(SDMMC_LW::DETECT_HIGH_LEVEL)
}
@@ -116679,12 +112368,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `CAN_L`"]
- pub enum CAN_LW {
- #[doc = "Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum CAN_LW {# [ doc = "Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl CAN_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116708,13 +112392,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(CAN_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(CAN_LW::DETECT_HIGH_LEVEL)
}
@@ -116737,12 +112419,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `TIM2_L`"]
- pub enum TIM2_LW {
- #[doc = "Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum TIM2_LW {# [ doc = "Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl TIM2_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116766,13 +112443,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(TIM2_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(TIM2_LW::DETECT_HIGH_LEVEL)
}
@@ -116795,12 +112470,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `TIM6_L`"]
- pub enum TIM6_LW {
- #[doc = "Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum TIM6_LW {# [ doc = "Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl TIM6_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116824,13 +112494,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(TIM6_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(TIM6_LW::DETECT_HIGH_LEVEL)
}
@@ -116853,12 +112521,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `QEI_L`"]
- pub enum QEI_LW {
- #[doc = "Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum QEI_LW {# [ doc = "Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl QEI_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116882,13 +112545,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(QEI_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(QEI_LW::DETECT_HIGH_LEVEL)
}
@@ -116911,12 +112572,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `TIM14_L`"]
- pub enum TIM14_LW {
- #[doc = "Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1."]
- DETECT_LOW_LEVEL,
- #[doc = "Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL,
- }
+ pub enum TIM14_LW {# [ doc = "Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." ] DETECT_LOW_LEVEL , # [ doc = "Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." ] DETECT_HIGH_LEVEL}
impl TIM14_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116940,13 +112596,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level(self) -> &'a mut W {
self.variant(TIM14_LW::DETECT_LOW_LEVEL)
}
- #[doc = "Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level(self) -> &'a mut W {
self.variant(TIM14_LW::DETECT_HIGH_LEVEL)
}
@@ -116969,12 +112623,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `RESET_L`"]
- pub enum RESET_LW {
- #[doc = "Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1."]
- DETECT_LOW_LEVEL_IF,
- #[doc = "Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL_IF,
- }
+ pub enum RESET_LW {# [ doc = "Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." ] DETECT_LOW_LEVEL_IF , # [ doc = "Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." ] DETECT_HIGH_LEVEL_IF}
impl RESET_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -116998,13 +112647,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level_if(self) -> &'a mut W {
self.variant(RESET_LW::DETECT_LOW_LEVEL_IF)
}
- #[doc = "Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level_if(self) -> &'a mut W {
self.variant(RESET_LW::DETECT_HIGH_LEVEL_IF)
}
@@ -117027,12 +112674,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `BODRESET_L`"]
- pub enum BODRESET_LW {
- #[doc = "Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1."]
- DETECT_LOW_LEVEL_IF,
- #[doc = "Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL_IF,
- }
+ pub enum BODRESET_LW {# [ doc = "Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." ] DETECT_LOW_LEVEL_IF , # [ doc = "Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." ] DETECT_HIGH_LEVEL_IF}
impl BODRESET_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -117056,13 +112698,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level_if(self) -> &'a mut W {
self.variant(BODRESET_LW::DETECT_LOW_LEVEL_IF)
}
- #[doc = "Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level_if(self) -> &'a mut W {
self.variant(BODRESET_LW::DETECT_HIGH_LEVEL_IF)
}
@@ -117085,12 +112725,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `DPDRESET_L`"]
- pub enum DPDRESET_LW {
- #[doc = "Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1."]
- DETECT_LOW_LEVEL_IF,
- #[doc = "Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1."]
- DETECT_HIGH_LEVEL_IF,
- }
+ pub enum DPDRESET_LW {# [ doc = "Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." ] DETECT_LOW_LEVEL_IF , # [ doc = "Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." ] DETECT_HIGH_LEVEL_IF}
impl DPDRESET_LW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -117114,13 +112749,11 @@ pub mod eventrouter {
self.bit(variant._bits())
}
}
- #[doc = "Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_low_level_if(self) -> &'a mut W {
self.variant(DPDRESET_LW::DETECT_LOW_LEVEL_IF)
}
- #[doc = "Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1."]
- #[inline(always)]
+ # [ doc = "Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." ] # [ inline ( always ) ]
pub fn detect_high_level_if(self) -> &'a mut W {
self.variant(DPDRESET_LW::DETECT_HIGH_LEVEL_IF)
}
@@ -117157,8 +112790,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup1_l(&self) -> WAKEUP1_LR {
WAKEUP1_LR::_from({
const MASK: bool = true;
@@ -117346,8 +112978,7 @@ pub mod eventrouter {
pub fn wakeup0_l(&mut self) -> _WAKEUP0_LW {
_WAKEUP0_LW { w: self }
}
- #[doc = "Bit 1 - Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup1_l(&mut self) -> _WAKEUP1_LW {
_WAKEUP1_LW { w: self }
}
@@ -117495,11 +113126,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP0_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP0_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP0_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP0_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117541,11 +113168,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP1_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP1_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP1_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP1_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117587,11 +113210,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP2_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP2_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP2_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP2_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117633,11 +113252,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WAKEUP3_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WAKEUP3_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP3_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP3_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117679,11 +113294,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `ATIMER_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ATIMER_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_A,
- }
+ pub enum ATIMER_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." ] EDGE_DETECT_OF_THE_A}
impl ATIMER_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117725,11 +113336,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `RTC_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RTC_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum RTC_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl RTC_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117771,11 +113378,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `BOD_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BOD_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_B,
- }
+ pub enum BOD_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." ] EDGE_DETECT_OF_THE_B}
impl BOD_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117817,11 +113420,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `WWDT_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WWDT_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_W,
- }
+ pub enum WWDT_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." ] EDGE_DETECT_OF_THE_W}
impl WWDT_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117863,11 +113462,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `ETH_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ETH_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_E,
- }
+ pub enum ETH_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." ] EDGE_DETECT_OF_THE_E}
impl ETH_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117909,11 +113504,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `USB0_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum USB0_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_U,
- }
+ pub enum USB0_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." ] EDGE_DETECT_OF_THE_U}
impl USB0_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -117955,11 +113546,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `USB1_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum USB1_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_U,
- }
+ pub enum USB1_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." ] EDGE_DETECT_OF_THE_U}
impl USB1_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118001,11 +113588,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `SDMMC_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SDMMC_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_S,
- }
+ pub enum SDMMC_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." ] EDGE_DETECT_OF_THE_S}
impl SDMMC_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118047,11 +113630,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `CAN_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAN_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_C,
- }
+ pub enum CAN_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." ] EDGE_DETECT_OF_THE_C}
impl CAN_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118093,11 +113672,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `TIM2_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TIM2_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1."]
- EDGE_DETECT_OF_GIMA,
- }
+ pub enum TIM2_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." ] EDGE_DETECT_OF_GIMA}
impl TIM2_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118139,11 +113714,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `TIM6_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TIM6_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1."]
- EDGE_DETECT_OF_GIMA,
- }
+ pub enum TIM6_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." ] EDGE_DETECT_OF_GIMA}
impl TIM6_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118185,11 +113756,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `QEI_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum QEI_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1."]
- EDGE_DETECT_OF_QEI_I,
- }
+ pub enum QEI_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." ] EDGE_DETECT_OF_QEI_I}
impl QEI_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118231,11 +113798,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `TIM14_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TIM14_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1."]
- EDGE_DETECT_OF_GIMA,
- }
+ pub enum TIM14_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." ] EDGE_DETECT_OF_GIMA}
impl TIM14_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118277,11 +113840,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `RESET_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RESET_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum RESET_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl RESET_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118323,11 +113882,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `BODRESET_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BODRESET_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum BODRESET_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl BODRESET_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118369,11 +113924,7 @@ pub mod eventrouter {
}
#[doc = "Possible values of the field `DPDRESET_E`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DPDRESET_ER {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum DPDRESET_ER {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl DPDRESET_ER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -118414,11 +113965,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP0_E`"]
- pub enum WAKEUP0_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP0_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP0_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118447,8 +113994,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(WAKEUP0_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_wakeu(self) -> &'a mut W {
self.variant(WAKEUP0_EW::EDGE_DETECT_OF_WAKEU)
}
@@ -118471,11 +114017,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP1_E`"]
- pub enum WAKEUP1_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP1_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP1_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118504,8 +114046,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(WAKEUP1_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_wakeu(self) -> &'a mut W {
self.variant(WAKEUP1_EW::EDGE_DETECT_OF_WAKEU)
}
@@ -118528,11 +114069,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP2_E`"]
- pub enum WAKEUP2_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP2_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP2_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118561,8 +114098,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(WAKEUP2_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_wakeu(self) -> &'a mut W {
self.variant(WAKEUP2_EW::EDGE_DETECT_OF_WAKEU)
}
@@ -118585,11 +114121,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WAKEUP3_E`"]
- pub enum WAKEUP3_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1."]
- EDGE_DETECT_OF_WAKEU,
- }
+ pub enum WAKEUP3_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." ] EDGE_DETECT_OF_WAKEU}
impl WAKEUP3_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118618,8 +114150,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(WAKEUP3_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_wakeu(self) -> &'a mut W {
self.variant(WAKEUP3_EW::EDGE_DETECT_OF_WAKEU)
}
@@ -118642,11 +114173,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `ATIMER_E`"]
- pub enum ATIMER_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_A,
- }
+ pub enum ATIMER_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." ] EDGE_DETECT_OF_THE_A}
impl ATIMER_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118675,8 +114202,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(ATIMER_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_a(self) -> &'a mut W {
self.variant(ATIMER_EW::EDGE_DETECT_OF_THE_A)
}
@@ -118699,11 +114225,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `RTC_E`"]
- pub enum RTC_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum RTC_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl RTC_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118732,8 +114254,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(RTC_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_r(self) -> &'a mut W {
self.variant(RTC_EW::EDGE_DETECT_OF_THE_R)
}
@@ -118756,11 +114277,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `BOD_E`"]
- pub enum BOD_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_B,
- }
+ pub enum BOD_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." ] EDGE_DETECT_OF_THE_B}
impl BOD_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118789,8 +114306,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(BOD_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_b(self) -> &'a mut W {
self.variant(BOD_EW::EDGE_DETECT_OF_THE_B)
}
@@ -118813,11 +114329,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `WWDT_E`"]
- pub enum WWDT_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_W,
- }
+ pub enum WWDT_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." ] EDGE_DETECT_OF_THE_W}
impl WWDT_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118846,8 +114358,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(WWDT_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_w(self) -> &'a mut W {
self.variant(WWDT_EW::EDGE_DETECT_OF_THE_W)
}
@@ -118870,11 +114381,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `ETH_E`"]
- pub enum ETH_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_E,
- }
+ pub enum ETH_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." ] EDGE_DETECT_OF_THE_E}
impl ETH_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118903,8 +114410,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(ETH_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_e(self) -> &'a mut W {
self.variant(ETH_EW::EDGE_DETECT_OF_THE_E)
}
@@ -118927,11 +114433,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `USB0_E`"]
- pub enum USB0_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_U,
- }
+ pub enum USB0_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." ] EDGE_DETECT_OF_THE_U}
impl USB0_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -118960,8 +114462,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(USB0_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_u(self) -> &'a mut W {
self.variant(USB0_EW::EDGE_DETECT_OF_THE_U)
}
@@ -118984,11 +114485,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `USB1_E`"]
- pub enum USB1_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_U,
- }
+ pub enum USB1_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." ] EDGE_DETECT_OF_THE_U}
impl USB1_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119017,8 +114514,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(USB1_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_u(self) -> &'a mut W {
self.variant(USB1_EW::EDGE_DETECT_OF_THE_U)
}
@@ -119041,11 +114537,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `SDMMC_E`"]
- pub enum SDMMC_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_S,
- }
+ pub enum SDMMC_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." ] EDGE_DETECT_OF_THE_S}
impl SDMMC_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119074,8 +114566,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(SDMMC_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_s(self) -> &'a mut W {
self.variant(SDMMC_EW::EDGE_DETECT_OF_THE_S)
}
@@ -119098,11 +114589,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `CAN_E`"]
- pub enum CAN_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_C,
- }
+ pub enum CAN_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." ] EDGE_DETECT_OF_THE_C}
impl CAN_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119131,8 +114618,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(CAN_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_c(self) -> &'a mut W {
self.variant(CAN_EW::EDGE_DETECT_OF_THE_C)
}
@@ -119155,11 +114641,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `TIM2_E`"]
- pub enum TIM2_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1."]
- EDGE_DETECT_OF_GIMA,
- }
+ pub enum TIM2_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." ] EDGE_DETECT_OF_GIMA}
impl TIM2_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119188,8 +114670,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(TIM2_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_gima(self) -> &'a mut W {
self.variant(TIM2_EW::EDGE_DETECT_OF_GIMA)
}
@@ -119212,11 +114693,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `TIM6_E`"]
- pub enum TIM6_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1."]
- EDGE_DETECT_OF_GIMA,
- }
+ pub enum TIM6_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." ] EDGE_DETECT_OF_GIMA}
impl TIM6_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119245,8 +114722,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(TIM6_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_gima(self) -> &'a mut W {
self.variant(TIM6_EW::EDGE_DETECT_OF_GIMA)
}
@@ -119269,11 +114745,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `QEI_E`"]
- pub enum QEI_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1."]
- EDGE_DETECT_OF_QEI_I,
- }
+ pub enum QEI_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." ] EDGE_DETECT_OF_QEI_I}
impl QEI_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119302,8 +114774,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(QEI_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_qei_i(self) -> &'a mut W {
self.variant(QEI_EW::EDGE_DETECT_OF_QEI_I)
}
@@ -119326,11 +114797,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `TIM14_E`"]
- pub enum TIM14_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1."]
- EDGE_DETECT_OF_GIMA,
- }
+ pub enum TIM14_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." ] EDGE_DETECT_OF_GIMA}
impl TIM14_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119359,8 +114826,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(TIM14_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_gima(self) -> &'a mut W {
self.variant(TIM14_EW::EDGE_DETECT_OF_GIMA)
}
@@ -119383,11 +114849,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `RESET_E`"]
- pub enum RESET_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum RESET_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl RESET_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119416,8 +114878,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(RESET_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_r(self) -> &'a mut W {
self.variant(RESET_EW::EDGE_DETECT_OF_THE_R)
}
@@ -119440,11 +114901,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `BODRESET_E`"]
- pub enum BODRESET_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum BODRESET_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl BODRESET_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119473,8 +114930,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(BODRESET_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_r(self) -> &'a mut W {
self.variant(BODRESET_EW::EDGE_DETECT_OF_THE_R)
}
@@ -119497,11 +114953,7 @@ pub mod eventrouter {
}
}
#[doc = "Values that can be written to the field `DPDRESET_E`"]
- pub enum DPDRESET_EW {
- #[doc = "Level detect."] LEVEL_DETECT,
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1."]
- EDGE_DETECT_OF_THE_R,
- }
+ pub enum DPDRESET_EW {# [ doc = "Level detect." ] LEVEL_DETECT , # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." ] EDGE_DETECT_OF_THE_R}
impl DPDRESET_EW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -119530,8 +114982,7 @@ pub mod eventrouter {
pub fn level_detect(self) -> &'a mut W {
self.variant(DPDRESET_EW::LEVEL_DETECT)
}
- #[doc = "Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1."]
- #[inline(always)]
+ # [ doc = "Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." ] # [ inline ( always ) ]
pub fn edge_detect_of_the_r(self) -> &'a mut W {
self.variant(DPDRESET_EW::EDGE_DETECT_OF_THE_R)
}
@@ -119559,8 +115010,7 @@ pub mod eventrouter {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup0_e(&self) -> WAKEUP0_ER {
WAKEUP0_ER::_from({
const MASK: bool = true;
@@ -119568,8 +115018,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup1_e(&self) -> WAKEUP1_ER {
WAKEUP1_ER::_from({
const MASK: bool = true;
@@ -119577,8 +115026,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup2_e(&self) -> WAKEUP2_ER {
WAKEUP2_ER::_from({
const MASK: bool = true;
@@ -119586,8 +115034,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup3_e(&self) -> WAKEUP3_ER {
WAKEUP3_ER::_from({
const MASK: bool = true;
@@ -119595,8 +115042,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn atimer_e(&self) -> ATIMER_ER {
ATIMER_ER::_from({
const MASK: bool = true;
@@ -119604,8 +115050,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn rtc_e(&self) -> RTC_ER {
RTC_ER::_from({
const MASK: bool = true;
@@ -119613,8 +115058,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn bod_e(&self) -> BOD_ER {
BOD_ER::_from({
const MASK: bool = true;
@@ -119622,8 +115066,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wwdt_e(&self) -> WWDT_ER {
WWDT_ER::_from({
const MASK: bool = true;
@@ -119631,8 +115074,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn eth_e(&self) -> ETH_ER {
ETH_ER::_from({
const MASK: bool = true;
@@ -119640,8 +115082,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 9 - Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn usb0_e(&self) -> USB0_ER {
USB0_ER::_from({
const MASK: bool = true;
@@ -119649,8 +115090,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 10 - Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn usb1_e(&self) -> USB1_ER {
USB1_ER::_from({
const MASK: bool = true;
@@ -119658,8 +115098,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 11 - Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn sdmmc_e(&self) -> SDMMC_ER {
SDMMC_ER::_from({
const MASK: bool = true;
@@ -119667,8 +115106,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 12 - Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn can_e(&self) -> CAN_ER {
CAN_ER::_from({
const MASK: bool = true;
@@ -119676,8 +115114,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 13 - Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn tim2_e(&self) -> TIM2_ER {
TIM2_ER::_from({
const MASK: bool = true;
@@ -119685,8 +115122,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 14 - Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn tim6_e(&self) -> TIM6_ER {
TIM6_ER::_from({
const MASK: bool = true;
@@ -119694,8 +115130,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 15 - Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn qei_e(&self) -> QEI_ER {
QEI_ER::_from({
const MASK: bool = true;
@@ -119703,8 +115138,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 16 - Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn tim14_e(&self) -> TIM14_ER {
TIM14_ER::_from({
const MASK: bool = true;
@@ -119712,8 +115146,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 19 - Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn reset_e(&self) -> RESET_ER {
RESET_ER::_from({
const MASK: bool = true;
@@ -119721,8 +115154,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 20 - Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn bodreset_e(&self) -> BODRESET_ER {
BODRESET_ER::_from({
const MASK: bool = true;
@@ -119730,8 +115162,7 @@ pub mod eventrouter {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 21 - Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn dpdreset_e(&self) -> DPDRESET_ER {
DPDRESET_ER::_from({
const MASK: bool = true;
@@ -119752,103 +115183,83 @@ pub mod eventrouter {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup0_e(&mut self) -> _WAKEUP0_EW {
_WAKEUP0_EW { w: self }
}
- #[doc = "Bit 1 - Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup1_e(&mut self) -> _WAKEUP1_EW {
_WAKEUP1_EW { w: self }
}
- #[doc = "Bit 2 - Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup2_e(&mut self) -> _WAKEUP2_EW {
_WAKEUP2_EW { w: self }
}
- #[doc = "Bit 3 - Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wakeup3_e(&mut self) -> _WAKEUP3_EW {
_WAKEUP3_EW { w: self }
}
- #[doc = "Bit 4 - Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn atimer_e(&mut self) -> _ATIMER_EW {
_ATIMER_EW { w: self }
}
- #[doc = "Bit 5 - Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn rtc_e(&mut self) -> _RTC_EW {
_RTC_EW { w: self }
}
- #[doc = "Bit 6 - Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn bod_e(&mut self) -> _BOD_EW {
_BOD_EW { w: self }
}
- #[doc = "Bit 7 - Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn wwdt_e(&mut self) -> _WWDT_EW {
_WWDT_EW { w: self }
}
- #[doc = "Bit 8 - Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn eth_e(&mut self) -> _ETH_EW {
_ETH_EW { w: self }
}
- #[doc = "Bit 9 - Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn usb0_e(&mut self) -> _USB0_EW {
_USB0_EW { w: self }
}
- #[doc = "Bit 10 - Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn usb1_e(&mut self) -> _USB1_EW {
_USB1_EW { w: self }
}
- #[doc = "Bit 11 - Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn sdmmc_e(&mut self) -> _SDMMC_EW {
_SDMMC_EW { w: self }
}
- #[doc = "Bit 12 - Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn can_e(&mut self) -> _CAN_EW {
_CAN_EW { w: self }
}
- #[doc = "Bit 13 - Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn tim2_e(&mut self) -> _TIM2_EW {
_TIM2_EW { w: self }
}
- #[doc = "Bit 14 - Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn tim6_e(&mut self) -> _TIM6_EW {
_TIM6_EW { w: self }
}
- #[doc = "Bit 15 - Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn qei_e(&mut self) -> _QEI_EW {
_QEI_EW { w: self }
}
- #[doc = "Bit 16 - Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn tim14_e(&mut self) -> _TIM14_EW {
_TIM14_EW { w: self }
}
- #[doc = "Bit 19 - Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn reset_e(&mut self) -> _RESET_EW {
_RESET_EW { w: self }
}
- #[doc = "Bit 20 - Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn bodreset_e(&mut self) -> _BODRESET_EW {
_BODRESET_EW { w: self }
}
- #[doc = "Bit 21 - Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0." ] # [ inline ( always ) ]
pub fn dpdreset_e(&mut self) -> _DPDRESET_EW {
_DPDRESET_EW { w: self }
}
@@ -120348,103 +115759,83 @@ pub mod eventrouter {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup0_clren(&mut self) -> _WAKEUP0_CLRENW {
_WAKEUP0_CLRENW { w: self }
}
- #[doc = "Bit 1 - Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup1_clren(&mut self) -> _WAKEUP1_CLRENW {
_WAKEUP1_CLRENW { w: self }
}
- #[doc = "Bit 2 - Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup2_clren(&mut self) -> _WAKEUP2_CLRENW {
_WAKEUP2_CLRENW { w: self }
}
- #[doc = "Bit 3 - Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup3_clren(&mut self) -> _WAKEUP3_CLRENW {
_WAKEUP3_CLRENW { w: self }
}
- #[doc = "Bit 4 - Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." ] # [ inline ( always ) ]
pub fn atimer_clren(&mut self) -> _ATIMER_CLRENW {
_ATIMER_CLRENW { w: self }
}
- #[doc = "Bit 5 - Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." ] # [ inline ( always ) ]
pub fn rtc_clren(&mut self) -> _RTC_CLRENW {
_RTC_CLRENW { w: self }
}
- #[doc = "Bit 6 - Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." ] # [ inline ( always ) ]
pub fn bod_clren(&mut self) -> _BOD_CLRENW {
_BOD_CLRENW { w: self }
}
- #[doc = "Bit 7 - Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wwdt_clren(&mut self) -> _WWDT_CLRENW {
_WWDT_CLRENW { w: self }
}
- #[doc = "Bit 8 - Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." ] # [ inline ( always ) ]
pub fn eth_clren(&mut self) -> _ETH_CLRENW {
_ETH_CLRENW { w: self }
}
- #[doc = "Bit 9 - Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." ] # [ inline ( always ) ]
pub fn usb0_clren(&mut self) -> _USB0_CLRENW {
_USB0_CLRENW { w: self }
}
- #[doc = "Bit 10 - Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." ] # [ inline ( always ) ]
pub fn usb1_clren(&mut self) -> _USB1_CLRENW {
_USB1_CLRENW { w: self }
}
- #[doc = "Bit 11 - Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." ] # [ inline ( always ) ]
pub fn sdmmc_clren(&mut self) -> _SDMMC_CLRENW {
_SDMMC_CLRENW { w: self }
}
- #[doc = "Bit 12 - Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." ] # [ inline ( always ) ]
pub fn can_clren(&mut self) -> _CAN_CLRENW {
_CAN_CLRENW { w: self }
}
- #[doc = "Bit 13 - Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." ] # [ inline ( always ) ]
pub fn tim2_clren(&mut self) -> _TIM2_CLRENW {
_TIM2_CLRENW { w: self }
}
- #[doc = "Bit 14 - Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." ] # [ inline ( always ) ]
pub fn tim6_clren(&mut self) -> _TIM6_CLRENW {
_TIM6_CLRENW { w: self }
}
- #[doc = "Bit 15 - Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." ] # [ inline ( always ) ]
pub fn qei_clren(&mut self) -> _QEI_CLRENW {
_QEI_CLRENW { w: self }
}
- #[doc = "Bit 16 - Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." ] # [ inline ( always ) ]
pub fn tim14_clren(&mut self) -> _TIM14_CLRENW {
_TIM14_CLRENW { w: self }
}
- #[doc = "Bit 19 - Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." ] # [ inline ( always ) ]
pub fn reset_clren(&mut self) -> _RESET_CLRENW {
_RESET_CLRENW { w: self }
}
- #[doc = "Bit 20 - Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." ] # [ inline ( always ) ]
pub fn bodreset_clren(&mut self) -> _BODRESET_CLRENW {
_BODRESET_CLRENW { w: self }
}
- #[doc = "Bit 21 - Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." ] # [ inline ( always ) ]
pub fn dpdreset_clren(&mut self) -> _DPDRESET_CLRENW {
_DPDRESET_CLRENW { w: self }
}
@@ -120944,103 +116335,83 @@ pub mod eventrouter {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup0_seten(&mut self) -> _WAKEUP0_SETENW {
_WAKEUP0_SETENW { w: self }
}
- #[doc = "Bit 1 - Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup1_seten(&mut self) -> _WAKEUP1_SETENW {
_WAKEUP1_SETENW { w: self }
}
- #[doc = "Bit 2 - Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup2_seten(&mut self) -> _WAKEUP2_SETENW {
_WAKEUP2_SETENW { w: self }
}
- #[doc = "Bit 3 - Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wakeup3_seten(&mut self) -> _WAKEUP3_SETENW {
_WAKEUP3_SETENW { w: self }
}
- #[doc = "Bit 4 - Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." ] # [ inline ( always ) ]
pub fn atimer_seten(&mut self) -> _ATIMER_SETENW {
_ATIMER_SETENW { w: self }
}
- #[doc = "Bit 5 - Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." ] # [ inline ( always ) ]
pub fn rtc_seten(&mut self) -> _RTC_SETENW {
_RTC_SETENW { w: self }
}
- #[doc = "Bit 6 - Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." ] # [ inline ( always ) ]
pub fn bod_seten(&mut self) -> _BOD_SETENW {
_BOD_SETENW { w: self }
}
- #[doc = "Bit 7 - Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." ] # [ inline ( always ) ]
pub fn wwdt_seten(&mut self) -> _WWDT_SETENW {
_WWDT_SETENW { w: self }
}
- #[doc = "Bit 8 - Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." ] # [ inline ( always ) ]
pub fn eth_seten(&mut self) -> _ETH_SETENW {
_ETH_SETENW { w: self }
}
- #[doc = "Bit 9 - Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." ] # [ inline ( always ) ]
pub fn usb0_seten(&mut self) -> _USB0_SETENW {
_USB0_SETENW { w: self }
}
- #[doc = "Bit 10 - Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." ] # [ inline ( always ) ]
pub fn usb1_seten(&mut self) -> _USB1_SETENW {
_USB1_SETENW { w: self }
}
- #[doc = "Bit 11 - Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." ] # [ inline ( always ) ]
pub fn sdmmc_seten(&mut self) -> _SDMMC_SETENW {
_SDMMC_SETENW { w: self }
}
- #[doc = "Bit 12 - Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." ] # [ inline ( always ) ]
pub fn can_seten(&mut self) -> _CAN_SETENW {
_CAN_SETENW { w: self }
}
- #[doc = "Bit 13 - Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." ] # [ inline ( always ) ]
pub fn tim2_seten(&mut self) -> _TIM2_SETENW {
_TIM2_SETENW { w: self }
}
- #[doc = "Bit 14 - Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." ] # [ inline ( always ) ]
pub fn tim6_seten(&mut self) -> _TIM6_SETENW {
_TIM6_SETENW { w: self }
}
- #[doc = "Bit 15 - Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." ] # [ inline ( always ) ]
pub fn qei_seten(&mut self) -> _QEI_SETENW {
_QEI_SETENW { w: self }
}
- #[doc = "Bit 16 - Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." ] # [ inline ( always ) ]
pub fn tim14_seten(&mut self) -> _TIM14_SETENW {
_TIM14_SETENW { w: self }
}
- #[doc = "Bit 19 - Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." ] # [ inline ( always ) ]
pub fn reset_seten(&mut self) -> _RESET_SETENW {
_RESET_SETENW { w: self }
}
- #[doc = "Bit 20 - Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." ] # [ inline ( always ) ]
pub fn bodreset_seten(&mut self) -> _BODRESET_SETENW {
_BODRESET_SETENW { w: self }
}
- #[doc = "Bit 21 - Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." ] # [ inline ( always ) ]
pub fn dpdreset_seten(&mut self) -> _DPDRESET_SETENW {
_DPDRESET_SETENW { w: self }
}
@@ -121621,8 +116992,7 @@ pub mod eventrouter {
};
CAN_STR { bits }
}
- #[doc = "Bit 13 - A 1 in this bit shows that the combined timer 2 output event has been raised."]
- #[inline(always)]
+ # [ doc = "Bit 13 - A 1 in this bit shows that the combined timer 2 output event has been raised." ] # [ inline ( always ) ]
pub fn tim2_st(&self) -> TIM2_STR {
let bits = {
const MASK: bool = true;
@@ -121631,8 +117001,7 @@ pub mod eventrouter {
};
TIM2_STR { bits }
}
- #[doc = "Bit 14 - A 1 in this bit shows that the combined timer 6 output event has been raised."]
- #[inline(always)]
+ # [ doc = "Bit 14 - A 1 in this bit shows that the combined timer 6 output event has been raised." ] # [ inline ( always ) ]
pub fn tim6_st(&self) -> TIM6_STR {
let bits = {
const MASK: bool = true;
@@ -121651,8 +117020,7 @@ pub mod eventrouter {
};
QEI_STR { bits }
}
- #[doc = "Bit 16 - A 1 in this bit shows that the combined timer 14 output event has been raised."]
- #[inline(always)]
+ # [ doc = "Bit 16 - A 1 in this bit shows that the combined timer 14 output event has been raised." ] # [ inline ( always ) ]
pub fn tim14_st(&self) -> TIM14_STR {
let bits = {
const MASK: bool = true;
@@ -122138,8 +117506,7 @@ pub mod eventrouter {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup0_en(&self) -> WAKEUP0_ENR {
let bits = {
const MASK: bool = true;
@@ -122148,8 +117515,7 @@ pub mod eventrouter {
};
WAKEUP0_ENR { bits }
}
- #[doc = "Bit 1 - A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup1_en(&self) -> WAKEUP1_ENR {
let bits = {
const MASK: bool = true;
@@ -122158,8 +117524,7 @@ pub mod eventrouter {
};
WAKEUP1_ENR { bits }
}
- #[doc = "Bit 2 - A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup2_en(&self) -> WAKEUP2_ENR {
let bits = {
const MASK: bool = true;
@@ -122168,8 +117533,7 @@ pub mod eventrouter {
};
WAKEUP2_ENR { bits }
}
- #[doc = "Bit 3 - A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 3 - A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup3_en(&self) -> WAKEUP3_ENR {
let bits = {
const MASK: bool = true;
@@ -122178,8 +117542,7 @@ pub mod eventrouter {
};
WAKEUP3_ENR { bits }
}
- #[doc = "Bit 4 - A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn atimer_en(&self) -> ATIMER_ENR {
let bits = {
const MASK: bool = true;
@@ -122188,8 +117551,7 @@ pub mod eventrouter {
};
ATIMER_ENR { bits }
}
- #[doc = "Bit 5 - A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn rtc_en(&self) -> RTC_ENR {
let bits = {
const MASK: bool = true;
@@ -122198,8 +117560,7 @@ pub mod eventrouter {
};
RTC_ENR { bits }
}
- #[doc = "Bit 6 - A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn bod_en(&self) -> BOD_ENR {
let bits = {
const MASK: bool = true;
@@ -122208,8 +117569,7 @@ pub mod eventrouter {
};
BOD_ENR { bits }
}
- #[doc = "Bit 7 - A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn wwdt_en(&self) -> WWDT_ENR {
let bits = {
const MASK: bool = true;
@@ -122218,8 +117578,7 @@ pub mod eventrouter {
};
WWDT_ENR { bits }
}
- #[doc = "Bit 8 - A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn eth_en(&self) -> ETH_ENR {
let bits = {
const MASK: bool = true;
@@ -122228,8 +117587,7 @@ pub mod eventrouter {
};
ETH_ENR { bits }
}
- #[doc = "Bit 9 - A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn usb0_en(&self) -> USB0_ENR {
let bits = {
const MASK: bool = true;
@@ -122238,8 +117596,7 @@ pub mod eventrouter {
};
USB0_ENR { bits }
}
- #[doc = "Bit 10 - A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn usb1_en(&self) -> USB1_ENR {
let bits = {
const MASK: bool = true;
@@ -122248,8 +117605,7 @@ pub mod eventrouter {
};
USB1_ENR { bits }
}
- #[doc = "Bit 11 - A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 11 - A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn sdmmc_en(&self) -> SDMMC_ENR {
let bits = {
const MASK: bool = true;
@@ -122258,8 +117614,7 @@ pub mod eventrouter {
};
SDMMC_ENR { bits }
}
- #[doc = "Bit 12 - A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 12 - A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn can_en(&self) -> CAN_ENR {
let bits = {
const MASK: bool = true;
@@ -122268,8 +117623,7 @@ pub mod eventrouter {
};
CAN_ENR { bits }
}
- #[doc = "Bit 13 - A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 13 - A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim2_en(&self) -> TIM2_ENR {
let bits = {
const MASK: bool = true;
@@ -122278,8 +117632,7 @@ pub mod eventrouter {
};
TIM2_ENR { bits }
}
- #[doc = "Bit 14 - A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 14 - A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim6_en(&self) -> TIM6_ENR {
let bits = {
const MASK: bool = true;
@@ -122288,8 +117641,7 @@ pub mod eventrouter {
};
TIM6_ENR { bits }
}
- #[doc = "Bit 15 - A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 15 - A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn qei_en(&self) -> QEI_ENR {
let bits = {
const MASK: bool = true;
@@ -122298,8 +117650,7 @@ pub mod eventrouter {
};
QEI_ENR { bits }
}
- #[doc = "Bit 16 - A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 16 - A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim14_en(&self) -> TIM14_ENR {
let bits = {
const MASK: bool = true;
@@ -122308,8 +117659,7 @@ pub mod eventrouter {
};
TIM14_ENR { bits }
}
- #[doc = "Bit 19 - A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 19 - A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn reset_en(&self) -> RESET_ENR {
let bits = {
const MASK: bool = true;
@@ -122318,8 +117668,7 @@ pub mod eventrouter {
};
RESET_ENR { bits }
}
- #[doc = "Bit 20 - A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 20 - A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn bodreset_en(&self) -> BODRESET_ENR {
let bits = {
const MASK: bool = true;
@@ -122328,8 +117677,7 @@ pub mod eventrouter {
};
BODRESET_ENR { bits }
}
- #[doc = "Bit 21 - A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 21 - A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn dpdreset_en(&self) -> DPDRESET_ENR {
let bits = {
const MASK: bool = true;
@@ -122834,103 +118182,83 @@ pub mod eventrouter {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup0_clrst(&mut self) -> _WAKEUP0_CLRSTW {
_WAKEUP0_CLRSTW { w: self }
}
- #[doc = "Bit 1 - Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup1_clrst(&mut self) -> _WAKEUP1_CLRSTW {
_WAKEUP1_CLRSTW { w: self }
}
- #[doc = "Bit 2 - Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup2_clrst(&mut self) -> _WAKEUP2_CLRSTW {
_WAKEUP2_CLRSTW { w: self }
}
- #[doc = "Bit 3 - Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup3_clrst(&mut self) -> _WAKEUP3_CLRSTW {
_WAKEUP3_CLRSTW { w: self }
}
- #[doc = "Bit 4 - Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." ] # [ inline ( always ) ]
pub fn atimer_clrst(&mut self) -> _ATIMER_CLRSTW {
_ATIMER_CLRSTW { w: self }
}
- #[doc = "Bit 5 - Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." ] # [ inline ( always ) ]
pub fn rtc_clrst(&mut self) -> _RTC_CLRSTW {
_RTC_CLRSTW { w: self }
}
- #[doc = "Bit 6 - Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." ] # [ inline ( always ) ]
pub fn bod_clrst(&mut self) -> _BOD_CLRSTW {
_BOD_CLRSTW { w: self }
}
- #[doc = "Bit 7 - Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." ] # [ inline ( always ) ]
pub fn wwdt_clrst(&mut self) -> _WWDT_CLRSTW {
_WWDT_CLRSTW { w: self }
}
- #[doc = "Bit 8 - Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." ] # [ inline ( always ) ]
pub fn eth_clrst(&mut self) -> _ETH_CLRSTW {
_ETH_CLRSTW { w: self }
}
- #[doc = "Bit 9 - Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." ] # [ inline ( always ) ]
pub fn usb0_clrst(&mut self) -> _USB0_CLRSTW {
_USB0_CLRSTW { w: self }
}
- #[doc = "Bit 10 - Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." ] # [ inline ( always ) ]
pub fn usb1_clrst(&mut self) -> _USB1_CLRSTW {
_USB1_CLRSTW { w: self }
}
- #[doc = "Bit 11 - Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." ] # [ inline ( always ) ]
pub fn sdmmc_clrst(&mut self) -> _SDMMC_CLRSTW {
_SDMMC_CLRSTW { w: self }
}
- #[doc = "Bit 12 - Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." ] # [ inline ( always ) ]
pub fn can_clrst(&mut self) -> _CAN_CLRSTW {
_CAN_CLRSTW { w: self }
}
- #[doc = "Bit 13 - Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim2_clrst(&mut self) -> _TIM2_CLRSTW {
_TIM2_CLRSTW { w: self }
}
- #[doc = "Bit 14 - Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim6_clrst(&mut self) -> _TIM6_CLRSTW {
_TIM6_CLRSTW { w: self }
}
- #[doc = "Bit 15 - Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." ] # [ inline ( always ) ]
pub fn qei_clrst(&mut self) -> _QEI_CLRSTW {
_QEI_CLRSTW { w: self }
}
- #[doc = "Bit 16 - Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim14_clrst(&mut self) -> _TIM14_CLRSTW {
_TIM14_CLRSTW { w: self }
}
- #[doc = "Bit 19 - Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." ] # [ inline ( always ) ]
pub fn reset_clrst(&mut self) -> _RESET_CLRSTW {
_RESET_CLRSTW { w: self }
}
- #[doc = "Bit 20 - Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." ] # [ inline ( always ) ]
pub fn bodreset_clrst(&mut self) -> _BODRESET_CLRSTW {
_BODRESET_CLRSTW { w: self }
}
- #[doc = "Bit 21 - Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." ] # [ inline ( always ) ]
pub fn dpdreset_clrst(&mut self) -> _DPDRESET_CLRSTW {
_DPDRESET_CLRSTW { w: self }
}
@@ -123430,103 +118758,83 @@ pub mod eventrouter {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup0_setst(&mut self) -> _WAKEUP0_SETSTW {
_WAKEUP0_SETSTW { w: self }
}
- #[doc = "Bit 1 - Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup1_setst(&mut self) -> _WAKEUP1_SETSTW {
_WAKEUP1_SETSTW { w: self }
}
- #[doc = "Bit 2 - Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup2_setst(&mut self) -> _WAKEUP2_SETSTW {
_WAKEUP2_SETSTW { w: self }
}
- #[doc = "Bit 3 - Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." ] # [ inline ( always ) ]
pub fn wakeup3_setst(&mut self) -> _WAKEUP3_SETSTW {
_WAKEUP3_SETSTW { w: self }
}
- #[doc = "Bit 4 - Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." ] # [ inline ( always ) ]
pub fn atimer_setst(&mut self) -> _ATIMER_SETSTW {
_ATIMER_SETSTW { w: self }
}
- #[doc = "Bit 5 - Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." ] # [ inline ( always ) ]
pub fn rtc_setst(&mut self) -> _RTC_SETSTW {
_RTC_SETSTW { w: self }
}
- #[doc = "Bit 6 - Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." ] # [ inline ( always ) ]
pub fn bod_setst(&mut self) -> _BOD_SETSTW {
_BOD_SETSTW { w: self }
}
- #[doc = "Bit 7 - Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." ] # [ inline ( always ) ]
pub fn wwdt_setst(&mut self) -> _WWDT_SETSTW {
_WWDT_SETSTW { w: self }
}
- #[doc = "Bit 8 - Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." ] # [ inline ( always ) ]
pub fn eth_setst(&mut self) -> _ETH_SETSTW {
_ETH_SETSTW { w: self }
}
- #[doc = "Bit 9 - Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." ] # [ inline ( always ) ]
pub fn usb0_setst(&mut self) -> _USB0_SETSTW {
_USB0_SETSTW { w: self }
}
- #[doc = "Bit 10 - Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." ] # [ inline ( always ) ]
pub fn usb1_setst(&mut self) -> _USB1_SETSTW {
_USB1_SETSTW { w: self }
}
- #[doc = "Bit 11 - Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." ] # [ inline ( always ) ]
pub fn sdmmc_setst(&mut self) -> _SDMMC_SETSTW {
_SDMMC_SETSTW { w: self }
}
- #[doc = "Bit 12 - Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." ] # [ inline ( always ) ]
pub fn can_setst(&mut self) -> _CAN_SETSTW {
_CAN_SETSTW { w: self }
}
- #[doc = "Bit 13 - Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim2_setst(&mut self) -> _TIM2_SETSTW {
_TIM2_SETSTW { w: self }
}
- #[doc = "Bit 14 - Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim6_setst(&mut self) -> _TIM6_SETSTW {
_TIM6_SETSTW { w: self }
}
- #[doc = "Bit 15 - Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." ] # [ inline ( always ) ]
pub fn qei_setst(&mut self) -> _QEI_SETSTW {
_QEI_SETSTW { w: self }
}
- #[doc = "Bit 16 - Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." ] # [ inline ( always ) ]
pub fn tim14_setst(&mut self) -> _TIM14_SETSTW {
_TIM14_SETSTW { w: self }
}
- #[doc = "Bit 19 - Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." ] # [ inline ( always ) ]
pub fn reset_setst(&mut self) -> _RESET_SETSTW {
_RESET_SETSTW { w: self }
}
- #[doc = "Bit 20 - Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." ] # [ inline ( always ) ]
pub fn bodreset_setst(&mut self) -> _BODRESET_SETSTW {
_BODRESET_SETSTW { w: self }
}
- #[doc = "Bit 21 - Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." ] # [ inline ( always ) ]
pub fn dpdreset_setst(&mut self) -> _DPDRESET_SETSTW {
_DPDRESET_SETSTW { w: self }
}
@@ -123550,55 +118858,7 @@ pub mod rtc {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Interrupt Location Register"] pub ilr: ILR,
- _reserved0: [u8; 4usize],
- #[doc = "0x08 - Clock Control Register"] pub ccr: CCR,
- #[doc = "0x0c - Counter Increment Interrupt Register"] pub ciir: CIIR,
- #[doc = "0x10 - Alarm Mask Register"] pub amr: AMR,
- #[doc = "0x14 - Consolidated Time Register 0"] pub ctime0: CTIME0,
- #[doc = "0x18 - Consolidated Time Register 1"] pub ctime1: CTIME1,
- #[doc = "0x1c - Consolidated Time Register 2"] pub ctime2: CTIME2,
- #[doc = "0x20 - Seconds Register"] pub sec: SEC,
- #[doc = "0x24 - Minutes Register"] pub min: MIN,
- #[doc = "0x28 - Hours Register"] pub hrs: HRS,
- #[doc = "0x2c - Day of Month Register"] pub dom: DOM,
- #[doc = "0x30 - Day of Week Register"] pub dow: DOW,
- #[doc = "0x34 - Day of Year Register"] pub doy: DOY,
- #[doc = "0x38 - Months Register"] pub month: MONTH,
- #[doc = "0x3c - Years Register"] pub year: YEAR,
- #[doc = "0x40 - Calibration Value Register"]
- pub calibration: CALIBRATION,
- _reserved1: [u8; 28usize],
- #[doc = "0x60 - Alarm value for Seconds"] pub asec: ASEC,
- #[doc = "0x64 - Alarm value for Minutes"] pub amin: AMIN,
- #[doc = "0x68 - Alarm value for Hours"] pub ahrs: AHRS,
- #[doc = "0x6c - Alarm value for Day of Month"] pub adom: ADOM,
- #[doc = "0x70 - Alarm value for Day of Week"] pub adow: ADOW,
- #[doc = "0x74 - Alarm value for Day of Year"] pub adoy: ADOY,
- #[doc = "0x78 - Alarm value for Months"] pub amon: AMON,
- #[doc = "0x7c - Alarm value for Year"] pub ayrs: AYRS,
- #[doc = "0x80 - Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions."]
- pub erstatus: ERSTATUS,
- #[doc = "0x84 - Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup."]
- pub ercontro: ERCONTRO,
- #[doc = "0x88 - Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels."]
- pub ercounters: ERCOUNTERS,
- _reserved2: [u8; 4usize],
- #[doc = "0x90 - Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0."]
- pub erfirststamp0: ERFIRSTSTAMP,
- #[doc = "0x94 - Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0."]
- pub erfirststamp1: ERFIRSTSTAMP,
- #[doc = "0x98 - Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0."]
- pub erfirststamp2: ERFIRSTSTAMP,
- _reserved3: [u8; 4usize],
- #[doc = "0xa0 - Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0."]
- pub erlaststamp0: ERLASTSTAMP,
- #[doc = "0xa4 - Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0."]
- pub erlaststamp1: ERLASTSTAMP,
- #[doc = "0xa8 - Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0."]
- pub erlaststamp2: ERLASTSTAMP,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - Interrupt Location Register" ] pub ilr : ILR , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x08 - Clock Control Register" ] pub ccr : CCR , # [ doc = "0x0c - Counter Increment Interrupt Register" ] pub ciir : CIIR , # [ doc = "0x10 - Alarm Mask Register" ] pub amr : AMR , # [ doc = "0x14 - Consolidated Time Register 0" ] pub ctime0 : CTIME0 , # [ doc = "0x18 - Consolidated Time Register 1" ] pub ctime1 : CTIME1 , # [ doc = "0x1c - Consolidated Time Register 2" ] pub ctime2 : CTIME2 , # [ doc = "0x20 - Seconds Register" ] pub sec : SEC , # [ doc = "0x24 - Minutes Register" ] pub min : MIN , # [ doc = "0x28 - Hours Register" ] pub hrs : HRS , # [ doc = "0x2c - Day of Month Register" ] pub dom : DOM , # [ doc = "0x30 - Day of Week Register" ] pub dow : DOW , # [ doc = "0x34 - Day of Year Register" ] pub doy : DOY , # [ doc = "0x38 - Months Register" ] pub month : MONTH , # [ doc = "0x3c - Years Register" ] pub year : YEAR , # [ doc = "0x40 - Calibration Value Register" ] pub calibration : CALIBRATION , _reserved1 : [ u8 ; 28usize ] , # [ doc = "0x60 - Alarm value for Seconds" ] pub asec : ASEC , # [ doc = "0x64 - Alarm value for Minutes" ] pub amin : AMIN , # [ doc = "0x68 - Alarm value for Hours" ] pub ahrs : AHRS , # [ doc = "0x6c - Alarm value for Day of Month" ] pub adom : ADOM , # [ doc = "0x70 - Alarm value for Day of Week" ] pub adow : ADOW , # [ doc = "0x74 - Alarm value for Day of Year" ] pub adoy : ADOY , # [ doc = "0x78 - Alarm value for Months" ] pub amon : AMON , # [ doc = "0x7c - Alarm value for Year" ] pub ayrs : AYRS , # [ doc = "0x80 - Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." ] pub erstatus : ERSTATUS , # [ doc = "0x84 - Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." ] pub ercontro : ERCONTRO , # [ doc = "0x88 - Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." ] pub ercounters : ERCOUNTERS , _reserved2 : [ u8 ; 4usize ] , # [ doc = "0x90 - Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." ] pub erfirststamp0 : ERFIRSTSTAMP , # [ doc = "0x94 - Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." ] pub erfirststamp1 : ERFIRSTSTAMP , # [ doc = "0x98 - Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." ] pub erfirststamp2 : ERFIRSTSTAMP , _reserved3 : [ u8 ; 4usize ] , # [ doc = "0xa0 - Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." ] pub erlaststamp0 : ERLASTSTAMP , # [ doc = "0xa4 - Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." ] pub erlaststamp1 : ERLASTSTAMP , # [ doc = "0xa8 - Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." ] pub erlaststamp2 : ERLASTSTAMP , }
#[doc = "Interrupt Location Register"]
pub struct ILR {
register: VolatileCell<u32>,
@@ -123679,13 +118939,11 @@ pub mod rtc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." ] # [ inline ( always ) ]
pub fn rtccif(&mut self) -> _RTCCIFW {
_RTCCIFW { w: self }
}
- #[doc = "Bit 1 - When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." ] # [ inline ( always ) ]
pub fn rtcalf(&mut self) -> _RTCALFW {
_RTCALFW { w: self }
}
@@ -123744,8 +119002,7 @@ pub mod rtc {
#[doc = "Possible values of the field `CLKEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKENR {
- #[doc = "The time counters are disabled so that they may be initialized."]
- DISABLED,
+ #[doc = "The time counters are disabled so that they may be initialized."] DISABLED,
#[doc = "The time counters are enabled."] ENABLED,
}
impl CLKENR {
@@ -123789,11 +119046,7 @@ pub mod rtc {
}
#[doc = "Possible values of the field `CTCRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CTCRSTR {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software."]
- RESET,
- }
+ pub enum CTCRSTR {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." ] RESET}
impl CTCRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -123835,12 +119088,7 @@ pub mod rtc {
}
#[doc = "Possible values of the field `CCALEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CCALENR {
- #[doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1."]
- ENABLED,
- #[doc = "The calibration counter is disabled and reset to zero."]
- DISABLED,
- }
+ pub enum CCALENR {# [ doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1." ] ENABLED , # [ doc = "The calibration counter is disabled and reset to zero." ] DISABLED}
impl CCALENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -123882,8 +119130,7 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `CLKEN`"]
pub enum CLKENW {
- #[doc = "The time counters are disabled so that they may be initialized."]
- DISABLED,
+ #[doc = "The time counters are disabled so that they may be initialized."] DISABLED,
#[doc = "The time counters are enabled."] ENABLED,
}
impl CLKENW {
@@ -123938,11 +119185,7 @@ pub mod rtc {
}
}
#[doc = "Values that can be written to the field `CTCRST`"]
- pub enum CTCRSTW {
- #[doc = "No effect."] NO_EFFECT,
- #[doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software."]
- RESET,
- }
+ pub enum CTCRSTW {# [ doc = "No effect." ] NO_EFFECT , # [ doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." ] RESET}
impl CTCRSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -123971,8 +119214,7 @@ pub mod rtc {
pub fn no_effect(self) -> &'a mut W {
self.variant(CTCRSTW::NO_EFFECT)
}
- #[doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software."]
- #[inline(always)]
+ # [ doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." ] # [ inline ( always ) ]
pub fn reset(self) -> &'a mut W {
self.variant(CTCRSTW::RESET)
}
@@ -123995,12 +119237,7 @@ pub mod rtc {
}
}
#[doc = "Values that can be written to the field `CCALEN`"]
- pub enum CCALENW {
- #[doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1."]
- ENABLED,
- #[doc = "The calibration counter is disabled and reset to zero."]
- DISABLED,
- }
+ pub enum CCALENW {# [ doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1." ] ENABLED , # [ doc = "The calibration counter is disabled and reset to zero." ] DISABLED}
impl CCALENW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -124024,8 +119261,7 @@ pub mod rtc {
self.bit(variant._bits())
}
}
- #[doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1."]
- #[inline(always)]
+ # [ doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(CCALENW::ENABLED)
}
@@ -125370,8 +120606,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." ] # [ inline ( always ) ]
pub fn dom(&self) -> DOMR {
let bits = {
const MASK: u8 = 31;
@@ -125868,8 +121103,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." ] # [ inline ( always ) ]
pub fn dom(&self) -> DOMR {
let bits = {
const MASK: u8 = 31;
@@ -125891,8 +121125,7 @@ pub mod rtc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." ] # [ inline ( always ) ]
pub fn dom(&mut self) -> _DOMW {
_DOMW { w: self }
}
@@ -126409,12 +121642,7 @@ pub mod rtc {
}
#[doc = "Possible values of the field `CALDIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CALDIRR {
- #[doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds."]
- FORWARD_CALIBRATION_,
- #[doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second."]
- BACKWARD_CALIBRATION,
- }
+ pub enum CALDIRR {# [ doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." ] FORWARD_CALIBRATION_ , # [ doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." ] BACKWARD_CALIBRATION}
impl CALDIRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -126470,12 +121698,7 @@ pub mod rtc {
}
}
#[doc = "Values that can be written to the field `CALDIR`"]
- pub enum CALDIRW {
- #[doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds."]
- FORWARD_CALIBRATION_,
- #[doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second."]
- BACKWARD_CALIBRATION,
- }
+ pub enum CALDIRW {# [ doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." ] FORWARD_CALIBRATION_ , # [ doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." ] BACKWARD_CALIBRATION}
impl CALDIRW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -126499,13 +121722,11 @@ pub mod rtc {
self.bit(variant._bits())
}
}
- #[doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds."]
- #[inline(always)]
+ # [ doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." ] # [ inline ( always ) ]
pub fn forward_calibration_(self) -> &'a mut W {
self.variant(CALDIRW::FORWARD_CALIBRATION_)
}
- #[doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second."]
- #[inline(always)]
+ # [ doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." ] # [ inline ( always ) ]
pub fn backward_calibration(self) -> &'a mut W {
self.variant(CALDIRW::BACKWARD_CALIBRATION)
}
@@ -126533,8 +121754,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:16 - If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0."]
- #[inline(always)]
+ # [ doc = "Bits 0:16 - If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." ] # [ inline ( always ) ]
pub fn calval(&self) -> CALVALR {
let bits = {
const MASK: u32 = 131071;
@@ -126565,8 +121785,7 @@ pub mod rtc {
self.bits = bits;
self
}
- #[doc = "Bits 0:16 - If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0."]
- #[inline(always)]
+ # [ doc = "Bits 0:16 - If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." ] # [ inline ( always ) ]
pub fn calval(&mut self) -> _CALVALW {
_CALVALW { w: self }
}
@@ -126995,8 +122214,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." ] # [ inline ( always ) ]
pub fn dom(&self) -> DOMR {
let bits = {
const MASK: u8 = 31;
@@ -127018,8 +122236,7 @@ pub mod rtc {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." ] # [ inline ( always ) ]
pub fn dom(&mut self) -> _DOMW {
_DOMW { w: self }
}
@@ -127473,11 +122690,11 @@ pub mod rtc {
}
}
}
- #[doc = "Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup."]
+ # [ doc = "Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." ]
pub struct ERCONTRO {
register: VolatileCell<u32>,
}
- #[doc = "Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup."]
+ # [ doc = "Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." ]
pub mod ercontro {
#[doc = r" Value read from the register"]
pub struct R {
@@ -127526,8 +122743,7 @@ pub mod rtc {
#[doc = "Possible values of the field `INTWAKE_EN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTWAKE_EN0R {
- #[doc = "No interrupt or wake-up will be generated by event channel 0."]
- DISABLED,
+ #[doc = "No interrupt or wake-up will be generated by event channel 0."] DISABLED,
#[doc = "An event in channel 0 will trigger an (RTC) interrupt and a wake-up request."]
ENABLED,
}
@@ -127572,12 +122788,7 @@ pub mod rtc {
}
#[doc = "Possible values of the field `GPCLEAR_EN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum GPCLEAR_EN0R {
- #[doc = "Channel 0 has no influence on the general purpose registers."]
- DISABLED,
- #[doc = "An event in channel 0 will clear the general purpose registers asynchronously."]
- ENABLED,
- }
+ pub enum GPCLEAR_EN0R {# [ doc = "Channel 0 has no influence on the general purpose registers." ] DISABLED , # [ doc = "An event in channel 0 will clear the general purpose registers asynchronously." ] ENABLED}
impl GPCLEAR_EN0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -127620,10 +122831,8 @@ pub mod rtc {
#[doc = "Possible values of the field `POL0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL0R {
- #[doc = "A channel 0 event is defined as a negative edge on WAKEUP0."]
- NEGATIVE,
- #[doc = "A channel 0 event is defined as a positive edge on WAKEUP0."]
- POSITIVE,
+ #[doc = "A channel 0 event is defined as a negative edge on WAKEUP0."] NEGATIVE,
+ #[doc = "A channel 0 event is defined as a positive edge on WAKEUP0."] POSITIVE,
}
impl POL0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -127667,8 +122876,7 @@ pub mod rtc {
#[doc = "Possible values of the field `EV0_INPUT_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EV0_INPUT_ENR {
- #[doc = "Event 0 input is disabled and forced high internally."]
- DISABLED,
+ #[doc = "Event 0 input is disabled and forced high internally."] DISABLED,
#[doc = "Event 0 input is enabled."] ENABLED,
}
impl EV0_INPUT_ENR {
@@ -127713,8 +122921,7 @@ pub mod rtc {
#[doc = "Possible values of the field `INTWAKE_EN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTWAKE_EN1R {
- #[doc = "No interrupt or wake-up will be generated by event channel 1."]
- DISABLED,
+ #[doc = "No interrupt or wake-up will be generated by event channel 1."] DISABLED,
#[doc = "An event in channel 1 will trigger an (RTC) interrupt and a wake-up request."]
ENABLED,
}
@@ -127759,12 +122966,7 @@ pub mod rtc {
}
#[doc = "Possible values of the field `GPCLEAR_EN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum GPCLEAR_EN1R {
- #[doc = "Channel 1 has no influence on the general purpose registers."]
- DISABLED,
- #[doc = "A n event in channel 1 will clear the general purpose registers asynchronously."]
- ENABLED,
- }
+ pub enum GPCLEAR_EN1R {# [ doc = "Channel 1 has no influence on the general purpose registers." ] DISABLED , # [ doc = "A n event in channel 1 will clear the general purpose registers asynchronously." ] ENABLED}
impl GPCLEAR_EN1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -127807,10 +123009,8 @@ pub mod rtc {
#[doc = "Possible values of the field `POL1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL1R {
- #[doc = "A channel 1 event is defined as a negative edge on WAKEUP1."]
- NEGATIVE,
- #[doc = "A channel 1 event is defined as a positive edge on WAKEUP1."]
- POSITIVE,
+ #[doc = "A channel 1 event is defined as a negative edge on WAKEUP1."] NEGATIVE,
+ #[doc = "A channel 1 event is defined as a positive edge on WAKEUP1."] POSITIVE,
}
impl POL1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -127854,8 +123054,7 @@ pub mod rtc {
#[doc = "Possible values of the field `EV1_INPUT_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EV1_INPUT_ENR {
- #[doc = "Event 1 input is disabled and forced high internally."]
- DISABLED,
+ #[doc = "Event 1 input is disabled and forced high internally."] DISABLED,
#[doc = "Event 1 input is enabled."] ENABLED,
}
impl EV1_INPUT_ENR {
@@ -127900,8 +123099,7 @@ pub mod rtc {
#[doc = "Possible values of the field `INTWAKE_EN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTWAKE_EN2R {
- #[doc = "No interrupt or wake-up will be generated by event channel 2."]
- DISABLED,
+ #[doc = "No interrupt or wake-up will be generated by event channel 2."] DISABLED,
#[doc = "An event in channel 2 will trigger an (RTC) interrupt and a wake-up request."]
ENABLED,
}
@@ -127946,12 +123144,7 @@ pub mod rtc {
}
#[doc = "Possible values of the field `GPCLEAR_EN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum GPCLEAR_EN2R {
- #[doc = "Channel 2 has no influence on the general purpose registers."]
- DISABLED,
- #[doc = "An event in channel 2 will clear the general purpose registers asynchronously."]
- ENABLED,
- }
+ pub enum GPCLEAR_EN2R {# [ doc = "Channel 2 has no influence on the general purpose registers." ] DISABLED , # [ doc = "An event in channel 2 will clear the general purpose registers asynchronously." ] ENABLED}
impl GPCLEAR_EN2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -127994,10 +123187,8 @@ pub mod rtc {
#[doc = "Possible values of the field `POL2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POL2R {
- #[doc = "A channel 2 event is defined as a negative edge on WAKEUP2."]
- NEGATIVE,
- #[doc = "A channel 2 event is defined as a positive edge on WAKEUP2."]
- POSITIVE,
+ #[doc = "A channel 2 event is defined as a negative edge on WAKEUP2."] NEGATIVE,
+ #[doc = "A channel 2 event is defined as a positive edge on WAKEUP2."] POSITIVE,
}
impl POL2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -128041,8 +123232,7 @@ pub mod rtc {
#[doc = "Possible values of the field `EV2_INPUT_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EV2_INPUT_ENR {
- #[doc = "Event 2 input is disabled and forced high internally."]
- DISABLED,
+ #[doc = "Event 2 input is disabled and forced high internally."] DISABLED,
#[doc = "Event 2 input is enabled."] ENABLED,
}
impl EV2_INPUT_ENR {
@@ -128086,16 +123276,7 @@ pub mod rtc {
}
#[doc = "Possible values of the field `ERMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ERMODER {
- #[doc = "Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected."]
- DISABLE_EVENT_MONITO,
- #[doc = "16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out."]
- _16_HZ_SAMPLE_CLOCK,
- #[doc = "64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out."]
- _64_HZ_SAMPLE_CLOCK,
- #[doc = "1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out."]
- _1_KHZ_SAMPLE_CLOCK,
- }
+ pub enum ERMODER {# [ doc = "Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." ] DISABLE_EVENT_MONITO , # [ doc = "16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." ] _16_HZ_SAMPLE_CLOCK , # [ doc = "64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." ] _64_HZ_SAMPLE_CLOCK , # [ doc = "1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." ] _1_KHZ_SAMPLE_CLOCK}
impl ERMODER {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -128142,8 +123323,7 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `INTWAKE_EN0`"]
pub enum INTWAKE_EN0W {
- #[doc = "No interrupt or wake-up will be generated by event channel 0."]
- DISABLED,
+ #[doc = "No interrupt or wake-up will be generated by event channel 0."] DISABLED,
#[doc = "An event in channel 0 will trigger an (RTC) interrupt and a wake-up request."]
ENABLED,
}
@@ -128199,12 +123379,7 @@ pub mod rtc {
}
}
#[doc = "Values that can be written to the field `GPCLEAR_EN0`"]
- pub enum GPCLEAR_EN0W {
- #[doc = "Channel 0 has no influence on the general purpose registers."]
- DISABLED,
- #[doc = "An event in channel 0 will clear the general purpose registers asynchronously."]
- ENABLED,
- }
+ pub enum GPCLEAR_EN0W {# [ doc = "Channel 0 has no influence on the general purpose registers." ] DISABLED , # [ doc = "An event in channel 0 will clear the general purpose registers asynchronously." ] ENABLED}
impl GPCLEAR_EN0W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -128258,10 +123433,8 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `POL0`"]
pub enum POL0W {
- #[doc = "A channel 0 event is defined as a negative edge on WAKEUP0."]
- NEGATIVE,
- #[doc = "A channel 0 event is defined as a positive edge on WAKEUP0."]
- POSITIVE,
+ #[doc = "A channel 0 event is defined as a negative edge on WAKEUP0."] NEGATIVE,
+ #[doc = "A channel 0 event is defined as a positive edge on WAKEUP0."] POSITIVE,
}
impl POL0W {
#[allow(missing_docs)]
@@ -128316,8 +123489,7 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `EV0_INPUT_EN`"]
pub enum EV0_INPUT_ENW {
- #[doc = "Event 0 input is disabled and forced high internally."]
- DISABLED,
+ #[doc = "Event 0 input is disabled and forced high internally."] DISABLED,
#[doc = "Event 0 input is enabled."] ENABLED,
}
impl EV0_INPUT_ENW {
@@ -128373,8 +123545,7 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `INTWAKE_EN1`"]
pub enum INTWAKE_EN1W {
- #[doc = "No interrupt or wake-up will be generated by event channel 1."]
- DISABLED,
+ #[doc = "No interrupt or wake-up will be generated by event channel 1."] DISABLED,
#[doc = "An event in channel 1 will trigger an (RTC) interrupt and a wake-up request."]
ENABLED,
}
@@ -128430,12 +123601,7 @@ pub mod rtc {
}
}
#[doc = "Values that can be written to the field `GPCLEAR_EN1`"]
- pub enum GPCLEAR_EN1W {
- #[doc = "Channel 1 has no influence on the general purpose registers."]
- DISABLED,
- #[doc = "A n event in channel 1 will clear the general purpose registers asynchronously."]
- ENABLED,
- }
+ pub enum GPCLEAR_EN1W {# [ doc = "Channel 1 has no influence on the general purpose registers." ] DISABLED , # [ doc = "A n event in channel 1 will clear the general purpose registers asynchronously." ] ENABLED}
impl GPCLEAR_EN1W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -128464,8 +123630,7 @@ pub mod rtc {
pub fn disabled(self) -> &'a mut W {
self.variant(GPCLEAR_EN1W::DISABLED)
}
- #[doc = "A n event in channel 1 will clear the general purpose registers asynchronously."]
- #[inline(always)]
+ # [ doc = "A n event in channel 1 will clear the general purpose registers asynchronously." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(GPCLEAR_EN1W::ENABLED)
}
@@ -128489,10 +123654,8 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `POL1`"]
pub enum POL1W {
- #[doc = "A channel 1 event is defined as a negative edge on WAKEUP1."]
- NEGATIVE,
- #[doc = "A channel 1 event is defined as a positive edge on WAKEUP1."]
- POSITIVE,
+ #[doc = "A channel 1 event is defined as a negative edge on WAKEUP1."] NEGATIVE,
+ #[doc = "A channel 1 event is defined as a positive edge on WAKEUP1."] POSITIVE,
}
impl POL1W {
#[allow(missing_docs)]
@@ -128547,8 +123710,7 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `EV1_INPUT_EN`"]
pub enum EV1_INPUT_ENW {
- #[doc = "Event 1 input is disabled and forced high internally."]
- DISABLED,
+ #[doc = "Event 1 input is disabled and forced high internally."] DISABLED,
#[doc = "Event 1 input is enabled."] ENABLED,
}
impl EV1_INPUT_ENW {
@@ -128604,8 +123766,7 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `INTWAKE_EN2`"]
pub enum INTWAKE_EN2W {
- #[doc = "No interrupt or wake-up will be generated by event channel 2."]
- DISABLED,
+ #[doc = "No interrupt or wake-up will be generated by event channel 2."] DISABLED,
#[doc = "An event in channel 2 will trigger an (RTC) interrupt and a wake-up request."]
ENABLED,
}
@@ -128661,12 +123822,7 @@ pub mod rtc {
}
}
#[doc = "Values that can be written to the field `GPCLEAR_EN2`"]
- pub enum GPCLEAR_EN2W {
- #[doc = "Channel 2 has no influence on the general purpose registers."]
- DISABLED,
- #[doc = "An event in channel 2 will clear the general purpose registers asynchronously."]
- ENABLED,
- }
+ pub enum GPCLEAR_EN2W {# [ doc = "Channel 2 has no influence on the general purpose registers." ] DISABLED , # [ doc = "An event in channel 2 will clear the general purpose registers asynchronously." ] ENABLED}
impl GPCLEAR_EN2W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -128720,10 +123876,8 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `POL2`"]
pub enum POL2W {
- #[doc = "A channel 2 event is defined as a negative edge on WAKEUP2."]
- NEGATIVE,
- #[doc = "A channel 2 event is defined as a positive edge on WAKEUP2."]
- POSITIVE,
+ #[doc = "A channel 2 event is defined as a negative edge on WAKEUP2."] NEGATIVE,
+ #[doc = "A channel 2 event is defined as a positive edge on WAKEUP2."] POSITIVE,
}
impl POL2W {
#[allow(missing_docs)]
@@ -128778,8 +123932,7 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `EV2_INPUT_EN`"]
pub enum EV2_INPUT_ENW {
- #[doc = "Event 2 input is disabled and forced high internally."]
- DISABLED,
+ #[doc = "Event 2 input is disabled and forced high internally."] DISABLED,
#[doc = "Event 2 input is enabled."] ENABLED,
}
impl EV2_INPUT_ENW {
@@ -128834,16 +123987,7 @@ pub mod rtc {
}
}
#[doc = "Values that can be written to the field `ERMODE`"]
- pub enum ERMODEW {
- #[doc = "Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected."]
- DISABLE_EVENT_MONITO,
- #[doc = "16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out."]
- _16_HZ_SAMPLE_CLOCK,
- #[doc = "64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out."]
- _64_HZ_SAMPLE_CLOCK,
- #[doc = "1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out."]
- _1_KHZ_SAMPLE_CLOCK,
- }
+ pub enum ERMODEW {# [ doc = "Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." ] DISABLE_EVENT_MONITO , # [ doc = "16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." ] _16_HZ_SAMPLE_CLOCK , # [ doc = "64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." ] _64_HZ_SAMPLE_CLOCK , # [ doc = "1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." ] _1_KHZ_SAMPLE_CLOCK}
impl ERMODEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -128869,23 +124013,19 @@ pub mod rtc {
self.bits(variant._bits())
}
}
- #[doc = "Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected."]
- #[inline(always)]
+ # [ doc = "Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." ] # [ inline ( always ) ]
pub fn disable_event_monito(self) -> &'a mut W {
self.variant(ERMODEW::DISABLE_EVENT_MONITO)
}
- #[doc = "16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out."]
- #[inline(always)]
+ # [ doc = "16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." ] # [ inline ( always ) ]
pub fn _16_hz_sample_clock(self) -> &'a mut W {
self.variant(ERMODEW::_16_HZ_SAMPLE_CLOCK)
}
- #[doc = "64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out."]
- #[inline(always)]
+ # [ doc = "64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." ] # [ inline ( always ) ]
pub fn _64_hz_sample_clock(self) -> &'a mut W {
self.variant(ERMODEW::_64_HZ_SAMPLE_CLOCK)
}
- #[doc = "1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out."]
- #[inline(always)]
+ # [ doc = "1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." ] # [ inline ( always ) ]
pub fn _1_khz_sample_clock(self) -> &'a mut W {
self.variant(ERMODEW::_1_KHZ_SAMPLE_CLOCK)
}
@@ -128914,8 +124054,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0." ] # [ inline ( always ) ]
pub fn gpclear_en0(&self) -> GPCLEAR_EN0R {
GPCLEAR_EN0R::_from({
const MASK: bool = true;
@@ -128932,8 +124071,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function." ] # [ inline ( always ) ]
pub fn ev0_input_en(&self) -> EV0_INPUT_ENR {
EV0_INPUT_ENR::_from({
const MASK: bool = true;
@@ -128950,8 +124088,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 11 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1." ] # [ inline ( always ) ]
pub fn gpclear_en1(&self) -> GPCLEAR_EN1R {
GPCLEAR_EN1R::_from({
const MASK: bool = true;
@@ -128968,8 +124105,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 13 - Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function." ] # [ inline ( always ) ]
pub fn ev1_input_en(&self) -> EV1_INPUT_ENR {
EV1_INPUT_ENR::_from({
const MASK: bool = true;
@@ -128986,8 +124122,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 21 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2." ] # [ inline ( always ) ]
pub fn gpclear_en2(&self) -> GPCLEAR_EN2R {
GPCLEAR_EN2R::_from({
const MASK: bool = true;
@@ -129004,8 +124139,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 23 - Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function." ] # [ inline ( always ) ]
pub fn ev2_input_en(&self) -> EV2_INPUT_ENR {
EV2_INPUT_ENR::_from({
const MASK: bool = true;
@@ -129013,8 +124147,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 30:31 - Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized."]
- #[inline(always)]
+ # [ doc = "Bits 30:31 - Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized." ] # [ inline ( always ) ]
pub fn ermode(&self) -> ERMODER {
ERMODER::_from({
const MASK: u8 = 3;
@@ -129040,8 +124173,7 @@ pub mod rtc {
pub fn intwake_en0(&mut self) -> _INTWAKE_EN0W {
_INTWAKE_EN0W { w: self }
}
- #[doc = "Bit 1 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0." ] # [ inline ( always ) ]
pub fn gpclear_en0(&mut self) -> _GPCLEAR_EN0W {
_GPCLEAR_EN0W { w: self }
}
@@ -129050,8 +124182,7 @@ pub mod rtc {
pub fn pol0(&mut self) -> _POL0W {
_POL0W { w: self }
}
- #[doc = "Bit 3 - Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function." ] # [ inline ( always ) ]
pub fn ev0_input_en(&mut self) -> _EV0_INPUT_ENW {
_EV0_INPUT_ENW { w: self }
}
@@ -129060,8 +124191,7 @@ pub mod rtc {
pub fn intwake_en1(&mut self) -> _INTWAKE_EN1W {
_INTWAKE_EN1W { w: self }
}
- #[doc = "Bit 11 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1." ] # [ inline ( always ) ]
pub fn gpclear_en1(&mut self) -> _GPCLEAR_EN1W {
_GPCLEAR_EN1W { w: self }
}
@@ -129070,8 +124200,7 @@ pub mod rtc {
pub fn pol1(&mut self) -> _POL1W {
_POL1W { w: self }
}
- #[doc = "Bit 13 - Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function." ] # [ inline ( always ) ]
pub fn ev1_input_en(&mut self) -> _EV1_INPUT_ENW {
_EV1_INPUT_ENW { w: self }
}
@@ -129080,8 +124209,7 @@ pub mod rtc {
pub fn intwake_en2(&mut self) -> _INTWAKE_EN2W {
_INTWAKE_EN2W { w: self }
}
- #[doc = "Bit 21 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2." ] # [ inline ( always ) ]
pub fn gpclear_en2(&mut self) -> _GPCLEAR_EN2W {
_GPCLEAR_EN2W { w: self }
}
@@ -129090,23 +124218,21 @@ pub mod rtc {
pub fn pol2(&mut self) -> _POL2W {
_POL2W { w: self }
}
- #[doc = "Bit 23 - Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function." ] # [ inline ( always ) ]
pub fn ev2_input_en(&mut self) -> _EV2_INPUT_ENW {
_EV2_INPUT_ENW { w: self }
}
- #[doc = "Bits 30:31 - Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized."]
- #[inline(always)]
+ # [ doc = "Bits 30:31 - Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized." ] # [ inline ( always ) ]
pub fn ermode(&mut self) -> _ERMODEW {
_ERMODEW { w: self }
}
}
}
- #[doc = "Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions."]
+ # [ doc = "Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." ]
pub struct ERSTATUS {
register: VolatileCell<u32>,
}
- #[doc = "Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions."]
+ # [ doc = "Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." ]
pub mod erstatus {
#[doc = r" Value read from the register"]
pub struct R {
@@ -129290,10 +124416,8 @@ pub mod rtc {
#[doc = "Possible values of the field `GP_CLEARED`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GP_CLEAREDR {
- #[doc = "General purpose registers have not been asynchronous cleared."]
- NO_CHANGE,
- #[doc = "General purpose registers have been asynchronous cleared."]
- EVENT,
+ #[doc = "General purpose registers have not been asynchronous cleared."] NO_CHANGE,
+ #[doc = "General purpose registers have been asynchronous cleared."] EVENT,
}
impl GP_CLEAREDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -129549,10 +124673,8 @@ pub mod rtc {
}
#[doc = "Values that can be written to the field `GP_CLEARED`"]
pub enum GP_CLEAREDW {
- #[doc = "General purpose registers have not been asynchronous cleared."]
- NO_CHANGE,
- #[doc = "General purpose registers have been asynchronous cleared."]
- EVENT,
+ #[doc = "General purpose registers have not been asynchronous cleared."] NO_CHANGE,
+ #[doc = "General purpose registers have been asynchronous cleared."] EVENT,
}
impl GP_CLEAREDW {
#[allow(missing_docs)]
@@ -129667,8 +124789,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn ev0(&self) -> EV0R {
EV0R::_from({
const MASK: bool = true;
@@ -129676,8 +124797,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn ev1(&self) -> EV1R {
EV1R::_from({
const MASK: bool = true;
@@ -129685,8 +124805,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn ev2(&self) -> EV2R {
EV2R::_from({
const MASK: bool = true;
@@ -129694,8 +124813,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 3 - General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn gp_cleared(&self) -> GP_CLEAREDR {
GP_CLEAREDR::_from({
const MASK: bool = true;
@@ -129703,8 +124821,7 @@ pub mod rtc {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 31 - Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
WAKEUPR::_from({
const MASK: bool = true;
@@ -129725,38 +124842,33 @@ pub mod rtc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn ev0(&mut self) -> _EV0W {
_EV0W { w: self }
}
- #[doc = "Bit 1 - Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn ev1(&mut self) -> _EV1W {
_EV1W { w: self }
}
- #[doc = "Bit 2 - Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn ev2(&mut self) -> _EV2W {
_EV2W { w: self }
}
- #[doc = "Bit 3 - General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 3 - General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn gp_cleared(&mut self) -> _GP_CLEAREDW {
_GP_CLEAREDW { w: self }
}
- #[doc = "Bit 31 - Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect." ] # [ inline ( always ) ]
pub fn wakeup(&mut self) -> _WAKEUPW {
_WAKEUPW { w: self }
}
}
}
- #[doc = "Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels."]
+ # [ doc = "Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." ]
pub struct ERCOUNTERS {
register: VolatileCell<u32>,
}
- #[doc = "Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels."]
+ # [ doc = "Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." ]
pub mod ercounters {
#[doc = r" Value read from the register"]
pub struct R {
@@ -129810,8 +124922,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:2 - Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software."]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." ] # [ inline ( always ) ]
pub fn counter0(&self) -> COUNTER0R {
let bits = {
const MASK: u8 = 7;
@@ -129842,11 +124953,11 @@ pub mod rtc {
}
}
}
- #[doc = "Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0."]
+ # [ doc = "Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." ]
pub struct ERFIRSTSTAMP {
register: VolatileCell<u32>,
}
- #[doc = "Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0."]
+ # [ doc = "Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." ]
pub mod erfirststamp {
#[doc = r" Value read from the register"]
pub struct R {
@@ -129953,11 +125064,11 @@ pub mod rtc {
}
}
}
- #[doc = "Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0."]
+ # [ doc = "Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." ]
pub struct ERLASTSTAMP {
register: VolatileCell<u32>,
}
- #[doc = "Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0."]
+ # [ doc = "Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." ]
pub mod erlaststamp {
#[doc = r" Value read from the register"]
pub struct R {
@@ -130085,38 +125196,23 @@ pub mod cgu {
pub struct RegisterBlock {
_reserved0: [u8; 20usize],
#[doc = "0x14 - Frequency monitor register"] pub freq_mon: FREQ_MON,
- #[doc = "0x18 - Crystal oscillator control register"]
- pub xtal_osc_ctrl: XTAL_OSC_CTRL,
- #[doc = "0x1c - PLL0USB status register"]
- pub pll0usb_stat: PLL0USB_STAT,
- #[doc = "0x20 - PLL0USB control register"]
- pub pll0usb_ctrl: PLL0USB_CTRL,
- #[doc = "0x24 - PLL0USB M-divider register"]
- pub pll0usb_mdiv: PLL0USB_MDIV,
- #[doc = "0x28 - PLL0USB N/P-divider register"]
- pub pll0usb_np_div: PLL0USB_NP_DIV,
- #[doc = "0x2c - PLL0AUDIO status register"]
- pub pll0audio_stat: PLL0AUDIO_STAT,
- #[doc = "0x30 - PLL0AUDIO control register"]
- pub pll0audio_ctrl: PLL0AUDIO_CTRL,
- #[doc = "0x34 - PLL0AUDIO M-divider register"]
- pub pll0audio_mdiv: PLL0AUDIO_MDIV,
- #[doc = "0x38 - PLL0AUDIO N/P-divider register"]
- pub pll0audio_np_div: PLL0AUDIO_NP_DIV,
- #[doc = "0x3c - PLL0AUDIO fractional divider register"]
- pub pll0audio_frac: PLL0AUDIO_FRAC,
+ #[doc = "0x18 - Crystal oscillator control register"] pub xtal_osc_ctrl: XTAL_OSC_CTRL,
+ #[doc = "0x1c - PLL0USB status register"] pub pll0usb_stat: PLL0USB_STAT,
+ #[doc = "0x20 - PLL0USB control register"] pub pll0usb_ctrl: PLL0USB_CTRL,
+ #[doc = "0x24 - PLL0USB M-divider register"] pub pll0usb_mdiv: PLL0USB_MDIV,
+ #[doc = "0x28 - PLL0USB N/P-divider register"] pub pll0usb_np_div: PLL0USB_NP_DIV,
+ #[doc = "0x2c - PLL0AUDIO status register"] pub pll0audio_stat: PLL0AUDIO_STAT,
+ #[doc = "0x30 - PLL0AUDIO control register"] pub pll0audio_ctrl: PLL0AUDIO_CTRL,
+ #[doc = "0x34 - PLL0AUDIO M-divider register"] pub pll0audio_mdiv: PLL0AUDIO_MDIV,
+ #[doc = "0x38 - PLL0AUDIO N/P-divider register"] pub pll0audio_np_div: PLL0AUDIO_NP_DIV,
+ #[doc = "0x3c - PLL0AUDIO fractional divider register"] pub pll0audio_frac: PLL0AUDIO_FRAC,
#[doc = "0x40 - PLL1 status register"] pub pll1_stat: PLL1_STAT,
#[doc = "0x44 - PLL1 control register"] pub pll1_ctrl: PLL1_CTRL,
- #[doc = "0x48 - Integer divider A control register"]
- pub idiva_ctrl: IDIVA_CTRL,
- #[doc = "0x4c - Integer divider B control register"]
- pub idivb_ctrl: IDIVB_CTRL,
- #[doc = "0x50 - Integer divider C control register"]
- pub idivc_ctrl: IDIVC_CTRL,
- #[doc = "0x54 - Integer divider D control register"]
- pub idivd_ctrl: IDIVD_CTRL,
- #[doc = "0x58 - Integer divider E control register"]
- pub idive_ctrl: IDIVE_CTRL,
+ #[doc = "0x48 - Integer divider A control register"] pub idiva_ctrl: IDIVA_CTRL,
+ #[doc = "0x4c - Integer divider B control register"] pub idivb_ctrl: IDIVB_CTRL,
+ #[doc = "0x50 - Integer divider C control register"] pub idivc_ctrl: IDIVC_CTRL,
+ #[doc = "0x54 - Integer divider D control register"] pub idivd_ctrl: IDIVD_CTRL,
+ #[doc = "0x58 - Integer divider E control register"] pub idive_ctrl: IDIVE_CTRL,
#[doc = "0x5c - Output stage 0 control register for base clock BASE_SAFE_CLK"]
pub base_safe_clk: BASE_SAFE_CLK,
#[doc = "0x60 - Output stage 1 control register for base clock BASE_USB0_CLK"]
@@ -130125,12 +125221,10 @@ pub mod cgu {
pub base_periph_clk: BASE_PERIPH_CLK,
#[doc = "0x68 - Output stage 3 control register for base clock BASE_USB1_CLK"]
pub base_usb1_clk: BASE_USB1_CLK,
- #[doc = "0x6c - Output stage BASE_M4_CLK control register"]
- pub base_m4_clk: BASE_M4_CLK,
+ #[doc = "0x6c - Output stage BASE_M4_CLK control register"] pub base_m4_clk: BASE_M4_CLK,
#[doc = "0x70 - Output stage BASE_SPIFI_CLK control register"]
pub base_spifi_clk: BASE_SPIFI_CLK,
- #[doc = "0x74 - Output stage BASE_SPI_CLK control register"]
- pub base_spi_clk: BASE_SPI_CLK,
+ #[doc = "0x74 - Output stage BASE_SPI_CLK control register"] pub base_spi_clk: BASE_SPI_CLK,
#[doc = "0x78 - Output stage BASE_PHY_RX_CLK control register"]
pub base_phy_rx_clk: BASE_PHY_RX_CLK,
#[doc = "0x7c - Output stage BASE_PHY_TX_CLK control register"]
@@ -130139,8 +125233,7 @@ pub mod cgu {
pub base_apb1_clk: BASE_APB1_CLK,
#[doc = "0x84 - Output stage BASE_APB3_CLK control register"]
pub base_apb3_clk: BASE_APB3_CLK,
- #[doc = "0x88 - Output stage BASE_LCD_CLK control register"]
- pub base_lcd_clk: BASE_LCD_CLK,
+ #[doc = "0x88 - Output stage BASE_LCD_CLK control register"] pub base_lcd_clk: BASE_LCD_CLK,
_reserved1: [u8; 4usize],
#[doc = "0x90 - Output stage BASE_SDIO_CLK control register"]
pub base_sdio_clk: BASE_SDIO_CLK,
@@ -130668,8 +125761,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 24:28 - Clock-source selection for the clock to be measured. All other values are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 24:28 - Clock-source selection for the clock to be measured. All other values are reserved." ] # [ inline ( always ) ]
pub fn clk_sel(&self) -> CLK_SELR {
CLK_SELR::_from({
const MASK: u8 = 31;
@@ -130705,8 +125797,7 @@ pub mod cgu {
pub fn meas(&mut self) -> _MEASW {
_MEASW { w: self }
}
- #[doc = "Bits 24:28 - Clock-source selection for the clock to be measured. All other values are reserved."]
- #[inline(always)]
+ # [ doc = "Bits 24:28 - Clock-source selection for the clock to be measured. All other values are reserved." ] # [ inline ( always ) ]
pub fn clk_sel(&mut self) -> _CLK_SELW {
_CLK_SELW { w: self }
}
@@ -130809,12 +125900,7 @@ pub mod cgu {
}
#[doc = "Possible values of the field `BYPASS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BYPASSR {
- #[doc = "Crystal. Operation with crystal connected (default)."]
- CRYSTAL,
- #[doc = "Bypass mode. Use this mode when an external clock source is used instead of a crystal."]
- BYPASS_MODE,
- }
+ pub enum BYPASSR {# [ doc = "Crystal. Operation with crystal connected (default)." ] CRYSTAL , # [ doc = "Bypass mode. Use this mode when an external clock source is used instead of a crystal." ] BYPASS_MODE}
impl BYPASSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -130856,12 +125942,7 @@ pub mod cgu {
}
#[doc = "Possible values of the field `HF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum HFR {
- #[doc = "Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care."]
- LOW,
- #[doc = "High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care."]
- HIGH,
- }
+ pub enum HFR {# [ doc = "Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." ] LOW , # [ doc = "High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." ] HIGH}
impl HFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -130958,12 +126039,7 @@ pub mod cgu {
}
}
#[doc = "Values that can be written to the field `BYPASS`"]
- pub enum BYPASSW {
- #[doc = "Crystal. Operation with crystal connected (default)."]
- CRYSTAL,
- #[doc = "Bypass mode. Use this mode when an external clock source is used instead of a crystal."]
- BYPASS_MODE,
- }
+ pub enum BYPASSW {# [ doc = "Crystal. Operation with crystal connected (default)." ] CRYSTAL , # [ doc = "Bypass mode. Use this mode when an external clock source is used instead of a crystal." ] BYPASS_MODE}
impl BYPASSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -130992,8 +126068,7 @@ pub mod cgu {
pub fn crystal(self) -> &'a mut W {
self.variant(BYPASSW::CRYSTAL)
}
- #[doc = "Bypass mode. Use this mode when an external clock source is used instead of a crystal."]
- #[inline(always)]
+ # [ doc = "Bypass mode. Use this mode when an external clock source is used instead of a crystal." ] # [ inline ( always ) ]
pub fn bypass_mode(self) -> &'a mut W {
self.variant(BYPASSW::BYPASS_MODE)
}
@@ -131016,12 +126091,7 @@ pub mod cgu {
}
}
#[doc = "Values that can be written to the field `HF`"]
- pub enum HFW {
- #[doc = "Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care."]
- LOW,
- #[doc = "High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care."]
- HIGH,
- }
+ pub enum HFW {# [ doc = "Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." ] LOW , # [ doc = "High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." ] HIGH}
impl HFW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -131045,13 +126115,11 @@ pub mod cgu {
self.bit(variant._bits())
}
}
- #[doc = "Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care."]
- #[inline(always)]
+ # [ doc = "Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." ] # [ inline ( always ) ]
pub fn low(self) -> &'a mut W {
self.variant(HFW::LOW)
}
- #[doc = "High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care."]
- #[inline(always)]
+ # [ doc = "High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." ] # [ inline ( always ) ]
pub fn high(self) -> &'a mut W {
self.variant(HFW::HIGH)
}
@@ -131079,8 +126147,7 @@ pub mod cgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!" ] # [ inline ( always ) ]
pub fn enable(&self) -> ENABLER {
ENABLER::_from({
const MASK: bool = true;
@@ -131088,8 +126155,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!" ] # [ inline ( always ) ]
pub fn bypass(&self) -> BYPASSR {
BYPASSR::_from({
const MASK: bool = true;
@@ -131119,13 +126185,11 @@ pub mod cgu {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!" ] # [ inline ( always ) ]
pub fn enable(&mut self) -> _ENABLEW {
_ENABLEW { w: self }
}
- #[doc = "Bit 1 - Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!" ] # [ inline ( always ) ]
pub fn bypass(&mut self) -> _BYPASSW {
_BYPASSW { w: self }
}
@@ -131325,8 +126389,7 @@ pub mod cgu {
pub enum BYPASSR {
#[doc = "CCO clock sent to post-dividers. Use this in normal operation."]
CCO_CLOCK_SENT_TO_PO,
- #[doc = "PLL0 input clock sent to post-dividers (default)."]
- PLL0_INPUT_CLOCK_SEN,
+ #[doc = "PLL0 input clock sent to post-dividers (default)."] PLL0_INPUT_CLOCK_SEN,
}
impl BYPASSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -131674,8 +126737,7 @@ pub mod cgu {
pub enum BYPASSW {
#[doc = "CCO clock sent to post-dividers. Use this in normal operation."]
CCO_CLOCK_SENT_TO_PO,
- #[doc = "PLL0 input clock sent to post-dividers (default)."]
- PLL0_INPUT_CLOCK_SEN,
+ #[doc = "PLL0 input clock sent to post-dividers (default)."] PLL0_INPUT_CLOCK_SEN,
}
impl BYPASSW {
#[allow(missing_docs)]
@@ -132289,8 +127351,7 @@ pub mod cgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071."]
- #[inline(always)]
+ # [ doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." ] # [ inline ( always ) ]
pub fn mdec(&self) -> MDECR {
let bits = {
const MASK: u32 = 131071;
@@ -132342,8 +127403,7 @@ pub mod cgu {
self.bits = bits;
self
}
- #[doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071."]
- #[inline(always)]
+ # [ doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." ] # [ inline ( always ) ]
pub fn mdec(&mut self) -> _MDECW {
_MDECW { w: self }
}
@@ -132706,8 +127766,7 @@ pub mod cgu {
pub enum BYPASSR {
#[doc = "CCO clock sent to post-dividers. Use this in normal operation."]
CCO_CLOCK_SENT_TO_PO,
- #[doc = "PLL0 input clock sent to post-dividers (default)."]
- PLL0_INPUT_CLOCK_SEN,
+ #[doc = "PLL0 input clock sent to post-dividers (default)."] PLL0_INPUT_CLOCK_SEN,
}
impl BYPASSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -133166,8 +128225,7 @@ pub mod cgu {
pub enum BYPASSW {
#[doc = "CCO clock sent to post-dividers. Use this in normal operation."]
CCO_CLOCK_SENT_TO_PO,
- #[doc = "PLL0 input clock sent to post-dividers (default)."]
- PLL0_INPUT_CLOCK_SEN,
+ #[doc = "PLL0 input clock sent to post-dividers (default)."] PLL0_INPUT_CLOCK_SEN,
}
impl BYPASSW {
#[allow(missing_docs)]
@@ -133692,8 +128750,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 12 - Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." ] # [ inline ( always ) ]
pub fn pllfract_req(&self) -> PLLFRACT_REQR {
let bits = {
const MASK: bool = true;
@@ -133777,8 +128834,7 @@ pub mod cgu {
pub fn autoblock(&mut self) -> _AUTOBLOCKW {
_AUTOBLOCKW { w: self }
}
- #[doc = "Bit 12 - Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." ] # [ inline ( always ) ]
pub fn pllfract_req(&mut self) -> _PLLFRACT_REQW {
_PLLFRACT_REQW { w: self }
}
@@ -133881,8 +128937,7 @@ pub mod cgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071."]
- #[inline(always)]
+ # [ doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." ] # [ inline ( always ) ]
pub fn mdec(&self) -> MDECR {
let bits = {
const MASK: u32 = 131071;
@@ -133904,8 +128959,7 @@ pub mod cgu {
self.bits = bits;
self
}
- #[doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071."]
- #[inline(always)]
+ # [ doc = "Bits 0:16 - Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." ] # [ inline ( always ) ]
pub fn mdec(&mut self) -> _MDECW {
_MDECW { w: self }
}
@@ -134332,10 +129386,8 @@ pub mod cgu {
#[doc = "Possible values of the field `BYPASS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BYPASSR {
- #[doc = "Normal. CCO clock sent to post-dividers. Use for normal operation."]
- NORMAL,
- #[doc = "Input clock. PLL1 input clock sent to post-dividers (default)."]
- INPUT_CLOCK,
+ #[doc = "Normal. CCO clock sent to post-dividers. Use for normal operation."] NORMAL,
+ #[doc = "Input clock. PLL1 input clock sent to post-dividers (default)."] INPUT_CLOCK,
}
impl BYPASSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -134378,12 +129430,7 @@ pub mod cgu {
}
#[doc = "Possible values of the field `FBSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum FBSELR {
- #[doc = "CCO out. CCO output is used as feedback divider input clock."]
- CCO_OUT,
- #[doc = "PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation."]
- PLL_OUT,
- }
+ pub enum FBSELR {# [ doc = "CCO out. CCO output is used as feedback divider input clock." ] CCO_OUT , # [ doc = "PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." ] PLL_OUT}
impl FBSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -134812,10 +129859,8 @@ pub mod cgu {
}
#[doc = "Values that can be written to the field `BYPASS`"]
pub enum BYPASSW {
- #[doc = "Normal. CCO clock sent to post-dividers. Use for normal operation."]
- NORMAL,
- #[doc = "Input clock. PLL1 input clock sent to post-dividers (default)."]
- INPUT_CLOCK,
+ #[doc = "Normal. CCO clock sent to post-dividers. Use for normal operation."] NORMAL,
+ #[doc = "Input clock. PLL1 input clock sent to post-dividers (default)."] INPUT_CLOCK,
}
impl BYPASSW {
#[allow(missing_docs)]
@@ -134869,12 +129914,7 @@ pub mod cgu {
}
}
#[doc = "Values that can be written to the field `FBSEL`"]
- pub enum FBSELW {
- #[doc = "CCO out. CCO output is used as feedback divider input clock."]
- CCO_OUT,
- #[doc = "PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation."]
- PLL_OUT,
- }
+ pub enum FBSELW {# [ doc = "CCO out. CCO output is used as feedback divider input clock." ] CCO_OUT , # [ doc = "PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." ] PLL_OUT}
impl FBSELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -134903,8 +129943,7 @@ pub mod cgu {
pub fn cco_out(self) -> &'a mut W {
self.variant(FBSELW::CCO_OUT)
}
- #[doc = "PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation."]
- #[inline(always)]
+ # [ doc = "PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." ] # [ inline ( always ) ]
pub fn pll_out(self) -> &'a mut W {
self.variant(FBSELW::PLL_OUT)
}
@@ -135369,8 +130408,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:23 - Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 ... 11111111 = 256"]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 ... 11111111 = 256" ] # [ inline ( always ) ]
pub fn msel(&self) -> MSELR {
let bits = {
const MASK: u8 = 255;
@@ -135436,8 +130474,7 @@ pub mod cgu {
pub fn nsel(&mut self) -> _NSELW {
_NSELW { w: self }
}
- #[doc = "Bits 16:23 - Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 ... 11111111 = 256"]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 ... 11111111 = 256" ] # [ inline ( always ) ]
pub fn msel(&mut self) -> _MSELW {
_MSELW { w: self }
}
@@ -136562,8 +131599,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16" ] # [ inline ( always ) ]
pub fn idiv(&self) -> IDIVR {
let bits = {
const MASK: u8 = 15;
@@ -136608,8 +131644,7 @@ pub mod cgu {
pub fn pd(&mut self) -> _PDW {
_PDW { w: self }
}
- #[doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16" ] # [ inline ( always ) ]
pub fn idiv(&mut self) -> _IDIVW {
_IDIVW { w: self }
}
@@ -137107,8 +132142,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16" ] # [ inline ( always ) ]
pub fn idiv(&self) -> IDIVR {
let bits = {
const MASK: u8 = 15;
@@ -137153,8 +132187,7 @@ pub mod cgu {
pub fn pd(&mut self) -> _PDW {
_PDW { w: self }
}
- #[doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16" ] # [ inline ( always ) ]
pub fn idiv(&mut self) -> _IDIVW {
_IDIVW { w: self }
}
@@ -137652,8 +132685,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16" ] # [ inline ( always ) ]
pub fn idiv(&self) -> IDIVR {
let bits = {
const MASK: u8 = 15;
@@ -137698,8 +132730,7 @@ pub mod cgu {
pub fn pd(&mut self) -> _PDW {
_PDW { w: self }
}
- #[doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16"]
- #[inline(always)]
+ # [ doc = "Bits 2:5 - Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16" ] # [ inline ( always ) ]
pub fn idiv(&mut self) -> _IDIVW {
_IDIVW { w: self }
}
@@ -138197,8 +133228,7 @@ pub mod cgu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 2:9 - Integer divider E divider values (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256"]
- #[inline(always)]
+ # [ doc = "Bits 2:9 - Integer divider E divider values (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256" ] # [ inline ( always ) ]
pub fn idiv(&self) -> IDIVR {
let bits = {
const MASK: u8 = 255;
@@ -138243,8 +133273,7 @@ pub mod cgu {
pub fn pd(&mut self) -> _PDW {
_PDW { w: self }
}
- #[doc = "Bits 2:9 - Integer divider E divider values (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256"]
- #[inline(always)]
+ # [ doc = "Bits 2:9 - Integer divider E divider values (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256" ] # [ inline ( always ) ]
pub fn idiv(&mut self) -> _IDIVW {
_IDIVW { w: self }
}
@@ -150710,7 +145739,206 @@ pub mod ccu1 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock { # [ doc = "0x00 - CCU1 power mode register" ] pub pm : PM , # [ doc = "0x04 - CCU1 base clocks status register" ] pub base_stat : BASE_STAT , _reserved0 : [ u8 ; 248usize ] , # [ doc = "0x100 - CLK_APB3_BUS clock configuration register" ] pub clk_apb3_bus_cfg : CLK_APB3_BUS_CFG , # [ doc = "0x104 - CLK_APB3_BUS clock status register" ] pub clk_apb3_bus_stat : CLK_APB3_BUS_STAT , # [ doc = "0x108 - CLK_APB3_I2C1 clock configuration register" ] pub clk_apb3_i2c1_cfg : CLK_APB3_I2C1_CFG , # [ doc = "0x10c - CLK_APB3_I2C1 clock status register" ] pub clk_apb3_i2c1_stat : CLK_APB3_I2C1_STAT , # [ doc = "0x110 - CLK_APB3_DAC clock configuration register" ] pub clk_apb3_dac_cfg : CLK_APB3_DAC_CFG , # [ doc = "0x114 - CLK_APB3_DAC clock status register" ] pub clk_apb3_dac_stat : CLK_APB3_DAC_STAT , # [ doc = "0x118 - CLK_APB3_ADC0 clock configuration register" ] pub clk_apb3_adc0_cfg : CLK_APB3_ADC0_CFG , # [ doc = "0x11c - CLK_APB3_ADC0 clock status register" ] pub clk_apb3_adc0_stat : CLK_APB3_ADC0_STAT , # [ doc = "0x120 - CLK_APB3_ADC1 clock configuration register" ] pub clk_apb3_adc1_cfg : CLK_APB3_ADC1_CFG , # [ doc = "0x124 - CLK_APB3_ADC1 clock status register" ] pub clk_apb3_adc1_stat : CLK_APB3_ADC1_STAT , # [ doc = "0x128 - CLK_APB3_CAN0 clock configuration register" ] pub clk_apb3_can0_cfg : CLK_APB3_CAN0_CFG , # [ doc = "0x12c - CLK_APB3_CAN0 clock status register" ] pub clk_apb3_can0_stat : CLK_APB3_CAN0_STAT , _reserved1 : [ u8 ; 208usize ] , # [ doc = "0x200 - CLK_APB1_BUS clock configuration register" ] pub clk_apb1_bus_cfg : CLK_APB1_BUS_CFG , # [ doc = "0x204 - CLK_APB1_BUS clock status register" ] pub clk_apb1_bus_stat : CLK_APB1_BUS_STAT , # [ doc = "0x208 - CLK_APB1_MOTOCONPWM clock configuration register" ] pub clk_apb1_motoconpwm_cfg : CLK_APB1_MOTOCONPWM_CFG , # [ doc = "0x20c - CLK_APB1_MOTOCONPWM clock status register" ] pub clk_apb1_motoconpwm_stat : CLK_APB1_MOTOCONPWM_STAT , # [ doc = "0x210 - CLK_ABP1_I2C0 clock configuration register" ] pub clk_apb1_i2c0_cfg : CLK_APB1_I2C0_CFG , # [ doc = "0x214 - CLK_APB1_I2C0 clock status register" ] pub clk_apb1_i2c0_stat : CLK_APB1_I2C0_STAT , # [ doc = "0x218 - CLK_APB1_I2S clock configuration register" ] pub clk_apb1_i2s_cfg : CLK_APB1_I2S_CFG , # [ doc = "0x21c - CLK_APB1_I2S clock status register" ] pub clk_apb1_i2s_stat : CLK_APB1_I2S_STAT , # [ doc = "0x220 - CLK_APB1_CAN1 clock configuration register" ] pub clk_apb1_can1_cfg : CLK_APB1_CAN1_CFG , # [ doc = "0x224 - CLK_APB1_CAN1 clock status register" ] pub clk_apb1_can1_stat : CLK_APB1_CAN1_STAT , _reserved2 : [ u8 ; 216usize ] , # [ doc = "0x300 - CLK_SPIFI clock configuration register" ] pub clk_spifi_cfg : CLK_SPIFI_CFG , # [ doc = "0x304 - CLK_APB1_SPIFI clock status register" ] pub clk_spifi_stat : CLK_SPIFI_STAT , _reserved3 : [ u8 ; 248usize ] , # [ doc = "0x400 - CLK_M4_BUS clock configuration register" ] pub clk_m4_bus_cfg : CLK_M4_BUS_CFG , # [ doc = "0x404 - CLK_M4_BUSclock status register" ] pub clk_m4_bus_stat : CLK_M4_BUS_STAT , # [ doc = "0x408 - CLK_M4_SPIFI clock configuration register" ] pub clk_m4_spifi_cfg : CLK_M4_SPIFI_CFG , # [ doc = "0x40c - CLK_M4_SPIFI clock status register" ] pub clk_m4_spifi_stat : CLK_M4_SPIFI_STAT , # [ doc = "0x410 - CLK_M4_GPIO clock configuration register" ] pub clk_m4_gpio_cfg : CLK_M4_GPIO_CFG , # [ doc = "0x414 - CLK_M4_GPIO clock status register" ] pub clk_m4_gpio_stat : CLK_M4_GPIO_STAT , # [ doc = "0x418 - CLK_M4_LCD clock configuration register" ] pub clk_m4_lcd_cfg : CLK_M4_LCD_CFG , # [ doc = "0x41c - CLK_M4_LCD clock status register" ] pub clk_m4_lcd_stat : CLK_M4_LCD_STAT , # [ doc = "0x420 - CLK_M4_ETHERNET clock configuration register" ] pub clk_m4_ethernet_cfg : CLK_M4_ETHERNET_CFG , # [ doc = "0x424 - CLK_M4_ETHERNET clock status register" ] pub clk_m4_ethernet_stat : CLK_M4_ETHERNET_STAT , # [ doc = "0x428 - CLK_M4_USB0 clock configuration register" ] pub clk_m4_usb0_cfg : CLK_M4_USB0_CFG , # [ doc = "0x42c - CLK_M4_USB0 clock status register" ] pub clk_m4_usb0_stat : CLK_M4_USB0_STAT , # [ doc = "0x430 - CLK_M4_EMC clock configuration register" ] pub clk_m4_emc_cfg : CLK_M4_EMC_CFG , # [ doc = "0x434 - CLK_M4_EMC clock status register" ] pub clk_m4_emc_stat : CLK_M4_EMC_STAT , # [ doc = "0x438 - CLK_M4_SDIO clock configuration register" ] pub clk_m4_sdio_cfg : CLK_M4_SDIO_CFG , # [ doc = "0x43c - CLK_M4_SDIO clock status register" ] pub clk_m4_sdio_stat : CLK_M4_SDIO_STAT , # [ doc = "0x440 - CLK_M4_DMA clock configuration register" ] pub clk_m4_dma_cfg : CLK_M4_DMA_CFG , # [ doc = "0x444 - CLK_M4_DMA clock status register" ] pub clk_m4_dma_stat : CLK_M4_DMA_STAT , # [ doc = "0x448 - CLK_M4_M4CORE clock configuration register" ] pub clk_m4_m4core_cfg : CLK_M4_M4CORE_CFG , # [ doc = "0x44c - CLK_M4_M3CORE clock status register" ] pub clk_m4_m4core_stat : CLK_M4_M4CORE_STAT , _reserved4 : [ u8 ; 24usize ] , # [ doc = "0x468 - CLK_M4_SCT clock configuration register" ] pub clk_m4_sct_cfg : CLK_M4_SCT_CFG , # [ doc = "0x46c - CLK_M4_SCT clock status register" ] pub clk_m4_sct_stat : CLK_M4_SCT_STAT , # [ doc = "0x470 - CLK_M4_USB1 clock configuration register" ] pub clk_m4_usb1_cfg : CLK_M4_USB1_CFG , # [ doc = "0x474 - CLK_M4_USB1 clock status register" ] pub clk_m4_usb1_stat : CLK_M4_USB1_STAT , # [ doc = "0x478 - CLK_M4_EMCDIV clock configuration register" ] pub clk_m4_emcdiv_cfg : CLK_M4_EMCDIV_CFG , # [ doc = "0x47c - CLK_M4_EMCDIV clock status register" ] pub clk_m4_emcdiv_stat : CLK_M4_EMCDIV_STAT , # [ doc = "0x480 - CLK_M4_FLASHA clock configuration register" ] pub clk_m4_flasha_cfg : CLK_M4_FLASHA_CFG , # [ doc = "0x484 - CLK_M4_FLASHA clock status register" ] pub clk_m4_flasha_stat : CLK_M4_FLASHA_STAT , # [ doc = "0x488 - CLK_M4_FLASHB clock configuration register" ] pub clk_m4_flashb_cfg : CLK_M4_FLASHB_CFG , # [ doc = "0x48c - CLK_M4_FLASHB clock status register" ] pub clk_m4_flashb_stat : CLK_M4_FLASHB_STAT , # [ doc = "0x490 - CLK_M0APP_CFG clock configuration register" ] pub clk_m4_m0app_cfg : CLK_M4_M0APP_CFG , # [ doc = "0x494 - CLK_M4_MOAPP clock status register" ] pub clk_m4_m0app_stat : CLK_M4_M0APP_STAT , # [ doc = "0x498 - CLK_ADCHS_CFG clock configuration register" ] pub clk_m4_adchs_cfg : CLK_M4_ADCHS_CFG , # [ doc = "0x49c - CLK_M4_ADCHS clock status register" ] pub clk_m4_adchs_stat : CLK_M4_ADCHS_STAT , # [ doc = "0x4a0 - CLK_EEPROM_CFG clock configuration register" ] pub clk_m4_eeprom_cfg : CLK_M4_EEPROM_CFG , # [ doc = "0x4a4 - CLK_M4_EEPROM clock status register" ] pub clk_m4_eeprom_stat : CLK_M4_EEPROM_STAT , _reserved5 : [ u8 ; 88usize ] , # [ doc = "0x500 - CLK_M4_WWDT clock configuration register" ] pub clk_m4_wwdt_cfg : CLK_M4_WWDT_CFG , # [ doc = "0x504 - CLK_M4_WWDT clock status register" ] pub clk_m4_wwdt_stat : CLK_M4_WWDT_STAT , # [ doc = "0x508 - CLK_M4_USART0 clock configuration register" ] pub clk_m4_usart0_cfg : CLK_M4_USART0_CFG , # [ doc = "0x50c - CLK_M4_USART0 clock status register" ] pub clk_m4_usart0_stat : CLK_M4_USART0_STAT , # [ doc = "0x510 - CLK_M4_UART1 clock configuration register" ] pub clk_m4_uart1_cfg : CLK_M4_UART1_CFG , # [ doc = "0x514 - CLK_M4_UART1 clock status register" ] pub clk_m4_uart1_stat : CLK_M4_UART1_STAT , # [ doc = "0x518 - CLK_M4_SSP0 clock configuration register" ] pub clk_m4_ssp0_cfg : CLK_M4_SSP0_CFG , # [ doc = "0x51c - CLK_M4_SSP0 clock status register" ] pub clk_m4_ssp0_stat : CLK_M4_SSP0_STAT , # [ doc = "0x520 - CLK_M4_TIMER0 clock configuration register" ] pub clk_m4_timer0_cfg : CLK_M4_TIMER0_CFG , # [ doc = "0x524 - CLK_M4_TIMER0 clock status register" ] pub clk_m4_timer0_stat : CLK_M4_TIMER0_STAT , # [ doc = "0x528 - CLK_M4_TIMER1clock configuration register" ] pub clk_m4_timer1_cfg : CLK_M4_TIMER1_CFG , # [ doc = "0x52c - CLK_M4_TIMER1 clock status register" ] pub clk_m4_timer1_stat : CLK_M4_TIMER1_STAT , # [ doc = "0x530 - CLK_M4_SCU clock configuration register" ] pub clk_m4_scu_cfg : CLK_M4_SCU_CFG , # [ doc = "0x534 - CLK_SCU_XXX clock status register" ] pub clk_m4_scu_stat : CLK_M4_SCU_STAT , # [ doc = "0x538 - CLK_M4_CREGclock configuration register" ] pub clk_m4_creg_cfg : CLK_M4_CREG_CFG , # [ doc = "0x53c - CLK_M4_CREG clock status register" ] pub clk_m4_creg_stat : CLK_M4_CREG_STAT , _reserved6 : [ u8 ; 192usize ] , # [ doc = "0x600 - CLK_M4_RITIMER clock configuration register" ] pub clk_m4_ritimer_cfg : CLK_M4_RITIMER_CFG , # [ doc = "0x604 - CLK_M4_RITIMER clock status register" ] pub clk_m4_ritimer_stat : CLK_M4_RITIMER_STAT , # [ doc = "0x608 - CLK_M4_USART2 clock configuration register" ] pub clk_m4_usart2_cfg : CLK_M4_USART2_CFG , # [ doc = "0x60c - CLK_M4_USART2 clock status register" ] pub clk_m4_usart2_stat : CLK_M4_USART2_STAT , # [ doc = "0x610 - CLK_M4_USART3 clock configuration register" ] pub clk_m4_usart3_cfg : CLK_M4_USART3_CFG , # [ doc = "0x614 - CLK_M4_USART3 clock status register" ] pub clk_m4_usart3_stat : CLK_M4_USART3_STAT , # [ doc = "0x618 - CLK_M4_TIMER2 clock configuration register" ] pub clk_m4_timer2_cfg : CLK_M4_TIMER2_CFG , # [ doc = "0x61c - CLK_M4_TIMER2 clock status register" ] pub clk_m4_timer2_stat : CLK_M4_TIMER2_STAT , # [ doc = "0x620 - CLK_M4_TIMER3 clock configuration register" ] pub clk_m4_timer3_cfg : CLK_M4_TIMER3_CFG , # [ doc = "0x624 - CLK_M4_TIMER3 clock status register" ] pub clk_m4_timer3_stat : CLK_M4_TIMER3_STAT , # [ doc = "0x628 - CLK_M4_SSP1 clock configuration register" ] pub clk_m4_ssp1_cfg : CLK_M4_SSP1_CFG , # [ doc = "0x62c - CLK_M4_SSP1 clock status register" ] pub clk_m4_ssp1_stat : CLK_M4_SSP1_STAT , # [ doc = "0x630 - CLK_M4_QEIclock configuration register" ] pub clk_m4_qei_cfg : CLK_M4_QEI_CFG , # [ doc = "0x634 - CLK_M4_QEI clock status register" ] pub clk_m4_qei_stat : CLK_M4_QEI_STAT , _reserved7 : [ u8 ; 200usize ] , # [ doc = "0x700 - CLK_PERIPH_BUS_CFG clock configuration register" ] pub clk_periph_bus_cfg : CLK_PERIPH_BUS_CFG , # [ doc = "0x704 - CLK_PERIPH_BUS_STAT clock status register" ] pub clk_periph_bus_stat : CLK_PERIPH_BUS_STAT , _reserved8 : [ u8 ; 8usize ] , # [ doc = "0x710 - CLK_PERIPH_CORE_CFG clock configuration register" ] pub clk_periph_core_cfg : CLK_PERIPH_CORE_CFG , # [ doc = "0x714 - CLK_CORE_BUS_STAT clock status register" ] pub clk_periph_core_stat : CLK_PERIPH_CORE_STAT , # [ doc = "0x718 - CLK_PERIPH_SGPIO_CFG clock configuration register" ] pub clk_periph_sgpio_cfg : CLK_PERIPH_SGPIO_CFG , # [ doc = "0x71c - CLK_CORE_SGPIO_STAT clock status register" ] pub clk_periph_sgpio_stat : CLK_PERIPH_SGPIO_STAT , _reserved9 : [ u8 ; 224usize ] , # [ doc = "0x800 - CLK_M4_USB0 clock configuration register" ] pub clk_usb0_cfg : CLK_USB0_CFG , # [ doc = "0x804 - CLK_USB0 clock status register" ] pub clk_usb0_stat : CLK_USB0_STAT , _reserved10 : [ u8 ; 248usize ] , # [ doc = "0x900 - CLK_USB1 clock configuration register" ] pub clk_usb1_cfg : CLK_USB1_CFG , # [ doc = "0x904 - CLK_USB1 clock status register" ] pub clk_usb1_stat : CLK_USB1_STAT , _reserved11 : [ u8 ; 248usize ] , # [ doc = "0xa00 - CLK_SPI clock configuration register" ] pub clk_spi_cfg : CLK_SPI_CFG , # [ doc = "0xa04 - CLK_SPI clock status register" ] pub clk_spi_stat : CLK_SPI_STAT , _reserved12 : [ u8 ; 248usize ] , # [ doc = "0xb00 - CLK_ADCHS clock configuration register" ] pub clk_adchs_cfg : CLK_ADCHS_CFG , # [ doc = "0xb04 - CLK_ADCHS clock status register" ] pub clk_adchs_stat : CLK_ADCHS_STAT , }
+ pub struct RegisterBlock {
+ #[doc = "0x00 - CCU1 power mode register"] pub pm: PM,
+ #[doc = "0x04 - CCU1 base clocks status register"] pub base_stat: BASE_STAT,
+ _reserved0: [u8; 248usize],
+ #[doc = "0x100 - CLK_APB3_BUS clock configuration register"]
+ pub clk_apb3_bus_cfg: CLK_APB3_BUS_CFG,
+ #[doc = "0x104 - CLK_APB3_BUS clock status register"]
+ pub clk_apb3_bus_stat: CLK_APB3_BUS_STAT,
+ #[doc = "0x108 - CLK_APB3_I2C1 clock configuration register"]
+ pub clk_apb3_i2c1_cfg: CLK_APB3_I2C1_CFG,
+ #[doc = "0x10c - CLK_APB3_I2C1 clock status register"]
+ pub clk_apb3_i2c1_stat: CLK_APB3_I2C1_STAT,
+ #[doc = "0x110 - CLK_APB3_DAC clock configuration register"]
+ pub clk_apb3_dac_cfg: CLK_APB3_DAC_CFG,
+ #[doc = "0x114 - CLK_APB3_DAC clock status register"]
+ pub clk_apb3_dac_stat: CLK_APB3_DAC_STAT,
+ #[doc = "0x118 - CLK_APB3_ADC0 clock configuration register"]
+ pub clk_apb3_adc0_cfg: CLK_APB3_ADC0_CFG,
+ #[doc = "0x11c - CLK_APB3_ADC0 clock status register"]
+ pub clk_apb3_adc0_stat: CLK_APB3_ADC0_STAT,
+ #[doc = "0x120 - CLK_APB3_ADC1 clock configuration register"]
+ pub clk_apb3_adc1_cfg: CLK_APB3_ADC1_CFG,
+ #[doc = "0x124 - CLK_APB3_ADC1 clock status register"]
+ pub clk_apb3_adc1_stat: CLK_APB3_ADC1_STAT,
+ #[doc = "0x128 - CLK_APB3_CAN0 clock configuration register"]
+ pub clk_apb3_can0_cfg: CLK_APB3_CAN0_CFG,
+ #[doc = "0x12c - CLK_APB3_CAN0 clock status register"]
+ pub clk_apb3_can0_stat: CLK_APB3_CAN0_STAT,
+ _reserved1: [u8; 208usize],
+ #[doc = "0x200 - CLK_APB1_BUS clock configuration register"]
+ pub clk_apb1_bus_cfg: CLK_APB1_BUS_CFG,
+ #[doc = "0x204 - CLK_APB1_BUS clock status register"]
+ pub clk_apb1_bus_stat: CLK_APB1_BUS_STAT,
+ #[doc = "0x208 - CLK_APB1_MOTOCONPWM clock configuration register"]
+ pub clk_apb1_motoconpwm_cfg: CLK_APB1_MOTOCONPWM_CFG,
+ #[doc = "0x20c - CLK_APB1_MOTOCONPWM clock status register"]
+ pub clk_apb1_motoconpwm_stat: CLK_APB1_MOTOCONPWM_STAT,
+ #[doc = "0x210 - CLK_ABP1_I2C0 clock configuration register"]
+ pub clk_apb1_i2c0_cfg: CLK_APB1_I2C0_CFG,
+ #[doc = "0x214 - CLK_APB1_I2C0 clock status register"]
+ pub clk_apb1_i2c0_stat: CLK_APB1_I2C0_STAT,
+ #[doc = "0x218 - CLK_APB1_I2S clock configuration register"]
+ pub clk_apb1_i2s_cfg: CLK_APB1_I2S_CFG,
+ #[doc = "0x21c - CLK_APB1_I2S clock status register"]
+ pub clk_apb1_i2s_stat: CLK_APB1_I2S_STAT,
+ #[doc = "0x220 - CLK_APB1_CAN1 clock configuration register"]
+ pub clk_apb1_can1_cfg: CLK_APB1_CAN1_CFG,
+ #[doc = "0x224 - CLK_APB1_CAN1 clock status register"]
+ pub clk_apb1_can1_stat: CLK_APB1_CAN1_STAT,
+ _reserved2: [u8; 216usize],
+ #[doc = "0x300 - CLK_SPIFI clock configuration register"] pub clk_spifi_cfg: CLK_SPIFI_CFG,
+ #[doc = "0x304 - CLK_APB1_SPIFI clock status register"] pub clk_spifi_stat: CLK_SPIFI_STAT,
+ _reserved3: [u8; 248usize],
+ #[doc = "0x400 - CLK_M4_BUS clock configuration register"]
+ pub clk_m4_bus_cfg: CLK_M4_BUS_CFG,
+ #[doc = "0x404 - CLK_M4_BUSclock status register"] pub clk_m4_bus_stat: CLK_M4_BUS_STAT,
+ #[doc = "0x408 - CLK_M4_SPIFI clock configuration register"]
+ pub clk_m4_spifi_cfg: CLK_M4_SPIFI_CFG,
+ #[doc = "0x40c - CLK_M4_SPIFI clock status register"]
+ pub clk_m4_spifi_stat: CLK_M4_SPIFI_STAT,
+ #[doc = "0x410 - CLK_M4_GPIO clock configuration register"]
+ pub clk_m4_gpio_cfg: CLK_M4_GPIO_CFG,
+ #[doc = "0x414 - CLK_M4_GPIO clock status register"] pub clk_m4_gpio_stat: CLK_M4_GPIO_STAT,
+ #[doc = "0x418 - CLK_M4_LCD clock configuration register"]
+ pub clk_m4_lcd_cfg: CLK_M4_LCD_CFG,
+ #[doc = "0x41c - CLK_M4_LCD clock status register"] pub clk_m4_lcd_stat: CLK_M4_LCD_STAT,
+ #[doc = "0x420 - CLK_M4_ETHERNET clock configuration register"]
+ pub clk_m4_ethernet_cfg: CLK_M4_ETHERNET_CFG,
+ #[doc = "0x424 - CLK_M4_ETHERNET clock status register"]
+ pub clk_m4_ethernet_stat: CLK_M4_ETHERNET_STAT,
+ #[doc = "0x428 - CLK_M4_USB0 clock configuration register"]
+ pub clk_m4_usb0_cfg: CLK_M4_USB0_CFG,
+ #[doc = "0x42c - CLK_M4_USB0 clock status register"] pub clk_m4_usb0_stat: CLK_M4_USB0_STAT,
+ #[doc = "0x430 - CLK_M4_EMC clock configuration register"]
+ pub clk_m4_emc_cfg: CLK_M4_EMC_CFG,
+ #[doc = "0x434 - CLK_M4_EMC clock status register"] pub clk_m4_emc_stat: CLK_M4_EMC_STAT,
+ #[doc = "0x438 - CLK_M4_SDIO clock configuration register"]
+ pub clk_m4_sdio_cfg: CLK_M4_SDIO_CFG,
+ #[doc = "0x43c - CLK_M4_SDIO clock status register"] pub clk_m4_sdio_stat: CLK_M4_SDIO_STAT,
+ #[doc = "0x440 - CLK_M4_DMA clock configuration register"]
+ pub clk_m4_dma_cfg: CLK_M4_DMA_CFG,
+ #[doc = "0x444 - CLK_M4_DMA clock status register"] pub clk_m4_dma_stat: CLK_M4_DMA_STAT,
+ #[doc = "0x448 - CLK_M4_M4CORE clock configuration register"]
+ pub clk_m4_m4core_cfg: CLK_M4_M4CORE_CFG,
+ #[doc = "0x44c - CLK_M4_M3CORE clock status register"]
+ pub clk_m4_m4core_stat: CLK_M4_M4CORE_STAT,
+ _reserved4: [u8; 24usize],
+ #[doc = "0x468 - CLK_M4_SCT clock configuration register"]
+ pub clk_m4_sct_cfg: CLK_M4_SCT_CFG,
+ #[doc = "0x46c - CLK_M4_SCT clock status register"] pub clk_m4_sct_stat: CLK_M4_SCT_STAT,
+ #[doc = "0x470 - CLK_M4_USB1 clock configuration register"]
+ pub clk_m4_usb1_cfg: CLK_M4_USB1_CFG,
+ #[doc = "0x474 - CLK_M4_USB1 clock status register"] pub clk_m4_usb1_stat: CLK_M4_USB1_STAT,
+ #[doc = "0x478 - CLK_M4_EMCDIV clock configuration register"]
+ pub clk_m4_emcdiv_cfg: CLK_M4_EMCDIV_CFG,
+ #[doc = "0x47c - CLK_M4_EMCDIV clock status register"]
+ pub clk_m4_emcdiv_stat: CLK_M4_EMCDIV_STAT,
+ #[doc = "0x480 - CLK_M4_FLASHA clock configuration register"]
+ pub clk_m4_flasha_cfg: CLK_M4_FLASHA_CFG,
+ #[doc = "0x484 - CLK_M4_FLASHA clock status register"]
+ pub clk_m4_flasha_stat: CLK_M4_FLASHA_STAT,
+ #[doc = "0x488 - CLK_M4_FLASHB clock configuration register"]
+ pub clk_m4_flashb_cfg: CLK_M4_FLASHB_CFG,
+ #[doc = "0x48c - CLK_M4_FLASHB clock status register"]
+ pub clk_m4_flashb_stat: CLK_M4_FLASHB_STAT,
+ #[doc = "0x490 - CLK_M0APP_CFG clock configuration register"]
+ pub clk_m4_m0app_cfg: CLK_M4_M0APP_CFG,
+ #[doc = "0x494 - CLK_M4_MOAPP clock status register"]
+ pub clk_m4_m0app_stat: CLK_M4_M0APP_STAT,
+ #[doc = "0x498 - CLK_ADCHS_CFG clock configuration register"]
+ pub clk_m4_adchs_cfg: CLK_M4_ADCHS_CFG,
+ #[doc = "0x49c - CLK_M4_ADCHS clock status register"]
+ pub clk_m4_adchs_stat: CLK_M4_ADCHS_STAT,
+ #[doc = "0x4a0 - CLK_EEPROM_CFG clock configuration register"]
+ pub clk_m4_eeprom_cfg: CLK_M4_EEPROM_CFG,
+ #[doc = "0x4a4 - CLK_M4_EEPROM clock status register"]
+ pub clk_m4_eeprom_stat: CLK_M4_EEPROM_STAT,
+ _reserved5: [u8; 88usize],
+ #[doc = "0x500 - CLK_M4_WWDT clock configuration register"]
+ pub clk_m4_wwdt_cfg: CLK_M4_WWDT_CFG,
+ #[doc = "0x504 - CLK_M4_WWDT clock status register"] pub clk_m4_wwdt_stat: CLK_M4_WWDT_STAT,
+ #[doc = "0x508 - CLK_M4_USART0 clock configuration register"]
+ pub clk_m4_usart0_cfg: CLK_M4_USART0_CFG,
+ #[doc = "0x50c - CLK_M4_USART0 clock status register"]
+ pub clk_m4_usart0_stat: CLK_M4_USART0_STAT,
+ #[doc = "0x510 - CLK_M4_UART1 clock configuration register"]
+ pub clk_m4_uart1_cfg: CLK_M4_UART1_CFG,
+ #[doc = "0x514 - CLK_M4_UART1 clock status register"]
+ pub clk_m4_uart1_stat: CLK_M4_UART1_STAT,
+ #[doc = "0x518 - CLK_M4_SSP0 clock configuration register"]
+ pub clk_m4_ssp0_cfg: CLK_M4_SSP0_CFG,
+ #[doc = "0x51c - CLK_M4_SSP0 clock status register"] pub clk_m4_ssp0_stat: CLK_M4_SSP0_STAT,
+ #[doc = "0x520 - CLK_M4_TIMER0 clock configuration register"]
+ pub clk_m4_timer0_cfg: CLK_M4_TIMER0_CFG,
+ #[doc = "0x524 - CLK_M4_TIMER0 clock status register"]
+ pub clk_m4_timer0_stat: CLK_M4_TIMER0_STAT,
+ #[doc = "0x528 - CLK_M4_TIMER1clock configuration register"]
+ pub clk_m4_timer1_cfg: CLK_M4_TIMER1_CFG,
+ #[doc = "0x52c - CLK_M4_TIMER1 clock status register"]
+ pub clk_m4_timer1_stat: CLK_M4_TIMER1_STAT,
+ #[doc = "0x530 - CLK_M4_SCU clock configuration register"]
+ pub clk_m4_scu_cfg: CLK_M4_SCU_CFG,
+ #[doc = "0x534 - CLK_SCU_XXX clock status register"] pub clk_m4_scu_stat: CLK_M4_SCU_STAT,
+ #[doc = "0x538 - CLK_M4_CREGclock configuration register"]
+ pub clk_m4_creg_cfg: CLK_M4_CREG_CFG,
+ #[doc = "0x53c - CLK_M4_CREG clock status register"] pub clk_m4_creg_stat: CLK_M4_CREG_STAT,
+ _reserved6: [u8; 192usize],
+ #[doc = "0x600 - CLK_M4_RITIMER clock configuration register"]
+ pub clk_m4_ritimer_cfg: CLK_M4_RITIMER_CFG,
+ #[doc = "0x604 - CLK_M4_RITIMER clock status register"]
+ pub clk_m4_ritimer_stat: CLK_M4_RITIMER_STAT,
+ #[doc = "0x608 - CLK_M4_USART2 clock configuration register"]
+ pub clk_m4_usart2_cfg: CLK_M4_USART2_CFG,
+ #[doc = "0x60c - CLK_M4_USART2 clock status register"]
+ pub clk_m4_usart2_stat: CLK_M4_USART2_STAT,
+ #[doc = "0x610 - CLK_M4_USART3 clock configuration register"]
+ pub clk_m4_usart3_cfg: CLK_M4_USART3_CFG,
+ #[doc = "0x614 - CLK_M4_USART3 clock status register"]
+ pub clk_m4_usart3_stat: CLK_M4_USART3_STAT,
+ #[doc = "0x618 - CLK_M4_TIMER2 clock configuration register"]
+ pub clk_m4_timer2_cfg: CLK_M4_TIMER2_CFG,
+ #[doc = "0x61c - CLK_M4_TIMER2 clock status register"]
+ pub clk_m4_timer2_stat: CLK_M4_TIMER2_STAT,
+ #[doc = "0x620 - CLK_M4_TIMER3 clock configuration register"]
+ pub clk_m4_timer3_cfg: CLK_M4_TIMER3_CFG,
+ #[doc = "0x624 - CLK_M4_TIMER3 clock status register"]
+ pub clk_m4_timer3_stat: CLK_M4_TIMER3_STAT,
+ #[doc = "0x628 - CLK_M4_SSP1 clock configuration register"]
+ pub clk_m4_ssp1_cfg: CLK_M4_SSP1_CFG,
+ #[doc = "0x62c - CLK_M4_SSP1 clock status register"] pub clk_m4_ssp1_stat: CLK_M4_SSP1_STAT,
+ #[doc = "0x630 - CLK_M4_QEIclock configuration register"]
+ pub clk_m4_qei_cfg: CLK_M4_QEI_CFG,
+ #[doc = "0x634 - CLK_M4_QEI clock status register"] pub clk_m4_qei_stat: CLK_M4_QEI_STAT,
+ _reserved7: [u8; 200usize],
+ #[doc = "0x700 - CLK_PERIPH_BUS_CFG clock configuration register"]
+ pub clk_periph_bus_cfg: CLK_PERIPH_BUS_CFG,
+ #[doc = "0x704 - CLK_PERIPH_BUS_STAT clock status register"]
+ pub clk_periph_bus_stat: CLK_PERIPH_BUS_STAT,
+ _reserved8: [u8; 8usize],
+ #[doc = "0x710 - CLK_PERIPH_CORE_CFG clock configuration register"]
+ pub clk_periph_core_cfg: CLK_PERIPH_CORE_CFG,
+ #[doc = "0x714 - CLK_CORE_BUS_STAT clock status register"]
+ pub clk_periph_core_stat: CLK_PERIPH_CORE_STAT,
+ #[doc = "0x718 - CLK_PERIPH_SGPIO_CFG clock configuration register"]
+ pub clk_periph_sgpio_cfg: CLK_PERIPH_SGPIO_CFG,
+ #[doc = "0x71c - CLK_CORE_SGPIO_STAT clock status register"]
+ pub clk_periph_sgpio_stat: CLK_PERIPH_SGPIO_STAT,
+ _reserved9: [u8; 224usize],
+ #[doc = "0x800 - CLK_M4_USB0 clock configuration register"] pub clk_usb0_cfg: CLK_USB0_CFG,
+ #[doc = "0x804 - CLK_USB0 clock status register"] pub clk_usb0_stat: CLK_USB0_STAT,
+ _reserved10: [u8; 248usize],
+ #[doc = "0x900 - CLK_USB1 clock configuration register"] pub clk_usb1_cfg: CLK_USB1_CFG,
+ #[doc = "0x904 - CLK_USB1 clock status register"] pub clk_usb1_stat: CLK_USB1_STAT,
+ _reserved11: [u8; 248usize],
+ #[doc = "0xa00 - CLK_SPI clock configuration register"] pub clk_spi_cfg: CLK_SPI_CFG,
+ #[doc = "0xa04 - CLK_SPI clock status register"] pub clk_spi_stat: CLK_SPI_STAT,
+ _reserved12: [u8; 248usize],
+ #[doc = "0xb00 - CLK_ADCHS clock configuration register"] pub clk_adchs_cfg: CLK_ADCHS_CFG,
+ #[doc = "0xb04 - CLK_ADCHS clock status register"] pub clk_adchs_stat: CLK_ADCHS_STAT,
+ }
#[doc = "CCU1 power mode register"]
pub struct PM {
register: VolatileCell<u32>,
@@ -150765,8 +145993,7 @@ pub mod ccu1 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PDR {
#[doc = "Normal operation."] NORMAL_OPERATION_,
- #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."]
- CLOCKS_WITH_WAKE_UP_,
+ #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."] CLOCKS_WITH_WAKE_UP_,
}
impl PDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -150810,8 +146037,7 @@ pub mod ccu1 {
#[doc = "Values that can be written to the field `PD`"]
pub enum PDW {
#[doc = "Normal operation."] NORMAL_OPERATION_,
- #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."]
- CLOCKS_WITH_WAKE_UP_,
+ #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."] CLOCKS_WITH_WAKE_UP_,
}
impl PDW {
#[allow(missing_docs)]
@@ -151050,8 +146276,7 @@ pub mod ccu1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_apb3_clk_ind(&self) -> BASE_APB3_CLK_INDR {
let bits = {
const MASK: bool = true;
@@ -151060,8 +146285,7 @@ pub mod ccu1 {
};
BASE_APB3_CLK_INDR { bits }
}
- #[doc = "Bit 1 - Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_apb1_clk_ind(&self) -> BASE_APB1_CLK_INDR {
let bits = {
const MASK: bool = true;
@@ -151070,8 +146294,7 @@ pub mod ccu1 {
};
BASE_APB1_CLK_INDR { bits }
}
- #[doc = "Bit 2 - Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_spifi_clk_ind(&self) -> BASE_SPIFI_CLK_INDR {
let bits = {
const MASK: bool = true;
@@ -151080,8 +146303,7 @@ pub mod ccu1 {
};
BASE_SPIFI_CLK_INDR { bits }
}
- #[doc = "Bit 3 - Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_m3_clk_ind(&self) -> BASE_M3_CLK_INDR {
let bits = {
const MASK: bool = true;
@@ -151090,8 +146312,7 @@ pub mod ccu1 {
};
BASE_M3_CLK_INDR { bits }
}
- #[doc = "Bit 7 - Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_usb0_clk_ind(&self) -> BASE_USB0_CLK_INDR {
let bits = {
const MASK: bool = true;
@@ -151100,8 +146321,7 @@ pub mod ccu1 {
};
BASE_USB0_CLK_INDR { bits }
}
- #[doc = "Bit 8 - Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." ] # [ inline ( always ) ]
pub fn base_usb1_clk_ind(&self) -> BASE_USB1_CLK_INDR {
let bits = {
const MASK: bool = true;
@@ -172940,8 +168160,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -172950,8 +168169,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173060,8 +168278,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173070,8 +168287,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173180,8 +168396,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173190,8 +168405,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173300,8 +168514,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173310,8 +168523,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173420,8 +168632,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173430,8 +168641,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173540,8 +168750,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173550,8 +168759,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173660,8 +168868,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173670,8 +168877,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173780,8 +168986,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173790,8 +168995,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -173900,8 +169104,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -173910,8 +169113,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174020,8 +169222,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174030,8 +169231,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174140,8 +169340,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174150,8 +169349,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174260,8 +169458,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174270,8 +169467,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174380,8 +169576,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174390,8 +169585,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174500,8 +169694,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174510,8 +169703,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174620,8 +169812,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174630,8 +169821,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174740,8 +169930,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174750,8 +169939,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174860,8 +170048,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174870,8 +170057,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -174980,8 +170166,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -174990,8 +170175,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175100,8 +170284,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175110,8 +170293,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175220,8 +170402,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175230,8 +170411,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175340,8 +170520,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175350,8 +170529,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175460,8 +170638,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175470,8 +170647,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175580,8 +170756,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175590,8 +170765,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175700,8 +170874,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175710,8 +170883,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175820,8 +170992,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175830,8 +171001,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -175940,8 +171110,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -175950,8 +171119,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176060,8 +171228,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176070,8 +171237,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176180,8 +171346,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176190,8 +171355,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176300,8 +171464,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176310,8 +171473,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176420,8 +171582,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176430,8 +171591,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176540,8 +171700,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176550,8 +171709,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176660,8 +171818,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176670,8 +171827,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176780,8 +171936,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176790,8 +171945,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -176900,8 +172054,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -176910,8 +172063,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177020,8 +172172,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177030,8 +172181,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177140,8 +172290,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177150,8 +172299,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177260,8 +172408,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177270,8 +172417,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177380,8 +172526,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177390,8 +172535,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177500,8 +172644,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177510,8 +172653,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177620,8 +172762,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177630,8 +172771,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177740,8 +172880,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177750,8 +172889,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177860,8 +172998,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177870,8 +173007,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -177980,8 +173116,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -177990,8 +173125,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178100,8 +173234,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178110,8 +173243,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178220,8 +173352,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178230,8 +173361,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178340,8 +173470,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178350,8 +173479,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178460,8 +173588,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178470,8 +173597,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178580,8 +173706,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178590,8 +173715,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178700,8 +173824,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178710,8 +173833,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178820,8 +173942,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178830,8 +173951,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -178940,8 +174060,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -178950,8 +174069,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -179060,8 +174178,7 @@ pub mod ccu1 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -179070,8 +174187,7 @@ pub mod ccu1 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -179102,13 +174218,10 @@ pub mod ccu2 {
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Power mode register"] pub pm: PM,
- #[doc = "0x04 - CCU base clocks status register"]
- pub base_stat: BASE_STAT,
+ #[doc = "0x04 - CCU base clocks status register"] pub base_stat: BASE_STAT,
_reserved0: [u8; 248usize],
- #[doc = "0x100 - CLK_AUDIO clock configuration register"]
- pub clk_audio_cfg: CLK_AUDIO_CFG,
- #[doc = "0x104 - CLK_AUDIO clock status register"]
- pub clk_audio_stat: CLK_AUDIO_STAT,
+ #[doc = "0x100 - CLK_AUDIO clock configuration register"] pub clk_audio_cfg: CLK_AUDIO_CFG,
+ #[doc = "0x104 - CLK_AUDIO clock status register"] pub clk_audio_stat: CLK_AUDIO_STAT,
_reserved1: [u8; 248usize],
#[doc = "0x200 - CLK_APB2_USART3 clock configuration register"]
pub clk_apb2_usart3_cfg: CLK_APB2_USART3_CFG,
@@ -179140,10 +174253,8 @@ pub mod ccu2 {
#[doc = "0x704 - CLK_APB0_SSP0 clock status register"]
pub clk_apb0_ssp0_stat: CLK_APB0_SSP0_STAT,
_reserved7: [u8; 248usize],
- #[doc = "0x800 - CLK_SDIO clock configuration register"]
- pub clk_sdio_cfg: CLK_SDIO_CFG,
- #[doc = "0x804 - CLK_SDIO clock status register"]
- pub clk_sdio_stat: CLK_SDIO_STAT,
+ #[doc = "0x800 - CLK_SDIO clock configuration register"] pub clk_sdio_cfg: CLK_SDIO_CFG,
+ #[doc = "0x804 - CLK_SDIO clock status register"] pub clk_sdio_stat: CLK_SDIO_STAT,
}
#[doc = "Power mode register"]
pub struct PM {
@@ -179199,8 +174310,7 @@ pub mod ccu2 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PDR {
#[doc = "Normal operation."] NORMAL_OPERATION_,
- #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."]
- CLOCKS_WITH_WAKE_UP_,
+ #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."] CLOCKS_WITH_WAKE_UP_,
}
impl PDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -179244,8 +174354,7 @@ pub mod ccu2 {
#[doc = "Values that can be written to the field `PD`"]
pub enum PDW {
#[doc = "Normal operation."] NORMAL_OPERATION_,
- #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."]
- CLOCKS_WITH_WAKE_UP_,
+ #[doc = "Clocks with wake-up mode enabled (W = 1) are disabled."] CLOCKS_WITH_WAKE_UP_,
}
impl PDW {
#[allow(missing_docs)]
@@ -179484,8 +174593,7 @@ pub mod ccu2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 1 - Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_uart3_clk(&self) -> BASE_UART3_CLKR {
let bits = {
const MASK: bool = true;
@@ -179494,8 +174602,7 @@ pub mod ccu2 {
};
BASE_UART3_CLKR { bits }
}
- #[doc = "Bit 2 - Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_uart2_clk(&self) -> BASE_UART2_CLKR {
let bits = {
const MASK: bool = true;
@@ -179504,8 +174611,7 @@ pub mod ccu2 {
};
BASE_UART2_CLKR { bits }
}
- #[doc = "Bit 3 - Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_uart1_clk(&self) -> BASE_UART1_CLKR {
let bits = {
const MASK: bool = true;
@@ -179514,8 +174620,7 @@ pub mod ccu2 {
};
BASE_UART1_CLKR { bits }
}
- #[doc = "Bit 4 - Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_uart0_clk(&self) -> BASE_UART0_CLKR {
let bits = {
const MASK: bool = true;
@@ -179524,8 +174629,7 @@ pub mod ccu2 {
};
BASE_UART0_CLKR { bits }
}
- #[doc = "Bit 5 - Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_ssp1_clk(&self) -> BASE_SSP1_CLKR {
let bits = {
const MASK: bool = true;
@@ -179534,8 +174638,7 @@ pub mod ccu2 {
};
BASE_SSP1_CLKR { bits }
}
- #[doc = "Bit 6 - Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." ] # [ inline ( always ) ]
pub fn base_ssp0_clk(&self) -> BASE_SSP0_CLKR {
let bits = {
const MASK: bool = true;
@@ -182972,8 +178075,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -182982,8 +178084,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183092,8 +178193,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -183102,8 +178202,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183212,8 +178311,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -183222,8 +178320,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183332,8 +178429,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -183342,8 +178438,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183452,8 +178547,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -183462,8 +178556,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183572,8 +178665,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -183582,8 +178674,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183692,8 +178783,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -183702,8 +178792,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183812,8 +178901,7 @@ pub mod ccu2 {
};
RUNR { bits }
}
- #[doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." ] # [ inline ( always ) ]
pub fn auto(&self) -> AUTOR {
let bits = {
const MASK: bool = true;
@@ -183822,8 +178910,7 @@ pub mod ccu2 {
};
AUTOR { bits }
}
- #[doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." ] # [ inline ( always ) ]
pub fn wakeup(&self) -> WAKEUPR {
let bits = {
const MASK: bool = true;
@@ -183852,7 +178939,79 @@ pub mod rgu {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock { _reserved0 : [ u8 ; 256usize ] , # [ doc = "0x100 - Reset control register 0" ] pub reset_ctrl0 : RESET_CTRL0 , # [ doc = "0x104 - Reset control register 1" ] pub reset_ctrl1 : RESET_CTRL1 , _reserved1 : [ u8 ; 8usize ] , # [ doc = "0x110 - Reset status register 0" ] pub reset_status0 : RESET_STATUS0 , # [ doc = "0x114 - Reset status register 1" ] pub reset_status1 : RESET_STATUS1 , # [ doc = "0x118 - Reset status register 2" ] pub reset_status2 : RESET_STATUS2 , # [ doc = "0x11c - Reset status register 3" ] pub reset_status3 : RESET_STATUS3 , _reserved2 : [ u8 ; 48usize ] , # [ doc = "0x150 - Reset active status register 0" ] pub reset_active_status0 : RESET_ACTIVE_STATUS0 , # [ doc = "0x154 - Reset active status register 1" ] pub reset_active_status1 : RESET_ACTIVE_STATUS1 , _reserved3 : [ u8 ; 684usize ] , # [ doc = "0x404 - Reset external status register 1 for PERIPH_RST" ] pub reset_ext_stat1 : RESET_EXT_STAT1 , # [ doc = "0x408 - Reset external status register 2 for MASTER_RST" ] pub reset_ext_stat2 : RESET_EXT_STAT2 , _reserved4 : [ u8 ; 8usize ] , # [ doc = "0x414 - Reset external status register 5 for CREG_RST" ] pub reset_ext_stat5 : RESET_EXT_STAT5 , _reserved5 : [ u8 ; 8usize ] , # [ doc = "0x420 - Reset external status register" ] pub reset_ext_stat8 : RESET_EXT_STAT8 , # [ doc = "0x424 - Reset external status register" ] pub reset_ext_stat9 : RESET_EXT_STAT9 , _reserved6 : [ u8 ; 8usize ] , # [ doc = "0x430 - Reset external status register" ] pub reset_ext_stat12 : RESET_EXT_STAT12 , # [ doc = "0x434 - Reset external status register" ] pub reset_ext_stat13 : RESET_EXT_STAT13 , _reserved7 : [ u8 ; 8usize ] , # [ doc = "0x440 - Reset external status register" ] pub reset_ext_stat16 : RESET_EXT_STAT16 , # [ doc = "0x444 - Reset external status register" ] pub reset_ext_stat17 : RESET_EXT_STAT17 , # [ doc = "0x448 - Reset external status register" ] pub reset_ext_stat18 : RESET_EXT_STAT18 , # [ doc = "0x44c - Reset external status register" ] pub reset_ext_stat19 : RESET_EXT_STAT19 , # [ doc = "0x450 - Reset external status register" ] pub reset_ext_stat20 : RESET_EXT_STAT20 , # [ doc = "0x454 - Reset external status register" ] pub reset_ext_stat21 : RESET_EXT_STAT21 , # [ doc = "0x458 - Reset external status register" ] pub reset_ext_stat22 : RESET_EXT_STAT22 , _reserved8 : [ u8 ; 8usize ] , # [ doc = "0x464 - Reset external status register" ] pub reset_ext_stat25 : RESET_EXT_STAT25 , _reserved9 : [ u8 ; 4usize ] , # [ doc = "0x46c - Reset external status register" ] pub reset_ext_stat27 : RESET_EXT_STAT27 , # [ doc = "0x470 - Reset external status register" ] pub reset_ext_stat28 : RESET_EXT_STAT28 , # [ doc = "0x474 - Reset external status register" ] pub reset_ext_stat29 : RESET_EXT_STAT29 , _reserved10 : [ u8 ; 8usize ] , # [ doc = "0x480 - Reset external status register" ] pub reset_ext_stat32 : RESET_EXT_STAT32 , # [ doc = "0x484 - Reset external status register" ] pub reset_ext_stat33 : RESET_EXT_STAT33 , # [ doc = "0x488 - Reset external status register" ] pub reset_ext_stat34 : RESET_EXT_STAT34 , # [ doc = "0x48c - Reset external status register" ] pub reset_ext_stat35 : RESET_EXT_STAT35 , # [ doc = "0x490 - Reset external status register" ] pub reset_ext_stat36 : RESET_EXT_STAT36 , # [ doc = "0x494 - Reset external status register" ] pub reset_ext_stat37 : RESET_EXT_STAT37 , # [ doc = "0x498 - Reset external status register" ] pub reset_ext_stat38 : RESET_EXT_STAT38 , # [ doc = "0x49c - Reset external status register" ] pub reset_ext_stat39 : RESET_EXT_STAT39 , # [ doc = "0x4a0 - Reset external status register" ] pub reset_ext_stat40 : RESET_EXT_STAT40 , # [ doc = "0x4a4 - Reset external status register" ] pub reset_ext_stat41 : RESET_EXT_STAT41 , # [ doc = "0x4a8 - Reset external status register" ] pub reset_ext_stat42 : RESET_EXT_STAT42 , _reserved11 : [ u8 ; 4usize ] , # [ doc = "0x4b0 - Reset external status register" ] pub reset_ext_stat44 : RESET_EXT_STAT44 , # [ doc = "0x4b4 - Reset external status register" ] pub reset_ext_stat45 : RESET_EXT_STAT45 , # [ doc = "0x4b8 - Reset external status register" ] pub reset_ext_stat46 : RESET_EXT_STAT46 , # [ doc = "0x4bc - Reset external status register" ] pub reset_ext_stat47 : RESET_EXT_STAT47 , # [ doc = "0x4c0 - Reset external status register" ] pub reset_ext_stat48 : RESET_EXT_STAT48 , # [ doc = "0x4c4 - Reset external status register" ] pub reset_ext_stat49 : RESET_EXT_STAT49 , # [ doc = "0x4c8 - Reset external status register" ] pub reset_ext_stat50 : RESET_EXT_STAT50 , # [ doc = "0x4cc - Reset external status register" ] pub reset_ext_stat51 : RESET_EXT_STAT51 , # [ doc = "0x4d0 - Reset external status register" ] pub reset_ext_stat52 : RESET_EXT_STAT52 , # [ doc = "0x4d4 - Reset external status register" ] pub reset_ext_stat53 : RESET_EXT_STAT53 , # [ doc = "0x4d8 - Reset external status register" ] pub reset_ext_stat54 : RESET_EXT_STAT54 , # [ doc = "0x4dc - Reset external status register" ] pub reset_ext_stat55 : RESET_EXT_STAT55 , # [ doc = "0x4e0 - Reset external status register" ] pub reset_ext_stat56 : RESET_EXT_STAT56 , # [ doc = "0x4e4 - Reset external status register" ] pub reset_ext_stat57 : RESET_EXT_STAT57 , # [ doc = "0x4e8 - Reset external status register" ] pub reset_ext_stat58 : RESET_EXT_STAT58 , _reserved12 : [ u8 ; 4usize ] , # [ doc = "0x4f0 - Reset external status register" ] pub reset_ext_stat60 : RESET_EXT_STAT60 , }
+ pub struct RegisterBlock {
+ _reserved0: [u8; 256usize],
+ #[doc = "0x100 - Reset control register 0"] pub reset_ctrl0: RESET_CTRL0,
+ #[doc = "0x104 - Reset control register 1"] pub reset_ctrl1: RESET_CTRL1,
+ _reserved1: [u8; 8usize],
+ #[doc = "0x110 - Reset status register 0"] pub reset_status0: RESET_STATUS0,
+ #[doc = "0x114 - Reset status register 1"] pub reset_status1: RESET_STATUS1,
+ #[doc = "0x118 - Reset status register 2"] pub reset_status2: RESET_STATUS2,
+ #[doc = "0x11c - Reset status register 3"] pub reset_status3: RESET_STATUS3,
+ _reserved2: [u8; 48usize],
+ #[doc = "0x150 - Reset active status register 0"]
+ pub reset_active_status0: RESET_ACTIVE_STATUS0,
+ #[doc = "0x154 - Reset active status register 1"]
+ pub reset_active_status1: RESET_ACTIVE_STATUS1,
+ _reserved3: [u8; 684usize],
+ #[doc = "0x404 - Reset external status register 1 for PERIPH_RST"]
+ pub reset_ext_stat1: RESET_EXT_STAT1,
+ #[doc = "0x408 - Reset external status register 2 for MASTER_RST"]
+ pub reset_ext_stat2: RESET_EXT_STAT2,
+ _reserved4: [u8; 8usize],
+ #[doc = "0x414 - Reset external status register 5 for CREG_RST"]
+ pub reset_ext_stat5: RESET_EXT_STAT5,
+ _reserved5: [u8; 8usize],
+ #[doc = "0x420 - Reset external status register"] pub reset_ext_stat8: RESET_EXT_STAT8,
+ #[doc = "0x424 - Reset external status register"] pub reset_ext_stat9: RESET_EXT_STAT9,
+ _reserved6: [u8; 8usize],
+ #[doc = "0x430 - Reset external status register"] pub reset_ext_stat12: RESET_EXT_STAT12,
+ #[doc = "0x434 - Reset external status register"] pub reset_ext_stat13: RESET_EXT_STAT13,
+ _reserved7: [u8; 8usize],
+ #[doc = "0x440 - Reset external status register"] pub reset_ext_stat16: RESET_EXT_STAT16,
+ #[doc = "0x444 - Reset external status register"] pub reset_ext_stat17: RESET_EXT_STAT17,
+ #[doc = "0x448 - Reset external status register"] pub reset_ext_stat18: RESET_EXT_STAT18,
+ #[doc = "0x44c - Reset external status register"] pub reset_ext_stat19: RESET_EXT_STAT19,
+ #[doc = "0x450 - Reset external status register"] pub reset_ext_stat20: RESET_EXT_STAT20,
+ #[doc = "0x454 - Reset external status register"] pub reset_ext_stat21: RESET_EXT_STAT21,
+ #[doc = "0x458 - Reset external status register"] pub reset_ext_stat22: RESET_EXT_STAT22,
+ _reserved8: [u8; 8usize],
+ #[doc = "0x464 - Reset external status register"] pub reset_ext_stat25: RESET_EXT_STAT25,
+ _reserved9: [u8; 4usize],
+ #[doc = "0x46c - Reset external status register"] pub reset_ext_stat27: RESET_EXT_STAT27,
+ #[doc = "0x470 - Reset external status register"] pub reset_ext_stat28: RESET_EXT_STAT28,
+ #[doc = "0x474 - Reset external status register"] pub reset_ext_stat29: RESET_EXT_STAT29,
+ _reserved10: [u8; 8usize],
+ #[doc = "0x480 - Reset external status register"] pub reset_ext_stat32: RESET_EXT_STAT32,
+ #[doc = "0x484 - Reset external status register"] pub reset_ext_stat33: RESET_EXT_STAT33,
+ #[doc = "0x488 - Reset external status register"] pub reset_ext_stat34: RESET_EXT_STAT34,
+ #[doc = "0x48c - Reset external status register"] pub reset_ext_stat35: RESET_EXT_STAT35,
+ #[doc = "0x490 - Reset external status register"] pub reset_ext_stat36: RESET_EXT_STAT36,
+ #[doc = "0x494 - Reset external status register"] pub reset_ext_stat37: RESET_EXT_STAT37,
+ #[doc = "0x498 - Reset external status register"] pub reset_ext_stat38: RESET_EXT_STAT38,
+ #[doc = "0x49c - Reset external status register"] pub reset_ext_stat39: RESET_EXT_STAT39,
+ #[doc = "0x4a0 - Reset external status register"] pub reset_ext_stat40: RESET_EXT_STAT40,
+ #[doc = "0x4a4 - Reset external status register"] pub reset_ext_stat41: RESET_EXT_STAT41,
+ #[doc = "0x4a8 - Reset external status register"] pub reset_ext_stat42: RESET_EXT_STAT42,
+ _reserved11: [u8; 4usize],
+ #[doc = "0x4b0 - Reset external status register"] pub reset_ext_stat44: RESET_EXT_STAT44,
+ #[doc = "0x4b4 - Reset external status register"] pub reset_ext_stat45: RESET_EXT_STAT45,
+ #[doc = "0x4b8 - Reset external status register"] pub reset_ext_stat46: RESET_EXT_STAT46,
+ #[doc = "0x4bc - Reset external status register"] pub reset_ext_stat47: RESET_EXT_STAT47,
+ #[doc = "0x4c0 - Reset external status register"] pub reset_ext_stat48: RESET_EXT_STAT48,
+ #[doc = "0x4c4 - Reset external status register"] pub reset_ext_stat49: RESET_EXT_STAT49,
+ #[doc = "0x4c8 - Reset external status register"] pub reset_ext_stat50: RESET_EXT_STAT50,
+ #[doc = "0x4cc - Reset external status register"] pub reset_ext_stat51: RESET_EXT_STAT51,
+ #[doc = "0x4d0 - Reset external status register"] pub reset_ext_stat52: RESET_EXT_STAT52,
+ #[doc = "0x4d4 - Reset external status register"] pub reset_ext_stat53: RESET_EXT_STAT53,
+ #[doc = "0x4d8 - Reset external status register"] pub reset_ext_stat54: RESET_EXT_STAT54,
+ #[doc = "0x4dc - Reset external status register"] pub reset_ext_stat55: RESET_EXT_STAT55,
+ #[doc = "0x4e0 - Reset external status register"] pub reset_ext_stat56: RESET_EXT_STAT56,
+ #[doc = "0x4e4 - Reset external status register"] pub reset_ext_stat57: RESET_EXT_STAT57,
+ #[doc = "0x4e8 - Reset external status register"] pub reset_ext_stat58: RESET_EXT_STAT58,
+ _reserved12: [u8; 4usize],
+ #[doc = "0x4f0 - Reset external status register"] pub reset_ext_stat60: RESET_EXT_STAT60,
+ }
#[doc = "Reset control register 0"]
pub struct RESET_CTRL0 {
register: VolatileCell<u32>,
@@ -184347,18 +179506,15 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn core_rst(&mut self) -> _CORE_RSTW {
_CORE_RSTW { w: self }
}
- #[doc = "Bit 1 - Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." ] # [ inline ( always ) ]
pub fn periph_rst(&mut self) -> _PERIPH_RSTW {
_PERIPH_RSTW { w: self }
}
- #[doc = "Bit 2 - Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." ] # [ inline ( always ) ]
pub fn master_rst(&mut self) -> _MASTER_RSTW {
_MASTER_RSTW { w: self }
}
@@ -184372,78 +179528,63 @@ pub mod rgu {
pub fn creg_rst(&mut self) -> _CREG_RSTW {
_CREG_RSTW { w: self }
}
- #[doc = "Bit 8 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" ] # [ inline ( always ) ]
pub fn bus_rst(&mut self) -> _BUS_RSTW {
_BUS_RSTW { w: self }
}
- #[doc = "Bit 9 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn scu_rst(&mut self) -> _SCU_RSTW {
_SCU_RSTW { w: self }
}
- #[doc = "Bit 12 - Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." ] # [ inline ( always ) ]
pub fn m0_sub_rst(&mut self) -> _M0_SUB_RSTW {
_M0_SUB_RSTW { w: self }
}
- #[doc = "Bit 13 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn m4_rst(&mut self) -> _M4_RSTW {
_M4_RSTW { w: self }
}
- #[doc = "Bit 16 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn lcd_rst(&mut self) -> _LCD_RSTW {
_LCD_RSTW { w: self }
}
- #[doc = "Bit 17 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn usb0_rst(&mut self) -> _USB0_RSTW {
_USB0_RSTW { w: self }
}
- #[doc = "Bit 18 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn usb1_rst(&mut self) -> _USB1_RSTW {
_USB1_RSTW { w: self }
}
- #[doc = "Bit 19 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn dma_rst(&mut self) -> _DMA_RSTW {
_DMA_RSTW { w: self }
}
- #[doc = "Bit 20 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn sdio_rst(&mut self) -> _SDIO_RSTW {
_SDIO_RSTW { w: self }
}
- #[doc = "Bit 21 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn emc_rst(&mut self) -> _EMC_RSTW {
_EMC_RSTW { w: self }
}
- #[doc = "Bit 22 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn ethernet_rst(&mut self) -> _ETHERNET_RSTW {
_ETHERNET_RSTW { w: self }
}
- #[doc = "Bit 25 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn flasha_rst(&mut self) -> _FLASHA_RSTW {
_FLASHA_RSTW { w: self }
}
- #[doc = "Bit 27 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn eeprom_rst(&mut self) -> _EEPROM_RSTW {
_EEPROM_RSTW { w: self }
}
- #[doc = "Bit 28 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn gpio_rst(&mut self) -> _GPIO_RSTW {
_GPIO_RSTW { w: self }
}
- #[doc = "Bit 29 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn flashb_rst(&mut self) -> _FLASHB_RSTW {
_FLASHB_RSTW { w: self }
}
@@ -185104,138 +180245,111 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn timer0_rst(&mut self) -> _TIMER0_RSTW {
_TIMER0_RSTW { w: self }
}
- #[doc = "Bit 1 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn timer1_rst(&mut self) -> _TIMER1_RSTW {
_TIMER1_RSTW { w: self }
}
- #[doc = "Bit 2 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn timer2_rst(&mut self) -> _TIMER2_RSTW {
_TIMER2_RSTW { w: self }
}
- #[doc = "Bit 3 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn timer3_rst(&mut self) -> _TIMER3_RSTW {
_TIMER3_RSTW { w: self }
}
- #[doc = "Bit 4 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn ritimer_rst(&mut self) -> _RITIMER_RSTW {
_RITIMER_RSTW { w: self }
}
- #[doc = "Bit 5 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn sct_rst(&mut self) -> _SCT_RSTW {
_SCT_RSTW { w: self }
}
- #[doc = "Bit 6 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn motoconpwm_rst(&mut self) -> _MOTOCONPWM_RSTW {
_MOTOCONPWM_RSTW { w: self }
}
- #[doc = "Bit 7 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn qei_rst(&mut self) -> _QEI_RSTW {
_QEI_RSTW { w: self }
}
- #[doc = "Bit 8 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn adc0_rst(&mut self) -> _ADC0_RSTW {
_ADC0_RSTW { w: self }
}
- #[doc = "Bit 9 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn adc1_rst(&mut self) -> _ADC1_RSTW {
_ADC1_RSTW { w: self }
}
- #[doc = "Bit 10 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn dac_rst(&mut self) -> _DAC_RSTW {
_DAC_RSTW { w: self }
}
- #[doc = "Bit 12 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn uart0_rst(&mut self) -> _UART0_RSTW {
_UART0_RSTW { w: self }
}
- #[doc = "Bit 13 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn uart1_rst(&mut self) -> _UART1_RSTW {
_UART1_RSTW { w: self }
}
- #[doc = "Bit 14 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn uart2_rst(&mut self) -> _UART2_RSTW {
_UART2_RSTW { w: self }
}
- #[doc = "Bit 15 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn uart3_rst(&mut self) -> _UART3_RSTW {
_UART3_RSTW { w: self }
}
- #[doc = "Bit 16 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn i2c0_rst(&mut self) -> _I2C0_RSTW {
_I2C0_RSTW { w: self }
}
- #[doc = "Bit 17 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn i2c1_rst(&mut self) -> _I2C1_RSTW {
_I2C1_RSTW { w: self }
}
- #[doc = "Bit 18 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn ssp0_rst(&mut self) -> _SSP0_RSTW {
_SSP0_RSTW { w: self }
}
- #[doc = "Bit 19 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn ssp1_rst(&mut self) -> _SSP1_RSTW {
_SSP1_RSTW { w: self }
}
- #[doc = "Bit 20 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn i2s_rst(&mut self) -> _I2S_RSTW {
_I2S_RSTW { w: self }
}
- #[doc = "Bit 21 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn spifi_rst(&mut self) -> _SPIFI_RSTW {
_SPIFI_RSTW { w: self }
}
- #[doc = "Bit 22 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn can1_rst(&mut self) -> _CAN1_RSTW {
_CAN1_RSTW { w: self }
}
- #[doc = "Bit 23 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn can0_rst(&mut self) -> _CAN0_RSTW {
_CAN0_RSTW { w: self }
}
- #[doc = "Bit 24 - Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." ] # [ inline ( always ) ]
pub fn m0app_rst(&mut self) -> _M0APP_RSTW {
_M0APP_RSTW { w: self }
}
- #[doc = "Bit 25 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn sgpio_rst(&mut self) -> _SGPIO_RSTW {
_SGPIO_RSTW { w: self }
}
- #[doc = "Bit 26 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn spi_rst(&mut self) -> _SPI_RSTW {
_SPI_RSTW { w: self }
}
- #[doc = "Bit 28 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." ] # [ inline ( always ) ]
pub fn adchs_rst(&mut self) -> _ADCHS_RSTW {
_ADCHS_RSTW { w: self }
}
@@ -185505,8 +180619,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 2:3 - Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn periph_rst(&self) -> PERIPH_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185515,8 +180628,7 @@ pub mod rgu {
};
PERIPH_RSTR { bits }
}
- #[doc = "Bits 4:5 - Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn master_rst(&self) -> MASTER_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185525,8 +180637,7 @@ pub mod rgu {
};
MASTER_RSTR { bits }
}
- #[doc = "Bits 8:9 - Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" ] # [ inline ( always ) ]
pub fn wwdt_rst(&self) -> WWDT_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185535,8 +180646,7 @@ pub mod rgu {
};
WWDT_RSTR { bits }
}
- #[doc = "Bits 10:11 - Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" ] # [ inline ( always ) ]
pub fn creg_rst(&self) -> CREG_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185545,8 +180655,7 @@ pub mod rgu {
};
CREG_RSTR { bits }
}
- #[doc = "Bits 16:17 - Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn bus_rst(&self) -> BUS_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185555,8 +180664,7 @@ pub mod rgu {
};
BUS_RSTR { bits }
}
- #[doc = "Bits 18:19 - Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn scu_rst(&self) -> SCU_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185565,8 +180673,7 @@ pub mod rgu {
};
SCU_RSTR { bits }
}
- #[doc = "Bits 24:25 - Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn m0sub_rst(&self) -> M0SUB_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185575,8 +180682,7 @@ pub mod rgu {
};
M0SUB_RSTR { bits }
}
- #[doc = "Bits 26:27 - Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn m4_rst(&self) -> M4_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185598,43 +180704,35 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bits 2:3 - Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn periph_rst(&mut self) -> _PERIPH_RSTW {
_PERIPH_RSTW { w: self }
}
- #[doc = "Bits 4:5 - Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn master_rst(&mut self) -> _MASTER_RSTW {
_MASTER_RSTW { w: self }
}
- #[doc = "Bits 8:9 - Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" ] # [ inline ( always ) ]
pub fn wwdt_rst(&mut self) -> _WWDT_RSTW {
_WWDT_RSTW { w: self }
}
- #[doc = "Bits 10:11 - Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" ] # [ inline ( always ) ]
pub fn creg_rst(&mut self) -> _CREG_RSTW {
_CREG_RSTW { w: self }
}
- #[doc = "Bits 16:17 - Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn bus_rst(&mut self) -> _BUS_RSTW {
_BUS_RSTW { w: self }
}
- #[doc = "Bits 18:19 - Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn scu_rst(&mut self) -> _SCU_RSTW {
_SCU_RSTW { w: self }
}
- #[doc = "Bits 24:25 - Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn m0sub_rst(&mut self) -> _M0SUB_RSTW {
_M0SUB_RSTW { w: self }
}
- #[doc = "Bits 26:27 - Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn m4_rst(&mut self) -> _M4_RSTW {
_M4_RSTW { w: self }
}
@@ -185982,8 +181080,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn lcd_rst(&self) -> LCD_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -185992,8 +181089,7 @@ pub mod rgu {
};
LCD_RSTR { bits }
}
- #[doc = "Bits 2:3 - Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn usb0_rst(&self) -> USB0_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186002,8 +181098,7 @@ pub mod rgu {
};
USB0_RSTR { bits }
}
- #[doc = "Bits 4:5 - Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn usb1_rst(&self) -> USB1_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186012,8 +181107,7 @@ pub mod rgu {
};
USB1_RSTR { bits }
}
- #[doc = "Bits 6:7 - Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn dma_rst(&self) -> DMA_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186022,8 +181116,7 @@ pub mod rgu {
};
DMA_RSTR { bits }
}
- #[doc = "Bits 8:9 - Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn sdio_rst(&self) -> SDIO_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186032,8 +181125,7 @@ pub mod rgu {
};
SDIO_RSTR { bits }
}
- #[doc = "Bits 10:11 - Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn emc_rst(&self) -> EMC_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186042,8 +181134,7 @@ pub mod rgu {
};
EMC_RSTR { bits }
}
- #[doc = "Bits 12:13 - Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ethernet_rst(&self) -> ETHERNET_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186052,8 +181143,7 @@ pub mod rgu {
};
ETHERNET_RSTR { bits }
}
- #[doc = "Bits 18:19 - Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn flasha_rst(&self) -> FLASHA_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186062,8 +181152,7 @@ pub mod rgu {
};
FLASHA_RSTR { bits }
}
- #[doc = "Bits 22:23 - Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn eeprom_rst(&self) -> EEPROM_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186072,8 +181161,7 @@ pub mod rgu {
};
EEPROM_RSTR { bits }
}
- #[doc = "Bits 24:25 - Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn gpio_rst(&self) -> GPIO_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186082,8 +181170,7 @@ pub mod rgu {
};
GPIO_RSTR { bits }
}
- #[doc = "Bits 26:27 - Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn flashb_rst(&self) -> FLASHB_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186105,58 +181192,47 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn lcd_rst(&mut self) -> _LCD_RSTW {
_LCD_RSTW { w: self }
}
- #[doc = "Bits 2:3 - Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn usb0_rst(&mut self) -> _USB0_RSTW {
_USB0_RSTW { w: self }
}
- #[doc = "Bits 4:5 - Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn usb1_rst(&mut self) -> _USB1_RSTW {
_USB1_RSTW { w: self }
}
- #[doc = "Bits 6:7 - Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn dma_rst(&mut self) -> _DMA_RSTW {
_DMA_RSTW { w: self }
}
- #[doc = "Bits 8:9 - Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn sdio_rst(&mut self) -> _SDIO_RSTW {
_SDIO_RSTW { w: self }
}
- #[doc = "Bits 10:11 - Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn emc_rst(&mut self) -> _EMC_RSTW {
_EMC_RSTW { w: self }
}
- #[doc = "Bits 12:13 - Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ethernet_rst(&mut self) -> _ETHERNET_RSTW {
_ETHERNET_RSTW { w: self }
}
- #[doc = "Bits 18:19 - Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn flasha_rst(&mut self) -> _FLASHA_RSTW {
_FLASHA_RSTW { w: self }
}
- #[doc = "Bits 22:23 - Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn eeprom_rst(&mut self) -> _EEPROM_RSTW {
_EEPROM_RSTW { w: self }
}
- #[doc = "Bits 24:25 - Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn gpio_rst(&mut self) -> _GPIO_RSTW {
_GPIO_RSTW { w: self }
}
- #[doc = "Bits 26:27 - Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn flashb_rst(&mut self) -> _FLASHB_RSTW {
_FLASHB_RSTW { w: self }
}
@@ -186608,8 +181684,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer0_rst(&self) -> TIMER0_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186618,8 +181693,7 @@ pub mod rgu {
};
TIMER0_RSTR { bits }
}
- #[doc = "Bits 2:3 - Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer1_rst(&self) -> TIMER1_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186628,8 +181702,7 @@ pub mod rgu {
};
TIMER1_RSTR { bits }
}
- #[doc = "Bits 4:5 - Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer2_rst(&self) -> TIMER2_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186638,8 +181711,7 @@ pub mod rgu {
};
TIMER2_RSTR { bits }
}
- #[doc = "Bits 6:7 - Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer3_rst(&self) -> TIMER3_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186648,8 +181720,7 @@ pub mod rgu {
};
TIMER3_RSTR { bits }
}
- #[doc = "Bits 8:9 - Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ritimer_rst(&self) -> RITIMER_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186658,8 +181729,7 @@ pub mod rgu {
};
RITIMER_RSTR { bits }
}
- #[doc = "Bits 10:11 - Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn sct_rst(&self) -> SCT_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186668,8 +181738,7 @@ pub mod rgu {
};
SCT_RSTR { bits }
}
- #[doc = "Bits 12:13 - Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn motoconpwm_rst(&self) -> MOTOCONPWM_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186678,8 +181747,7 @@ pub mod rgu {
};
MOTOCONPWM_RSTR { bits }
}
- #[doc = "Bits 14:15 - Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn qei_rst(&self) -> QEI_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186688,8 +181756,7 @@ pub mod rgu {
};
QEI_RSTR { bits }
}
- #[doc = "Bits 16:17 - Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn adc0_rst(&self) -> ADC0_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186698,8 +181765,7 @@ pub mod rgu {
};
ADC0_RSTR { bits }
}
- #[doc = "Bits 18:19 - Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn adc1_rst(&self) -> ADC1_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186708,8 +181774,7 @@ pub mod rgu {
};
ADC1_RSTR { bits }
}
- #[doc = "Bits 20:21 - Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 20:21 - Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn dac_rst(&self) -> DAC_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186718,8 +181783,7 @@ pub mod rgu {
};
DAC_RSTR { bits }
}
- #[doc = "Bits 24:25 - Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart0_rst(&self) -> UART0_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186728,8 +181792,7 @@ pub mod rgu {
};
UART0_RSTR { bits }
}
- #[doc = "Bits 26:27 - Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart1_rst(&self) -> UART1_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186738,8 +181801,7 @@ pub mod rgu {
};
UART1_RSTR { bits }
}
- #[doc = "Bits 28:29 - Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 28:29 - Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart2_rst(&self) -> UART2_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186748,8 +181810,7 @@ pub mod rgu {
};
UART2_RSTR { bits }
}
- #[doc = "Bits 30:31 - Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 30:31 - Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart3_rst(&self) -> UART3_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -186771,78 +181832,63 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer0_rst(&mut self) -> _TIMER0_RSTW {
_TIMER0_RSTW { w: self }
}
- #[doc = "Bits 2:3 - Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer1_rst(&mut self) -> _TIMER1_RSTW {
_TIMER1_RSTW { w: self }
}
- #[doc = "Bits 4:5 - Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer2_rst(&mut self) -> _TIMER2_RSTW {
_TIMER2_RSTW { w: self }
}
- #[doc = "Bits 6:7 - Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn timer3_rst(&mut self) -> _TIMER3_RSTW {
_TIMER3_RSTW { w: self }
}
- #[doc = "Bits 8:9 - Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ritimer_rst(&mut self) -> _RITIMER_RSTW {
_RITIMER_RSTW { w: self }
}
- #[doc = "Bits 10:11 - Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn sct_rst(&mut self) -> _SCT_RSTW {
_SCT_RSTW { w: self }
}
- #[doc = "Bits 12:13 - Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn motoconpwm_rst(&mut self) -> _MOTOCONPWM_RSTW {
_MOTOCONPWM_RSTW { w: self }
}
- #[doc = "Bits 14:15 - Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn qei_rst(&mut self) -> _QEI_RSTW {
_QEI_RSTW { w: self }
}
- #[doc = "Bits 16:17 - Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn adc0_rst(&mut self) -> _ADC0_RSTW {
_ADC0_RSTW { w: self }
}
- #[doc = "Bits 18:19 - Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn adc1_rst(&mut self) -> _ADC1_RSTW {
_ADC1_RSTW { w: self }
}
- #[doc = "Bits 20:21 - Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 20:21 - Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn dac_rst(&mut self) -> _DAC_RSTW {
_DAC_RSTW { w: self }
}
- #[doc = "Bits 24:25 - Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart0_rst(&mut self) -> _UART0_RSTW {
_UART0_RSTW { w: self }
}
- #[doc = "Bits 26:27 - Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 26:27 - Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart1_rst(&mut self) -> _UART1_RSTW {
_UART1_RSTW { w: self }
}
- #[doc = "Bits 28:29 - Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 28:29 - Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart2_rst(&mut self) -> _UART2_RSTW {
_UART2_RSTW { w: self }
}
- #[doc = "Bits 30:31 - Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 30:31 - Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn uart3_rst(&mut self) -> _UART3_RSTW {
_UART3_RSTW { w: self }
}
@@ -187216,8 +182262,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn i2c0_rst(&self) -> I2C0_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187226,8 +182271,7 @@ pub mod rgu {
};
I2C0_RSTR { bits }
}
- #[doc = "Bits 2:3 - Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn i2c1_rst(&self) -> I2C1_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187236,8 +182280,7 @@ pub mod rgu {
};
I2C1_RSTR { bits }
}
- #[doc = "Bits 4:5 - Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ssp0_rst(&self) -> SSP0_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187246,8 +182289,7 @@ pub mod rgu {
};
SSP0_RSTR { bits }
}
- #[doc = "Bits 6:7 - Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ssp1_rst(&self) -> SSP1_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187256,8 +182298,7 @@ pub mod rgu {
};
SSP1_RSTR { bits }
}
- #[doc = "Bits 8:9 - Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn i2s_rst(&self) -> I2S_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187266,8 +182307,7 @@ pub mod rgu {
};
I2S_RSTR { bits }
}
- #[doc = "Bits 10:11 - Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn spifi_rst(&self) -> SPIFI_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187276,8 +182316,7 @@ pub mod rgu {
};
SPIFI_RSTR { bits }
}
- #[doc = "Bits 12:13 - Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn can1_rst(&self) -> CAN1_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187286,8 +182325,7 @@ pub mod rgu {
};
CAN1_RSTR { bits }
}
- #[doc = "Bits 14:15 - Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn can0_rst(&self) -> CAN0_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187296,8 +182334,7 @@ pub mod rgu {
};
CAN0_RSTR { bits }
}
- #[doc = "Bits 16:17 - Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn m0app_rst(&self) -> M0APP_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187306,8 +182343,7 @@ pub mod rgu {
};
M0APP_RSTR { bits }
}
- #[doc = "Bits 18:19 - Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn sgpio_rst(&self) -> SGPIO_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187316,8 +182352,7 @@ pub mod rgu {
};
SGPIO_RSTR { bits }
}
- #[doc = "Bits 20:21 - Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 20:21 - Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn spi_rst(&self) -> SPI_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187326,8 +182361,7 @@ pub mod rgu {
};
SPI_RSTR { bits }
}
- #[doc = "Bits 24:25 - Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn adchs_rst(&self) -> ADCHS_RSTR {
let bits = {
const MASK: u8 = 3;
@@ -187349,63 +182383,51 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn i2c0_rst(&mut self) -> _I2C0_RSTW {
_I2C0_RSTW { w: self }
}
- #[doc = "Bits 2:3 - Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn i2c1_rst(&mut self) -> _I2C1_RSTW {
_I2C1_RSTW { w: self }
}
- #[doc = "Bits 4:5 - Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ssp0_rst(&mut self) -> _SSP0_RSTW {
_SSP0_RSTW { w: self }
}
- #[doc = "Bits 6:7 - Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn ssp1_rst(&mut self) -> _SSP1_RSTW {
_SSP1_RSTW { w: self }
}
- #[doc = "Bits 8:9 - Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn i2s_rst(&mut self) -> _I2S_RSTW {
_I2S_RSTW { w: self }
}
- #[doc = "Bits 10:11 - Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn spifi_rst(&mut self) -> _SPIFI_RSTW {
_SPIFI_RSTW { w: self }
}
- #[doc = "Bits 12:13 - Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 12:13 - Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn can1_rst(&mut self) -> _CAN1_RSTW {
_CAN1_RSTW { w: self }
}
- #[doc = "Bits 14:15 - Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 14:15 - Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn can0_rst(&mut self) -> _CAN0_RSTW {
_CAN0_RSTW { w: self }
}
- #[doc = "Bits 16:17 - Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 16:17 - Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn m0app_rst(&mut self) -> _M0APP_RSTW {
_M0APP_RSTW { w: self }
}
- #[doc = "Bits 18:19 - Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 18:19 - Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn sgpio_rst(&mut self) -> _SGPIO_RSTW {
_SGPIO_RSTW { w: self }
}
- #[doc = "Bits 20:21 - Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 20:21 - Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn spi_rst(&mut self) -> _SPI_RSTW {
_SPI_RSTW { w: self }
}
- #[doc = "Bits 24:25 - Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register"]
- #[inline(always)]
+ # [ doc = "Bits 24:25 - Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" ] # [ inline ( always ) ]
pub fn adchs_rst(&mut self) -> _ADCHS_RSTW {
_ADCHS_RSTW { w: self }
}
@@ -189022,8 +184044,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn core_reset(&self) -> CORE_RESETR {
let bits = {
const MASK: bool = true;
@@ -189045,8 +184066,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn core_reset(&mut self) -> _CORE_RESETW {
_CORE_RESETW { w: self }
}
@@ -189152,8 +184172,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -189175,8 +184194,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -189282,8 +184300,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn core_reset(&self) -> CORE_RESETR {
let bits = {
const MASK: bool = true;
@@ -189305,8 +184322,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn core_reset(&mut self) -> _CORE_RESETW {
_CORE_RESETW { w: self }
}
@@ -189412,8 +184428,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -189435,8 +184450,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -189542,8 +184556,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -189565,8 +184578,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -189672,8 +184684,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -189695,8 +184706,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -189802,8 +184812,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -189825,8 +184834,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -189932,8 +184940,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -189955,8 +184962,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190062,8 +185068,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190085,8 +185090,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190192,8 +185196,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190215,8 +185218,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190322,8 +185324,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190345,8 +185346,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190452,8 +185452,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190475,8 +185474,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190582,8 +185580,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190605,8 +185602,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190712,8 +185708,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190735,8 +185730,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190842,8 +185836,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190865,8 +185858,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -190972,8 +185964,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -190995,8 +185986,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -191102,8 +186092,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -191125,8 +186114,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -191232,8 +186220,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&self) -> MASTER_RESETR {
let bits = {
const MASK: bool = true;
@@ -191255,8 +186242,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn master_reset(&mut self) -> _MASTER_RESETW {
_MASTER_RESETW { w: self }
}
@@ -191362,8 +186348,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -191385,8 +186370,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -191492,8 +186476,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -191515,8 +186498,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -191622,8 +186604,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -191645,8 +186626,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -191752,8 +186732,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -191775,8 +186754,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -191882,8 +186860,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -191905,8 +186882,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192012,8 +186988,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192035,8 +187010,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192142,8 +187116,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192165,8 +187138,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192272,8 +187244,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192295,8 +187266,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192402,8 +187372,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192425,8 +187394,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192532,8 +187500,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192555,8 +187522,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192662,8 +187628,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192685,8 +187650,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192792,8 +187756,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192815,8 +187778,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -192922,8 +187884,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -192945,8 +187906,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193052,8 +188012,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193075,8 +188034,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193182,8 +188140,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193205,8 +188162,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193312,8 +188268,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193335,8 +188290,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193442,8 +188396,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193465,8 +188418,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193572,8 +188524,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193595,8 +188546,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193702,8 +188652,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193725,8 +188674,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193832,8 +188780,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193855,8 +188802,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -193962,8 +188908,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -193985,8 +188930,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -194092,8 +189036,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -194115,8 +189058,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -194222,8 +189164,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -194245,8 +189186,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -194352,8 +189292,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -194375,8 +189314,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -194482,8 +189420,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -194505,8 +189442,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -194612,8 +189548,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -194635,8 +189570,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -194742,8 +189676,7 @@ pub mod rgu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&self) -> PERIPHERAL_RESETR {
let bits = {
const MASK: bool = true;
@@ -194765,8 +189698,7 @@ pub mod rgu {
self.bits = bits;
self
}
- #[doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" ] # [ inline ( always ) ]
pub fn peripheral_reset(&mut self) -> _PERIPHERAL_RESETW {
_PERIPHERAL_RESETW { w: self }
}
@@ -194790,26 +189722,12 @@ pub mod wwdt {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."]
- pub mod_: MOD,
- #[doc = "0x04 - Watchdog timer constant register. This register determines the time-out value."]
- pub tc: TC,
- #[doc = "0x08 - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."]
- pub feed: FEED,
- #[doc = "0x0c - Watchdog timer value register. This register reads out the current value of the Watchdog timer."]
- pub tv: TV,
- _reserved0: [u8; 4usize],
- #[doc = "0x14 - Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value."]
- pub warnint: WARNINT,
- #[doc = "0x18 - Watchdog timer window register. This register contains the Watchdog window value."]
- pub window: WINDOW,
- }
- #[doc = "Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."]
+ pub struct RegisterBlock { # [ doc = "0x00 - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." ] pub mod_ : MOD , # [ doc = "0x04 - Watchdog timer constant register. This register determines the time-out value." ] pub tc : TC , # [ doc = "0x08 - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." ] pub feed : FEED , # [ doc = "0x0c - Watchdog timer value register. This register reads out the current value of the Watchdog timer." ] pub tv : TV , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x14 - Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." ] pub warnint : WARNINT , # [ doc = "0x18 - Watchdog timer window register. This register contains the Watchdog window value." ] pub window : WINDOW , }
+ # [ doc = "Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." ]
pub struct MOD {
register: VolatileCell<u32>,
}
- #[doc = "Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."]
+ # [ doc = "Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." ]
pub mod mod_ {
#[doc = r" Value read from the register"]
pub struct R {
@@ -194989,12 +189907,7 @@ pub mod wwdt {
}
#[doc = "Possible values of the field `WDPROTECT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum WDPROTECTR {
- #[doc = "The watchdog time-out value (WDTC) can be changed at any time."]
- NO_LOCK,
- #[doc = "The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW."]
- LOCK,
- }
+ pub enum WDPROTECTR {# [ doc = "The watchdog time-out value (WDTC) can be changed at any time." ] NO_LOCK , # [ doc = "The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." ] LOCK}
impl WDPROTECTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -195193,12 +190106,7 @@ pub mod wwdt {
}
}
#[doc = "Values that can be written to the field `WDPROTECT`"]
- pub enum WDPROTECTW {
- #[doc = "The watchdog time-out value (WDTC) can be changed at any time."]
- NO_LOCK,
- #[doc = "The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW."]
- LOCK,
- }
+ pub enum WDPROTECTW {# [ doc = "The watchdog time-out value (WDTC) can be changed at any time." ] NO_LOCK , # [ doc = "The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." ] LOCK}
impl WDPROTECTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -195227,8 +190135,7 @@ pub mod wwdt {
pub fn no_lock(self) -> &'a mut W {
self.variant(WDPROTECTW::NO_LOCK)
}
- #[doc = "The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW."]
- #[inline(always)]
+ # [ doc = "The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." ] # [ inline ( always ) ]
pub fn lock(self) -> &'a mut W {
self.variant(WDPROTECTW::LOCK)
}
@@ -195274,8 +190181,7 @@ pub mod wwdt {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." ] # [ inline ( always ) ]
pub fn wdtof(&self) -> WDTOFR {
let bits = {
const MASK: bool = true;
@@ -195284,8 +190190,7 @@ pub mod wwdt {
};
WDTOFR { bits }
}
- #[doc = "Bit 3 - Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." ] # [ inline ( always ) ]
pub fn wdint(&self) -> WDINTR {
let bits = {
const MASK: bool = true;
@@ -195326,13 +190231,11 @@ pub mod wwdt {
pub fn wdreset(&mut self) -> _WDRESETW {
_WDRESETW { w: self }
}
- #[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." ] # [ inline ( always ) ]
pub fn wdtof(&mut self) -> _WDTOFW {
_WDTOFW { w: self }
}
- #[doc = "Bit 3 - Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." ] # [ inline ( always ) ]
pub fn wdint(&mut self) -> _WDINTW {
_WDINTW { w: self }
}
@@ -195455,11 +190358,11 @@ pub mod wwdt {
}
}
}
- #[doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."]
+ # [ doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." ]
pub struct FEED {
register: VolatileCell<u32>,
}
- #[doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."]
+ # [ doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." ]
pub mod feed {
#[doc = r" Value to write to the register"]
pub struct W {
@@ -195511,11 +190414,11 @@ pub mod wwdt {
}
}
}
- #[doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer."]
+ # [ doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer." ]
pub struct TV {
register: VolatileCell<u32>,
}
- #[doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer."]
+ # [ doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer." ]
pub mod tv {
#[doc = r" Value read from the register"]
pub struct R {
@@ -195559,11 +190462,11 @@ pub mod wwdt {
}
}
}
- #[doc = "Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value."]
+ # [ doc = "Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." ]
pub struct WARNINT {
register: VolatileCell<u32>,
}
- #[doc = "Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value."]
+ # [ doc = "Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." ]
pub mod warnint {
#[doc = r" Value read from the register"]
pub struct R {
@@ -195838,8 +190741,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." ] # [ inline ( always ) ]
pub fn rbr(&self) -> RBRR {
let bits = {
const MASK: u8 = 255;
@@ -195850,11 +190752,11 @@ pub mod usart0 {
}
}
}
- #[doc = "Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)."]
+ # [ doc = "Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." ]
pub struct THR {
register: VolatileCell<u32>,
}
- #[doc = "Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)."]
+ # [ doc = "Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." ]
pub mod thr {
#[doc = r" Value to write to the register"]
pub struct W {
@@ -195899,18 +190801,17 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." ] # [ inline ( always ) ]
pub fn thr(&mut self) -> _THRW {
_THRW { w: self }
}
}
}
- #[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)."]
+ # [ doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." ]
pub struct DLL {
register: VolatileCell<u32>,
}
- #[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)."]
+ # [ doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." ]
pub mod dll {
#[doc = r" Value read from the register"]
pub struct R {
@@ -195988,8 +190889,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." ] # [ inline ( always ) ]
pub fn dllsb(&self) -> DLLSBR {
let bits = {
const MASK: u8 = 255;
@@ -196011,18 +190911,17 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." ] # [ inline ( always ) ]
pub fn dllsb(&mut self) -> _DLLSBW {
_DLLSBW { w: self }
}
}
}
- #[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)."]
+ # [ doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." ]
pub struct DLM {
register: VolatileCell<u32>,
}
- #[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)."]
+ # [ doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." ]
pub mod dlm {
#[doc = r" Value read from the register"]
pub struct R {
@@ -196100,8 +190999,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Divisor latch MSB. The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor latch MSB. The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." ] # [ inline ( always ) ]
pub fn dlmsb(&self) -> DLMSBR {
let bits = {
const MASK: u8 = 255;
@@ -196123,18 +191021,17 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Divisor latch MSB. The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor latch MSB. The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." ] # [ inline ( always ) ]
pub fn dlmsb(&mut self) -> _DLMSBW {
_DLMSBW { w: self }
}
}
}
- #[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)."]
+ # [ doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." ]
pub struct IER {
register: VolatileCell<u32>,
}
- #[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)."]
+ # [ doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." ]
pub mod ier {
#[doc = r" Value read from the register"]
pub struct R {
@@ -196691,8 +191588,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt." ] # [ inline ( always ) ]
pub fn rbrie(&self) -> RBRIER {
RBRIER::_from({
const MASK: bool = true;
@@ -196700,8 +191596,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5]."]
- #[inline(always)]
+ # [ doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5]." ] # [ inline ( always ) ]
pub fn threie(&self) -> THREIER {
THREIER::_from({
const MASK: bool = true;
@@ -196709,8 +191604,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]."]
- #[inline(always)]
+ # [ doc = "Bit 2 - RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]." ] # [ inline ( always ) ]
pub fn rxie(&self) -> RXIER {
RXIER::_from({
const MASK: bool = true;
@@ -196749,18 +191643,15 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt." ] # [ inline ( always ) ]
pub fn rbrie(&mut self) -> _RBRIEW {
_RBRIEW { w: self }
}
- #[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5]."]
- #[inline(always)]
+ # [ doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5]." ] # [ inline ( always ) ]
pub fn threie(&mut self) -> _THREIEW {
_THREIEW { w: self }
}
- #[doc = "Bit 2 - RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]."]
- #[inline(always)]
+ # [ doc = "Bit 2 - RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]." ] # [ inline ( always ) ]
pub fn rxie(&mut self) -> _RXIEW {
_RXIEW { w: self }
}
@@ -196798,8 +191689,7 @@ pub mod usart0 {
#[doc = "Possible values of the field `INTSTATUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTSTATUSR {
- #[doc = "Interrupt pending. At least one interrupt is pending."]
- INTERRUPT_PENDING,
+ #[doc = "Interrupt pending. At least one interrupt is pending."] INTERRUPT_PENDING,
#[doc = "Not pending. No interrupt is pending."] NOT_PENDING,
}
impl INTSTATUSR {
@@ -196844,8 +191734,7 @@ pub mod usart0 {
#[doc = "Possible values of the field `INTID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTIDR {
- #[doc = "RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)."]
- RLS,
+ #[doc = "RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)."] RLS,
#[doc = "RDA. Priority 2 - Receive Data Available (RDA)."] RDA,
#[doc = "CTI. Priority 2 - Character Time-out Indicator (CTI)."] CTI,
#[doc = "THRE. Priority 3 - THRE Interrupt."] THRE,
@@ -196955,8 +191844,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]." ] # [ inline ( always ) ]
pub fn intstatus(&self) -> INTSTATUSR {
INTSTATUSR::_from({
const MASK: bool = true;
@@ -196964,8 +191852,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 1:3 - Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)."]
- #[inline(always)]
+ # [ doc = "Bits 1:3 - Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)." ] # [ inline ( always ) ]
pub fn intid(&self) -> INTIDR {
INTIDR::_from({
const MASK: u8 = 7;
@@ -196983,8 +191870,7 @@ pub mod usart0 {
};
FIFOENABLER { bits }
}
- #[doc = "Bit 8 - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 8 - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." ] # [ inline ( always ) ]
pub fn abeoint(&self) -> ABEOINTR {
let bits = {
const MASK: bool = true;
@@ -196993,8 +191879,7 @@ pub mod usart0 {
};
ABEOINTR { bits }
}
- #[doc = "Bit 9 - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." ] # [ inline ( always ) ]
pub fn abtoint(&self) -> ABTOINTR {
let bits = {
const MASK: bool = true;
@@ -197028,12 +191913,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `FIFOEN`"]
- pub enum FIFOENW {
- #[doc = "Disabled. USART FIFOs are disabled. Must not be used in the application."]
- DISABLED,
- #[doc = "Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs."]
- ENABLED,
- }
+ pub enum FIFOENW {# [ doc = "Disabled. USART FIFOs are disabled. Must not be used in the application." ] DISABLED , # [ doc = "Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." ] ENABLED}
impl FIFOENW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -197062,8 +191942,7 @@ pub mod usart0 {
pub fn disabled(self) -> &'a mut W {
self.variant(FIFOENW::DISABLED)
}
- #[doc = "Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs."]
- #[inline(always)]
+ # [ doc = "Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(FIFOENW::ENABLED)
}
@@ -197086,11 +191965,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `RXFIFORES`"]
- pub enum RXFIFORESW {
- #[doc = "No effect. No impact on either of USART FIFOs."] NO_EFFECT,
- #[doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing."]
- CLEAR,
- }
+ pub enum RXFIFORESW {# [ doc = "No effect. No impact on either of USART FIFOs." ] NO_EFFECT , # [ doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." ] CLEAR}
impl RXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -197119,8 +191994,7 @@ pub mod usart0 {
pub fn no_effect(self) -> &'a mut W {
self.variant(RXFIFORESW::NO_EFFECT)
}
- #[doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing."]
- #[inline(always)]
+ # [ doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(RXFIFORESW::CLEAR)
}
@@ -197143,11 +192017,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `TXFIFORES`"]
- pub enum TXFIFORESW {
- #[doc = "No effect. No impact on either of USART FIFOs."] NO_EFFECT,
- #[doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing."]
- CLEAR,
- }
+ pub enum TXFIFORESW {# [ doc = "No effect. No impact on either of USART FIFOs." ] NO_EFFECT , # [ doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." ] CLEAR}
impl TXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -197176,8 +192046,7 @@ pub mod usart0 {
pub fn no_effect(self) -> &'a mut W {
self.variant(TXFIFORESW::NO_EFFECT)
}
- #[doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing."]
- #[inline(always)]
+ # [ doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(TXFIFORESW::CLEAR)
}
@@ -197311,13 +192180,11 @@ pub mod usart0 {
pub fn txfifores(&mut self) -> _TXFIFORESW {
_TXFIFORESW { w: self }
}
- #[doc = "Bit 3 - DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode."]
- #[inline(always)]
+ # [ doc = "Bit 3 - DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." ] # [ inline ( always ) ]
pub fn dmamode(&mut self) -> _DMAMODEW {
_DMAMODEW { w: self }
}
- #[doc = "Bits 6:7 - RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated." ] # [ inline ( always ) ]
pub fn rxtriglvl(&mut self) -> _RXTRIGLVLW {
_RXTRIGLVLW { w: self }
}
@@ -197473,10 +192340,8 @@ pub mod usart0 {
#[doc = "Possible values of the field `PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PER {
- #[doc = "Disable parity generation and checking."]
- DISABLE_PARITY_GENER,
- #[doc = "Enable parity generation and checking."]
- ENABLE_PARITY_GENERA,
+ #[doc = "Disable parity generation and checking."] DISABLE_PARITY_GENER,
+ #[doc = "Enable parity generation and checking."] ENABLE_PARITY_GENERA,
}
impl PER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -197519,14 +192384,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `PS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PSR {
- #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
- ODD_PARITY,
- #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
- EVEN_PARITY,
- #[doc = "Force HIGH. Forced 1 stick parity."] FORCE_HIGH,
- #[doc = "Force LOW. Forced 0 stick parity."] FORCE_LOW,
- }
+ pub enum PSR {# [ doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." ] ODD_PARITY , # [ doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." ] EVEN_PARITY , # [ doc = "Force HIGH. Forced 1 stick parity." ] FORCE_HIGH , # [ doc = "Force LOW. Forced 0 stick parity." ] FORCE_LOW}
impl PSR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -197573,11 +192431,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `BC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BCR {
- #[doc = "Disabled. Disable break transmission."] DISABLED,
- #[doc = "Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high."]
- ENABLED,
- }
+ pub enum BCR {# [ doc = "Disabled. Disable break transmission." ] DISABLED , # [ doc = "Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." ] ENABLED}
impl BCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -197782,10 +192636,8 @@ pub mod usart0 {
}
#[doc = "Values that can be written to the field `PE`"]
pub enum PEW {
- #[doc = "Disable parity generation and checking."]
- DISABLE_PARITY_GENER,
- #[doc = "Enable parity generation and checking."]
- ENABLE_PARITY_GENERA,
+ #[doc = "Disable parity generation and checking."] DISABLE_PARITY_GENER,
+ #[doc = "Enable parity generation and checking."] ENABLE_PARITY_GENERA,
}
impl PEW {
#[allow(missing_docs)]
@@ -197839,14 +192691,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `PS`"]
- pub enum PSW {
- #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
- ODD_PARITY,
- #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
- EVEN_PARITY,
- #[doc = "Force HIGH. Forced 1 stick parity."] FORCE_HIGH,
- #[doc = "Force LOW. Forced 0 stick parity."] FORCE_LOW,
- }
+ pub enum PSW {# [ doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." ] ODD_PARITY , # [ doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." ] EVEN_PARITY , # [ doc = "Force HIGH. Forced 1 stick parity." ] FORCE_HIGH , # [ doc = "Force LOW. Forced 0 stick parity." ] FORCE_LOW}
impl PSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -197872,13 +192717,11 @@ pub mod usart0 {
self.bits(variant._bits())
}
}
- #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
- #[inline(always)]
+ # [ doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." ] # [ inline ( always ) ]
pub fn odd_parity(self) -> &'a mut W {
self.variant(PSW::ODD_PARITY)
}
- #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
- #[inline(always)]
+ # [ doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." ] # [ inline ( always ) ]
pub fn even_parity(self) -> &'a mut W {
self.variant(PSW::EVEN_PARITY)
}
@@ -197903,11 +192746,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `BC`"]
- pub enum BCW {
- #[doc = "Disabled. Disable break transmission."] DISABLED,
- #[doc = "Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high."]
- ENABLED,
- }
+ pub enum BCW {# [ doc = "Disabled. Disable break transmission." ] DISABLED , # [ doc = "Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." ] ENABLED}
impl BCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -197936,8 +192775,7 @@ pub mod usart0 {
pub fn disabled(self) -> &'a mut W {
self.variant(BCW::DISABLED)
}
- #[doc = "Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high."]
- #[inline(always)]
+ # [ doc = "Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(BCW::ENABLED)
}
@@ -198120,11 +192958,11 @@ pub mod usart0 {
}
}
}
- #[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
+ # [ doc = "Line Status Register. Contains flags for transmit and receive status, including line errors." ]
pub struct LSR {
register: VolatileCell<u32>,
}
- #[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
+ # [ doc = "Line Status Register. Contains flags for transmit and receive status, including line errors." ]
pub mod lsr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -198412,8 +193250,7 @@ pub mod usart0 {
#[doc = "Possible values of the field `TEMT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TEMTR {
- #[doc = "Not empty. THR and/or the TSR contains valid data."]
- NOT_EMPTY,
+ #[doc = "Not empty. THR and/or the TSR contains valid data."] NOT_EMPTY,
#[doc = "Empty. THR and the TSR are empty."] EMPTY,
}
impl TEMTR {
@@ -198458,10 +193295,8 @@ pub mod usart0 {
#[doc = "Possible values of the field `RXFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXFER {
- #[doc = "No error. RBR contains no USART RX errors or FCR[0]=0."]
- NO_ERROR,
- #[doc = "Error. USART RBR contains at least one USART RX error."]
- ERROR,
+ #[doc = "No error. RBR contains no USART RX errors or FCR[0]=0."] NO_ERROR,
+ #[doc = "Error. USART RBR contains at least one USART RX error."] ERROR,
}
impl RXFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -198506,8 +193341,7 @@ pub mod usart0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TXERRR {
#[doc = "No error. No error (normal default condition)."] NO_ERROR,
- #[doc = "NACK. A NACK response is received during Smart card T=0 operation."]
- NACK,
+ #[doc = "NACK. A NACK response is received during Smart card T=0 operation."] NACK,
}
impl TXERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -198554,8 +193388,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty." ] # [ inline ( always ) ]
pub fn rdr(&self) -> RDRR {
RDRR::_from({
const MASK: bool = true;
@@ -198563,8 +193396,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost." ] # [ inline ( always ) ]
pub fn oe(&self) -> OER {
OER::_from({
const MASK: bool = true;
@@ -198572,8 +193404,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO." ] # [ inline ( always ) ]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
@@ -198581,8 +193412,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO." ] # [ inline ( always ) ]
pub fn fe(&self) -> FER {
FER::_from({
const MASK: bool = true;
@@ -198590,8 +193420,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO." ] # [ inline ( always ) ]
pub fn bi(&self) -> BIR {
BIR::_from({
const MASK: bool = true;
@@ -198599,8 +193428,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write." ] # [ inline ( always ) ]
pub fn thre(&self) -> THRER {
THRER::_from({
const MASK: bool = true;
@@ -198608,8 +193436,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data." ] # [ inline ( always ) ]
pub fn temt(&self) -> TEMTR {
TEMTR::_from({
const MASK: bool = true;
@@ -198617,8 +193444,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO." ] # [ inline ( always ) ]
pub fn rxfe(&self) -> RXFER {
RXFER::_from({
const MASK: bool = true;
@@ -198626,8 +193452,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 8 - Error in transmitted character. A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Error in transmitted character. A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read." ] # [ inline ( always ) ]
pub fn txerr(&self) -> TXERRR {
TXERRR::_from({
const MASK: bool = true;
@@ -198801,11 +193626,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `START`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum STARTR {
- #[doc = "Stop. Auto-baud stop (auto-baud is not running)."] STOP,
- #[doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
- START,
- }
+ pub enum STARTR {# [ doc = "Stop. Auto-baud stop (auto-baud is not running)." ] STOP , # [ doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." ] START}
impl STARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -198892,11 +193713,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `AUTORESTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum AUTORESTARTR {
- #[doc = "No restart."] NO_RESTART,
- #[doc = "Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)"]
- RESTART,
- }
+ pub enum AUTORESTARTR {# [ doc = "No restart." ] NO_RESTART , # [ doc = "Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" ] RESTART}
impl AUTORESTARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -198940,8 +193757,7 @@ pub mod usart0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABEOINTCLRR {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABEOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -198986,8 +193802,7 @@ pub mod usart0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABTOINTCLRR {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABTOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -199029,11 +193844,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `START`"]
- pub enum STARTW {
- #[doc = "Stop. Auto-baud stop (auto-baud is not running)."] STOP,
- #[doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
- START,
- }
+ pub enum STARTW {# [ doc = "Stop. Auto-baud stop (auto-baud is not running)." ] STOP , # [ doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." ] START}
impl STARTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -199062,8 +193873,7 @@ pub mod usart0 {
pub fn stop(self) -> &'a mut W {
self.variant(STARTW::STOP)
}
- #[doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
- #[inline(always)]
+ # [ doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." ] # [ inline ( always ) ]
pub fn start(self) -> &'a mut W {
self.variant(STARTW::START)
}
@@ -199142,11 +193952,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `AUTORESTART`"]
- pub enum AUTORESTARTW {
- #[doc = "No restart."] NO_RESTART,
- #[doc = "Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)"]
- RESTART,
- }
+ pub enum AUTORESTARTW {# [ doc = "No restart." ] NO_RESTART , # [ doc = "Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" ] RESTART}
impl AUTORESTARTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -199175,8 +193981,7 @@ pub mod usart0 {
pub fn no_restart(self) -> &'a mut W {
self.variant(AUTORESTARTW::NO_RESTART)
}
- #[doc = "Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)"]
- #[inline(always)]
+ # [ doc = "Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" ] # [ inline ( always ) ]
pub fn restart(self) -> &'a mut W {
self.variant(AUTORESTARTW::RESTART)
}
@@ -199201,8 +194006,7 @@ pub mod usart0 {
#[doc = "Values that can be written to the field `ABEOINTCLR`"]
pub enum ABEOINTCLRW {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABEOINTCLRW {
#[allow(missing_docs)]
@@ -199258,8 +194062,7 @@ pub mod usart0 {
#[doc = "Values that can be written to the field `ABTOINTCLR`"]
pub enum ABTOINTCLRW {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABTOINTCLRW {
#[allow(missing_docs)]
@@ -199318,8 +194121,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion." ] # [ inline ( always ) ]
pub fn start(&self) -> STARTR {
STARTR::_from({
const MASK: bool = true;
@@ -199376,8 +194178,7 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion." ] # [ inline ( always ) ]
pub fn start(&mut self) -> _STARTW {
_STARTW { w: self }
}
@@ -199501,12 +194302,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `IRDAINV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum IRDAINVR {
- #[doc = "Not inverted. The serial input is not inverted."]
- NOT_INVERTED,
- #[doc = "Inverted. The serial input is inverted. This has no effect on the serial output."]
- INVERTED,
- }
+ pub enum IRDAINVR {# [ doc = "Not inverted. The serial input is not inverted." ] NOT_INVERTED , # [ doc = "Inverted. The serial input is inverted. This has no effect on the serial output." ] INVERTED}
impl IRDAINVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -199660,12 +194456,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `IRDAINV`"]
- pub enum IRDAINVW {
- #[doc = "Not inverted. The serial input is not inverted."]
- NOT_INVERTED,
- #[doc = "Inverted. The serial input is inverted. This has no effect on the serial output."]
- INVERTED,
- }
+ pub enum IRDAINVW {# [ doc = "Not inverted. The serial input is not inverted." ] NOT_INVERTED , # [ doc = "Inverted. The serial input is inverted. This has no effect on the serial output." ] INVERTED}
impl IRDAINVW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -199694,8 +194485,7 @@ pub mod usart0 {
pub fn not_inverted(self) -> &'a mut W {
self.variant(IRDAINVW::NOT_INVERTED)
}
- #[doc = "Inverted. The serial input is inverted. This has no effect on the serial output."]
- #[inline(always)]
+ # [ doc = "Inverted. The serial input is inverted. This has no effect on the serial output." ] # [ inline ( always ) ]
pub fn inverted(self) -> &'a mut W {
self.variant(IRDAINVW::INVERTED)
}
@@ -199821,8 +194611,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 3:5 - Configures the pulse when FixPulseEn = 1. See Table 885 for details."]
- #[inline(always)]
+ # [ doc = "Bits 3:5 - Configures the pulse when FixPulseEn = 1. See Table 885 for details." ] # [ inline ( always ) ]
pub fn pulsediv(&self) -> PULSEDIVR {
let bits = {
const MASK: u8 = 7;
@@ -199859,8 +194648,7 @@ pub mod usart0 {
pub fn fixpulseen(&mut self) -> _FIXPULSEENW {
_FIXPULSEENW { w: self }
}
- #[doc = "Bits 3:5 - Configures the pulse when FixPulseEn = 1. See Table 885 for details."]
- #[inline(always)]
+ # [ doc = "Bits 3:5 - Configures the pulse when FixPulseEn = 1. See Table 885 for details." ] # [ inline ( always ) ]
pub fn pulsediv(&mut self) -> _PULSEDIVW {
_PULSEDIVW { w: self }
}
@@ -199974,8 +194762,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." ] # [ inline ( always ) ]
pub fn divaddval(&self) -> DIVADDVALR {
let bits = {
const MASK: u8 = 15;
@@ -199984,8 +194771,7 @@ pub mod usart0 {
};
DIVADDVALR { bits }
}
- #[doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." ] # [ inline ( always ) ]
pub fn mulval(&self) -> MULVALR {
let bits = {
const MASK: u8 = 15;
@@ -200007,13 +194793,11 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." ] # [ inline ( always ) ]
pub fn divaddval(&mut self) -> _DIVADDVALW {
_DIVADDVALW { w: self }
}
- #[doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." ] # [ inline ( always ) ]
pub fn mulval(&mut self) -> _MULVALW {
_MULVALW { w: self }
}
@@ -200153,8 +194937,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 1:3 - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)"]
- #[inline(always)]
+ # [ doc = "Bits 1:3 - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" ] # [ inline ( always ) ]
pub fn osfrac(&self) -> OSFRACR {
let bits = {
const MASK: u8 = 7;
@@ -200163,8 +194946,7 @@ pub mod usart0 {
};
OSFRACR { bits }
}
- #[doc = "Bits 4:7 - Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." ] # [ inline ( always ) ]
pub fn osint(&self) -> OSINTR {
let bits = {
const MASK: u8 = 15;
@@ -200173,8 +194955,7 @@ pub mod usart0 {
};
OSINTR { bits }
}
- #[doc = "Bits 8:14 - In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372."]
- #[inline(always)]
+ # [ doc = "Bits 8:14 - In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." ] # [ inline ( always ) ]
pub fn fdint(&self) -> FDINTR {
let bits = {
const MASK: u8 = 127;
@@ -200196,18 +194977,15 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bits 1:3 - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)"]
- #[inline(always)]
+ # [ doc = "Bits 1:3 - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" ] # [ inline ( always ) ]
pub fn osfrac(&mut self) -> _OSFRACW {
_OSFRACW { w: self }
}
- #[doc = "Bits 4:7 - Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." ] # [ inline ( always ) ]
pub fn osint(&mut self) -> _OSINTW {
_OSINTW { w: self }
}
- #[doc = "Bits 8:14 - In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372."]
- #[inline(always)]
+ # [ doc = "Bits 8:14 - In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." ] # [ inline ( always ) ]
pub fn fdint(&mut self) -> _FDINTW {
_FDINTW { w: self }
}
@@ -200453,8 +195231,7 @@ pub mod usart0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCIENR {
#[doc = "Disabled. Smart card interface disabled."] DISABLED,
- #[doc = "Enabled. synchronous half duplex smart card interface is enabled."]
- ENABLED,
+ #[doc = "Enabled. synchronous half duplex smart card interface is enabled."] ENABLED,
}
impl SCIENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -200610,8 +195387,7 @@ pub mod usart0 {
#[doc = "Values that can be written to the field `SCIEN`"]
pub enum SCIENW {
#[doc = "Disabled. Smart card interface disabled."] DISABLED,
- #[doc = "Enabled. synchronous half duplex smart card interface is enabled."]
- ENABLED,
+ #[doc = "Enabled. synchronous half duplex smart card interface is enabled."] ENABLED,
}
impl SCIENW {
#[allow(missing_docs)]
@@ -200839,8 +195615,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 5:7 - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled."]
- #[inline(always)]
+ # [ doc = "Bits 5:7 - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." ] # [ inline ( always ) ]
pub fn txretry(&self) -> TXRETRYR {
let bits = {
const MASK: u8 = 7;
@@ -200849,8 +195624,7 @@ pub mod usart0 {
};
TXRETRYR { bits }
}
- #[doc = "Bits 8:15 - Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." ] # [ inline ( always ) ]
pub fn guardtime(&self) -> GUARDTIMER {
let bits = {
const MASK: u8 = 255;
@@ -200887,23 +195661,21 @@ pub mod usart0 {
pub fn protsel(&mut self) -> _PROTSELW {
_PROTSELW { w: self }
}
- #[doc = "Bits 5:7 - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled."]
- #[inline(always)]
+ # [ doc = "Bits 5:7 - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." ] # [ inline ( always ) ]
pub fn txretry(&mut self) -> _TXRETRYW {
_TXRETRYW { w: self }
}
- #[doc = "Bits 8:15 - Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." ] # [ inline ( always ) ]
pub fn guardtime(&mut self) -> _GUARDTIMEW {
_GUARDTIMEW { w: self }
}
}
}
- #[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
+ # [ doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." ]
pub struct RS485CTRL {
register: VolatileCell<u32>,
}
- #[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
+ # [ doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." ]
pub mod rs485ctrl {
#[doc = r" Value read from the register"]
pub struct R {
@@ -200951,12 +195723,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `NMMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum NMMENR {
- #[doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."]
- DISABLED,
- #[doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt."]
- ENABLED,
- }
+ pub enum NMMENR {# [ doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." ] DISABLED , # [ doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." ] ENABLED}
impl NMMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -201133,12 +195900,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `OINV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum OINVR {
- #[doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
- LOW,
- #[doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
- HIGH,
- }
+ pub enum OINVR {# [ doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." ] LOW , # [ doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." ] HIGH}
impl OINVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -201179,12 +195941,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `NMMEN`"]
- pub enum NMMENW {
- #[doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."]
- DISABLED,
- #[doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt."]
- ENABLED,
- }
+ pub enum NMMENW {# [ doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." ] DISABLED , # [ doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." ] ENABLED}
impl NMMENW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -201213,8 +195970,7 @@ pub mod usart0 {
pub fn disabled(self) -> &'a mut W {
self.variant(NMMENW::DISABLED)
}
- #[doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt."]
- #[inline(always)]
+ # [ doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(NMMENW::ENABLED)
}
@@ -201405,12 +196161,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `OINV`"]
- pub enum OINVW {
- #[doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
- LOW,
- #[doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
- HIGH,
- }
+ pub enum OINVW {# [ doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." ] LOW , # [ doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." ] HIGH}
impl OINVW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -201434,13 +196185,11 @@ pub mod usart0 {
self.bit(variant._bits())
}
}
- #[doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
- #[inline(always)]
+ # [ doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." ] # [ inline ( always ) ]
pub fn low(self) -> &'a mut W {
self.variant(OINVW::LOW)
}
- #[doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
- #[inline(always)]
+ # [ doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." ] # [ inline ( always ) ]
pub fn high(self) -> &'a mut W {
self.variant(OINVW::HIGH)
}
@@ -201504,8 +196253,7 @@ pub mod usart0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin." ] # [ inline ( always ) ]
pub fn oinv(&self) -> OINVR {
OINVR::_from({
const MASK: bool = true;
@@ -201546,18 +196294,17 @@ pub mod usart0 {
pub fn dctrl(&mut self) -> _DCTRLW {
_DCTRLW { w: self }
}
- #[doc = "Bit 5 - Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin." ] # [ inline ( always ) ]
pub fn oinv(&mut self) -> _OINVW {
_OINVW { w: self }
}
}
}
- #[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
+ # [ doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." ]
pub struct RS485ADRMATCH {
register: VolatileCell<u32>,
}
- #[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
+ # [ doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." ]
pub mod rs485adrmatch {
#[doc = r" Value read from the register"]
pub struct R {
@@ -201747,8 +196494,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Contains the direction control delay value. This register works in conjunction with an 8-bit counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Contains the direction control delay value. This register works in conjunction with an 8-bit counter." ] # [ inline ( always ) ]
pub fn dly(&self) -> DLYR {
let bits = {
const MASK: u8 = 255;
@@ -201770,8 +196516,7 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Contains the direction control delay value. This register works in conjunction with an 8-bit counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Contains the direction control delay value. This register works in conjunction with an 8-bit counter." ] # [ inline ( always ) ]
pub fn dly(&mut self) -> _DLYW {
_DLYW { w: self }
}
@@ -201876,8 +196621,7 @@ pub mod usart0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CSRCR {
#[doc = "Slave mode. Synchronous slave mode (SCLK in)"] SLAVE_MODE,
- #[doc = "Master mode. Synchronous master mode (SCLK out)"]
- MASTER_MODE,
+ #[doc = "Master mode. Synchronous master mode (SCLK out)"] MASTER_MODE,
}
impl CSRCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -201922,8 +196666,7 @@ pub mod usart0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FESR {
#[doc = "Rising. RxD is sampled on the rising edge of SCLK."] RISING,
- #[doc = "Falling. RxD is sampled on the falling edge of SCLK."]
- FALLING,
+ #[doc = "Falling. RxD is sampled on the falling edge of SCLK."] FALLING,
}
impl FESR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -201966,12 +196709,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `TSBYPASS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TSBYPASSR {
- #[doc = "Synchronized. The input clock is synchronized prior to being used in clock edge detection logic."]
- SYNCHRONIZED,
- #[doc = "Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability."]
- NOT_SYNCHRONIZED,
- }
+ pub enum TSBYPASSR {# [ doc = "Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." ] SYNCHRONIZED , # [ doc = "Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." ] NOT_SYNCHRONIZED}
impl TSBYPASSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -202013,12 +196751,7 @@ pub mod usart0 {
}
#[doc = "Possible values of the field `CSCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CSCENR {
- #[doc = "On character. SCLK cycles only when characters are being sent on TxD."]
- ON_CHARACTER,
- #[doc = "Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)."]
- CONTINUOUSLY,
- }
+ pub enum CSCENR {# [ doc = "On character. SCLK cycles only when characters are being sent on TxD." ] ON_CHARACTER , # [ doc = "Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." ] CONTINUOUSLY}
impl CSCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -202107,8 +196840,7 @@ pub mod usart0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCCLRR {
#[doc = "Software. CSCEN is under software control."] SOFTWARE,
- #[doc = "Hardware. Hardware clears CSCEN after each character is received."]
- HARDWARE,
+ #[doc = "Hardware. Hardware clears CSCEN after each character is received."] HARDWARE,
}
impl CCCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -202208,8 +196940,7 @@ pub mod usart0 {
#[doc = "Values that can be written to the field `CSRC`"]
pub enum CSRCW {
#[doc = "Slave mode. Synchronous slave mode (SCLK in)"] SLAVE_MODE,
- #[doc = "Master mode. Synchronous master mode (SCLK out)"]
- MASTER_MODE,
+ #[doc = "Master mode. Synchronous master mode (SCLK out)"] MASTER_MODE,
}
impl CSRCW {
#[allow(missing_docs)]
@@ -202265,8 +196996,7 @@ pub mod usart0 {
#[doc = "Values that can be written to the field `FES`"]
pub enum FESW {
#[doc = "Rising. RxD is sampled on the rising edge of SCLK."] RISING,
- #[doc = "Falling. RxD is sampled on the falling edge of SCLK."]
- FALLING,
+ #[doc = "Falling. RxD is sampled on the falling edge of SCLK."] FALLING,
}
impl FESW {
#[allow(missing_docs)]
@@ -202320,12 +197050,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `TSBYPASS`"]
- pub enum TSBYPASSW {
- #[doc = "Synchronized. The input clock is synchronized prior to being used in clock edge detection logic."]
- SYNCHRONIZED,
- #[doc = "Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability."]
- NOT_SYNCHRONIZED,
- }
+ pub enum TSBYPASSW {# [ doc = "Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." ] SYNCHRONIZED , # [ doc = "Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." ] NOT_SYNCHRONIZED}
impl TSBYPASSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -202349,13 +197074,11 @@ pub mod usart0 {
self.bit(variant._bits())
}
}
- #[doc = "Synchronized. The input clock is synchronized prior to being used in clock edge detection logic."]
- #[inline(always)]
+ # [ doc = "Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." ] # [ inline ( always ) ]
pub fn synchronized(self) -> &'a mut W {
self.variant(TSBYPASSW::SYNCHRONIZED)
}
- #[doc = "Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability."]
- #[inline(always)]
+ # [ doc = "Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." ] # [ inline ( always ) ]
pub fn not_synchronized(self) -> &'a mut W {
self.variant(TSBYPASSW::NOT_SYNCHRONIZED)
}
@@ -202378,12 +197101,7 @@ pub mod usart0 {
}
}
#[doc = "Values that can be written to the field `CSCEN`"]
- pub enum CSCENW {
- #[doc = "On character. SCLK cycles only when characters are being sent on TxD."]
- ON_CHARACTER,
- #[doc = "Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)."]
- CONTINUOUSLY,
- }
+ pub enum CSCENW {# [ doc = "On character. SCLK cycles only when characters are being sent on TxD." ] ON_CHARACTER , # [ doc = "Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." ] CONTINUOUSLY}
impl CSCENW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -202412,8 +197130,7 @@ pub mod usart0 {
pub fn on_character(self) -> &'a mut W {
self.variant(CSCENW::ON_CHARACTER)
}
- #[doc = "Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)."]
- #[inline(always)]
+ # [ doc = "Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." ] # [ inline ( always ) ]
pub fn continuously(self) -> &'a mut W {
self.variant(CSCENW::CONTINUOUSLY)
}
@@ -202494,8 +197211,7 @@ pub mod usart0 {
#[doc = "Values that can be written to the field `CCCLR`"]
pub enum CCCLRW {
#[doc = "Software. CSCEN is under software control."] SOFTWARE,
- #[doc = "Hardware. Hardware clears CSCEN after each character is received."]
- HARDWARE,
+ #[doc = "Hardware. Hardware clears CSCEN after each character is received."] HARDWARE,
}
impl CCCLRW {
#[allow(missing_docs)]
@@ -202667,11 +197383,11 @@ pub mod usart0 {
}
}
}
- #[doc = "Transmit Enable Register. Turns off USART transmitter for use with software flow control."]
+ # [ doc = "Transmit Enable Register. Turns off USART transmitter for use with software flow control." ]
pub struct TER {
register: VolatileCell<u32>,
}
- #[doc = "Transmit Enable Register. Turns off USART transmitter for use with software flow control."]
+ # [ doc = "Transmit Enable Register. Turns off USART transmitter for use with software flow control." ]
pub mod ter {
#[doc = r" Value read from the register"]
pub struct R {
@@ -202767,8 +197483,7 @@ pub mod usart0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." ] # [ inline ( always ) ]
pub fn txen(&self) -> TXENR {
let bits = {
const MASK: bool = true;
@@ -202790,8 +197505,7 @@ pub mod usart0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." ] # [ inline ( always ) ]
pub fn txen(&mut self) -> _TXENW {
_TXENW { w: self }
}
@@ -202876,8 +197590,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." ] # [ inline ( always ) ]
pub fn rbr(&self) -> RBRR {
let bits = {
const MASK: u8 = 255;
@@ -202888,11 +197601,11 @@ pub mod uart1 {
}
}
}
- #[doc = "Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)"]
+ # [ doc = "Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" ]
pub struct THR {
register: VolatileCell<u32>,
}
- #[doc = "Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)"]
+ # [ doc = "Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" ]
pub mod thr {
#[doc = r" Value to write to the register"]
pub struct W {
@@ -202937,18 +197650,17 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." ] # [ inline ( always ) ]
pub fn thr(&mut self) -> _THRW {
_THRW { w: self }
}
}
}
- #[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)"]
+ # [ doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" ]
pub struct DLL {
register: VolatileCell<u32>,
}
- #[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)"]
+ # [ doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" ]
pub mod dll {
#[doc = r" Value read from the register"]
pub struct R {
@@ -203026,8 +197738,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Divisor Latch LSB. The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor Latch LSB. The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." ] # [ inline ( always ) ]
pub fn dllsb(&self) -> DLLSBR {
let bits = {
const MASK: u8 = 255;
@@ -203049,18 +197760,17 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Divisor Latch LSB. The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor Latch LSB. The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." ] # [ inline ( always ) ]
pub fn dllsb(&mut self) -> _DLLSBW {
_DLLSBW { w: self }
}
}
}
- #[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)"]
+ # [ doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" ]
pub struct DLM {
register: VolatileCell<u32>,
}
- #[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)"]
+ # [ doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" ]
pub mod dlm {
#[doc = r" Value read from the register"]
pub struct R {
@@ -203138,8 +197848,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Divisor Latch MSB. The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor Latch MSB. The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." ] # [ inline ( always ) ]
pub fn dlmsb(&self) -> DLMSBR {
let bits = {
const MASK: u8 = 255;
@@ -203161,18 +197870,17 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Divisor Latch MSB. The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Divisor Latch MSB. The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." ] # [ inline ( always ) ]
pub fn dlmsb(&mut self) -> _DLMSBW {
_DLMSBW { w: self }
}
}
}
- #[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)"]
+ # [ doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" ]
pub struct IER {
register: VolatileCell<u32>,
}
- #[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)"]
+ # [ doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" ]
pub mod ier {
#[doc = r" Value read from the register"]
pub struct R {
@@ -203931,8 +198639,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt." ] # [ inline ( always ) ]
pub fn rbrie(&self) -> RBRIER {
RBRIER::_from({
const MASK: bool = true;
@@ -203940,8 +198647,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]."]
- #[inline(always)]
+ # [ doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]." ] # [ inline ( always ) ]
pub fn threie(&self) -> THREIER {
THREIER::_from({
const MASK: bool = true;
@@ -203949,8 +198655,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]."]
- #[inline(always)]
+ # [ doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]." ] # [ inline ( always ) ]
pub fn rxie(&self) -> RXIER {
RXIER::_from({
const MASK: bool = true;
@@ -203958,8 +198663,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]." ] # [ inline ( always ) ]
pub fn msie(&self) -> MSIER {
MSIER::_from({
const MASK: bool = true;
@@ -203967,8 +198671,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set."]
- #[inline(always)]
+ # [ doc = "Bit 7 - CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set." ] # [ inline ( always ) ]
pub fn ctsie(&self) -> CTSIER {
CTSIER::_from({
const MASK: bool = true;
@@ -204007,28 +198710,23 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt." ] # [ inline ( always ) ]
pub fn rbrie(&mut self) -> _RBRIEW {
_RBRIEW { w: self }
}
- #[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]."]
- #[inline(always)]
+ # [ doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]." ] # [ inline ( always ) ]
pub fn threie(&mut self) -> _THREIEW {
_THREIEW { w: self }
}
- #[doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]."]
- #[inline(always)]
+ # [ doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]." ] # [ inline ( always ) ]
pub fn rxie(&mut self) -> _RXIEW {
_RXIEW { w: self }
}
- #[doc = "Bit 3 - Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]." ] # [ inline ( always ) ]
pub fn msie(&mut self) -> _MSIEW {
_MSIEW { w: self }
}
- #[doc = "Bit 7 - CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set."]
- #[inline(always)]
+ # [ doc = "Bit 7 - CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set." ] # [ inline ( always ) ]
pub fn ctsie(&mut self) -> _CTSIEW {
_CTSIEW { w: self }
}
@@ -204066,8 +198764,7 @@ pub mod uart1 {
#[doc = "Possible values of the field `INTSTATUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTSTATUSR {
- #[doc = "Interrupt pending. At least one interrupt is pending."]
- INTERRUPT_PENDING,
+ #[doc = "Interrupt pending. At least one interrupt is pending."] INTERRUPT_PENDING,
#[doc = "Not pending. No interrupt is pending."] NOT_PENDING,
}
impl INTSTATUSR {
@@ -204112,8 +198809,7 @@ pub mod uart1 {
#[doc = "Possible values of the field `INTID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTIDR {
- #[doc = "RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)."]
- RLS,
+ #[doc = "RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)."] RLS,
#[doc = "RDA. Priority 2 - Receive Data Available (RDA)."] RDA,
#[doc = "CTI. Priority 2 - Character Time-out Indicator (CTI)."] CTI,
#[doc = "THRE. Priority 3 - THRE Interrupt."] THRE,
@@ -204223,8 +198919,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]." ] # [ inline ( always ) ]
pub fn intstatus(&self) -> INTSTATUSR {
INTSTATUSR::_from({
const MASK: bool = true;
@@ -204232,8 +198927,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 1:3 - Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)."]
- #[inline(always)]
+ # [ doc = "Bits 1:3 - Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111)." ] # [ inline ( always ) ]
pub fn intid(&self) -> INTIDR {
INTIDR::_from({
const MASK: u8 = 7;
@@ -204251,8 +198945,7 @@ pub mod uart1 {
};
FIFOENABLER { bits }
}
- #[doc = "Bit 8 - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 8 - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." ] # [ inline ( always ) ]
pub fn abeoint(&self) -> ABEOINTR {
let bits = {
const MASK: bool = true;
@@ -204261,8 +198954,7 @@ pub mod uart1 {
};
ABEOINTR { bits }
}
- #[doc = "Bit 9 - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." ] # [ inline ( always ) ]
pub fn abtoint(&self) -> ABTOINTR {
let bits = {
const MASK: bool = true;
@@ -204296,11 +198988,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `FIFOEN`"]
- pub enum FIFOENW {
- #[doc = "Disabled. Must not be used in the application."] DISABLED,
- #[doc = "Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs."]
- ENABLED,
- }
+ pub enum FIFOENW {# [ doc = "Disabled. Must not be used in the application." ] DISABLED , # [ doc = "Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." ] ENABLED}
impl FIFOENW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -204329,8 +199017,7 @@ pub mod uart1 {
pub fn disabled(self) -> &'a mut W {
self.variant(FIFOENW::DISABLED)
}
- #[doc = "Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs."]
- #[inline(always)]
+ # [ doc = "Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(FIFOENW::ENABLED)
}
@@ -204353,11 +199040,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `RXFIFORES`"]
- pub enum RXFIFORESW {
- #[doc = "No effect. No impact on either of UART1 FIFOs."] NO_EFFECT,
- #[doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing."]
- CLEAR,
- }
+ pub enum RXFIFORESW {# [ doc = "No effect. No impact on either of UART1 FIFOs." ] NO_EFFECT , # [ doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." ] CLEAR}
impl RXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -204386,8 +199069,7 @@ pub mod uart1 {
pub fn no_effect(self) -> &'a mut W {
self.variant(RXFIFORESW::NO_EFFECT)
}
- #[doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing."]
- #[inline(always)]
+ # [ doc = "Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(RXFIFORESW::CLEAR)
}
@@ -204410,11 +199092,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `TXFIFORES`"]
- pub enum TXFIFORESW {
- #[doc = "No effect. No impact on either of UART1 FIFOs."] NO_EFFECT,
- #[doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing."]
- CLEAR,
- }
+ pub enum TXFIFORESW {# [ doc = "No effect. No impact on either of UART1 FIFOs." ] NO_EFFECT , # [ doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." ] CLEAR}
impl TXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -204443,8 +199121,7 @@ pub mod uart1 {
pub fn no_effect(self) -> &'a mut W {
self.variant(TXFIFORESW::NO_EFFECT)
}
- #[doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing."]
- #[inline(always)]
+ # [ doc = "Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(TXFIFORESW::CLEAR)
}
@@ -204578,13 +199255,11 @@ pub mod uart1 {
pub fn txfifores(&mut self) -> _TXFIFORESW {
_TXFIFORESW { w: self }
}
- #[doc = "Bit 3 - DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1."]
- #[inline(always)]
+ # [ doc = "Bit 3 - DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." ] # [ inline ( always ) ]
pub fn dmamode(&mut self) -> _DMAMODEW {
_DMAMODEW { w: self }
}
- #[doc = "Bits 6:7 - RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated." ] # [ inline ( always ) ]
pub fn rxtriglvl(&mut self) -> _RXTRIGLVLW {
_RXTRIGLVLW { w: self }
}
@@ -204740,10 +199415,8 @@ pub mod uart1 {
#[doc = "Possible values of the field `PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PER {
- #[doc = "Disable parity generation and checking."]
- DISABLE_PARITY_GENER,
- #[doc = "Enable parity generation and checking."]
- ENABLE_PARITY_GENERA,
+ #[doc = "Disable parity generation and checking."] DISABLE_PARITY_GENER,
+ #[doc = "Enable parity generation and checking."] ENABLE_PARITY_GENERA,
}
impl PER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -204786,14 +199459,7 @@ pub mod uart1 {
}
#[doc = "Possible values of the field `PS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum PSR {
- #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
- ODD_PARITY,
- #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
- EVEN_PARITY,
- #[doc = "Force HIGH. Forced 1 stick parity."] FORCE_HIGH,
- #[doc = "Force LOW. Forced 0 stick parity."] FORCE_LOW,
- }
+ pub enum PSR {# [ doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." ] ODD_PARITY , # [ doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." ] EVEN_PARITY , # [ doc = "Force HIGH. Forced 1 stick parity." ] FORCE_HIGH , # [ doc = "Force LOW. Forced 0 stick parity." ] FORCE_LOW}
impl PSR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -204840,11 +199506,7 @@ pub mod uart1 {
}
#[doc = "Possible values of the field `BC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BCR {
- #[doc = "Disabled. Disable break transmission."] DISABLED,
- #[doc = "Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high."]
- ENABLED,
- }
+ pub enum BCR {# [ doc = "Disabled. Disable break transmission." ] DISABLED , # [ doc = "Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." ] ENABLED}
impl BCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -205049,10 +199711,8 @@ pub mod uart1 {
}
#[doc = "Values that can be written to the field `PE`"]
pub enum PEW {
- #[doc = "Disable parity generation and checking."]
- DISABLE_PARITY_GENER,
- #[doc = "Enable parity generation and checking."]
- ENABLE_PARITY_GENERA,
+ #[doc = "Disable parity generation and checking."] DISABLE_PARITY_GENER,
+ #[doc = "Enable parity generation and checking."] ENABLE_PARITY_GENERA,
}
impl PEW {
#[allow(missing_docs)]
@@ -205106,14 +199766,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `PS`"]
- pub enum PSW {
- #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
- ODD_PARITY,
- #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
- EVEN_PARITY,
- #[doc = "Force HIGH. Forced 1 stick parity."] FORCE_HIGH,
- #[doc = "Force LOW. Forced 0 stick parity."] FORCE_LOW,
- }
+ pub enum PSW {# [ doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." ] ODD_PARITY , # [ doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." ] EVEN_PARITY , # [ doc = "Force HIGH. Forced 1 stick parity." ] FORCE_HIGH , # [ doc = "Force LOW. Forced 0 stick parity." ] FORCE_LOW}
impl PSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -205139,13 +199792,11 @@ pub mod uart1 {
self.bits(variant._bits())
}
}
- #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
- #[inline(always)]
+ # [ doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." ] # [ inline ( always ) ]
pub fn odd_parity(self) -> &'a mut W {
self.variant(PSW::ODD_PARITY)
}
- #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
- #[inline(always)]
+ # [ doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." ] # [ inline ( always ) ]
pub fn even_parity(self) -> &'a mut W {
self.variant(PSW::EVEN_PARITY)
}
@@ -205170,11 +199821,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `BC`"]
- pub enum BCW {
- #[doc = "Disabled. Disable break transmission."] DISABLED,
- #[doc = "Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high."]
- ENABLED,
- }
+ pub enum BCW {# [ doc = "Disabled. Disable break transmission." ] DISABLED , # [ doc = "Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." ] ENABLED}
impl BCW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -205203,8 +199850,7 @@ pub mod uart1 {
pub fn disabled(self) -> &'a mut W {
self.variant(BCW::DISABLED)
}
- #[doc = "Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high."]
- #[inline(always)]
+ # [ doc = "Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(BCW::ENABLED)
}
@@ -205387,11 +200033,11 @@ pub mod uart1 {
}
}
}
- #[doc = "Modem Control Register. Contains controls for flow control handshaking and loopback mode."]
+ # [ doc = "Modem Control Register. Contains controls for flow control handshaking and loopback mode." ]
pub struct MCR {
register: VolatileCell<u32>,
}
- #[doc = "Modem Control Register. Contains controls for flow control handshaking and loopback mode."]
+ # [ doc = "Modem Control Register. Contains controls for flow control handshaking and loopback mode." ]
pub mod mcr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -205834,8 +200480,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."]
- #[inline(always)]
+ # [ doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." ] # [ inline ( always ) ]
pub fn dtrctrl(&self) -> DTRCTRLR {
let bits = {
const MASK: bool = true;
@@ -205844,8 +200489,7 @@ pub mod uart1 {
};
DTRCTRLR { bits }
}
- #[doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."]
- #[inline(always)]
+ # [ doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." ] # [ inline ( always ) ]
pub fn rtsctrl(&self) -> RTSCTRLR {
let bits = {
const MASK: bool = true;
@@ -205854,8 +200498,7 @@ pub mod uart1 {
};
RTSCTRLR { bits }
}
- #[doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR." ] # [ inline ( always ) ]
pub fn lms(&self) -> LMSR {
LMSR::_from({
const MASK: bool = true;
@@ -205894,18 +200537,15 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."]
- #[inline(always)]
+ # [ doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." ] # [ inline ( always ) ]
pub fn dtrctrl(&mut self) -> _DTRCTRLW {
_DTRCTRLW { w: self }
}
- #[doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."]
- #[inline(always)]
+ # [ doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." ] # [ inline ( always ) ]
pub fn rtsctrl(&mut self) -> _RTSCTRLW {
_RTSCTRLW { w: self }
}
- #[doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR." ] # [ inline ( always ) ]
pub fn lms(&mut self) -> _LMSW {
_LMSW { w: self }
}
@@ -205921,11 +200561,11 @@ pub mod uart1 {
}
}
}
- #[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
+ # [ doc = "Line Status Register. Contains flags for transmit and receive status, including line errors." ]
pub struct LSR {
register: VolatileCell<u32>,
}
- #[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
+ # [ doc = "Line Status Register. Contains flags for transmit and receive status, including line errors." ]
pub mod lsr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -206213,8 +200853,7 @@ pub mod uart1 {
#[doc = "Possible values of the field `TEMT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TEMTR {
- #[doc = "Not empty. THR and/or the TSR contains valid data."]
- NOT_EMPTY,
+ #[doc = "Not empty. THR and/or the TSR contains valid data."] NOT_EMPTY,
#[doc = "Empty. THR and the TSR are empty."] EMPTY,
}
impl TEMTR {
@@ -206259,10 +200898,8 @@ pub mod uart1 {
#[doc = "Possible values of the field `RXFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXFER {
- #[doc = "No error. RBR contains no UART1 RX errors or FCR[0]=0."]
- NO_ERROR,
- #[doc = "Error. UART1 RBR contains at least one UART1 RX error."]
- ERROR,
+ #[doc = "No error. RBR contains no UART1 RX errors or FCR[0]=0."] NO_ERROR,
+ #[doc = "Error. UART1 RBR contains at least one UART1 RX error."] ERROR,
}
impl RXFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -206309,8 +200946,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty." ] # [ inline ( always ) ]
pub fn rdr(&self) -> RDRR {
RDRR::_from({
const MASK: bool = true;
@@ -206318,8 +200954,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 1 - Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost." ] # [ inline ( always ) ]
pub fn oe(&self) -> OER {
OER::_from({
const MASK: bool = true;
@@ -206327,8 +200962,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO." ] # [ inline ( always ) ]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
@@ -206336,8 +200970,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO." ] # [ inline ( always ) ]
pub fn fe(&self) -> FER {
FER::_from({
const MASK: bool = true;
@@ -206345,8 +200978,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO." ] # [ inline ( always ) ]
pub fn bi(&self) -> BIR {
BIR::_from({
const MASK: bool = true;
@@ -206354,8 +200986,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write." ] # [ inline ( always ) ]
pub fn thre(&self) -> THRER {
THRER::_from({
const MASK: bool = true;
@@ -206363,8 +200994,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data." ] # [ inline ( always ) ]
pub fn temt(&self) -> TEMTR {
TEMTR::_from({
const MASK: bool = true;
@@ -206372,8 +201002,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO." ] # [ inline ( always ) ]
pub fn rxfe(&self) -> RXFER {
RXFER::_from({
const MASK: bool = true;
@@ -206405,10 +201034,8 @@ pub mod uart1 {
#[doc = "Possible values of the field `DCTS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCTSR {
- #[doc = "No change. No change detected on modem input, CTS."]
- NO_CHANGE,
- #[doc = "State change. State change detected on modem input, CTS."]
- STATE_CHANGE,
+ #[doc = "No change. No change detected on modem input, CTS."] NO_CHANGE,
+ #[doc = "State change. State change detected on modem input, CTS."] STATE_CHANGE,
}
impl DCTSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -206452,10 +201079,8 @@ pub mod uart1 {
#[doc = "Possible values of the field `DDSR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DDSRR {
- #[doc = "No change. No change detected on modem input, DSR."]
- NO_CHANGE,
- #[doc = "State change. State change detected on modem input, DSR."]
- STATE_CHANGE,
+ #[doc = "No change. No change detected on modem input, DSR."] NO_CHANGE,
+ #[doc = "State change. State change detected on modem input, DSR."] STATE_CHANGE,
}
impl DDSRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -206499,8 +201124,7 @@ pub mod uart1 {
#[doc = "Possible values of the field `TERI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TERIR {
- #[doc = "No change. No change detected on modem input, RI."]
- NO_CHANGE,
+ #[doc = "No change. No change detected on modem input, RI."] NO_CHANGE,
#[doc = "Rising. Low-to-high transition detected on RI."] RISING,
}
impl TERIR {
@@ -206545,10 +201169,8 @@ pub mod uart1 {
#[doc = "Possible values of the field `DDCD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DDCDR {
- #[doc = "No change. No change detected on modem input, DCD."]
- NO_CHANGE,
- #[doc = "State change. State change detected on modem input, DCD."]
- STATE_CHANGE,
+ #[doc = "No change. No change detected on modem input, DCD."] NO_CHANGE,
+ #[doc = "State change. State change detected on modem input, DCD."] STATE_CHANGE,
}
impl DDCDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -206697,8 +201319,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read." ] # [ inline ( always ) ]
pub fn teri(&self) -> TERIR {
TERIR::_from({
const MASK: bool = true;
@@ -206715,8 +201336,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." ] # [ inline ( always ) ]
pub fn cts(&self) -> CTSR {
let bits = {
const MASK: bool = true;
@@ -206725,8 +201345,7 @@ pub mod uart1 {
};
CTSR { bits }
}
- #[doc = "Bit 5 - Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." ] # [ inline ( always ) ]
pub fn dsr(&self) -> DSRR {
let bits = {
const MASK: bool = true;
@@ -206735,8 +201354,7 @@ pub mod uart1 {
};
DSRR { bits }
}
- #[doc = "Bit 6 - Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." ] # [ inline ( always ) ]
pub fn ri(&self) -> RIR {
let bits = {
const MASK: bool = true;
@@ -206745,8 +201363,7 @@ pub mod uart1 {
};
RIR { bits }
}
- #[doc = "Bit 7 - Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." ] # [ inline ( always ) ]
pub fn dcd(&self) -> DCDR {
let bits = {
const MASK: bool = true;
@@ -206921,11 +201538,7 @@ pub mod uart1 {
}
#[doc = "Possible values of the field `START`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum STARTR {
- #[doc = "Stop. Auto-baud stop (auto-baud is not running)."] STOP,
- #[doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
- START,
- }
+ pub enum STARTR {# [ doc = "Stop. Auto-baud stop (auto-baud is not running)." ] STOP , # [ doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." ] START}
impl STARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -207012,11 +201625,7 @@ pub mod uart1 {
}
#[doc = "Possible values of the field `AUTORESTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum AUTORESTARTR {
- #[doc = "No restart"] NO_RESTART,
- #[doc = "Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)"]
- RESTART,
- }
+ pub enum AUTORESTARTR {# [ doc = "No restart" ] NO_RESTART , # [ doc = "Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" ] RESTART}
impl AUTORESTARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -207060,8 +201669,7 @@ pub mod uart1 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABEOINTCLRR {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABEOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -207106,8 +201714,7 @@ pub mod uart1 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABTOINTCLRR {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABTOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -207149,11 +201756,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `START`"]
- pub enum STARTW {
- #[doc = "Stop. Auto-baud stop (auto-baud is not running)."] STOP,
- #[doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
- START,
- }
+ pub enum STARTW {# [ doc = "Stop. Auto-baud stop (auto-baud is not running)." ] STOP , # [ doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." ] START}
impl STARTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -207182,8 +201785,7 @@ pub mod uart1 {
pub fn stop(self) -> &'a mut W {
self.variant(STARTW::STOP)
}
- #[doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
- #[inline(always)]
+ # [ doc = "Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." ] # [ inline ( always ) ]
pub fn start(self) -> &'a mut W {
self.variant(STARTW::START)
}
@@ -207262,11 +201864,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `AUTORESTART`"]
- pub enum AUTORESTARTW {
- #[doc = "No restart"] NO_RESTART,
- #[doc = "Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)"]
- RESTART,
- }
+ pub enum AUTORESTARTW {# [ doc = "No restart" ] NO_RESTART , # [ doc = "Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" ] RESTART}
impl AUTORESTARTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -207295,8 +201893,7 @@ pub mod uart1 {
pub fn no_restart(self) -> &'a mut W {
self.variant(AUTORESTARTW::NO_RESTART)
}
- #[doc = "Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)"]
- #[inline(always)]
+ # [ doc = "Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" ] # [ inline ( always ) ]
pub fn restart(self) -> &'a mut W {
self.variant(AUTORESTARTW::RESTART)
}
@@ -207321,8 +201918,7 @@ pub mod uart1 {
#[doc = "Values that can be written to the field `ABEOINTCLR`"]
pub enum ABEOINTCLRW {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABEOINTCLRW {
#[allow(missing_docs)]
@@ -207378,8 +201974,7 @@ pub mod uart1 {
#[doc = "Values that can be written to the field `ABTOINTCLR`"]
pub enum ABTOINTCLRW {
#[doc = "No effect. Writing a 0 has no impact."] NO_EFFECT,
- #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."]
- CLEAR,
+ #[doc = "Clear. Writing a 1 will clear the corresponding interrupt in the IIR."] CLEAR,
}
impl ABTOINTCLRW {
#[allow(missing_docs)]
@@ -207438,8 +202033,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Auto-baud start bit. This bit is automatically cleared after auto-baud completion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Auto-baud start bit. This bit is automatically cleared after auto-baud completion." ] # [ inline ( always ) ]
pub fn start(&self) -> STARTR {
STARTR::_from({
const MASK: bool = true;
@@ -207496,8 +202090,7 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Auto-baud start bit. This bit is automatically cleared after auto-baud completion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Auto-baud start bit. This bit is automatically cleared after auto-baud completion." ] # [ inline ( always ) ]
pub fn start(&mut self) -> _STARTW {
_STARTW { w: self }
}
@@ -207631,8 +202224,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." ] # [ inline ( always ) ]
pub fn divaddval(&self) -> DIVADDVALR {
let bits = {
const MASK: u8 = 15;
@@ -207641,8 +202233,7 @@ pub mod uart1 {
};
DIVADDVALR { bits }
}
- #[doc = "Bits 4:7 - Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." ] # [ inline ( always ) ]
pub fn mulval(&self) -> MULVALR {
let bits = {
const MASK: u8 = 15;
@@ -207664,23 +202255,21 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." ] # [ inline ( always ) ]
pub fn divaddval(&mut self) -> _DIVADDVALW {
_DIVADDVALW { w: self }
}
- #[doc = "Bits 4:7 - Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not."]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." ] # [ inline ( always ) ]
pub fn mulval(&mut self) -> _MULVALW {
_MULVALW { w: self }
}
}
}
- #[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
+ # [ doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." ]
pub struct RS485CTRL {
register: VolatileCell<u32>,
}
- #[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
+ # [ doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." ]
pub mod rs485ctrl {
#[doc = r" Value read from the register"]
pub struct R {
@@ -207728,12 +202317,7 @@ pub mod uart1 {
}
#[doc = "Possible values of the field `NMMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum NMMENR {
- #[doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."]
- DISABLED,
- #[doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt."]
- ENABLED,
- }
+ pub enum NMMENR {# [ doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." ] DISABLED , # [ doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." ] ENABLED}
impl NMMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -207865,12 +202449,7 @@ pub mod uart1 {
}
#[doc = "Possible values of the field `SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SELR {
- #[doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."]
- RTS,
- #[doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."]
- DTR,
- }
+ pub enum SELR {# [ doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." ] RTS , # [ doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." ] DTR}
impl SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -207957,12 +202536,7 @@ pub mod uart1 {
}
#[doc = "Possible values of the field `OINV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum OINVR {
- #[doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
- LOW,
- #[doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
- HIGH,
- }
+ pub enum OINVR {# [ doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." ] LOW , # [ doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." ] HIGH}
impl OINVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -208003,12 +202577,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `NMMEN`"]
- pub enum NMMENW {
- #[doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."]
- DISABLED,
- #[doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt."]
- ENABLED,
- }
+ pub enum NMMENW {# [ doc = "Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." ] DISABLED , # [ doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." ] ENABLED}
impl NMMENW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -208037,8 +202606,7 @@ pub mod uart1 {
pub fn disabled(self) -> &'a mut W {
self.variant(NMMENW::DISABLED)
}
- #[doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt."]
- #[inline(always)]
+ # [ doc = "Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(NMMENW::ENABLED)
}
@@ -208173,12 +202741,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `SEL`"]
- pub enum SELW {
- #[doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."]
- RTS,
- #[doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."]
- DTR,
- }
+ pub enum SELW {# [ doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." ] RTS , # [ doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." ] DTR}
impl SELW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -208202,13 +202765,11 @@ pub mod uart1 {
self.bit(variant._bits())
}
}
- #[doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."]
- #[inline(always)]
+ # [ doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." ] # [ inline ( always ) ]
pub fn rts(self) -> &'a mut W {
self.variant(SELW::RTS)
}
- #[doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."]
- #[inline(always)]
+ # [ doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." ] # [ inline ( always ) ]
pub fn dtr(self) -> &'a mut W {
self.variant(SELW::DTR)
}
@@ -208287,12 +202848,7 @@ pub mod uart1 {
}
}
#[doc = "Values that can be written to the field `OINV`"]
- pub enum OINVW {
- #[doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
- LOW,
- #[doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
- HIGH,
- }
+ pub enum OINVW {# [ doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." ] LOW , # [ doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." ] HIGH}
impl OINVW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -208316,13 +202872,11 @@ pub mod uart1 {
self.bit(variant._bits())
}
}
- #[doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
- #[inline(always)]
+ # [ doc = "Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." ] # [ inline ( always ) ]
pub fn low(self) -> &'a mut W {
self.variant(OINVW::LOW)
}
- #[doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
- #[inline(always)]
+ # [ doc = "High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." ] # [ inline ( always ) ]
pub fn high(self) -> &'a mut W {
self.variant(OINVW::HIGH)
}
@@ -208395,8 +202949,7 @@ pub mod uart1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin." ] # [ inline ( always ) ]
pub fn oinv(&self) -> OINVR {
OINVR::_from({
const MASK: bool = true;
@@ -208442,18 +202995,17 @@ pub mod uart1 {
pub fn dctrl(&mut self) -> _DCTRLW {
_DCTRLW { w: self }
}
- #[doc = "Bit 5 - Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin." ] # [ inline ( always ) ]
pub fn oinv(&mut self) -> _OINVW {
_OINVW { w: self }
}
}
}
- #[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
+ # [ doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." ]
pub struct RS485ADRMATCH {
register: VolatileCell<u32>,
}
- #[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
+ # [ doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." ]
pub mod rs485adrmatch {
#[doc = r" Value read from the register"]
pub struct R {
@@ -208643,8 +203195,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." ] # [ inline ( always ) ]
pub fn dly(&self) -> DLYR {
let bits = {
const MASK: u8 = 255;
@@ -208666,18 +203217,17 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." ] # [ inline ( always ) ]
pub fn dly(&mut self) -> _DLYW {
_DLYW { w: self }
}
}
}
- #[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
+ # [ doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control." ]
pub struct TER {
register: VolatileCell<u32>,
}
- #[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
+ # [ doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control." ]
pub mod ter {
#[doc = r" Value read from the register"]
pub struct R {
@@ -208773,8 +203323,7 @@ pub mod uart1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." ] # [ inline ( always ) ]
pub fn txen(&self) -> TXENR {
let bits = {
const MASK: bool = true;
@@ -208796,8 +203345,7 @@ pub mod uart1 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." ] # [ inline ( always ) ]
pub fn txen(&mut self) -> _TXENW {
_TXENW { w: self }
}
@@ -208821,21 +203369,7 @@ pub mod ssp0 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Control Register 0. Selects the serial clock rate, bus type, and data size."]
- pub cr0: CR0,
- #[doc = "0x04 - Control Register 1. Selects master/slave and other modes."]
- pub cr1: CR1,
- #[doc = "0x08 - Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO."]
- pub dr: DR,
- #[doc = "0x0c - Status Register"] pub sr: SR,
- #[doc = "0x10 - Clock Prescale Register"] pub cpsr: CPSR,
- #[doc = "0x14 - Interrupt Mask Set and Clear Register"] pub imsc: IMSC,
- #[doc = "0x18 - Raw Interrupt Status Register"] pub ris: RIS,
- #[doc = "0x1c - Masked Interrupt Status Register"] pub mis: MIS,
- #[doc = "0x20 - SSPICR Interrupt Clear Register"] pub icr: ICR,
- #[doc = "0x24 - SSP0 DMA control register"] pub dmacr: DMACR,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - Control Register 0. Selects the serial clock rate, bus type, and data size." ] pub cr0 : CR0 , # [ doc = "0x04 - Control Register 1. Selects master/slave and other modes." ] pub cr1 : CR1 , # [ doc = "0x08 - Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." ] pub dr : DR , # [ doc = "0x0c - Status Register" ] pub sr : SR , # [ doc = "0x10 - Clock Prescale Register" ] pub cpsr : CPSR , # [ doc = "0x14 - Interrupt Mask Set and Clear Register" ] pub imsc : IMSC , # [ doc = "0x18 - Raw Interrupt Status Register" ] pub ris : RIS , # [ doc = "0x1c - Masked Interrupt Status Register" ] pub mis : MIS , # [ doc = "0x20 - SSPICR Interrupt Clear Register" ] pub icr : ICR , # [ doc = "0x24 - SSP0 DMA control register" ] pub dmacr : DMACR , }
#[doc = "Control Register 0. Selects the serial clock rate, bus type, and data size."]
pub struct CR0 {
register: VolatileCell<u32>,
@@ -209068,10 +203602,8 @@ pub mod ssp0 {
#[doc = "Possible values of the field `CPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPOLR {
- #[doc = "SSP controller maintains the bus clock low between frames."]
- BUS_LOW,
- #[doc = "SSP controller maintains the bus clock high between frames."]
- BUS_HIGH,
+ #[doc = "SSP controller maintains the bus clock low between frames."] BUS_LOW,
+ #[doc = "SSP controller maintains the bus clock high between frames."] BUS_HIGH,
}
impl CPOLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -209114,12 +203646,7 @@ pub mod ssp0 {
}
#[doc = "Possible values of the field `CPHA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CPHAR {
- #[doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."]
- FIRST_CLOCK,
- #[doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."]
- SECOND_CLOCK,
- }
+ pub enum CPHAR {# [ doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." ] FIRST_CLOCK , # [ doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." ] SECOND_CLOCK}
impl CPHAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -209358,10 +203885,8 @@ pub mod ssp0 {
}
#[doc = "Values that can be written to the field `CPOL`"]
pub enum CPOLW {
- #[doc = "SSP controller maintains the bus clock low between frames."]
- BUS_LOW,
- #[doc = "SSP controller maintains the bus clock high between frames."]
- BUS_HIGH,
+ #[doc = "SSP controller maintains the bus clock low between frames."] BUS_LOW,
+ #[doc = "SSP controller maintains the bus clock high between frames."] BUS_HIGH,
}
impl CPOLW {
#[allow(missing_docs)]
@@ -209415,12 +203940,7 @@ pub mod ssp0 {
}
}
#[doc = "Values that can be written to the field `CPHA`"]
- pub enum CPHAW {
- #[doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."]
- FIRST_CLOCK,
- #[doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."]
- SECOND_CLOCK,
- }
+ pub enum CPHAW {# [ doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." ] FIRST_CLOCK , # [ doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." ] SECOND_CLOCK}
impl CPHAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -209444,13 +203964,11 @@ pub mod ssp0 {
self.bit(variant._bits())
}
}
- #[doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."]
- #[inline(always)]
+ # [ doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." ] # [ inline ( always ) ]
pub fn first_clock(self) -> &'a mut W {
self.variant(CPHAW::FIRST_CLOCK)
}
- #[doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."]
- #[inline(always)]
+ # [ doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." ] # [ inline ( always ) ]
pub fn second_clock(self) -> &'a mut W {
self.variant(CPHAW::SECOND_CLOCK)
}
@@ -209493,8 +204011,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used." ] # [ inline ( always ) ]
pub fn dss(&self) -> DSSR {
DSSR::_from({
const MASK: u8 = 15;
@@ -209529,8 +204046,7 @@ pub mod ssp0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." ] # [ inline ( always ) ]
pub fn scr(&self) -> SCRR {
let bits = {
const MASK: u8 = 255;
@@ -209552,8 +204068,7 @@ pub mod ssp0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used." ] # [ inline ( always ) ]
pub fn dss(&mut self) -> _DSSW {
_DSSW { w: self }
}
@@ -209572,8 +204087,7 @@ pub mod ssp0 {
pub fn cpha(&mut self) -> _CPHAW {
_CPHAW { w: self }
}
- #[doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." ] # [ inline ( always ) ]
pub fn scr(&mut self) -> _SCRW {
_SCRW { w: self }
}
@@ -209631,11 +204145,7 @@ pub mod ssp0 {
}
#[doc = "Possible values of the field `LBM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum LBMR {
- #[doc = "During normal operation."] NORMAL,
- #[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."]
- OUPTU,
- }
+ pub enum LBMR {# [ doc = "During normal operation." ] NORMAL , # [ doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." ] OUPTU}
impl LBMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -209677,11 +204187,7 @@ pub mod ssp0 {
}
#[doc = "Possible values of the field `SSE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SSER {
- #[doc = "The SSP controller is disabled."] DISABLED,
- #[doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit."]
- ENABLED,
- }
+ pub enum SSER {# [ doc = "The SSP controller is disabled." ] DISABLED , # [ doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." ] ENABLED}
impl SSER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -209723,12 +204229,7 @@ pub mod ssp0 {
}
#[doc = "Possible values of the field `MS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MSR {
- #[doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."]
- MASTER,
- #[doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."]
- SLAVE,
- }
+ pub enum MSR {# [ doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." ] MASTER , # [ doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." ] SLAVE}
impl MSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -209790,11 +204291,7 @@ pub mod ssp0 {
}
}
#[doc = "Values that can be written to the field `LBM`"]
- pub enum LBMW {
- #[doc = "During normal operation."] NORMAL,
- #[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."]
- OUPTU,
- }
+ pub enum LBMW {# [ doc = "During normal operation." ] NORMAL , # [ doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." ] OUPTU}
impl LBMW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -209823,8 +204320,7 @@ pub mod ssp0 {
pub fn normal(self) -> &'a mut W {
self.variant(LBMW::NORMAL)
}
- #[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."]
- #[inline(always)]
+ # [ doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." ] # [ inline ( always ) ]
pub fn ouptu(self) -> &'a mut W {
self.variant(LBMW::OUPTU)
}
@@ -209847,11 +204343,7 @@ pub mod ssp0 {
}
}
#[doc = "Values that can be written to the field `SSE`"]
- pub enum SSEW {
- #[doc = "The SSP controller is disabled."] DISABLED,
- #[doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit."]
- ENABLED,
- }
+ pub enum SSEW {# [ doc = "The SSP controller is disabled." ] DISABLED , # [ doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." ] ENABLED}
impl SSEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -209880,8 +204372,7 @@ pub mod ssp0 {
pub fn disabled(self) -> &'a mut W {
self.variant(SSEW::DISABLED)
}
- #[doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit."]
- #[inline(always)]
+ # [ doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(SSEW::ENABLED)
}
@@ -209904,12 +204395,7 @@ pub mod ssp0 {
}
}
#[doc = "Values that can be written to the field `MS`"]
- pub enum MSW {
- #[doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."]
- MASTER,
- #[doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."]
- SLAVE,
- }
+ pub enum MSW {# [ doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." ] MASTER , # [ doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." ] SLAVE}
impl MSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -209933,13 +204419,11 @@ pub mod ssp0 {
self.bit(variant._bits())
}
}
- #[doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."]
- #[inline(always)]
+ # [ doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." ] # [ inline ( always ) ]
pub fn master(self) -> &'a mut W {
self.variant(MSW::MASTER)
}
- #[doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."]
- #[inline(always)]
+ # [ doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." ] # [ inline ( always ) ]
pub fn slave(self) -> &'a mut W {
self.variant(MSW::SLAVE)
}
@@ -210017,8 +204501,7 @@ pub mod ssp0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." ] # [ inline ( always ) ]
pub fn sod(&self) -> SODR {
let bits = {
const MASK: bool = true;
@@ -210055,8 +204538,7 @@ pub mod ssp0 {
pub fn ms(&mut self) -> _MSW {
_MSW { w: self }
}
- #[doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." ] # [ inline ( always ) ]
pub fn sod(&mut self) -> _SODW {
_SODW { w: self }
}
@@ -210144,8 +204626,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." ] # [ inline ( always ) ]
pub fn data(&self) -> DATAR {
let bits = {
const MASK: u16 = 65535;
@@ -210167,8 +204648,7 @@ pub mod ssp0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." ] # [ inline ( always ) ]
pub fn data(&mut self) -> _DATAW {
_DATAW { w: self }
}
@@ -210304,8 +204784,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." ] # [ inline ( always ) ]
pub fn tfe(&self) -> TFER {
let bits = {
const MASK: bool = true;
@@ -210314,8 +204793,7 @@ pub mod ssp0 {
};
TFER { bits }
}
- #[doc = "Bit 1 - Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." ] # [ inline ( always ) ]
pub fn tnf(&self) -> TNFR {
let bits = {
const MASK: bool = true;
@@ -210324,8 +204802,7 @@ pub mod ssp0 {
};
TNFR { bits }
}
- #[doc = "Bit 2 - Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." ] # [ inline ( always ) ]
pub fn rne(&self) -> RNER {
let bits = {
const MASK: bool = true;
@@ -210334,8 +204811,7 @@ pub mod ssp0 {
};
RNER { bits }
}
- #[doc = "Bit 3 - Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." ] # [ inline ( always ) ]
pub fn rff(&self) -> RFFR {
let bits = {
const MASK: bool = true;
@@ -210344,8 +204820,7 @@ pub mod ssp0 {
};
RFFR { bits }
}
- #[doc = "Bit 4 - Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." ] # [ inline ( always ) ]
pub fn bsy(&self) -> BSYR {
let bits = {
const MASK: bool = true;
@@ -210438,8 +204913,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." ] # [ inline ( always ) ]
pub fn cpsdvsr(&self) -> CPSDVSRR {
let bits = {
const MASK: u8 = 255;
@@ -210461,8 +204935,7 @@ pub mod ssp0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." ] # [ inline ( always ) ]
pub fn cpsdvsr(&mut self) -> _CPSDVSRW {
_CPSDVSRW { w: self }
}
@@ -210700,8 +205173,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." ] # [ inline ( always ) ]
pub fn rorim(&self) -> RORIMR {
let bits = {
const MASK: bool = true;
@@ -210710,8 +205182,7 @@ pub mod ssp0 {
};
RORIMR { bits }
}
- #[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." ] # [ inline ( always ) ]
pub fn rtim(&self) -> RTIMR {
let bits = {
const MASK: bool = true;
@@ -210720,8 +205191,7 @@ pub mod ssp0 {
};
RTIMR { bits }
}
- #[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full." ] # [ inline ( always ) ]
pub fn rxim(&self) -> RXIMR {
let bits = {
const MASK: bool = true;
@@ -210730,8 +205200,7 @@ pub mod ssp0 {
};
RXIMR { bits }
}
- #[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." ] # [ inline ( always ) ]
pub fn txim(&self) -> TXIMR {
let bits = {
const MASK: bool = true;
@@ -210753,23 +205222,19 @@ pub mod ssp0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." ] # [ inline ( always ) ]
pub fn rorim(&mut self) -> _RORIMW {
_RORIMW { w: self }
}
- #[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." ] # [ inline ( always ) ]
pub fn rtim(&mut self) -> _RTIMW {
_RTIMW { w: self }
}
- #[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full." ] # [ inline ( always ) ]
pub fn rxim(&mut self) -> _RXIMW {
_RXIMW { w: self }
}
- #[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." ] # [ inline ( always ) ]
pub fn txim(&mut self) -> _TXIMW {
_TXIMW { w: self }
}
@@ -210884,8 +205349,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." ] # [ inline ( always ) ]
pub fn rorris(&self) -> RORRISR {
let bits = {
const MASK: bool = true;
@@ -210894,8 +205358,7 @@ pub mod ssp0 {
};
RORRISR { bits }
}
- #[doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])."]
- #[inline(always)]
+ # [ doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." ] # [ inline ( always ) ]
pub fn rtris(&self) -> RTRISR {
let bits = {
const MASK: bool = true;
@@ -211035,8 +205498,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." ] # [ inline ( always ) ]
pub fn rormis(&self) -> RORMISR {
let bits = {
const MASK: bool = true;
@@ -211045,8 +205507,7 @@ pub mod ssp0 {
};
RORMISR { bits }
}
- #[doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])."]
- #[inline(always)]
+ # [ doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." ] # [ inline ( always ) ]
pub fn rtmis(&self) -> RTMISR {
let bits = {
const MASK: bool = true;
@@ -211055,8 +205516,7 @@ pub mod ssp0 {
};
RTMISR { bits }
}
- #[doc = "Bit 2 - This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." ] # [ inline ( always ) ]
pub fn rxmis(&self) -> RXMISR {
let bits = {
const MASK: bool = true;
@@ -211065,8 +205525,7 @@ pub mod ssp0 {
};
RXMISR { bits }
}
- #[doc = "Bit 3 - This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." ] # [ inline ( always ) ]
pub fn txmis(&self) -> TXMISR {
let bits = {
const MASK: bool = true;
@@ -211157,13 +205616,11 @@ pub mod ssp0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." ] # [ inline ( always ) ]
pub fn roric(&mut self) -> _RORICW {
_RORICW { w: self }
}
- #[doc = "Bit 1 - Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." ] # [ inline ( always ) ]
pub fn rtic(&mut self) -> _RTICW {
_RTICW { w: self }
}
@@ -211313,8 +205770,7 @@ pub mod ssp0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." ] # [ inline ( always ) ]
pub fn rxdmae(&self) -> RXDMAER {
let bits = {
const MASK: bool = true;
@@ -211323,8 +205779,7 @@ pub mod ssp0 {
};
RXDMAER { bits }
}
- #[doc = "Bit 1 - Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" ] # [ inline ( always ) ]
pub fn txdmae(&self) -> TXDMAER {
let bits = {
const MASK: bool = true;
@@ -211346,13 +205801,11 @@ pub mod ssp0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." ] # [ inline ( always ) ]
pub fn rxdmae(&mut self) -> _RXDMAEW {
_RXDMAEW { w: self }
}
- #[doc = "Bit 1 - Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" ] # [ inline ( always ) ]
pub fn txdmae(&mut self) -> _TXDMAEW {
_TXDMAEW { w: self }
}
@@ -211388,48 +205841,12 @@ pub mod timer0 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
- pub ir: IR,
- #[doc = "0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
- pub tcr: TCR,
- #[doc = "0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
- pub tc: TC,
- #[doc = "0x0c - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
- pub pr: PR,
- #[doc = "0x10 - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
- pub pc: PC,
- #[doc = "0x14 - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
- pub mcr: MCR,
- #[doc = "0x18 - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
- pub mr0: MR,
- #[doc = "0x1c - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
- pub mr1: MR,
- #[doc = "0x20 - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
- pub mr2: MR,
- #[doc = "0x24 - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
- pub mr3: MR,
- #[doc = "0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
- pub ccr: CCR,
- #[doc = "0x2c - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
- pub cr0: CR,
- #[doc = "0x30 - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
- pub cr1: CR,
- #[doc = "0x34 - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
- pub cr2: CR,
- #[doc = "0x38 - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
- pub cr3: CR,
- #[doc = "0x3c - External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)."]
- pub emr: EMR,
- _reserved0: [u8; 48usize],
- #[doc = "0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
- pub ctcr: CTCR,
- }
- #[doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
+ pub struct RegisterBlock { # [ doc = "0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." ] pub ir : IR , # [ doc = "0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." ] pub tcr : TCR , # [ doc = "0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." ] pub tc : TC , # [ doc = "0x0c - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." ] pub pr : PR , # [ doc = "0x10 - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." ] pub pc : PC , # [ doc = "0x14 - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." ] pub mcr : MCR , # [ doc = "0x18 - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." ] pub mr0 : MR , # [ doc = "0x1c - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." ] pub mr1 : MR , # [ doc = "0x20 - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." ] pub mr2 : MR , # [ doc = "0x24 - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." ] pub mr3 : MR , # [ doc = "0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." ] pub ccr : CCR , # [ doc = "0x2c - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." ] pub cr0 : CR , # [ doc = "0x30 - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." ] pub cr1 : CR , # [ doc = "0x34 - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." ] pub cr2 : CR , # [ doc = "0x38 - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." ] pub cr3 : CR , # [ doc = "0x3c - External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." ] pub emr : EMR , _reserved0 : [ u8 ; 48usize ] , # [ doc = "0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." ] pub ctcr : CTCR , }
+ # [ doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." ]
pub struct IR {
register: VolatileCell<u32>,
}
- #[doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
+ # [ doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." ]
pub mod ir {
#[doc = r" Value read from the register"]
pub struct R {
@@ -211968,11 +206385,11 @@ pub mod timer0 {
}
}
}
- #[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
+ # [ doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." ]
pub struct TCR {
register: VolatileCell<u32>,
}
- #[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
+ # [ doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." ]
pub mod tcr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -212112,8 +206529,7 @@ pub mod timer0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." ] # [ inline ( always ) ]
pub fn cen(&self) -> CENR {
let bits = {
const MASK: bool = true;
@@ -212122,8 +206538,7 @@ pub mod timer0 {
};
CENR { bits }
}
- #[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero."]
- #[inline(always)]
+ # [ doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." ] # [ inline ( always ) ]
pub fn crst(&self) -> CRSTR {
let bits = {
const MASK: bool = true;
@@ -212145,23 +206560,21 @@ pub mod timer0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." ] # [ inline ( always ) ]
pub fn cen(&mut self) -> _CENW {
_CENW { w: self }
}
- #[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero."]
- #[inline(always)]
+ # [ doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." ] # [ inline ( always ) ]
pub fn crst(&mut self) -> _CRSTW {
_CRSTW { w: self }
}
}
}
- #[doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
+ # [ doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." ]
pub struct TC {
register: VolatileCell<u32>,
}
- #[doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
+ # [ doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." ]
pub mod tc {
#[doc = r" Value read from the register"]
pub struct R {
@@ -212269,11 +206682,11 @@ pub mod timer0 {
}
}
}
- #[doc = "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
+ # [ doc = "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." ]
pub struct PR {
register: VolatileCell<u32>,
}
- #[doc = "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
+ # [ doc = "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." ]
pub mod pr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -212381,11 +206794,11 @@ pub mod timer0 {
}
}
}
- #[doc = "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
+ # [ doc = "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." ]
pub struct PC {
register: VolatileCell<u32>,
}
- #[doc = "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
+ # [ doc = "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." ]
pub mod pc {
#[doc = r" Value read from the register"]
pub struct R {
@@ -212493,11 +206906,11 @@ pub mod timer0 {
}
}
}
- #[doc = "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
+ # [ doc = "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." ]
pub struct MCR {
register: VolatileCell<u32>,
}
- #[doc = "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
+ # [ doc = "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." ]
pub mod mcr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -212636,11 +207049,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `MR0S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MR0SR {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."]
- MATCH,
- }
+ pub enum MR0SR {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." ] MATCH}
impl MR0SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -212684,8 +207093,7 @@ pub mod timer0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR1IR {
#[doc = "Disabled. Interrupt is disabled."] DISABLED,
- #[doc = "Match. Interrupt is generated when MR1 matches the value in the TC."]
- MATCH,
+ #[doc = "Match. Interrupt is generated when MR1 matches the value in the TC."] MATCH,
}
impl MR1IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -212773,11 +207181,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `MR1S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MR1SR {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."]
- STOP,
- }
+ pub enum MR1SR {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." ] STOP}
impl MR1SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -212821,8 +207225,7 @@ pub mod timer0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR2IR {
#[doc = "Disabled. Interrupt is disabled"] DISABLED,
- #[doc = "Match. Interrupt is generated when MR2 matches the value in the TC."]
- MATCH,
+ #[doc = "Match. Interrupt is generated when MR2 matches the value in the TC."] MATCH,
}
impl MR2IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -212910,11 +207313,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `MR2S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MR2SR {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."]
- STOP,
- }
+ pub enum MR2SR {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." ] STOP}
impl MR2SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -213047,11 +207446,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `MR3S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MR3SR {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."]
- STOP,
- }
+ pub enum MR3SR {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." ] STOP}
impl MR3SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -213205,11 +207600,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `MR0S`"]
- pub enum MR0SW {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."]
- MATCH,
- }
+ pub enum MR0SW {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." ] MATCH}
impl MR0SW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -213238,8 +207629,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(MR0SW::DISABLED)
}
- #[doc = "Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC."]
- #[inline(always)]
+ # [ doc = "Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." ] # [ inline ( always ) ]
pub fn match_(self) -> &'a mut W {
self.variant(MR0SW::MATCH)
}
@@ -213264,8 +207654,7 @@ pub mod timer0 {
#[doc = "Values that can be written to the field `MR1I`"]
pub enum MR1IW {
#[doc = "Disabled. Interrupt is disabled."] DISABLED,
- #[doc = "Match. Interrupt is generated when MR1 matches the value in the TC."]
- MATCH,
+ #[doc = "Match. Interrupt is generated when MR1 matches the value in the TC."] MATCH,
}
impl MR1IW {
#[allow(missing_docs)]
@@ -213375,11 +207764,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `MR1S`"]
- pub enum MR1SW {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."]
- STOP,
- }
+ pub enum MR1SW {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." ] STOP}
impl MR1SW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -213408,8 +207793,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(MR1SW::DISABLED)
}
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC."]
- #[inline(always)]
+ # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." ] # [ inline ( always ) ]
pub fn stop(self) -> &'a mut W {
self.variant(MR1SW::STOP)
}
@@ -213434,8 +207818,7 @@ pub mod timer0 {
#[doc = "Values that can be written to the field `MR2I`"]
pub enum MR2IW {
#[doc = "Disabled. Interrupt is disabled"] DISABLED,
- #[doc = "Match. Interrupt is generated when MR2 matches the value in the TC."]
- MATCH,
+ #[doc = "Match. Interrupt is generated when MR2 matches the value in the TC."] MATCH,
}
impl MR2IW {
#[allow(missing_docs)]
@@ -213545,11 +207928,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `MR2S`"]
- pub enum MR2SW {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."]
- STOP,
- }
+ pub enum MR2SW {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." ] STOP}
impl MR2SW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -213578,8 +207957,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(MR2SW::DISABLED)
}
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC."]
- #[inline(always)]
+ # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." ] # [ inline ( always ) ]
pub fn stop(self) -> &'a mut W {
self.variant(MR2SW::STOP)
}
@@ -213715,11 +208093,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `MR3S`"]
- pub enum MR3SW {
- #[doc = "Disabled. Feature disabled."] DISABLED,
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."]
- STOP,
- }
+ pub enum MR3SW {# [ doc = "Disabled. Feature disabled." ] DISABLED , # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." ] STOP}
impl MR3SW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -213748,8 +208122,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(MR3SW::DISABLED)
}
- #[doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC."]
- #[inline(always)]
+ # [ doc = "Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." ] # [ inline ( always ) ]
pub fn stop(self) -> &'a mut W {
self.variant(MR3SW::STOP)
}
@@ -213960,11 +208333,11 @@ pub mod timer0 {
}
}
}
- #[doc = "Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
+ # [ doc = "Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." ]
pub struct MR {
register: VolatileCell<u32>,
}
- #[doc = "Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
+ # [ doc = "Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." ]
pub mod mr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -214072,11 +208445,11 @@ pub mod timer0 {
}
}
}
- #[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
+ # [ doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." ]
pub struct CCR {
register: VolatileCell<u32>,
}
- #[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
+ # [ doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." ]
pub mod ccr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -214124,11 +208497,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP0RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP0RER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP0RER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP0RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214170,11 +208539,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP0FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP0FER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP0FER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP0FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214218,8 +208583,7 @@ pub mod timer0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP0IR {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR0 load due to a CAPn.0 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR0 load due to a CAPn.0 event will generate an interrupt."] LOAD,
}
impl CAP0IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -214262,11 +208626,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP1RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP1RER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP1RER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP1RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214308,11 +208668,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP1FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP1FER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP1FER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP1FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214356,8 +208712,7 @@ pub mod timer0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP1IR {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR1 load due to a CAPn.1 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR1 load due to a CAPn.1 event will generate an interrupt."] LOAD,
}
impl CAP1IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -214400,11 +208755,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP2RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP2RER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP2RER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP2RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214446,11 +208797,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP2FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP2FER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP2FER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP2FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214494,8 +208841,7 @@ pub mod timer0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP2IR {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR2 load due to a CAPn.2 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR2 load due to a CAPn.2 event will generate an interrupt."] LOAD,
}
impl CAP2IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -214538,11 +208884,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP3RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP3RER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP3RER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP3RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214584,11 +208926,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CAP3FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CAP3FER {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP3FER {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP3FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -214632,8 +208970,7 @@ pub mod timer0 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP3IR {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR3 load due to a CAPn.3 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR3 load due to a CAPn.3 event will generate an interrupt."] LOAD,
}
impl CAP3IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -214675,11 +209012,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP0RE`"]
- pub enum CAP0REW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP0REW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP0REW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -214708,8 +209041,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP0REW::DISABLED)
}
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn low_to_high(self) -> &'a mut W {
self.variant(CAP0REW::LOW_TO_HIGH)
}
@@ -214732,11 +209064,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP0FE`"]
- pub enum CAP0FEW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP0FEW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP0FEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -214765,8 +209093,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP0FEW::DISABLED)
}
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn high_to_low(self) -> &'a mut W {
self.variant(CAP0FEW::HIGH_TO_LOW)
}
@@ -214791,8 +209118,7 @@ pub mod timer0 {
#[doc = "Values that can be written to the field `CAP0I`"]
pub enum CAP0IW {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR0 load due to a CAPn.0 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR0 load due to a CAPn.0 event will generate an interrupt."] LOAD,
}
impl CAP0IW {
#[allow(missing_docs)]
@@ -214846,11 +209172,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP1RE`"]
- pub enum CAP1REW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP1REW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP1REW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -214879,8 +209201,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP1REW::DISABLED)
}
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn low_to_high(self) -> &'a mut W {
self.variant(CAP1REW::LOW_TO_HIGH)
}
@@ -214903,11 +209224,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP1FE`"]
- pub enum CAP1FEW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP1FEW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP1FEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -214936,8 +209253,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP1FEW::DISABLED)
}
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn high_to_low(self) -> &'a mut W {
self.variant(CAP1FEW::HIGH_TO_LOW)
}
@@ -214962,8 +209278,7 @@ pub mod timer0 {
#[doc = "Values that can be written to the field `CAP1I`"]
pub enum CAP1IW {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR1 load due to a CAPn.1 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR1 load due to a CAPn.1 event will generate an interrupt."] LOAD,
}
impl CAP1IW {
#[allow(missing_docs)]
@@ -215017,11 +209332,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP2RE`"]
- pub enum CAP2REW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP2REW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP2REW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -215050,8 +209361,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP2REW::DISABLED)
}
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn low_to_high(self) -> &'a mut W {
self.variant(CAP2REW::LOW_TO_HIGH)
}
@@ -215074,11 +209384,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP2FE`"]
- pub enum CAP2FEW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP2FEW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP2FEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -215107,8 +209413,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP2FEW::DISABLED)
}
- #[doc = "High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn high_to_low(self) -> &'a mut W {
self.variant(CAP2FEW::HIGH_TO_LOW)
}
@@ -215133,8 +209438,7 @@ pub mod timer0 {
#[doc = "Values that can be written to the field `CAP2I`"]
pub enum CAP2IW {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR2 load due to a CAPn.2 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR2 load due to a CAPn.2 event will generate an interrupt."] LOAD,
}
impl CAP2IW {
#[allow(missing_docs)]
@@ -215188,11 +209492,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP3RE`"]
- pub enum CAP3REW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC."]
- LOW_TO_HIGH,
- }
+ pub enum CAP3REW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." ] LOW_TO_HIGH}
impl CAP3REW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -215221,8 +209521,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP3REW::DISABLED)
}
- #[doc = "Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn low_to_high(self) -> &'a mut W {
self.variant(CAP3REW::LOW_TO_HIGH)
}
@@ -215245,11 +209544,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CAP3FE`"]
- pub enum CAP3FEW {
- #[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC."]
- HIGH_TO_LOW,
- }
+ pub enum CAP3FEW {# [ doc = "Disabled. This feature is disabled." ] DISABLED , # [ doc = "A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." ] HIGH_TO_LOW}
impl CAP3FEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -215278,8 +209573,7 @@ pub mod timer0 {
pub fn disabled(self) -> &'a mut W {
self.variant(CAP3FEW::DISABLED)
}
- #[doc = "A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC."]
- #[inline(always)]
+ # [ doc = "A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." ] # [ inline ( always ) ]
pub fn high_to_low(self) -> &'a mut W {
self.variant(CAP3FEW::HIGH_TO_LOW)
}
@@ -215304,8 +209598,7 @@ pub mod timer0 {
#[doc = "Values that can be written to the field `CAP3I`"]
pub enum CAP3IW {
#[doc = "Disabled. This feature is disabled."] DISABLED,
- #[doc = "Load. A CR3 load due to a CAPn.3 event will generate an interrupt."]
- LOAD,
+ #[doc = "Load. A CR3 load due to a CAPn.3 event will generate an interrupt."] LOAD,
}
impl CAP3IW {
#[allow(missing_docs)]
@@ -215547,11 +209840,11 @@ pub mod timer0 {
}
}
}
- #[doc = "Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
+ # [ doc = "Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." ]
pub struct CR {
register: VolatileCell<u32>,
}
- #[doc = "Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
+ # [ doc = "Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." ]
pub mod cr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -215595,11 +209888,11 @@ pub mod timer0 {
}
}
}
- #[doc = "External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)."]
+ # [ doc = "External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." ]
pub struct EMR {
register: VolatileCell<u32>,
}
- #[doc = "External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)."]
+ # [ doc = "External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." ]
pub mod emr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -215731,15 +210024,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `EMC0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EMC0R {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC0R {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC0R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -215786,15 +210071,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `EMC1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EMC1R {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC1R {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC1R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -215841,15 +210118,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `EMC2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EMC2R {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC2R {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC2R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -215896,15 +210165,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `EMC3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EMC3R {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC3R {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC3R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -216042,15 +210303,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `EMC0`"]
- pub enum EMC0W {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC0W {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC0W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -216081,13 +210334,11 @@ pub mod timer0 {
pub fn nop(self) -> &'a mut W {
self.variant(EMC0W::NOP)
}
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- #[inline(always)]
+ # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(EMC0W::CLEAR)
}
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- #[inline(always)]
+ # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] # [ inline ( always ) ]
pub fn set(self) -> &'a mut W {
self.variant(EMC0W::SET)
}
@@ -216107,15 +210358,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `EMC1`"]
- pub enum EMC1W {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC1W {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC1W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -216146,13 +210389,11 @@ pub mod timer0 {
pub fn nop(self) -> &'a mut W {
self.variant(EMC1W::NOP)
}
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- #[inline(always)]
+ # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(EMC1W::CLEAR)
}
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- #[inline(always)]
+ # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] # [ inline ( always ) ]
pub fn set(self) -> &'a mut W {
self.variant(EMC1W::SET)
}
@@ -216172,15 +210413,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `EMC2`"]
- pub enum EMC2W {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC2W {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC2W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -216211,13 +210444,11 @@ pub mod timer0 {
pub fn nop(self) -> &'a mut W {
self.variant(EMC2W::NOP)
}
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- #[inline(always)]
+ # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(EMC2W::CLEAR)
}
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- #[inline(always)]
+ # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] # [ inline ( always ) ]
pub fn set(self) -> &'a mut W {
self.variant(EMC2W::SET)
}
@@ -216237,15 +210468,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `EMC3`"]
- pub enum EMC3W {
- #[doc = "Do Nothing."] NOP,
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- CLEAR,
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- SET,
- #[doc = "Toggle. Toggle the corresponding External Match bit/output."]
- TOGGLE,
- }
+ pub enum EMC3W {# [ doc = "Do Nothing." ] NOP , # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] CLEAR , # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] SET , # [ doc = "Toggle. Toggle the corresponding External Match bit/output." ] TOGGLE}
impl EMC3W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -216276,13 +210499,11 @@ pub mod timer0 {
pub fn nop(self) -> &'a mut W {
self.variant(EMC3W::NOP)
}
- #[doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
- #[inline(always)]
+ # [ doc = "Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." ] # [ inline ( always ) ]
pub fn clear(self) -> &'a mut W {
self.variant(EMC3W::CLEAR)
}
- #[doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
- #[inline(always)]
+ # [ doc = "Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." ] # [ inline ( always ) ]
pub fn set(self) -> &'a mut W {
self.variant(EMC3W::SET)
}
@@ -216307,8 +210528,7 @@ pub mod timer0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em0(&self) -> EM0R {
let bits = {
const MASK: bool = true;
@@ -216317,8 +210537,7 @@ pub mod timer0 {
};
EM0R { bits }
}
- #[doc = "Bit 1 - External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em1(&self) -> EM1R {
let bits = {
const MASK: bool = true;
@@ -216327,8 +210546,7 @@ pub mod timer0 {
};
EM1R { bits }
}
- #[doc = "Bit 2 - External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em2(&self) -> EM2R {
let bits = {
const MASK: bool = true;
@@ -216337,8 +210555,7 @@ pub mod timer0 {
};
EM2R { bits }
}
- #[doc = "Bit 3 - External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em3(&self) -> EM3R {
let bits = {
const MASK: bool = true;
@@ -216347,8 +210564,7 @@ pub mod timer0 {
};
EM3R { bits }
}
- #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0." ] # [ inline ( always ) ]
pub fn emc0(&self) -> EMC0R {
EMC0R::_from({
const MASK: u8 = 3;
@@ -216356,8 +210572,7 @@ pub mod timer0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1." ] # [ inline ( always ) ]
pub fn emc1(&self) -> EMC1R {
EMC1R::_from({
const MASK: u8 = 3;
@@ -216365,8 +210580,7 @@ pub mod timer0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2." ] # [ inline ( always ) ]
pub fn emc2(&self) -> EMC2R {
EMC2R::_from({
const MASK: u8 = 3;
@@ -216374,8 +210588,7 @@ pub mod timer0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3." ] # [ inline ( always ) ]
pub fn emc3(&self) -> EMC3R {
EMC3R::_from({
const MASK: u8 = 3;
@@ -216396,53 +210609,45 @@ pub mod timer0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em0(&mut self) -> _EM0W {
_EM0W { w: self }
}
- #[doc = "Bit 1 - External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em1(&mut self) -> _EM1W {
_EM1W { w: self }
}
- #[doc = "Bit 2 - External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em2(&mut self) -> _EM2W {
_EM2W { w: self }
}
- #[doc = "Bit 3 - External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." ] # [ inline ( always ) ]
pub fn em3(&mut self) -> _EM3W {
_EM3W { w: self }
}
- #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0." ] # [ inline ( always ) ]
pub fn emc0(&mut self) -> _EMC0W {
_EMC0W { w: self }
}
- #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1." ] # [ inline ( always ) ]
pub fn emc1(&mut self) -> _EMC1W {
_EMC1W { w: self }
}
- #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
- #[inline(always)]
+ # [ doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2." ] # [ inline ( always ) ]
pub fn emc2(&mut self) -> _EMC2W {
_EMC2W { w: self }
}
- #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
- #[inline(always)]
+ # [ doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3." ] # [ inline ( always ) ]
pub fn emc3(&mut self) -> _EMC3W {
_EMC3W { w: self }
}
}
}
- #[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
+ # [ doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." ]
pub struct CTCR {
register: VolatileCell<u32>,
}
- #[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
+ # [ doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." ]
pub mod ctcr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -216490,15 +210695,7 @@ pub mod timer0 {
}
#[doc = "Possible values of the field `CTMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CTMODER {
- #[doc = "Timer Mode. Counts every rising PCLK edge"] TIMER_MODE,
- #[doc = "Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2."]
- COUNTER_MODE_RISING,
- #[doc = "Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2."]
- COUNTER_MODE_FALLING,
- #[doc = "Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2."]
- COUNTER_MODE_EDGES,
- }
+ pub enum CTMODER {# [ doc = "Timer Mode. Counts every rising PCLK edge" ] TIMER_MODE , # [ doc = "Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." ] COUNTER_MODE_RISING , # [ doc = "Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." ] COUNTER_MODE_FALLING , # [ doc = "Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." ] COUNTER_MODE_EDGES}
impl CTMODER {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -216596,15 +210793,7 @@ pub mod timer0 {
}
}
#[doc = "Values that can be written to the field `CTMODE`"]
- pub enum CTMODEW {
- #[doc = "Timer Mode. Counts every rising PCLK edge"] TIMER_MODE,
- #[doc = "Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2."]
- COUNTER_MODE_RISING,
- #[doc = "Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2."]
- COUNTER_MODE_FALLING,
- #[doc = "Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2."]
- COUNTER_MODE_EDGES,
- }
+ pub enum CTMODEW {# [ doc = "Timer Mode. Counts every rising PCLK edge" ] TIMER_MODE , # [ doc = "Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." ] COUNTER_MODE_RISING , # [ doc = "Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." ] COUNTER_MODE_FALLING , # [ doc = "Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." ] COUNTER_MODE_EDGES}
impl CTMODEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -216635,18 +210824,15 @@ pub mod timer0 {
pub fn timer_mode(self) -> &'a mut W {
self.variant(CTMODEW::TIMER_MODE)
}
- #[doc = "Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2."]
- #[inline(always)]
+ # [ doc = "Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." ] # [ inline ( always ) ]
pub fn counter_mode_rising(self) -> &'a mut W {
self.variant(CTMODEW::COUNTER_MODE_RISING)
}
- #[doc = "Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2."]
- #[inline(always)]
+ # [ doc = "Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." ] # [ inline ( always ) ]
pub fn counter_mode_falling(self) -> &'a mut W {
self.variant(CTMODEW::COUNTER_MODE_FALLING)
}
- #[doc = "Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2."]
- #[inline(always)]
+ # [ doc = "Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." ] # [ inline ( always ) ]
pub fn counter_mode_edges(self) -> &'a mut W {
self.variant(CTMODEW::COUNTER_MODE_EDGES)
}
@@ -216728,8 +210914,7 @@ pub mod timer0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register." ] # [ inline ( always ) ]
pub fn ctmode(&self) -> CTMODER {
CTMODER::_from({
const MASK: u8 = 3;
@@ -216737,8 +210922,7 @@ pub mod timer0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer." ] # [ inline ( always ) ]
pub fn cinsel(&self) -> CINSELR {
CINSELR::_from({
const MASK: u8 = 3;
@@ -216759,13 +210943,11 @@ pub mod timer0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register." ] # [ inline ( always ) ]
pub fn ctmode(&mut self) -> _CTMODEW {
_CTMODEW { w: self }
}
- #[doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer." ] # [ inline ( always ) ]
pub fn cinsel(&mut self) -> _CINSELW {
_CINSELW { w: self }
}
@@ -216825,7 +211007,217 @@ pub mod scu {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock { # [ doc = "0x00 - Pin configuration register for pins P0" ] pub sfsp0_0 : SFSP0_ , # [ doc = "0x04 - Pin configuration register for pins P0" ] pub sfsp0_1 : SFSP0_ , _reserved0 : [ u8 ; 120usize ] , # [ doc = "0x80 - Pin configuration register for pins P1" ] pub sfsp1_0 : SFSP1_ , # [ doc = "0x84 - Pin configuration register for pins P1" ] pub sfsp1_1 : SFSP1_ , # [ doc = "0x88 - Pin configuration register for pins P1" ] pub sfsp1_2 : SFSP1_ , # [ doc = "0x8c - Pin configuration register for pins P1" ] pub sfsp1_3 : SFSP1_ , # [ doc = "0x90 - Pin configuration register for pins P1" ] pub sfsp1_4 : SFSP1_ , # [ doc = "0x94 - Pin configuration register for pins P1" ] pub sfsp1_5 : SFSP1_ , # [ doc = "0x98 - Pin configuration register for pins P1" ] pub sfsp1_6 : SFSP1_ , # [ doc = "0x9c - Pin configuration register for pins P1" ] pub sfsp1_7 : SFSP1_ , # [ doc = "0xa0 - Pin configuration register for pins P1" ] pub sfsp1_8 : SFSP1_ , # [ doc = "0xa4 - Pin configuration register for pins P1" ] pub sfsp1_9 : SFSP1_ , # [ doc = "0xa8 - Pin configuration register for pins P1" ] pub sfsp1_10 : SFSP1_ , # [ doc = "0xac - Pin configuration register for pins P1" ] pub sfsp1_11 : SFSP1_ , # [ doc = "0xb0 - Pin configuration register for pins P1" ] pub sfsp1_12 : SFSP1_ , # [ doc = "0xb4 - Pin configuration register for pins P1" ] pub sfsp1_13 : SFSP1_ , # [ doc = "0xb8 - Pin configuration register for pins P1" ] pub sfsp1_14 : SFSP1_ , # [ doc = "0xbc - Pin configuration register for pins P1" ] pub sfsp1_15 : SFSP1_ , # [ doc = "0xc0 - Pin configuration register for pins P1" ] pub sfsp1_16 : SFSP1_ , # [ doc = "0xc4 - Pin configuration register for pins P1_17" ] pub sfsp1_17 : SFSP1_17 , # [ doc = "0xc8 - Pin configuration register for pins P1" ] pub sfsp1_18 : SFSP1_ , # [ doc = "0xcc - Pin configuration register for pins P1" ] pub sfsp1_19 : SFSP1_ , # [ doc = "0xd0 - Pin configuration register for pins P1" ] pub sfsp1_20 : SFSP1_ , _reserved1 : [ u8 ; 44usize ] , # [ doc = "0x100 - Pin configuration register for pins P2" ] pub sfsp2_0 : SFSP2_ , # [ doc = "0x104 - Pin configuration register for pins P2" ] pub sfsp2_1 : SFSP2_ , # [ doc = "0x108 - Pin configuration register for pins P2" ] pub sfsp2_2 : SFSP2_ , # [ doc = "0x10c - Pin configuration register for pins P2" ] pub sfsp2_3 : SFSP2_ , # [ doc = "0x110 - Pin configuration register for pins P2" ] pub sfsp2_4 : SFSP2_ , # [ doc = "0x114 - Pin configuration register for pins P2" ] pub sfsp2_5 : SFSP2_ , # [ doc = "0x118 - Pin configuration register for pins P2" ] pub sfsp2_6 : SFSP2_ , # [ doc = "0x11c - Pin configuration register for pins P2" ] pub sfsp2_7 : SFSP2_ , # [ doc = "0x120 - Pin configuration register for pins P2" ] pub sfsp2_8 : SFSP2_ , # [ doc = "0x124 - Pin configuration register for pins P2" ] pub sfsp2_9 : SFSP2_ , # [ doc = "0x128 - Pin configuration register for pins P2" ] pub sfsp2_10 : SFSP2_ , # [ doc = "0x12c - Pin configuration register for pins P2" ] pub sfsp2_11 : SFSP2_ , # [ doc = "0x130 - Pin configuration register for pins P2" ] pub sfsp2_12 : SFSP2_ , _reserved2 : [ u8 ; 76usize ] , # [ doc = "0x180 - Pin configuration register for pins P3" ] pub sfsp3_0 : SFSP3_ , # [ doc = "0x184 - Pin configuration register for pins P3" ] pub sfsp3_1 : SFSP3_ , # [ doc = "0x188 - Pin configuration register for pins P3" ] pub sfsp3_2 : SFSP3_ , # [ doc = "0x18c - Pin configuration register for pins P3" ] pub sfsp3_3 : SFSP3_3 , # [ doc = "0x190 - Pin configuration register for pins P3" ] pub sfsp3_4 : SFSP3_ , # [ doc = "0x194 - Pin configuration register for pins P3" ] pub sfsp3_5 : SFSP3_ , # [ doc = "0x198 - Pin configuration register for pins P3" ] pub sfsp3_6 : SFSP3_ , # [ doc = "0x19c - Pin configuration register for pins P3" ] pub sfsp3_7 : SFSP3_ , # [ doc = "0x1a0 - Pin configuration register for pins P3" ] pub sfsp3_8 : SFSP3_ , _reserved3 : [ u8 ; 92usize ] , # [ doc = "0x200 - Pin configuration register for pins P4" ] pub sfsp4_0 : SFSP4_ , # [ doc = "0x204 - Pin configuration register for pins P4" ] pub sfsp4_1 : SFSP4_ , # [ doc = "0x208 - Pin configuration register for pins P4" ] pub sfsp4_2 : SFSP4_ , # [ doc = "0x20c - Pin configuration register for pins P4" ] pub sfsp4_3 : SFSP4_ , # [ doc = "0x210 - Pin configuration register for pins P4" ] pub sfsp4_4 : SFSP4_ , # [ doc = "0x214 - Pin configuration register for pins P4" ] pub sfsp4_5 : SFSP4_ , # [ doc = "0x218 - Pin configuration register for pins P4" ] pub sfsp4_6 : SFSP4_ , # [ doc = "0x21c - Pin configuration register for pins P4" ] pub sfsp4_7 : SFSP4_ , # [ doc = "0x220 - Pin configuration register for pins P4" ] pub sfsp4_8 : SFSP4_ , # [ doc = "0x224 - Pin configuration register for pins P4" ] pub sfsp4_9 : SFSP4_ , # [ doc = "0x228 - Pin configuration register for pins P4" ] pub sfsp4_10 : SFSP4_ , _reserved4 : [ u8 ; 84usize ] , # [ doc = "0x280 - Pin configuration register for pins P5" ] pub sfsp5_0 : SFSP5_ , # [ doc = "0x284 - Pin configuration register for pins P5" ] pub sfsp5_1 : SFSP5_ , # [ doc = "0x288 - Pin configuration register for pins P5" ] pub sfsp5_2 : SFSP5_ , # [ doc = "0x28c - Pin configuration register for pins P5" ] pub sfsp5_3 : SFSP5_ , # [ doc = "0x290 - Pin configuration register for pins P5" ] pub sfsp5_4 : SFSP5_ , # [ doc = "0x294 - Pin configuration register for pins P5" ] pub sfsp5_5 : SFSP5_ , # [ doc = "0x298 - Pin configuration register for pins P5" ] pub sfsp5_6 : SFSP5_ , # [ doc = "0x29c - Pin configuration register for pins P5" ] pub sfsp5_7 : SFSP5_ , _reserved5 : [ u8 ; 96usize ] , # [ doc = "0x300 - Pin configuration register for pins P6" ] pub sfsp6_0 : SFSP6_ , # [ doc = "0x304 - Pin configuration register for pins P6" ] pub sfsp6_1 : SFSP6_ , # [ doc = "0x308 - Pin configuration register for pins P6" ] pub sfsp6_2 : SFSP6_ , # [ doc = "0x30c - Pin configuration register for pins P6" ] pub sfsp6_3 : SFSP6_ , # [ doc = "0x310 - Pin configuration register for pins P6" ] pub sfsp6_4 : SFSP6_ , # [ doc = "0x314 - Pin configuration register for pins P6" ] pub sfsp6_5 : SFSP6_ , # [ doc = "0x318 - Pin configuration register for pins P6" ] pub sfsp6_6 : SFSP6_ , # [ doc = "0x31c - Pin configuration register for pins P6" ] pub sfsp6_7 : SFSP6_ , # [ doc = "0x320 - Pin configuration register for pins P6" ] pub sfsp6_8 : SFSP6_ , # [ doc = "0x324 - Pin configuration register for pins P6" ] pub sfsp6_9 : SFSP6_ , # [ doc = "0x328 - Pin configuration register for pins P6" ] pub sfsp6_10 : SFSP6_ , # [ doc = "0x32c - Pin configuration register for pins P6" ] pub sfsp6_11 : SFSP6_ , # [ doc = "0x330 - Pin configuration register for pins P6" ] pub sfsp6_12 : SFSP6_ , _reserved6 : [ u8 ; 76usize ] , # [ doc = "0x380 - Pin configuration register for pins P7" ] pub sfsp7_0 : SFSP7_ , # [ doc = "0x384 - Pin configuration register for pins P7" ] pub sfsp7_1 : SFSP7_ , # [ doc = "0x388 - Pin configuration register for pins P7" ] pub sfsp7_2 : SFSP7_ , # [ doc = "0x38c - Pin configuration register for pins P7" ] pub sfsp7_3 : SFSP7_ , # [ doc = "0x390 - Pin configuration register for pins P7" ] pub sfsp7_4 : SFSP7_ , # [ doc = "0x394 - Pin configuration register for pins P7" ] pub sfsp7_5 : SFSP7_ , # [ doc = "0x398 - Pin configuration register for pins P7" ] pub sfsp7_6 : SFSP7_ , # [ doc = "0x39c - Pin configuration register for pins P7" ] pub sfsp7_7 : SFSP7_ , _reserved7 : [ u8 ; 96usize ] , # [ doc = "0x400 - Pin configuration register for pins P8" ] pub sfsp8_0 : SFSP8_ , # [ doc = "0x404 - Pin configuration register for pins P8" ] pub sfsp8_1 : SFSP8_ , # [ doc = "0x408 - Pin configuration register for pins P8" ] pub sfsp8_2 : SFSP8_ , # [ doc = "0x40c - Pin configuration register for pins P8" ] pub sfsp8_3 : SFSP8_ , # [ doc = "0x410 - Pin configuration register for pins P8" ] pub sfsp8_4 : SFSP8_ , # [ doc = "0x414 - Pin configuration register for pins P8" ] pub sfsp8_5 : SFSP8_ , # [ doc = "0x418 - Pin configuration register for pins P8" ] pub sfsp8_6 : SFSP8_ , # [ doc = "0x41c - Pin configuration register for pins P8" ] pub sfsp8_7 : SFSP8_ , # [ doc = "0x420 - Pin configuration register for pins P8" ] pub sfsp8_8 : SFSP8_ , _reserved8 : [ u8 ; 92usize ] , # [ doc = "0x480 - Pin configuration register for pins P9" ] pub sfsp9_0 : SFSP9_ , # [ doc = "0x484 - Pin configuration register for pins P9" ] pub sfsp9_1 : SFSP9_ , # [ doc = "0x488 - Pin configuration register for pins P9" ] pub sfsp9_2 : SFSP9_ , # [ doc = "0x48c - Pin configuration register for pins P9" ] pub sfsp9_3 : SFSP9_ , # [ doc = "0x490 - Pin configuration register for pins P9" ] pub sfsp9_4 : SFSP9_ , # [ doc = "0x494 - Pin configuration register for pins P9" ] pub sfsp9_5 : SFSP9_ , # [ doc = "0x498 - Pin configuration register for pins P9" ] pub sfsp9_6 : SFSP9_ , _reserved9 : [ u8 ; 100usize ] , # [ doc = "0x500 - Pin configuration register for pins PA" ] pub sfspa_0 : SFSPA_0 , # [ doc = "0x504 - Pin configuration register for pins PA" ] pub sfspa_1 : SFSPA_ , # [ doc = "0x508 - Pin configuration register for pins PA" ] pub sfspa_2 : SFSPA_ , # [ doc = "0x50c - Pin configuration register for pins PA" ] pub sfspa_3 : SFSPA_ , # [ doc = "0x510 - Pin configuration register for pins PA" ] pub sfspa_4 : SFSPA_4 , _reserved10 : [ u8 ; 108usize ] , # [ doc = "0x580 - Pin configuration register for pins PB" ] pub sfspb_0 : SFSPB_ , # [ doc = "0x584 - Pin configuration register for pins PB" ] pub sfspb_1 : SFSPB_ , # [ doc = "0x588 - Pin configuration register for pins PB" ] pub sfspb_2 : SFSPB_ , # [ doc = "0x58c - Pin configuration register for pins PB" ] pub sfspb_3 : SFSPB_ , # [ doc = "0x590 - Pin configuration register for pins PB" ] pub sfspb_4 : SFSPB_ , # [ doc = "0x594 - Pin configuration register for pins PB" ] pub sfspb_5 : SFSPB_ , # [ doc = "0x598 - Pin configuration register for pins PB" ] pub sfspb_6 : SFSPB_ , _reserved11 : [ u8 ; 100usize ] , # [ doc = "0x600 - Pin configuration register for pins PC" ] pub sfspc_0 : SFSPC_ , # [ doc = "0x604 - Pin configuration register for pins PC" ] pub sfspc_1 : SFSPC_ , # [ doc = "0x608 - Pin configuration register for pins PC" ] pub sfspc_2 : SFSPC_ , # [ doc = "0x60c - Pin configuration register for pins PC" ] pub sfspc_3 : SFSPC_ , # [ doc = "0x610 - Pin configuration register for pins PC" ] pub sfspc_4 : SFSPC_ , # [ doc = "0x614 - Pin configuration register for pins PC" ] pub sfspc_5 : SFSPC_ , # [ doc = "0x618 - Pin configuration register for pins PC" ] pub sfspc_6 : SFSPC_ , # [ doc = "0x61c - Pin configuration register for pins PC" ] pub sfspc_7 : SFSPC_ , # [ doc = "0x620 - Pin configuration register for pins PC" ] pub sfspc_8 : SFSPC_ , # [ doc = "0x624 - Pin configuration register for pins PC" ] pub sfspc_9 : SFSPC_ , # [ doc = "0x628 - Pin configuration register for pins PC" ] pub sfspc_10 : SFSPC_ , # [ doc = "0x62c - Pin configuration register for pins PC" ] pub sfspc_11 : SFSPC_ , # [ doc = "0x630 - Pin configuration register for pins PC" ] pub sfspc_12 : SFSPC_ , # [ doc = "0x634 - Pin configuration register for pins PC" ] pub sfspc_13 : SFSPC_ , # [ doc = "0x638 - Pin configuration register for pins PC" ] pub sfspc_14 : SFSPC_ , _reserved12 : [ u8 ; 68usize ] , # [ doc = "0x680 - Pin configuration register for pins PD" ] pub sfspd_0 : SFSPD_ , # [ doc = "0x684 - Pin configuration register for pins PD" ] pub sfspd_1 : SFSPD_ , # [ doc = "0x688 - Pin configuration register for pins PD" ] pub sfspd_2 : SFSPD_ , # [ doc = "0x68c - Pin configuration register for pins PD" ] pub sfspd_3 : SFSPD_ , # [ doc = "0x690 - Pin configuration register for pins PD" ] pub sfspd_4 : SFSPD_ , # [ doc = "0x694 - Pin configuration register for pins PD" ] pub sfspd_5 : SFSPD_ , # [ doc = "0x698 - Pin configuration register for pins PD" ] pub sfspd_6 : SFSPD_ , # [ doc = "0x69c - Pin configuration register for pins PD" ] pub sfspd_7 : SFSPD_ , # [ doc = "0x6a0 - Pin configuration register for pins PD" ] pub sfspd_8 : SFSPD_ , # [ doc = "0x6a4 - Pin configuration register for pins PD" ] pub sfspd_9 : SFSPD_ , # [ doc = "0x6a8 - Pin configuration register for pins PD" ] pub sfspd_10 : SFSPD_ , # [ doc = "0x6ac - Pin configuration register for pins PD" ] pub sfspd_11 : SFSPD_ , # [ doc = "0x6b0 - Pin configuration register for pins PD" ] pub sfspd_12 : SFSPD_ , # [ doc = "0x6b4 - Pin configuration register for pins PD" ] pub sfspd_13 : SFSPD_ , # [ doc = "0x6b8 - Pin configuration register for pins PD" ] pub sfspd_14 : SFSPD_ , # [ doc = "0x6bc - Pin configuration register for pins PD" ] pub sfspd_15 : SFSPD_ , # [ doc = "0x6c0 - Pin configuration register for pins PD" ] pub sfspd_16 : SFSPD_ , _reserved13 : [ u8 ; 60usize ] , # [ doc = "0x700 - Pin configuration register for pins PE" ] pub sfspe_0 : SFSPE_ , # [ doc = "0x704 - Pin configuration register for pins PE" ] pub sfspe_1 : SFSPE_ , # [ doc = "0x708 - Pin configuration register for pins PE" ] pub sfspe_2 : SFSPE_ , # [ doc = "0x70c - Pin configuration register for pins PE" ] pub sfspe_3 : SFSPE_ , # [ doc = "0x710 - Pin configuration register for pins PE" ] pub sfspe_4 : SFSPE_ , # [ doc = "0x714 - Pin configuration register for pins PE" ] pub sfspe_5 : SFSPE_ , # [ doc = "0x718 - Pin configuration register for pins PE" ] pub sfspe_6 : SFSPE_ , # [ doc = "0x71c - Pin configuration register for pins PE" ] pub sfspe_7 : SFSPE_ , # [ doc = "0x720 - Pin configuration register for pins PE" ] pub sfspe_8 : SFSPE_ , # [ doc = "0x724 - Pin configuration register for pins PE" ] pub sfspe_9 : SFSPE_ , # [ doc = "0x728 - Pin configuration register for pins PE" ] pub sfspe_10 : SFSPE_ , # [ doc = "0x72c - Pin configuration register for pins PE" ] pub sfspe_11 : SFSPE_ , # [ doc = "0x730 - Pin configuration register for pins PE" ] pub sfspe_12 : SFSPE_ , # [ doc = "0x734 - Pin configuration register for pins PE" ] pub sfspe_13 : SFSPE_ , # [ doc = "0x738 - Pin configuration register for pins PE" ] pub sfspe_14 : SFSPE_ , # [ doc = "0x73c - Pin configuration register for pins PE" ] pub sfspe_15 : SFSPE_ , _reserved14 : [ u8 ; 64usize ] , # [ doc = "0x780 - Pin configuration register for pins PF" ] pub sfspf_0 : SFSPF_ , # [ doc = "0x784 - Pin configuration register for pins PF" ] pub sfspf_1 : SFSPF_ , # [ doc = "0x788 - Pin configuration register for pins PF" ] pub sfspf_2 : SFSPF_ , # [ doc = "0x78c - Pin configuration register for pins PF" ] pub sfspf_3 : SFSPF_ , # [ doc = "0x790 - Pin configuration register for pins PF" ] pub sfspf_4 : SFSPF_ , # [ doc = "0x794 - Pin configuration register for pins PF" ] pub sfspf_5 : SFSPF_ , # [ doc = "0x798 - Pin configuration register for pins PF" ] pub sfspf_6 : SFSPF_ , # [ doc = "0x79c - Pin configuration register for pins PF" ] pub sfspf_7 : SFSPF_ , # [ doc = "0x7a0 - Pin configuration register for pins PF" ] pub sfspf_8 : SFSPF_ , # [ doc = "0x7a4 - Pin configuration register for pins PF" ] pub sfspf_9 : SFSPF_ , # [ doc = "0x7a8 - Pin configuration register for pins PF" ] pub sfspf_10 : SFSPF_ , # [ doc = "0x7ac - Pin configuration register for pins PF" ] pub sfspf_11 : SFSPF_ , _reserved15 : [ u8 ; 1104usize ] , # [ doc = "0xc00 - Pin configuration register for pins CLK" ] pub sfsclk_0 : SFSCLK_ , # [ doc = "0xc04 - Pin configuration register for pins CLK" ] pub sfsclk_1 : SFSCLK_ , # [ doc = "0xc08 - Pin configuration register for pins CLK" ] pub sfsclk_2 : SFSCLK_ , # [ doc = "0xc0c - Pin configuration register for pins CLK" ] pub sfsclk_3 : SFSCLK_ , _reserved16 : [ u8 ; 112usize ] , # [ doc = "0xc80 - Pin configuration register for pins USB1_DM and USB1_DP" ] pub sfsusb : SFSUSB , # [ doc = "0xc84 - Pin configuration register for I2C0-bus pins" ] pub sfsi2c0 : SFSI2C0 , # [ doc = "0xc88 - ADC0 function select register" ] pub enaio0 : ENAIO0 , # [ doc = "0xc8c - ADC1 function select register" ] pub enaio1 : ENAIO1 , # [ doc = "0xc90 - Analog function select register" ] pub enaio2 : ENAIO2 , _reserved17 : [ u8 ; 108usize ] , # [ doc = "0xd00 - EMC clock delay register" ] pub emcdelayclk : EMCDELAYCLK , _reserved18 : [ u8 ; 124usize ] , # [ doc = "0xd80 - SD/MMC sample and drive delay register" ] pub sddelay : SDDELAY , _reserved19 : [ u8 ; 124usize ] , # [ doc = "0xe00 - Pin interrupt select register for pin interrupts 0 to 3." ] pub pintsel0 : PINTSEL0 , # [ doc = "0xe04 - Pin interrupt select register for pin interrupts 4 to 7." ] pub pintsel1 : PINTSEL1 , }
+ pub struct RegisterBlock {
+ #[doc = "0x00 - Pin configuration register for pins P0"] pub sfsp0_0: SFSP0_,
+ #[doc = "0x04 - Pin configuration register for pins P0"] pub sfsp0_1: SFSP0_,
+ _reserved0: [u8; 120usize],
+ #[doc = "0x80 - Pin configuration register for pins P1"] pub sfsp1_0: SFSP1_,
+ #[doc = "0x84 - Pin configuration register for pins P1"] pub sfsp1_1: SFSP1_,
+ #[doc = "0x88 - Pin configuration register for pins P1"] pub sfsp1_2: SFSP1_,
+ #[doc = "0x8c - Pin configuration register for pins P1"] pub sfsp1_3: SFSP1_,
+ #[doc = "0x90 - Pin configuration register for pins P1"] pub sfsp1_4: SFSP1_,
+ #[doc = "0x94 - Pin configuration register for pins P1"] pub sfsp1_5: SFSP1_,
+ #[doc = "0x98 - Pin configuration register for pins P1"] pub sfsp1_6: SFSP1_,
+ #[doc = "0x9c - Pin configuration register for pins P1"] pub sfsp1_7: SFSP1_,
+ #[doc = "0xa0 - Pin configuration register for pins P1"] pub sfsp1_8: SFSP1_,
+ #[doc = "0xa4 - Pin configuration register for pins P1"] pub sfsp1_9: SFSP1_,
+ #[doc = "0xa8 - Pin configuration register for pins P1"] pub sfsp1_10: SFSP1_,
+ #[doc = "0xac - Pin configuration register for pins P1"] pub sfsp1_11: SFSP1_,
+ #[doc = "0xb0 - Pin configuration register for pins P1"] pub sfsp1_12: SFSP1_,
+ #[doc = "0xb4 - Pin configuration register for pins P1"] pub sfsp1_13: SFSP1_,
+ #[doc = "0xb8 - Pin configuration register for pins P1"] pub sfsp1_14: SFSP1_,
+ #[doc = "0xbc - Pin configuration register for pins P1"] pub sfsp1_15: SFSP1_,
+ #[doc = "0xc0 - Pin configuration register for pins P1"] pub sfsp1_16: SFSP1_,
+ #[doc = "0xc4 - Pin configuration register for pins P1"] pub sfsp1_17: SFSP1_,
+ #[doc = "0xc8 - Pin configuration register for pins P1"] pub sfsp1_18: SFSP1_,
+ #[doc = "0xcc - Pin configuration register for pins P1"] pub sfsp1_19: SFSP1_,
+ #[doc = "0xd0 - Pin configuration register for pins P1"] pub sfsp1_20: SFSP1_,
+ _reserved1: [u8; 44usize],
+ #[doc = "0x100 - Pin configuration register for pins P2"] pub sfsp2_0: SFSP2_,
+ #[doc = "0x104 - Pin configuration register for pins P2"] pub sfsp2_1: SFSP2_,
+ #[doc = "0x108 - Pin configuration register for pins P2"] pub sfsp2_2: SFSP2_,
+ #[doc = "0x10c - Pin configuration register for pins P2"] pub sfsp2_3: SFSP2_,
+ #[doc = "0x110 - Pin configuration register for pins P2"] pub sfsp2_4: SFSP2_,
+ #[doc = "0x114 - Pin configuration register for pins P2"] pub sfsp2_5: SFSP2_,
+ #[doc = "0x118 - Pin configuration register for pins P2"] pub sfsp2_6: SFSP2_,
+ #[doc = "0x11c - Pin configuration register for pins P2"] pub sfsp2_7: SFSP2_,
+ #[doc = "0x120 - Pin configuration register for pins P2"] pub sfsp2_8: SFSP2_,
+ #[doc = "0x124 - Pin configuration register for pins P2"] pub sfsp2_9: SFSP2_,
+ #[doc = "0x128 - Pin configuration register for pins P2"] pub sfsp2_10: SFSP2_,
+ #[doc = "0x12c - Pin configuration register for pins P2"] pub sfsp2_11: SFSP2_,
+ #[doc = "0x130 - Pin configuration register for pins P2"] pub sfsp2_12: SFSP2_,
+ _reserved2: [u8; 76usize],
+ #[doc = "0x180 - Pin configuration register for pins P3"] pub sfsp3_0: SFSP3_,
+ #[doc = "0x184 - Pin configuration register for pins P3"] pub sfsp3_1: SFSP3_,
+ #[doc = "0x188 - Pin configuration register for pins P3"] pub sfsp3_2: SFSP3_,
+ #[doc = "0x18c - Pin configuration register for pins P3"] pub sfsp3_3: SFSP3_,
+ #[doc = "0x190 - Pin configuration register for pins P3"] pub sfsp3_4: SFSP3_,
+ #[doc = "0x194 - Pin configuration register for pins P3"] pub sfsp3_5: SFSP3_,
+ #[doc = "0x198 - Pin configuration register for pins P3"] pub sfsp3_6: SFSP3_,
+ #[doc = "0x19c - Pin configuration register for pins P3"] pub sfsp3_7: SFSP3_,
+ #[doc = "0x1a0 - Pin configuration register for pins P3"] pub sfsp3_8: SFSP3_,
+ _reserved3: [u8; 92usize],
+ #[doc = "0x200 - Pin configuration register for pins P4"] pub sfsp4_0: SFSP4_,
+ #[doc = "0x204 - Pin configuration register for pins P4"] pub sfsp4_1: SFSP4_,
+ #[doc = "0x208 - Pin configuration register for pins P4"] pub sfsp4_2: SFSP4_,
+ #[doc = "0x20c - Pin configuration register for pins P4"] pub sfsp4_3: SFSP4_,
+ #[doc = "0x210 - Pin configuration register for pins P4"] pub sfsp4_4: SFSP4_,
+ #[doc = "0x214 - Pin configuration register for pins P4"] pub sfsp4_5: SFSP4_,
+ #[doc = "0x218 - Pin configuration register for pins P4"] pub sfsp4_6: SFSP4_,
+ #[doc = "0x21c - Pin configuration register for pins P4"] pub sfsp4_7: SFSP4_,
+ #[doc = "0x220 - Pin configuration register for pins P4"] pub sfsp4_8: SFSP4_,
+ #[doc = "0x224 - Pin configuration register for pins P4"] pub sfsp4_9: SFSP4_,
+ #[doc = "0x228 - Pin configuration register for pins P4"] pub sfsp4_10: SFSP4_,
+ _reserved4: [u8; 84usize],
+ #[doc = "0x280 - Pin configuration register for pins P5"] pub sfsp5_0: SFSP5_,
+ #[doc = "0x284 - Pin configuration register for pins P5"] pub sfsp5_1: SFSP5_,
+ #[doc = "0x288 - Pin configuration register for pins P5"] pub sfsp5_2: SFSP5_,
+ #[doc = "0x28c - Pin configuration register for pins P5"] pub sfsp5_3: SFSP5_,
+ #[doc = "0x290 - Pin configuration register for pins P5"] pub sfsp5_4: SFSP5_,
+ #[doc = "0x294 - Pin configuration register for pins P5"] pub sfsp5_5: SFSP5_,
+ #[doc = "0x298 - Pin configuration register for pins P5"] pub sfsp5_6: SFSP5_,
+ #[doc = "0x29c - Pin configuration register for pins P5"] pub sfsp5_7: SFSP5_,
+ _reserved5: [u8; 96usize],
+ #[doc = "0x300 - Pin configuration register for pins P6"] pub sfsp6_0: SFSP6_,
+ #[doc = "0x304 - Pin configuration register for pins P6"] pub sfsp6_1: SFSP6_,
+ #[doc = "0x308 - Pin configuration register for pins P6"] pub sfsp6_2: SFSP6_,
+ #[doc = "0x30c - Pin configuration register for pins P6"] pub sfsp6_3: SFSP6_,
+ #[doc = "0x310 - Pin configuration register for pins P6"] pub sfsp6_4: SFSP6_,
+ #[doc = "0x314 - Pin configuration register for pins P6"] pub sfsp6_5: SFSP6_,
+ #[doc = "0x318 - Pin configuration register for pins P6"] pub sfsp6_6: SFSP6_,
+ #[doc = "0x31c - Pin configuration register for pins P6"] pub sfsp6_7: SFSP6_,
+ #[doc = "0x320 - Pin configuration register for pins P6"] pub sfsp6_8: SFSP6_,
+ #[doc = "0x324 - Pin configuration register for pins P6"] pub sfsp6_9: SFSP6_,
+ #[doc = "0x328 - Pin configuration register for pins P6"] pub sfsp6_10: SFSP6_,
+ #[doc = "0x32c - Pin configuration register for pins P6"] pub sfsp6_11: SFSP6_,
+ #[doc = "0x330 - Pin configuration register for pins P6"] pub sfsp6_12: SFSP6_,
+ _reserved6: [u8; 76usize],
+ #[doc = "0x380 - Pin configuration register for pins P7"] pub sfsp7_0: SFSP7_,
+ #[doc = "0x384 - Pin configuration register for pins P7"] pub sfsp7_1: SFSP7_,
+ #[doc = "0x388 - Pin configuration register for pins P7"] pub sfsp7_2: SFSP7_,
+ #[doc = "0x38c - Pin configuration register for pins P7"] pub sfsp7_3: SFSP7_,
+ #[doc = "0x390 - Pin configuration register for pins P7"] pub sfsp7_4: SFSP7_,
+ #[doc = "0x394 - Pin configuration register for pins P7"] pub sfsp7_5: SFSP7_,
+ #[doc = "0x398 - Pin configuration register for pins P7"] pub sfsp7_6: SFSP7_,
+ #[doc = "0x39c - Pin configuration register for pins P7"] pub sfsp7_7: SFSP7_,
+ _reserved7: [u8; 96usize],
+ #[doc = "0x400 - Pin configuration register for pins P8"] pub sfsp8_0: SFSP8_,
+ #[doc = "0x404 - Pin configuration register for pins P8"] pub sfsp8_1: SFSP8_,
+ #[doc = "0x408 - Pin configuration register for pins P8"] pub sfsp8_2: SFSP8_,
+ #[doc = "0x40c - Pin configuration register for pins P8"] pub sfsp8_3: SFSP8_,
+ #[doc = "0x410 - Pin configuration register for pins P8"] pub sfsp8_4: SFSP8_,
+ #[doc = "0x414 - Pin configuration register for pins P8"] pub sfsp8_5: SFSP8_,
+ #[doc = "0x418 - Pin configuration register for pins P8"] pub sfsp8_6: SFSP8_,
+ #[doc = "0x41c - Pin configuration register for pins P8"] pub sfsp8_7: SFSP8_,
+ #[doc = "0x420 - Pin configuration register for pins P8"] pub sfsp8_8: SFSP8_,
+ _reserved8: [u8; 92usize],
+ #[doc = "0x480 - Pin configuration register for pins P9"] pub sfsp9_0: SFSP9_,
+ #[doc = "0x484 - Pin configuration register for pins P9"] pub sfsp9_1: SFSP9_,
+ #[doc = "0x488 - Pin configuration register for pins P9"] pub sfsp9_2: SFSP9_,
+ #[doc = "0x48c - Pin configuration register for pins P9"] pub sfsp9_3: SFSP9_,
+ #[doc = "0x490 - Pin configuration register for pins P9"] pub sfsp9_4: SFSP9_,
+ #[doc = "0x494 - Pin configuration register for pins P9"] pub sfsp9_5: SFSP9_,
+ #[doc = "0x498 - Pin configuration register for pins P9"] pub sfsp9_6: SFSP9_,
+ _reserved9: [u8; 100usize],
+ #[doc = "0x500 - Pin configuration register for pins PA"] pub sfspa_0: SFSPA_0,
+ #[doc = "0x504 - Pin configuration register for pins PA"] pub sfspa_1: SFSPA_,
+ #[doc = "0x508 - Pin configuration register for pins PA"] pub sfspa_2: SFSPA_,
+ #[doc = "0x50c - Pin configuration register for pins PA"] pub sfspa_3: SFSPA_,
+ #[doc = "0x510 - Pin configuration register for pins PA"] pub sfspa_4: SFSPA_4,
+ _reserved10: [u8; 108usize],
+ #[doc = "0x580 - Pin configuration register for pins PB"] pub sfspb_0: SFSPB_,
+ #[doc = "0x584 - Pin configuration register for pins PB"] pub sfspb_1: SFSPB_,
+ #[doc = "0x588 - Pin configuration register for pins PB"] pub sfspb_2: SFSPB_,
+ #[doc = "0x58c - Pin configuration register for pins PB"] pub sfspb_3: SFSPB_,
+ #[doc = "0x590 - Pin configuration register for pins PB"] pub sfspb_4: SFSPB_,
+ #[doc = "0x594 - Pin configuration register for pins PB"] pub sfspb_5: SFSPB_,
+ #[doc = "0x598 - Pin configuration register for pins PB"] pub sfspb_6: SFSPB_,
+ _reserved11: [u8; 100usize],
+ #[doc = "0x600 - Pin configuration register for pins PC"] pub sfspc_0: SFSPC_,
+ #[doc = "0x604 - Pin configuration register for pins PC"] pub sfspc_1: SFSPC_,
+ #[doc = "0x608 - Pin configuration register for pins PC"] pub sfspc_2: SFSPC_,
+ #[doc = "0x60c - Pin configuration register for pins PC"] pub sfspc_3: SFSPC_,
+ #[doc = "0x610 - Pin configuration register for pins PC"] pub sfspc_4: SFSPC_,
+ #[doc = "0x614 - Pin configuration register for pins PC"] pub sfspc_5: SFSPC_,
+ #[doc = "0x618 - Pin configuration register for pins PC"] pub sfspc_6: SFSPC_,
+ #[doc = "0x61c - Pin configuration register for pins PC"] pub sfspc_7: SFSPC_,
+ #[doc = "0x620 - Pin configuration register for pins PC"] pub sfspc_8: SFSPC_,
+ #[doc = "0x624 - Pin configuration register for pins PC"] pub sfspc_9: SFSPC_,
+ #[doc = "0x628 - Pin configuration register for pins PC"] pub sfspc_10: SFSPC_,
+ #[doc = "0x62c - Pin configuration register for pins PC"] pub sfspc_11: SFSPC_,
+ #[doc = "0x630 - Pin configuration register for pins PC"] pub sfspc_12: SFSPC_,
+ #[doc = "0x634 - Pin configuration register for pins PC"] pub sfspc_13: SFSPC_,
+ #[doc = "0x638 - Pin configuration register for pins PC"] pub sfspc_14: SFSPC_,
+ _reserved12: [u8; 68usize],
+ #[doc = "0x680 - Pin configuration register for pins PD"] pub sfspd_0: SFSPD_,
+ #[doc = "0x684 - Pin configuration register for pins PD"] pub sfspd_1: SFSPD_,
+ #[doc = "0x688 - Pin configuration register for pins PD"] pub sfspd_2: SFSPD_,
+ #[doc = "0x68c - Pin configuration register for pins PD"] pub sfspd_3: SFSPD_,
+ #[doc = "0x690 - Pin configuration register for pins PD"] pub sfspd_4: SFSPD_,
+ #[doc = "0x694 - Pin configuration register for pins PD"] pub sfspd_5: SFSPD_,
+ #[doc = "0x698 - Pin configuration register for pins PD"] pub sfspd_6: SFSPD_,
+ #[doc = "0x69c - Pin configuration register for pins PD"] pub sfspd_7: SFSPD_,
+ #[doc = "0x6a0 - Pin configuration register for pins PD"] pub sfspd_8: SFSPD_,
+ #[doc = "0x6a4 - Pin configuration register for pins PD"] pub sfspd_9: SFSPD_,
+ #[doc = "0x6a8 - Pin configuration register for pins PD"] pub sfspd_10: SFSPD_,
+ #[doc = "0x6ac - Pin configuration register for pins PD"] pub sfspd_11: SFSPD_,
+ #[doc = "0x6b0 - Pin configuration register for pins PD"] pub sfspd_12: SFSPD_,
+ #[doc = "0x6b4 - Pin configuration register for pins PD"] pub sfspd_13: SFSPD_,
+ #[doc = "0x6b8 - Pin configuration register for pins PD"] pub sfspd_14: SFSPD_,
+ #[doc = "0x6bc - Pin configuration register for pins PD"] pub sfspd_15: SFSPD_,
+ #[doc = "0x6c0 - Pin configuration register for pins PD"] pub sfspd_16: SFSPD_,
+ _reserved13: [u8; 60usize],
+ #[doc = "0x700 - Pin configuration register for pins PE"] pub sfspe_0: SFSPE_,
+ #[doc = "0x704 - Pin configuration register for pins PE"] pub sfspe_1: SFSPE_,
+ #[doc = "0x708 - Pin configuration register for pins PE"] pub sfspe_2: SFSPE_,
+ #[doc = "0x70c - Pin configuration register for pins PE"] pub sfspe_3: SFSPE_,
+ #[doc = "0x710 - Pin configuration register for pins PE"] pub sfspe_4: SFSPE_,
+ #[doc = "0x714 - Pin configuration register for pins PE"] pub sfspe_5: SFSPE_,
+ #[doc = "0x718 - Pin configuration register for pins PE"] pub sfspe_6: SFSPE_,
+ #[doc = "0x71c - Pin configuration register for pins PE"] pub sfspe_7: SFSPE_,
+ #[doc = "0x720 - Pin configuration register for pins PE"] pub sfspe_8: SFSPE_,
+ #[doc = "0x724 - Pin configuration register for pins PE"] pub sfspe_9: SFSPE_,
+ #[doc = "0x728 - Pin configuration register for pins PE"] pub sfspe_10: SFSPE_,
+ #[doc = "0x72c - Pin configuration register for pins PE"] pub sfspe_11: SFSPE_,
+ #[doc = "0x730 - Pin configuration register for pins PE"] pub sfspe_12: SFSPE_,
+ #[doc = "0x734 - Pin configuration register for pins PE"] pub sfspe_13: SFSPE_,
+ #[doc = "0x738 - Pin configuration register for pins PE"] pub sfspe_14: SFSPE_,
+ #[doc = "0x73c - Pin configuration register for pins PE"] pub sfspe_15: SFSPE_,
+ _reserved14: [u8; 64usize],
+ #[doc = "0x780 - Pin configuration register for pins PF"] pub sfspf_0: SFSPF_,
+ #[doc = "0x784 - Pin configuration register for pins PF"] pub sfspf_1: SFSPF_,
+ #[doc = "0x788 - Pin configuration register for pins PF"] pub sfspf_2: SFSPF_,
+ #[doc = "0x78c - Pin configuration register for pins PF"] pub sfspf_3: SFSPF_,
+ #[doc = "0x790 - Pin configuration register for pins PF"] pub sfspf_4: SFSPF_,
+ #[doc = "0x794 - Pin configuration register for pins PF"] pub sfspf_5: SFSPF_,
+ #[doc = "0x798 - Pin configuration register for pins PF"] pub sfspf_6: SFSPF_,
+ #[doc = "0x79c - Pin configuration register for pins PF"] pub sfspf_7: SFSPF_,
+ #[doc = "0x7a0 - Pin configuration register for pins PF"] pub sfspf_8: SFSPF_,
+ #[doc = "0x7a4 - Pin configuration register for pins PF"] pub sfspf_9: SFSPF_,
+ #[doc = "0x7a8 - Pin configuration register for pins PF"] pub sfspf_10: SFSPF_,
+ #[doc = "0x7ac - Pin configuration register for pins PF"] pub sfspf_11: SFSPF_,
+ _reserved15: [u8; 1104usize],
+ #[doc = "0xc00 - Pin configuration register for pins CLK"] pub sfsclk_0: SFSCLK_,
+ #[doc = "0xc04 - Pin configuration register for pins CLK"] pub sfsclk_1: SFSCLK_,
+ #[doc = "0xc08 - Pin configuration register for pins CLK"] pub sfsclk_2: SFSCLK_,
+ #[doc = "0xc0c - Pin configuration register for pins CLK"] pub sfsclk_3: SFSCLK_,
+ _reserved16: [u8; 112usize],
+ #[doc = "0xc80 - Pin configuration register for pins USB1_DM and USB1_DP"]
+ pub sfsusb: SFSUSB,
+ #[doc = "0xc84 - Pin configuration register for I2C0-bus pins"] pub sfsi2c0: SFSI2C0,
+ #[doc = "0xc88 - ADC0 function select register"] pub enaio0: ENAIO0,
+ #[doc = "0xc8c - ADC1 function select register"] pub enaio1: ENAIO1,
+ #[doc = "0xc90 - Analog function select register"] pub enaio2: ENAIO2,
+ _reserved17: [u8; 108usize],
+ #[doc = "0xd00 - EMC clock delay register"] pub emcdelayclk: EMCDELAYCLK,
+ _reserved18: [u8; 124usize],
+ #[doc = "0xd80 - SD/MMC sample and drive delay register"] pub sddelay: SDDELAY,
+ _reserved19: [u8; 124usize],
+ #[doc = "0xe00 - Pin interrupt select register for pin interrupts 0 to 3."]
+ pub pintsel0: PINTSEL0,
+ #[doc = "0xe04 - Pin interrupt select register for pin interrupts 4 to 7."]
+ pub pintsel1: PINTSEL1,
+ }
#[doc = "Pin configuration register for pins P0"]
pub struct SFSP0_ {
register: VolatileCell<u32>,
@@ -216962,11 +211354,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -217008,11 +211396,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -217278,11 +211662,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -217311,8 +211691,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -217335,11 +211714,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -217363,8 +211738,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -217583,8 +211957,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -217601,8 +211974,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -217610,8 +211982,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -217642,8 +212013,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -217652,13 +212022,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -217800,11 +212168,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -217846,11 +212210,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -218025,6 +212385,58 @@ pub mod scu {
*self == ZIFR::DISABLE_INPUT_GLITCH
}
}
+ #[doc = "Possible values of the field `EHD`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum EHDR {
+ #[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
+ #[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
+ #[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
+ #[doc = "Ultra high-drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
+ }
+ impl EHDR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline(always)]
+ pub fn bits(&self) -> u8 {
+ match *self {
+ EHDR::NORMAL_DRIVE_4_MA_D => 0,
+ EHDR::MEDIUM_DRIVE_8_MA_D => 1,
+ EHDR::HIGH_DRIVE_14_MA_DR => 2,
+ EHDR::ULTRA_HIGH_DRIVE_20 => 3,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline(always)]
+ pub fn _from(value: u8) -> EHDR {
+ match value {
+ 0 => EHDR::NORMAL_DRIVE_4_MA_D,
+ 1 => EHDR::MEDIUM_DRIVE_8_MA_D,
+ 2 => EHDR::HIGH_DRIVE_14_MA_DR,
+ 3 => EHDR::ULTRA_HIGH_DRIVE_20,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Checks if the value of the field is `NORMAL_DRIVE_4_MA_D`"]
+ #[inline(always)]
+ pub fn is_normal_drive_4_ma_d(&self) -> bool {
+ *self == EHDR::NORMAL_DRIVE_4_MA_D
+ }
+ #[doc = "Checks if the value of the field is `MEDIUM_DRIVE_8_MA_D`"]
+ #[inline(always)]
+ pub fn is_medium_drive_8_ma_d(&self) -> bool {
+ *self == EHDR::MEDIUM_DRIVE_8_MA_D
+ }
+ #[doc = "Checks if the value of the field is `HIGH_DRIVE_14_MA_DR`"]
+ #[inline(always)]
+ pub fn is_high_drive_14_ma_dr(&self) -> bool {
+ *self == EHDR::HIGH_DRIVE_14_MA_DR
+ }
+ #[doc = "Checks if the value of the field is `ULTRA_HIGH_DRIVE_20`"]
+ #[inline(always)]
+ pub fn is_ultra_high_drive_20(&self) -> bool {
+ *self == EHDR::ULTRA_HIGH_DRIVE_20
+ }
+ }
#[doc = "Values that can be written to the field `MODE`"]
pub enum MODEW {
#[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
@@ -218116,11 +212528,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -218149,8 +212557,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -218173,11 +212580,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -218201,8 +212604,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -218397,6 +212799,68 @@ pub mod scu {
self.w
}
}
+ #[doc = "Values that can be written to the field `EHD`"]
+ pub enum EHDW {
+ #[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
+ #[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
+ #[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
+ #[doc = "Ultra high-drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
+ }
+ impl EHDW {
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline(always)]
+ pub fn _bits(&self) -> u8 {
+ match *self {
+ EHDW::NORMAL_DRIVE_4_MA_D => 0,
+ EHDW::MEDIUM_DRIVE_8_MA_D => 1,
+ EHDW::HIGH_DRIVE_14_MA_DR => 2,
+ EHDW::ULTRA_HIGH_DRIVE_20 => 3,
+ }
+ }
+ }
+ #[doc = r" Proxy"]
+ pub struct _EHDW<'a> {
+ w: &'a mut W,
+ }
+ impl<'a> _EHDW<'a> {
+ #[doc = r" Writes `variant` to the field"]
+ #[inline(always)]
+ pub fn variant(self, variant: EHDW) -> &'a mut W {
+ {
+ self.bits(variant._bits())
+ }
+ }
+ #[doc = "Normal-drive: 4 mA drive strength"]
+ #[inline(always)]
+ pub fn normal_drive_4_ma_d(self) -> &'a mut W {
+ self.variant(EHDW::NORMAL_DRIVE_4_MA_D)
+ }
+ #[doc = "Medium-drive: 8 mA drive strength"]
+ #[inline(always)]
+ pub fn medium_drive_8_ma_d(self) -> &'a mut W {
+ self.variant(EHDW::MEDIUM_DRIVE_8_MA_D)
+ }
+ #[doc = "High-drive: 14 mA drive strength"]
+ #[inline(always)]
+ pub fn high_drive_14_ma_dr(self) -> &'a mut W {
+ self.variant(EHDW::HIGH_DRIVE_14_MA_DR)
+ }
+ #[doc = "Ultra high-drive: 20 mA drive strength"]
+ #[inline(always)]
+ pub fn ultra_high_drive_20(self) -> &'a mut W {
+ self.variant(EHDW::ULTRA_HIGH_DRIVE_20)
+ }
+ #[doc = r" Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bits(self, value: u8) -> &'a mut W {
+ const MASK: u8 = 3;
+ const OFFSET: u8 = 8;
+ self.w.bits &= !((MASK as u32) << OFFSET);
+ self.w.bits |= ((value & MASK) as u32) << OFFSET;
+ self.w
+ }
+ }
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline(always)]
@@ -218421,8 +212885,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -218439,8 +212902,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -218448,8 +212910,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -218457,6 +212918,15 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
+ #[doc = "Bits 8:9 - Select drive strength."]
+ #[inline(always)]
+ pub fn ehd(&self) -> EHDR {
+ EHDR::_from({
+ const MASK: u8 = 3;
+ const OFFSET: u8 = 8;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ })
+ }
}
impl W {
#[doc = r" Reset value of the register"]
@@ -218480,8 +212950,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -218490,24 +212959,27 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
+ #[doc = "Bits 8:9 - Select drive strength."]
+ #[inline(always)]
+ pub fn ehd(&mut self) -> _EHDW {
+ _EHDW { w: self }
+ }
}
}
- #[doc = "Pin configuration register for pins P1_17"]
- pub struct SFSP1_17 {
+ #[doc = "Pin configuration register for pins P2"]
+ pub struct SFSP2_ {
register: VolatileCell<u32>,
}
- #[doc = "Pin configuration register for pins P1_17"]
- pub mod sfsp1_17 {
+ #[doc = "Pin configuration register for pins P2"]
+ pub mod sfsp2_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
@@ -218516,7 +212988,7 @@ pub mod scu {
pub struct W {
bits: u32,
}
- impl super::SFSP1_17 {
+ impl super::SFSP2_ {
#[doc = r" Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
@@ -218638,11 +213110,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -218684,11 +213152,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up"] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -218728,6 +213192,51 @@ pub mod scu {
*self == EPUNR::DISABLE_PULL_UP
}
}
+ #[doc = "Possible values of the field `EHS`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum EHSR {
+ #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
+ #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
+ }
+ impl EHSR {
+ #[doc = r" Returns `true` if the bit is clear (0)"]
+ #[inline(always)]
+ pub fn bit_is_clear(&self) -> bool {
+ !self.bit()
+ }
+ #[doc = r" Returns `true` if the bit is set (1)"]
+ #[inline(always)]
+ pub fn bit_is_set(&self) -> bool {
+ self.bit()
+ }
+ #[doc = r" Value of the field as raw bits"]
+ #[inline(always)]
+ pub fn bit(&self) -> bool {
+ match *self {
+ EHSR::SLOW_LOW_NOISE_WITH => false,
+ EHSR::FAST_MEDIUM_NOISE_W => true,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline(always)]
+ pub fn _from(value: bool) -> EHSR {
+ match value {
+ false => EHSR::SLOW_LOW_NOISE_WITH,
+ true => EHSR::FAST_MEDIUM_NOISE_W,
+ }
+ }
+ #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
+ #[inline(always)]
+ pub fn is_slow_low_noise_with(&self) -> bool {
+ *self == EHSR::SLOW_LOW_NOISE_WITH
+ }
+ #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
+ #[inline(always)]
+ pub fn is_fast_medium_noise_w(&self) -> bool {
+ *self == EHSR::FAST_MEDIUM_NOISE_W
+ }
+ }
#[doc = "Possible values of the field `EZI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EZIR {
@@ -218824,8 +213333,7 @@ pub mod scu {
#[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
#[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
#[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra high-drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
+ #[doc = "Ultra high-drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
}
impl EHDR {
#[doc = r" Value of the field as raw bits"]
@@ -218962,11 +213470,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -218995,8 +213499,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -219019,11 +213522,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up"] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -219047,12 +213546,11 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
- #[doc = "Disable pull-up"]
+ #[doc = "Disable pull-up."]
#[inline(always)]
pub fn disable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::DISABLE_PULL_UP)
@@ -219075,6 +213573,62 @@ pub mod scu {
self.w
}
}
+ #[doc = "Values that can be written to the field `EHS`"]
+ pub enum EHSW {
+ #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
+ #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
+ }
+ impl EHSW {
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline(always)]
+ pub fn _bits(&self) -> bool {
+ match *self {
+ EHSW::SLOW_LOW_NOISE_WITH => false,
+ EHSW::FAST_MEDIUM_NOISE_W => true,
+ }
+ }
+ }
+ #[doc = r" Proxy"]
+ pub struct _EHSW<'a> {
+ w: &'a mut W,
+ }
+ impl<'a> _EHSW<'a> {
+ #[doc = r" Writes `variant` to the field"]
+ #[inline(always)]
+ pub fn variant(self, variant: EHSW) -> &'a mut W {
+ {
+ self.bit(variant._bits())
+ }
+ }
+ #[doc = "Slow (low noise with medium speed)"]
+ #[inline(always)]
+ pub fn slow_low_noise_with(self) -> &'a mut W {
+ self.variant(EHSW::SLOW_LOW_NOISE_WITH)
+ }
+ #[doc = "Fast (medium noise with fast speed)"]
+ #[inline(always)]
+ pub fn fast_medium_noise_w(self) -> &'a mut W {
+ self.variant(EHSW::FAST_MEDIUM_NOISE_W)
+ }
+ #[doc = r" Sets the field bit"]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r" Clears the field bit"]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r" Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ const MASK: bool = true;
+ const OFFSET: u8 = 5;
+ self.w.bits &= !((MASK as u32) << OFFSET);
+ self.w.bits |= ((value & MASK) as u32) << OFFSET;
+ self.w
+ }
+ }
#[doc = "Values that can be written to the field `EZI`"]
pub enum EZIW {
#[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
@@ -219192,8 +213746,7 @@ pub mod scu {
#[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
#[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
#[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra high-drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
+ #[doc = "Ultra high-drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
}
impl EHDW {
#[allow(missing_docs)]
@@ -219274,8 +213827,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -219283,8 +213835,16 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
+ #[doc = "Bit 5 - Select Slew rate."]
#[inline(always)]
+ pub fn ehs(&self) -> EHSR {
+ EHSR::_from({
+ const MASK: bool = true;
+ const OFFSET: u8 = 5;
+ ((self.bits >> OFFSET) & MASK as u32) != 0
+ })
+ }
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -219292,8 +213852,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -219333,18 +213892,20 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
+ #[doc = "Bit 5 - Select Slew rate."]
#[inline(always)]
+ pub fn ehs(&mut self) -> _EHSW {
+ _EHSW { w: self }
+ }
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -219355,12 +213916,12 @@ pub mod scu {
}
}
}
- #[doc = "Pin configuration register for pins P1"]
- pub struct SFSP1_ {
+ #[doc = "Pin configuration register for pins P3"]
+ pub struct SFSP3_ {
register: VolatileCell<u32>,
}
- #[doc = "Pin configuration register for pins P1"]
- pub mod sfsp1_ {
+ #[doc = "Pin configuration register for pins P3"]
+ pub mod sfsp3_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
@@ -219369,7 +213930,7 @@ pub mod scu {
pub struct W {
bits: u32,
}
- impl super::SFSP1_ {
+ impl super::SFSP3_ {
#[doc = r" Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
@@ -219491,11 +214052,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -219537,11 +214094,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -219807,11 +214360,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -219840,8 +214389,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -219864,11 +214412,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -219892,8 +214436,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -220112,8 +214655,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -220130,8 +214672,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -220139,8 +214680,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -220171,8 +214711,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -220181,24 +214720,22 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
}
}
- #[doc = "Pin configuration register for pins P2"]
- pub struct SFSP2_ {
+ #[doc = "Pin configuration register for pins P4"]
+ pub struct SFSP4_ {
register: VolatileCell<u32>,
}
- #[doc = "Pin configuration register for pins P2"]
- pub mod sfsp2_ {
+ #[doc = "Pin configuration register for pins P4"]
+ pub mod sfsp4_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
@@ -220207,7 +214744,7 @@ pub mod scu {
pub struct W {
bits: u32,
}
- impl super::SFSP2_ {
+ impl super::SFSP4_ {
#[doc = r" Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
@@ -220329,11 +214866,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -220375,11 +214908,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -220645,11 +215174,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -220678,8 +215203,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -220702,11 +215226,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -220730,8 +215250,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -220950,8 +215469,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -220968,8 +215486,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -220977,8 +215494,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -221009,8 +215525,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -221019,24 +215534,22 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
}
}
- #[doc = "Pin configuration register for pins P2"]
- pub struct SFSP2_ {
+ #[doc = "Pin configuration register for pins P5"]
+ pub struct SFSP5_ {
register: VolatileCell<u32>,
}
- #[doc = "Pin configuration register for pins P2"]
- pub mod sfsp2_ {
+ #[doc = "Pin configuration register for pins P5"]
+ pub mod sfsp5_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
@@ -221045,7 +215558,7 @@ pub mod scu {
pub struct W {
bits: u32,
}
- impl super::SFSP2_ {
+ impl super::SFSP5_ {
#[doc = r" Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
@@ -221167,11 +215680,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -221213,11 +215722,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up"] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -221257,6 +215762,51 @@ pub mod scu {
*self == EPUNR::DISABLE_PULL_UP
}
}
+ #[doc = "Possible values of the field `EHS`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum EHSR {
+ #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
+ #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
+ }
+ impl EHSR {
+ #[doc = r" Returns `true` if the bit is clear (0)"]
+ #[inline(always)]
+ pub fn bit_is_clear(&self) -> bool {
+ !self.bit()
+ }
+ #[doc = r" Returns `true` if the bit is set (1)"]
+ #[inline(always)]
+ pub fn bit_is_set(&self) -> bool {
+ self.bit()
+ }
+ #[doc = r" Value of the field as raw bits"]
+ #[inline(always)]
+ pub fn bit(&self) -> bool {
+ match *self {
+ EHSR::SLOW_LOW_NOISE_WITH => false,
+ EHSR::FAST_MEDIUM_NOISE_W => true,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline(always)]
+ pub fn _from(value: bool) -> EHSR {
+ match value {
+ false => EHSR::SLOW_LOW_NOISE_WITH,
+ true => EHSR::FAST_MEDIUM_NOISE_W,
+ }
+ }
+ #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
+ #[inline(always)]
+ pub fn is_slow_low_noise_with(&self) -> bool {
+ *self == EHSR::SLOW_LOW_NOISE_WITH
+ }
+ #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
+ #[inline(always)]
+ pub fn is_fast_medium_noise_w(&self) -> bool {
+ *self == EHSR::FAST_MEDIUM_NOISE_W
+ }
+ }
#[doc = "Possible values of the field `EZI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EZIR {
@@ -221347,59 +215897,6 @@ pub mod scu {
*self == ZIFR::DISABLE_INPUT_GLITCH
}
}
- #[doc = "Possible values of the field `EHD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHDR {
- #[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
- #[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
- #[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra high-drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
- }
- impl EHDR {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- EHDR::NORMAL_DRIVE_4_MA_D => 0,
- EHDR::MEDIUM_DRIVE_8_MA_D => 1,
- EHDR::HIGH_DRIVE_14_MA_DR => 2,
- EHDR::ULTRA_HIGH_DRIVE_20 => 3,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> EHDR {
- match value {
- 0 => EHDR::NORMAL_DRIVE_4_MA_D,
- 1 => EHDR::MEDIUM_DRIVE_8_MA_D,
- 2 => EHDR::HIGH_DRIVE_14_MA_DR,
- 3 => EHDR::ULTRA_HIGH_DRIVE_20,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `NORMAL_DRIVE_4_MA_D`"]
- #[inline(always)]
- pub fn is_normal_drive_4_ma_d(&self) -> bool {
- *self == EHDR::NORMAL_DRIVE_4_MA_D
- }
- #[doc = "Checks if the value of the field is `MEDIUM_DRIVE_8_MA_D`"]
- #[inline(always)]
- pub fn is_medium_drive_8_ma_d(&self) -> bool {
- *self == EHDR::MEDIUM_DRIVE_8_MA_D
- }
- #[doc = "Checks if the value of the field is `HIGH_DRIVE_14_MA_DR`"]
- #[inline(always)]
- pub fn is_high_drive_14_ma_dr(&self) -> bool {
- *self == EHDR::HIGH_DRIVE_14_MA_DR
- }
- #[doc = "Checks if the value of the field is `ULTRA_HIGH_DRIVE_20`"]
- #[inline(always)]
- pub fn is_ultra_high_drive_20(&self) -> bool {
- *self == EHDR::ULTRA_HIGH_DRIVE_20
- }
- }
#[doc = "Values that can be written to the field `MODE`"]
pub enum MODEW {
#[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
@@ -221491,5886 +215988,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPDW::DISABLE_PULL_DOWN => false,
- EPDW::ENABLE_PULL_DOWN => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPDW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable pull-down."]
- #[inline(always)]
- pub fn disable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::DISABLE_PULL_DOWN)
- }
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::ENABLE_PULL_DOWN)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up"] DISABLE_PULL_UP,
- }
- impl EPUNW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPUNW::ENABLE_PULL_UP => false,
- EPUNW::DISABLE_PULL_UP => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPUNW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPUNW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPUNW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::ENABLE_PULL_UP)
- }
- #[doc = "Disable pull-up"]
- #[inline(always)]
- pub fn disable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::DISABLE_PULL_UP)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EZI`"]
- pub enum EZIW {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EZIW::DISABLE_INPUT_BUFFER => false,
- EZIW::ENABLE_INPUT_BUFFER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EZIW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EZIW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EZIW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable input buffer"]
- #[inline(always)]
- pub fn disable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::DISABLE_INPUT_BUFFER)
- }
- #[doc = "Enable input buffer"]
- #[inline(always)]
- pub fn enable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::ENABLE_INPUT_BUFFER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `ZIF`"]
- pub enum ZIFW {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- ZIFW::ENABLE_INPUT_GLITCH => false,
- ZIFW::DISABLE_INPUT_GLITCH => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _ZIFW<'a> {
- w: &'a mut W,
- }
- impl<'a> _ZIFW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: ZIFW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable input glitch filter"]
- #[inline(always)]
- pub fn enable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::ENABLE_INPUT_GLITCH)
- }
- #[doc = "Disable input glitch filter"]
- #[inline(always)]
- pub fn disable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::DISABLE_INPUT_GLITCH)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EHD`"]
- pub enum EHDW {
- #[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
- #[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
- #[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra high-drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
- }
- impl EHDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- EHDW::NORMAL_DRIVE_4_MA_D => 0,
- EHDW::MEDIUM_DRIVE_8_MA_D => 1,
- EHDW::HIGH_DRIVE_14_MA_DR => 2,
- EHDW::ULTRA_HIGH_DRIVE_20 => 3,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EHDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EHDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EHDW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Normal-drive: 4 mA drive strength"]
- #[inline(always)]
- pub fn normal_drive_4_ma_d(self) -> &'a mut W {
- self.variant(EHDW::NORMAL_DRIVE_4_MA_D)
- }
- #[doc = "Medium-drive: 8 mA drive strength"]
- #[inline(always)]
- pub fn medium_drive_8_ma_d(self) -> &'a mut W {
- self.variant(EHDW::MEDIUM_DRIVE_8_MA_D)
- }
- #[doc = "High-drive: 14 mA drive strength"]
- #[inline(always)]
- pub fn high_drive_14_ma_dr(self) -> &'a mut W {
- self.variant(EHDW::HIGH_DRIVE_14_MA_DR)
- }
- #[doc = "Ultra high-drive: 20 mA drive strength"]
- #[inline(always)]
- pub fn ultra_high_drive_20(self) -> &'a mut W {
- self.variant(EHDW::ULTRA_HIGH_DRIVE_20)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 3;
- const OFFSET: u8 = 8;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- impl R {
- #[doc = r" Value of the register as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u32 {
- self.bits
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&self) -> MODER {
- MODER::_from({
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&self) -> EPDR {
- EPDR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&self) -> EPUNR {
- EPUNR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
- #[inline(always)]
- pub fn ezi(&self) -> EZIR {
- EZIR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&self) -> ZIFR {
- ZIFR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bits 8:9 - Select drive strength."]
- #[inline(always)]
- pub fn ehd(&self) -> EHDR {
- EHDR::_from({
- const MASK: u8 = 3;
- const OFFSET: u8 = 8;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- }
- impl W {
- #[doc = r" Reset value of the register"]
- #[inline(always)]
- pub fn reset_value() -> W {
- W { bits: 0 }
- }
- #[doc = r" Writes raw bits to the register"]
- #[inline(always)]
- pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.bits = bits;
- self
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&mut self) -> _MODEW {
- _MODEW { w: self }
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&mut self) -> _EPDW {
- _EPDW { w: self }
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&mut self) -> _EPUNW {
- _EPUNW { w: self }
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
- #[inline(always)]
- pub fn ezi(&mut self) -> _EZIW {
- _EZIW { w: self }
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&mut self) -> _ZIFW {
- _ZIFW { w: self }
- }
- #[doc = "Bits 8:9 - Select drive strength."]
- #[inline(always)]
- pub fn ehd(&mut self) -> _EHDW {
- _EHDW { w: self }
- }
- }
- }
- #[doc = "Pin configuration register for pins P2"]
- pub struct SFSP2_ {
- register: VolatileCell<u32>,
- }
- #[doc = "Pin configuration register for pins P2"]
- pub mod sfsp2_ {
- #[doc = r" Value read from the register"]
- pub struct R {
- bits: u32,
- }
- #[doc = r" Value to write to the register"]
- pub struct W {
- bits: u32,
- }
- impl super::SFSP2_ {
- #[doc = r" Modifies the contents of the register"]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
- {
- let bits = self.register.get();
- let r = R { bits: bits };
- let mut w = W { bits: bits };
- f(&r, &mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Reads the contents of the register"]
- #[inline(always)]
- pub fn read(&self) -> R {
- R {
- bits: self.register.get(),
- }
- }
- #[doc = r" Writes to the register"]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W::reset_value();
- f(&mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Writes the reset value to the register"]
- #[inline(always)]
- pub fn reset(&self) {
- self.write(|w| w)
- }
- }
- #[doc = "Possible values of the field `MODE`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODER {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODER {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- MODER::FUNCTION_0_DEFAULT => 0,
- MODER::FUNCTION_1 => 1,
- MODER::FUNCTION_2 => 2,
- MODER::FUNCTION_3 => 3,
- MODER::FUNCTION_4 => 4,
- MODER::FUNCTION_5 => 5,
- MODER::FUNCTION_6 => 6,
- MODER::FUNCTION_7 => 7,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> MODER {
- match value {
- 0 => MODER::FUNCTION_0_DEFAULT,
- 1 => MODER::FUNCTION_1,
- 2 => MODER::FUNCTION_2,
- 3 => MODER::FUNCTION_3,
- 4 => MODER::FUNCTION_4,
- 5 => MODER::FUNCTION_5,
- 6 => MODER::FUNCTION_6,
- 7 => MODER::FUNCTION_7,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `FUNCTION_0_DEFAULT`"]
- #[inline(always)]
- pub fn is_function_0_default(&self) -> bool {
- *self == MODER::FUNCTION_0_DEFAULT
- }
- #[doc = "Checks if the value of the field is `FUNCTION_1`"]
- #[inline(always)]
- pub fn is_function_1(&self) -> bool {
- *self == MODER::FUNCTION_1
- }
- #[doc = "Checks if the value of the field is `FUNCTION_2`"]
- #[inline(always)]
- pub fn is_function_2(&self) -> bool {
- *self == MODER::FUNCTION_2
- }
- #[doc = "Checks if the value of the field is `FUNCTION_3`"]
- #[inline(always)]
- pub fn is_function_3(&self) -> bool {
- *self == MODER::FUNCTION_3
- }
- #[doc = "Checks if the value of the field is `FUNCTION_4`"]
- #[inline(always)]
- pub fn is_function_4(&self) -> bool {
- *self == MODER::FUNCTION_4
- }
- #[doc = "Checks if the value of the field is `FUNCTION_5`"]
- #[inline(always)]
- pub fn is_function_5(&self) -> bool {
- *self == MODER::FUNCTION_5
- }
- #[doc = "Checks if the value of the field is `FUNCTION_6`"]
- #[inline(always)]
- pub fn is_function_6(&self) -> bool {
- *self == MODER::FUNCTION_6
- }
- #[doc = "Checks if the value of the field is `FUNCTION_7`"]
- #[inline(always)]
- pub fn is_function_7(&self) -> bool {
- *self == MODER::FUNCTION_7
- }
- }
- #[doc = "Possible values of the field `EPD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPDR::DISABLE_PULL_DOWN => false,
- EPDR::ENABLE_PULL_DOWN => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPDR {
- match value {
- false => EPDR::DISABLE_PULL_DOWN,
- true => EPDR::ENABLE_PULL_DOWN,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_disable_pull_down(&self) -> bool {
- *self == EPDR::DISABLE_PULL_DOWN
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_enable_pull_down(&self) -> bool {
- *self == EPDR::ENABLE_PULL_DOWN
- }
- }
- #[doc = "Possible values of the field `EPUN`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPUNR::ENABLE_PULL_UP => false,
- EPUNR::DISABLE_PULL_UP => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPUNR {
- match value {
- false => EPUNR::ENABLE_PULL_UP,
- true => EPUNR::DISABLE_PULL_UP,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_enable_pull_up(&self) -> bool {
- *self == EPUNR::ENABLE_PULL_UP
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_disable_pull_up(&self) -> bool {
- *self == EPUNR::DISABLE_PULL_UP
- }
- }
- #[doc = "Possible values of the field `EHS`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHSR {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EHSR::SLOW_LOW_NOISE_WITH => false,
- EHSR::FAST_MEDIUM_NOISE_W => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EHSR {
- match value {
- false => EHSR::SLOW_LOW_NOISE_WITH,
- true => EHSR::FAST_MEDIUM_NOISE_W,
- }
- }
- #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
- #[inline(always)]
- pub fn is_slow_low_noise_with(&self) -> bool {
- *self == EHSR::SLOW_LOW_NOISE_WITH
- }
- #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
- #[inline(always)]
- pub fn is_fast_medium_noise_w(&self) -> bool {
- *self == EHSR::FAST_MEDIUM_NOISE_W
- }
- }
- #[doc = "Possible values of the field `EZI`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EZIR {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EZIR::DISABLE_INPUT_BUFFER => false,
- EZIR::ENABLE_INPUT_BUFFER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EZIR {
- match value {
- false => EZIR::DISABLE_INPUT_BUFFER,
- true => EZIR::ENABLE_INPUT_BUFFER,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_disable_input_buffer(&self) -> bool {
- *self == EZIR::DISABLE_INPUT_BUFFER
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_enable_input_buffer(&self) -> bool {
- *self == EZIR::ENABLE_INPUT_BUFFER
- }
- }
- #[doc = "Possible values of the field `ZIF`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ZIFR {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- ZIFR::ENABLE_INPUT_GLITCH => false,
- ZIFR::DISABLE_INPUT_GLITCH => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> ZIFR {
- match value {
- false => ZIFR::ENABLE_INPUT_GLITCH,
- true => ZIFR::DISABLE_INPUT_GLITCH,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_enable_input_glitch(&self) -> bool {
- *self == ZIFR::ENABLE_INPUT_GLITCH
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_disable_input_glitch(&self) -> bool {
- *self == ZIFR::DISABLE_INPUT_GLITCH
- }
- }
- #[doc = "Values that can be written to the field `MODE`"]
- pub enum MODEW {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODEW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- MODEW::FUNCTION_0_DEFAULT => 0,
- MODEW::FUNCTION_1 => 1,
- MODEW::FUNCTION_2 => 2,
- MODEW::FUNCTION_3 => 3,
- MODEW::FUNCTION_4 => 4,
- MODEW::FUNCTION_5 => 5,
- MODEW::FUNCTION_6 => 6,
- MODEW::FUNCTION_7 => 7,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _MODEW<'a> {
- w: &'a mut W,
- }
- impl<'a> _MODEW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: MODEW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Function 0 (default)"]
- #[inline(always)]
- pub fn function_0_default(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_0_DEFAULT)
- }
- #[doc = "Function 1"]
- #[inline(always)]
- pub fn function_1(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_1)
- }
- #[doc = "Function 2"]
- #[inline(always)]
- pub fn function_2(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_2)
- }
- #[doc = "Function 3"]
- #[inline(always)]
- pub fn function_3(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_3)
- }
- #[doc = "Function 4"]
- #[inline(always)]
- pub fn function_4(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_4)
- }
- #[doc = "Function 5"]
- #[inline(always)]
- pub fn function_5(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_5)
- }
- #[doc = "Function 6"]
- #[inline(always)]
- pub fn function_6(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_6)
- }
- #[doc = "Function 7"]
- #[inline(always)]
- pub fn function_7(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_7)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPDW::DISABLE_PULL_DOWN => false,
- EPDW::ENABLE_PULL_DOWN => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPDW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable pull-down."]
- #[inline(always)]
- pub fn disable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::DISABLE_PULL_DOWN)
- }
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::ENABLE_PULL_DOWN)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPUNW::ENABLE_PULL_UP => false,
- EPUNW::DISABLE_PULL_UP => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPUNW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPUNW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPUNW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::ENABLE_PULL_UP)
- }
- #[doc = "Disable pull-up."]
- #[inline(always)]
- pub fn disable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::DISABLE_PULL_UP)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EHS`"]
- pub enum EHSW {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EHSW::SLOW_LOW_NOISE_WITH => false,
- EHSW::FAST_MEDIUM_NOISE_W => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EHSW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EHSW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EHSW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Slow (low noise with medium speed)"]
- #[inline(always)]
- pub fn slow_low_noise_with(self) -> &'a mut W {
- self.variant(EHSW::SLOW_LOW_NOISE_WITH)
- }
- #[doc = "Fast (medium noise with fast speed)"]
- #[inline(always)]
- pub fn fast_medium_noise_w(self) -> &'a mut W {
- self.variant(EHSW::FAST_MEDIUM_NOISE_W)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EZI`"]
- pub enum EZIW {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EZIW::DISABLE_INPUT_BUFFER => false,
- EZIW::ENABLE_INPUT_BUFFER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EZIW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EZIW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EZIW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable input buffer"]
- #[inline(always)]
- pub fn disable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::DISABLE_INPUT_BUFFER)
- }
- #[doc = "Enable input buffer"]
- #[inline(always)]
- pub fn enable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::ENABLE_INPUT_BUFFER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `ZIF`"]
- pub enum ZIFW {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- ZIFW::ENABLE_INPUT_GLITCH => false,
- ZIFW::DISABLE_INPUT_GLITCH => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _ZIFW<'a> {
- w: &'a mut W,
- }
- impl<'a> _ZIFW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: ZIFW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable input glitch filter"]
- #[inline(always)]
- pub fn enable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::ENABLE_INPUT_GLITCH)
- }
- #[doc = "Disable input glitch filter"]
- #[inline(always)]
- pub fn disable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::DISABLE_INPUT_GLITCH)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- impl R {
- #[doc = r" Value of the register as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u32 {
- self.bits
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&self) -> MODER {
- MODER::_from({
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&self) -> EPDR {
- EPDR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&self) -> EPUNR {
- EPUNR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&self) -> EHSR {
- EHSR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&self) -> EZIR {
- EZIR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&self) -> ZIFR {
- ZIFR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- }
- impl W {
- #[doc = r" Reset value of the register"]
- #[inline(always)]
- pub fn reset_value() -> W {
- W { bits: 0 }
- }
- #[doc = r" Writes raw bits to the register"]
- #[inline(always)]
- pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.bits = bits;
- self
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&mut self) -> _MODEW {
- _MODEW { w: self }
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&mut self) -> _EPDW {
- _EPDW { w: self }
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&mut self) -> _EPUNW {
- _EPUNW { w: self }
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&mut self) -> _EHSW {
- _EHSW { w: self }
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&mut self) -> _EZIW {
- _EZIW { w: self }
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&mut self) -> _ZIFW {
- _ZIFW { w: self }
- }
- }
- }
- #[doc = "Pin configuration register for pins P3"]
- pub struct SFSP3_ {
- register: VolatileCell<u32>,
- }
- #[doc = "Pin configuration register for pins P3"]
- pub mod sfsp3_ {
- #[doc = r" Value read from the register"]
- pub struct R {
- bits: u32,
- }
- #[doc = r" Value to write to the register"]
- pub struct W {
- bits: u32,
- }
- impl super::SFSP3_ {
- #[doc = r" Modifies the contents of the register"]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
- {
- let bits = self.register.get();
- let r = R { bits: bits };
- let mut w = W { bits: bits };
- f(&r, &mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Reads the contents of the register"]
- #[inline(always)]
- pub fn read(&self) -> R {
- R {
- bits: self.register.get(),
- }
- }
- #[doc = r" Writes to the register"]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W::reset_value();
- f(&mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Writes the reset value to the register"]
- #[inline(always)]
- pub fn reset(&self) {
- self.write(|w| w)
- }
- }
- #[doc = "Possible values of the field `MODE`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODER {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODER {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- MODER::FUNCTION_0_DEFAULT => 0,
- MODER::FUNCTION_1 => 1,
- MODER::FUNCTION_2 => 2,
- MODER::FUNCTION_3 => 3,
- MODER::FUNCTION_4 => 4,
- MODER::FUNCTION_5 => 5,
- MODER::FUNCTION_6 => 6,
- MODER::FUNCTION_7 => 7,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> MODER {
- match value {
- 0 => MODER::FUNCTION_0_DEFAULT,
- 1 => MODER::FUNCTION_1,
- 2 => MODER::FUNCTION_2,
- 3 => MODER::FUNCTION_3,
- 4 => MODER::FUNCTION_4,
- 5 => MODER::FUNCTION_5,
- 6 => MODER::FUNCTION_6,
- 7 => MODER::FUNCTION_7,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `FUNCTION_0_DEFAULT`"]
- #[inline(always)]
- pub fn is_function_0_default(&self) -> bool {
- *self == MODER::FUNCTION_0_DEFAULT
- }
- #[doc = "Checks if the value of the field is `FUNCTION_1`"]
- #[inline(always)]
- pub fn is_function_1(&self) -> bool {
- *self == MODER::FUNCTION_1
- }
- #[doc = "Checks if the value of the field is `FUNCTION_2`"]
- #[inline(always)]
- pub fn is_function_2(&self) -> bool {
- *self == MODER::FUNCTION_2
- }
- #[doc = "Checks if the value of the field is `FUNCTION_3`"]
- #[inline(always)]
- pub fn is_function_3(&self) -> bool {
- *self == MODER::FUNCTION_3
- }
- #[doc = "Checks if the value of the field is `FUNCTION_4`"]
- #[inline(always)]
- pub fn is_function_4(&self) -> bool {
- *self == MODER::FUNCTION_4
- }
- #[doc = "Checks if the value of the field is `FUNCTION_5`"]
- #[inline(always)]
- pub fn is_function_5(&self) -> bool {
- *self == MODER::FUNCTION_5
- }
- #[doc = "Checks if the value of the field is `FUNCTION_6`"]
- #[inline(always)]
- pub fn is_function_6(&self) -> bool {
- *self == MODER::FUNCTION_6
- }
- #[doc = "Checks if the value of the field is `FUNCTION_7`"]
- #[inline(always)]
- pub fn is_function_7(&self) -> bool {
- *self == MODER::FUNCTION_7
- }
- }
- #[doc = "Possible values of the field `EPD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPDR::DISABLE_PULL_DOWN => false,
- EPDR::ENABLE_PULL_DOWN => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPDR {
- match value {
- false => EPDR::DISABLE_PULL_DOWN,
- true => EPDR::ENABLE_PULL_DOWN,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_disable_pull_down(&self) -> bool {
- *self == EPDR::DISABLE_PULL_DOWN
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_enable_pull_down(&self) -> bool {
- *self == EPDR::ENABLE_PULL_DOWN
- }
- }
- #[doc = "Possible values of the field `EPUN`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPUNR::ENABLE_PULL_UP => false,
- EPUNR::DISABLE_PULL_UP => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPUNR {
- match value {
- false => EPUNR::ENABLE_PULL_UP,
- true => EPUNR::DISABLE_PULL_UP,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_enable_pull_up(&self) -> bool {
- *self == EPUNR::ENABLE_PULL_UP
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_disable_pull_up(&self) -> bool {
- *self == EPUNR::DISABLE_PULL_UP
- }
- }
- #[doc = "Possible values of the field `EHS`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHSR {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EHSR::SLOW_LOW_NOISE_WITH => false,
- EHSR::FAST_MEDIUM_NOISE_W => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EHSR {
- match value {
- false => EHSR::SLOW_LOW_NOISE_WITH,
- true => EHSR::FAST_MEDIUM_NOISE_W,
- }
- }
- #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
- #[inline(always)]
- pub fn is_slow_low_noise_with(&self) -> bool {
- *self == EHSR::SLOW_LOW_NOISE_WITH
- }
- #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
- #[inline(always)]
- pub fn is_fast_medium_noise_w(&self) -> bool {
- *self == EHSR::FAST_MEDIUM_NOISE_W
- }
- }
- #[doc = "Possible values of the field `EZI`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EZIR {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EZIR::DISABLE_INPUT_BUFFER => false,
- EZIR::ENABLE_INPUT_BUFFER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EZIR {
- match value {
- false => EZIR::DISABLE_INPUT_BUFFER,
- true => EZIR::ENABLE_INPUT_BUFFER,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_disable_input_buffer(&self) -> bool {
- *self == EZIR::DISABLE_INPUT_BUFFER
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_enable_input_buffer(&self) -> bool {
- *self == EZIR::ENABLE_INPUT_BUFFER
- }
- }
- #[doc = "Possible values of the field `ZIF`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ZIFR {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- ZIFR::ENABLE_INPUT_GLITCH => false,
- ZIFR::DISABLE_INPUT_GLITCH => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> ZIFR {
- match value {
- false => ZIFR::ENABLE_INPUT_GLITCH,
- true => ZIFR::DISABLE_INPUT_GLITCH,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_enable_input_glitch(&self) -> bool {
- *self == ZIFR::ENABLE_INPUT_GLITCH
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_disable_input_glitch(&self) -> bool {
- *self == ZIFR::DISABLE_INPUT_GLITCH
- }
- }
- #[doc = "Values that can be written to the field `MODE`"]
- pub enum MODEW {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODEW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- MODEW::FUNCTION_0_DEFAULT => 0,
- MODEW::FUNCTION_1 => 1,
- MODEW::FUNCTION_2 => 2,
- MODEW::FUNCTION_3 => 3,
- MODEW::FUNCTION_4 => 4,
- MODEW::FUNCTION_5 => 5,
- MODEW::FUNCTION_6 => 6,
- MODEW::FUNCTION_7 => 7,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _MODEW<'a> {
- w: &'a mut W,
- }
- impl<'a> _MODEW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: MODEW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Function 0 (default)"]
- #[inline(always)]
- pub fn function_0_default(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_0_DEFAULT)
- }
- #[doc = "Function 1"]
- #[inline(always)]
- pub fn function_1(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_1)
- }
- #[doc = "Function 2"]
- #[inline(always)]
- pub fn function_2(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_2)
- }
- #[doc = "Function 3"]
- #[inline(always)]
- pub fn function_3(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_3)
- }
- #[doc = "Function 4"]
- #[inline(always)]
- pub fn function_4(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_4)
- }
- #[doc = "Function 5"]
- #[inline(always)]
- pub fn function_5(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_5)
- }
- #[doc = "Function 6"]
- #[inline(always)]
- pub fn function_6(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_6)
- }
- #[doc = "Function 7"]
- #[inline(always)]
- pub fn function_7(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_7)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPDW::DISABLE_PULL_DOWN => false,
- EPDW::ENABLE_PULL_DOWN => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPDW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable pull-down."]
- #[inline(always)]
- pub fn disable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::DISABLE_PULL_DOWN)
- }
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::ENABLE_PULL_DOWN)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPUNW::ENABLE_PULL_UP => false,
- EPUNW::DISABLE_PULL_UP => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPUNW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPUNW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPUNW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::ENABLE_PULL_UP)
- }
- #[doc = "Disable pull-up."]
- #[inline(always)]
- pub fn disable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::DISABLE_PULL_UP)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EHS`"]
- pub enum EHSW {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EHSW::SLOW_LOW_NOISE_WITH => false,
- EHSW::FAST_MEDIUM_NOISE_W => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EHSW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EHSW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EHSW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Slow (low noise with medium speed)"]
- #[inline(always)]
- pub fn slow_low_noise_with(self) -> &'a mut W {
- self.variant(EHSW::SLOW_LOW_NOISE_WITH)
- }
- #[doc = "Fast (medium noise with fast speed)"]
- #[inline(always)]
- pub fn fast_medium_noise_w(self) -> &'a mut W {
- self.variant(EHSW::FAST_MEDIUM_NOISE_W)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EZI`"]
- pub enum EZIW {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EZIW::DISABLE_INPUT_BUFFER => false,
- EZIW::ENABLE_INPUT_BUFFER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EZIW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EZIW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EZIW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable input buffer"]
- #[inline(always)]
- pub fn disable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::DISABLE_INPUT_BUFFER)
- }
- #[doc = "Enable input buffer"]
- #[inline(always)]
- pub fn enable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::ENABLE_INPUT_BUFFER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `ZIF`"]
- pub enum ZIFW {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- ZIFW::ENABLE_INPUT_GLITCH => false,
- ZIFW::DISABLE_INPUT_GLITCH => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _ZIFW<'a> {
- w: &'a mut W,
- }
- impl<'a> _ZIFW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: ZIFW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable input glitch filter"]
- #[inline(always)]
- pub fn enable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::ENABLE_INPUT_GLITCH)
- }
- #[doc = "Disable input glitch filter"]
- #[inline(always)]
- pub fn disable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::DISABLE_INPUT_GLITCH)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- impl R {
- #[doc = r" Value of the register as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u32 {
- self.bits
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&self) -> MODER {
- MODER::_from({
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&self) -> EPDR {
- EPDR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&self) -> EPUNR {
- EPUNR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&self) -> EHSR {
- EHSR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&self) -> EZIR {
- EZIR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&self) -> ZIFR {
- ZIFR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- }
- impl W {
- #[doc = r" Reset value of the register"]
- #[inline(always)]
- pub fn reset_value() -> W {
- W { bits: 0 }
- }
- #[doc = r" Writes raw bits to the register"]
- #[inline(always)]
- pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.bits = bits;
- self
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&mut self) -> _MODEW {
- _MODEW { w: self }
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&mut self) -> _EPDW {
- _EPDW { w: self }
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&mut self) -> _EPUNW {
- _EPUNW { w: self }
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&mut self) -> _EHSW {
- _EHSW { w: self }
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&mut self) -> _EZIW {
- _EZIW { w: self }
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&mut self) -> _ZIFW {
- _ZIFW { w: self }
- }
- }
- }
- #[doc = "Pin configuration register for pins P3"]
- pub struct SFSP3_3 {
- register: VolatileCell<u32>,
- }
- #[doc = "Pin configuration register for pins P3"]
- pub mod sfsp3_3 {
- #[doc = r" Value read from the register"]
- pub struct R {
- bits: u32,
- }
- #[doc = r" Value to write to the register"]
- pub struct W {
- bits: u32,
- }
- impl super::SFSP3_3 {
- #[doc = r" Modifies the contents of the register"]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
- {
- let bits = self.register.get();
- let r = R { bits: bits };
- let mut w = W { bits: bits };
- f(&r, &mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Reads the contents of the register"]
- #[inline(always)]
- pub fn read(&self) -> R {
- R {
- bits: self.register.get(),
- }
- }
- #[doc = r" Writes to the register"]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W::reset_value();
- f(&mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Writes the reset value to the register"]
- #[inline(always)]
- pub fn reset(&self) {
- self.write(|w| w)
- }
- }
- #[doc = "Possible values of the field `MODE`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODER {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODER {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- MODER::FUNCTION_0_DEFAULT => 0,
- MODER::FUNCTION_1 => 1,
- MODER::FUNCTION_2 => 2,
- MODER::FUNCTION_3 => 3,
- MODER::FUNCTION_4 => 4,
- MODER::FUNCTION_5 => 5,
- MODER::FUNCTION_6 => 6,
- MODER::FUNCTION_7 => 7,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> MODER {
- match value {
- 0 => MODER::FUNCTION_0_DEFAULT,
- 1 => MODER::FUNCTION_1,
- 2 => MODER::FUNCTION_2,
- 3 => MODER::FUNCTION_3,
- 4 => MODER::FUNCTION_4,
- 5 => MODER::FUNCTION_5,
- 6 => MODER::FUNCTION_6,
- 7 => MODER::FUNCTION_7,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `FUNCTION_0_DEFAULT`"]
- #[inline(always)]
- pub fn is_function_0_default(&self) -> bool {
- *self == MODER::FUNCTION_0_DEFAULT
- }
- #[doc = "Checks if the value of the field is `FUNCTION_1`"]
- #[inline(always)]
- pub fn is_function_1(&self) -> bool {
- *self == MODER::FUNCTION_1
- }
- #[doc = "Checks if the value of the field is `FUNCTION_2`"]
- #[inline(always)]
- pub fn is_function_2(&self) -> bool {
- *self == MODER::FUNCTION_2
- }
- #[doc = "Checks if the value of the field is `FUNCTION_3`"]
- #[inline(always)]
- pub fn is_function_3(&self) -> bool {
- *self == MODER::FUNCTION_3
- }
- #[doc = "Checks if the value of the field is `FUNCTION_4`"]
- #[inline(always)]
- pub fn is_function_4(&self) -> bool {
- *self == MODER::FUNCTION_4
- }
- #[doc = "Checks if the value of the field is `FUNCTION_5`"]
- #[inline(always)]
- pub fn is_function_5(&self) -> bool {
- *self == MODER::FUNCTION_5
- }
- #[doc = "Checks if the value of the field is `FUNCTION_6`"]
- #[inline(always)]
- pub fn is_function_6(&self) -> bool {
- *self == MODER::FUNCTION_6
- }
- #[doc = "Checks if the value of the field is `FUNCTION_7`"]
- #[inline(always)]
- pub fn is_function_7(&self) -> bool {
- *self == MODER::FUNCTION_7
- }
- }
- #[doc = "Possible values of the field `EPD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPDR::DISABLE_PULL_DOWN => false,
- EPDR::ENABLE_PULL_DOWN => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPDR {
- match value {
- false => EPDR::DISABLE_PULL_DOWN,
- true => EPDR::ENABLE_PULL_DOWN,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_disable_pull_down(&self) -> bool {
- *self == EPDR::DISABLE_PULL_DOWN
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_enable_pull_down(&self) -> bool {
- *self == EPDR::ENABLE_PULL_DOWN
- }
- }
- #[doc = "Possible values of the field `EPUN`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPUNR::ENABLE_PULL_UP => false,
- EPUNR::DISABLE_PULL_UP => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPUNR {
- match value {
- false => EPUNR::ENABLE_PULL_UP,
- true => EPUNR::DISABLE_PULL_UP,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_enable_pull_up(&self) -> bool {
- *self == EPUNR::ENABLE_PULL_UP
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_disable_pull_up(&self) -> bool {
- *self == EPUNR::DISABLE_PULL_UP
- }
- }
- #[doc = "Possible values of the field `EHS`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHSR {
- #[doc = "Fast (low noise with fast speed)"] FAST_LOW_NOISE_WITH,
- #[doc = "High-speed (medium noise with high speed)"]
- HIGH_SPEED_MEDIUM_N,
- }
- impl EHSR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EHSR::FAST_LOW_NOISE_WITH => false,
- EHSR::HIGH_SPEED_MEDIUM_N => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EHSR {
- match value {
- false => EHSR::FAST_LOW_NOISE_WITH,
- true => EHSR::HIGH_SPEED_MEDIUM_N,
- }
- }
- #[doc = "Checks if the value of the field is `FAST_LOW_NOISE_WITH`"]
- #[inline(always)]
- pub fn is_fast_low_noise_with(&self) -> bool {
- *self == EHSR::FAST_LOW_NOISE_WITH
- }
- #[doc = "Checks if the value of the field is `HIGH_SPEED_MEDIUM_N`"]
- #[inline(always)]
- pub fn is_high_speed_medium_n(&self) -> bool {
- *self == EHSR::HIGH_SPEED_MEDIUM_N
- }
- }
- #[doc = "Possible values of the field `EZI`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EZIR {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EZIR::DISABLE_INPUT_BUFFER => false,
- EZIR::ENABLE_INPUT_BUFFER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EZIR {
- match value {
- false => EZIR::DISABLE_INPUT_BUFFER,
- true => EZIR::ENABLE_INPUT_BUFFER,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_disable_input_buffer(&self) -> bool {
- *self == EZIR::DISABLE_INPUT_BUFFER
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_enable_input_buffer(&self) -> bool {
- *self == EZIR::ENABLE_INPUT_BUFFER
- }
- }
- #[doc = "Possible values of the field `ZIF`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ZIFR {
- #[doc = "Enable input filter"] ENABLE_INPUT_FILTER,
- #[doc = "Disable input filter"] DISABLE_INPUT_FILTER,
- }
- impl ZIFR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- ZIFR::ENABLE_INPUT_FILTER => false,
- ZIFR::DISABLE_INPUT_FILTER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> ZIFR {
- match value {
- false => ZIFR::ENABLE_INPUT_FILTER,
- true => ZIFR::DISABLE_INPUT_FILTER,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_FILTER`"]
- #[inline(always)]
- pub fn is_enable_input_filter(&self) -> bool {
- *self == ZIFR::ENABLE_INPUT_FILTER
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_FILTER`"]
- #[inline(always)]
- pub fn is_disable_input_filter(&self) -> bool {
- *self == ZIFR::DISABLE_INPUT_FILTER
- }
- }
- #[doc = "Values that can be written to the field `MODE`"]
- pub enum MODEW {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODEW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- MODEW::FUNCTION_0_DEFAULT => 0,
- MODEW::FUNCTION_1 => 1,
- MODEW::FUNCTION_2 => 2,
- MODEW::FUNCTION_3 => 3,
- MODEW::FUNCTION_4 => 4,
- MODEW::FUNCTION_5 => 5,
- MODEW::FUNCTION_6 => 6,
- MODEW::FUNCTION_7 => 7,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _MODEW<'a> {
- w: &'a mut W,
- }
- impl<'a> _MODEW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: MODEW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Function 0 (default)"]
- #[inline(always)]
- pub fn function_0_default(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_0_DEFAULT)
- }
- #[doc = "Function 1"]
- #[inline(always)]
- pub fn function_1(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_1)
- }
- #[doc = "Function 2"]
- #[inline(always)]
- pub fn function_2(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_2)
- }
- #[doc = "Function 3"]
- #[inline(always)]
- pub fn function_3(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_3)
- }
- #[doc = "Function 4"]
- #[inline(always)]
- pub fn function_4(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_4)
- }
- #[doc = "Function 5"]
- #[inline(always)]
- pub fn function_5(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_5)
- }
- #[doc = "Function 6"]
- #[inline(always)]
- pub fn function_6(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_6)
- }
- #[doc = "Function 7"]
- #[inline(always)]
- pub fn function_7(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_7)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPDW::DISABLE_PULL_DOWN => false,
- EPDW::ENABLE_PULL_DOWN => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPDW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable pull-down."]
- #[inline(always)]
- pub fn disable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::DISABLE_PULL_DOWN)
- }
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::ENABLE_PULL_DOWN)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPUNW::ENABLE_PULL_UP => false,
- EPUNW::DISABLE_PULL_UP => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPUNW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPUNW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPUNW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::ENABLE_PULL_UP)
- }
- #[doc = "Disable pull-up."]
- #[inline(always)]
- pub fn disable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::DISABLE_PULL_UP)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EHS`"]
- pub enum EHSW {
- #[doc = "Fast (low noise with fast speed)"] FAST_LOW_NOISE_WITH,
- #[doc = "High-speed (medium noise with high speed)"]
- HIGH_SPEED_MEDIUM_N,
- }
- impl EHSW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EHSW::FAST_LOW_NOISE_WITH => false,
- EHSW::HIGH_SPEED_MEDIUM_N => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EHSW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EHSW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EHSW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Fast (low noise with fast speed)"]
- #[inline(always)]
- pub fn fast_low_noise_with(self) -> &'a mut W {
- self.variant(EHSW::FAST_LOW_NOISE_WITH)
- }
- #[doc = "High-speed (medium noise with high speed)"]
- #[inline(always)]
- pub fn high_speed_medium_n(self) -> &'a mut W {
- self.variant(EHSW::HIGH_SPEED_MEDIUM_N)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EZI`"]
- pub enum EZIW {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EZIW::DISABLE_INPUT_BUFFER => false,
- EZIW::ENABLE_INPUT_BUFFER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EZIW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EZIW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EZIW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable input buffer"]
- #[inline(always)]
- pub fn disable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::DISABLE_INPUT_BUFFER)
- }
- #[doc = "Enable input buffer"]
- #[inline(always)]
- pub fn enable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::ENABLE_INPUT_BUFFER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `ZIF`"]
- pub enum ZIFW {
- #[doc = "Enable input filter"] ENABLE_INPUT_FILTER,
- #[doc = "Disable input filter"] DISABLE_INPUT_FILTER,
- }
- impl ZIFW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- ZIFW::ENABLE_INPUT_FILTER => false,
- ZIFW::DISABLE_INPUT_FILTER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _ZIFW<'a> {
- w: &'a mut W,
- }
- impl<'a> _ZIFW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: ZIFW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable input filter"]
- #[inline(always)]
- pub fn enable_input_filter(self) -> &'a mut W {
- self.variant(ZIFW::ENABLE_INPUT_FILTER)
- }
- #[doc = "Disable input filter"]
- #[inline(always)]
- pub fn disable_input_filter(self) -> &'a mut W {
- self.variant(ZIFW::DISABLE_INPUT_FILTER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- impl R {
- #[doc = r" Value of the register as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u32 {
- self.bits
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&self) -> MODER {
- MODER::_from({
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&self) -> EPDR {
- EPDR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&self) -> EPUNR {
- EPUNR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 5 - Slew rate"]
- #[inline(always)]
- pub fn ehs(&self) -> EHSR {
- EHSR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&self) -> EZIR {
- EZIR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&self) -> ZIFR {
- ZIFR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- }
- impl W {
- #[doc = r" Reset value of the register"]
- #[inline(always)]
- pub fn reset_value() -> W {
- W { bits: 0 }
- }
- #[doc = r" Writes raw bits to the register"]
- #[inline(always)]
- pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.bits = bits;
- self
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&mut self) -> _MODEW {
- _MODEW { w: self }
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&mut self) -> _EPDW {
- _EPDW { w: self }
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&mut self) -> _EPUNW {
- _EPUNW { w: self }
- }
- #[doc = "Bit 5 - Slew rate"]
- #[inline(always)]
- pub fn ehs(&mut self) -> _EHSW {
- _EHSW { w: self }
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&mut self) -> _EZIW {
- _EZIW { w: self }
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&mut self) -> _ZIFW {
- _ZIFW { w: self }
- }
- }
- }
- #[doc = "Pin configuration register for pins P3"]
- pub struct SFSP3_ {
- register: VolatileCell<u32>,
- }
- #[doc = "Pin configuration register for pins P3"]
- pub mod sfsp3_ {
- #[doc = r" Value read from the register"]
- pub struct R {
- bits: u32,
- }
- #[doc = r" Value to write to the register"]
- pub struct W {
- bits: u32,
- }
- impl super::SFSP3_ {
- #[doc = r" Modifies the contents of the register"]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
- {
- let bits = self.register.get();
- let r = R { bits: bits };
- let mut w = W { bits: bits };
- f(&r, &mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Reads the contents of the register"]
- #[inline(always)]
- pub fn read(&self) -> R {
- R {
- bits: self.register.get(),
- }
- }
- #[doc = r" Writes to the register"]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W::reset_value();
- f(&mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Writes the reset value to the register"]
- #[inline(always)]
- pub fn reset(&self) {
- self.write(|w| w)
- }
- }
- #[doc = "Possible values of the field `MODE`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODER {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODER {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- MODER::FUNCTION_0_DEFAULT => 0,
- MODER::FUNCTION_1 => 1,
- MODER::FUNCTION_2 => 2,
- MODER::FUNCTION_3 => 3,
- MODER::FUNCTION_4 => 4,
- MODER::FUNCTION_5 => 5,
- MODER::FUNCTION_6 => 6,
- MODER::FUNCTION_7 => 7,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> MODER {
- match value {
- 0 => MODER::FUNCTION_0_DEFAULT,
- 1 => MODER::FUNCTION_1,
- 2 => MODER::FUNCTION_2,
- 3 => MODER::FUNCTION_3,
- 4 => MODER::FUNCTION_4,
- 5 => MODER::FUNCTION_5,
- 6 => MODER::FUNCTION_6,
- 7 => MODER::FUNCTION_7,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `FUNCTION_0_DEFAULT`"]
- #[inline(always)]
- pub fn is_function_0_default(&self) -> bool {
- *self == MODER::FUNCTION_0_DEFAULT
- }
- #[doc = "Checks if the value of the field is `FUNCTION_1`"]
- #[inline(always)]
- pub fn is_function_1(&self) -> bool {
- *self == MODER::FUNCTION_1
- }
- #[doc = "Checks if the value of the field is `FUNCTION_2`"]
- #[inline(always)]
- pub fn is_function_2(&self) -> bool {
- *self == MODER::FUNCTION_2
- }
- #[doc = "Checks if the value of the field is `FUNCTION_3`"]
- #[inline(always)]
- pub fn is_function_3(&self) -> bool {
- *self == MODER::FUNCTION_3
- }
- #[doc = "Checks if the value of the field is `FUNCTION_4`"]
- #[inline(always)]
- pub fn is_function_4(&self) -> bool {
- *self == MODER::FUNCTION_4
- }
- #[doc = "Checks if the value of the field is `FUNCTION_5`"]
- #[inline(always)]
- pub fn is_function_5(&self) -> bool {
- *self == MODER::FUNCTION_5
- }
- #[doc = "Checks if the value of the field is `FUNCTION_6`"]
- #[inline(always)]
- pub fn is_function_6(&self) -> bool {
- *self == MODER::FUNCTION_6
- }
- #[doc = "Checks if the value of the field is `FUNCTION_7`"]
- #[inline(always)]
- pub fn is_function_7(&self) -> bool {
- *self == MODER::FUNCTION_7
- }
- }
- #[doc = "Possible values of the field `EPD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPDR::DISABLE_PULL_DOWN => false,
- EPDR::ENABLE_PULL_DOWN => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPDR {
- match value {
- false => EPDR::DISABLE_PULL_DOWN,
- true => EPDR::ENABLE_PULL_DOWN,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_disable_pull_down(&self) -> bool {
- *self == EPDR::DISABLE_PULL_DOWN
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_enable_pull_down(&self) -> bool {
- *self == EPDR::ENABLE_PULL_DOWN
- }
- }
- #[doc = "Possible values of the field `EPUN`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPUNR::ENABLE_PULL_UP => false,
- EPUNR::DISABLE_PULL_UP => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPUNR {
- match value {
- false => EPUNR::ENABLE_PULL_UP,
- true => EPUNR::DISABLE_PULL_UP,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_enable_pull_up(&self) -> bool {
- *self == EPUNR::ENABLE_PULL_UP
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_disable_pull_up(&self) -> bool {
- *self == EPUNR::DISABLE_PULL_UP
- }
- }
- #[doc = "Possible values of the field `EHS`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHSR {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EHSR::SLOW_LOW_NOISE_WITH => false,
- EHSR::FAST_MEDIUM_NOISE_W => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EHSR {
- match value {
- false => EHSR::SLOW_LOW_NOISE_WITH,
- true => EHSR::FAST_MEDIUM_NOISE_W,
- }
- }
- #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
- #[inline(always)]
- pub fn is_slow_low_noise_with(&self) -> bool {
- *self == EHSR::SLOW_LOW_NOISE_WITH
- }
- #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
- #[inline(always)]
- pub fn is_fast_medium_noise_w(&self) -> bool {
- *self == EHSR::FAST_MEDIUM_NOISE_W
- }
- }
- #[doc = "Possible values of the field `EZI`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EZIR {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EZIR::DISABLE_INPUT_BUFFER => false,
- EZIR::ENABLE_INPUT_BUFFER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EZIR {
- match value {
- false => EZIR::DISABLE_INPUT_BUFFER,
- true => EZIR::ENABLE_INPUT_BUFFER,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_disable_input_buffer(&self) -> bool {
- *self == EZIR::DISABLE_INPUT_BUFFER
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_enable_input_buffer(&self) -> bool {
- *self == EZIR::ENABLE_INPUT_BUFFER
- }
- }
- #[doc = "Possible values of the field `ZIF`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ZIFR {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- ZIFR::ENABLE_INPUT_GLITCH => false,
- ZIFR::DISABLE_INPUT_GLITCH => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> ZIFR {
- match value {
- false => ZIFR::ENABLE_INPUT_GLITCH,
- true => ZIFR::DISABLE_INPUT_GLITCH,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_enable_input_glitch(&self) -> bool {
- *self == ZIFR::ENABLE_INPUT_GLITCH
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_disable_input_glitch(&self) -> bool {
- *self == ZIFR::DISABLE_INPUT_GLITCH
- }
- }
- #[doc = "Values that can be written to the field `MODE`"]
- pub enum MODEW {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODEW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- MODEW::FUNCTION_0_DEFAULT => 0,
- MODEW::FUNCTION_1 => 1,
- MODEW::FUNCTION_2 => 2,
- MODEW::FUNCTION_3 => 3,
- MODEW::FUNCTION_4 => 4,
- MODEW::FUNCTION_5 => 5,
- MODEW::FUNCTION_6 => 6,
- MODEW::FUNCTION_7 => 7,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _MODEW<'a> {
- w: &'a mut W,
- }
- impl<'a> _MODEW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: MODEW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Function 0 (default)"]
- #[inline(always)]
- pub fn function_0_default(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_0_DEFAULT)
- }
- #[doc = "Function 1"]
- #[inline(always)]
- pub fn function_1(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_1)
- }
- #[doc = "Function 2"]
- #[inline(always)]
- pub fn function_2(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_2)
- }
- #[doc = "Function 3"]
- #[inline(always)]
- pub fn function_3(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_3)
- }
- #[doc = "Function 4"]
- #[inline(always)]
- pub fn function_4(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_4)
- }
- #[doc = "Function 5"]
- #[inline(always)]
- pub fn function_5(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_5)
- }
- #[doc = "Function 6"]
- #[inline(always)]
- pub fn function_6(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_6)
- }
- #[doc = "Function 7"]
- #[inline(always)]
- pub fn function_7(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_7)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPDW::DISABLE_PULL_DOWN => false,
- EPDW::ENABLE_PULL_DOWN => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPDW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable pull-down."]
- #[inline(always)]
- pub fn disable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::DISABLE_PULL_DOWN)
- }
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::ENABLE_PULL_DOWN)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPUNW::ENABLE_PULL_UP => false,
- EPUNW::DISABLE_PULL_UP => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPUNW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPUNW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPUNW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::ENABLE_PULL_UP)
- }
- #[doc = "Disable pull-up."]
- #[inline(always)]
- pub fn disable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::DISABLE_PULL_UP)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EHS`"]
- pub enum EHSW {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EHSW::SLOW_LOW_NOISE_WITH => false,
- EHSW::FAST_MEDIUM_NOISE_W => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EHSW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EHSW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EHSW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Slow (low noise with medium speed)"]
- #[inline(always)]
- pub fn slow_low_noise_with(self) -> &'a mut W {
- self.variant(EHSW::SLOW_LOW_NOISE_WITH)
- }
- #[doc = "Fast (medium noise with fast speed)"]
- #[inline(always)]
- pub fn fast_medium_noise_w(self) -> &'a mut W {
- self.variant(EHSW::FAST_MEDIUM_NOISE_W)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EZI`"]
- pub enum EZIW {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EZIW::DISABLE_INPUT_BUFFER => false,
- EZIW::ENABLE_INPUT_BUFFER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EZIW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EZIW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EZIW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable input buffer"]
- #[inline(always)]
- pub fn disable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::DISABLE_INPUT_BUFFER)
- }
- #[doc = "Enable input buffer"]
- #[inline(always)]
- pub fn enable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::ENABLE_INPUT_BUFFER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `ZIF`"]
- pub enum ZIFW {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- ZIFW::ENABLE_INPUT_GLITCH => false,
- ZIFW::DISABLE_INPUT_GLITCH => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _ZIFW<'a> {
- w: &'a mut W,
- }
- impl<'a> _ZIFW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: ZIFW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable input glitch filter"]
- #[inline(always)]
- pub fn enable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::ENABLE_INPUT_GLITCH)
- }
- #[doc = "Disable input glitch filter"]
- #[inline(always)]
- pub fn disable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::DISABLE_INPUT_GLITCH)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- impl R {
- #[doc = r" Value of the register as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u32 {
- self.bits
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&self) -> MODER {
- MODER::_from({
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&self) -> EPDR {
- EPDR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&self) -> EPUNR {
- EPUNR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&self) -> EHSR {
- EHSR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&self) -> EZIR {
- EZIR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&self) -> ZIFR {
- ZIFR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- }
- impl W {
- #[doc = r" Reset value of the register"]
- #[inline(always)]
- pub fn reset_value() -> W {
- W { bits: 0 }
- }
- #[doc = r" Writes raw bits to the register"]
- #[inline(always)]
- pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.bits = bits;
- self
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&mut self) -> _MODEW {
- _MODEW { w: self }
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&mut self) -> _EPDW {
- _EPDW { w: self }
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&mut self) -> _EPUNW {
- _EPUNW { w: self }
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&mut self) -> _EHSW {
- _EHSW { w: self }
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&mut self) -> _EZIW {
- _EZIW { w: self }
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&mut self) -> _ZIFW {
- _ZIFW { w: self }
- }
- }
- }
- #[doc = "Pin configuration register for pins P4"]
- pub struct SFSP4_ {
- register: VolatileCell<u32>,
- }
- #[doc = "Pin configuration register for pins P4"]
- pub mod sfsp4_ {
- #[doc = r" Value read from the register"]
- pub struct R {
- bits: u32,
- }
- #[doc = r" Value to write to the register"]
- pub struct W {
- bits: u32,
- }
- impl super::SFSP4_ {
- #[doc = r" Modifies the contents of the register"]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
- {
- let bits = self.register.get();
- let r = R { bits: bits };
- let mut w = W { bits: bits };
- f(&r, &mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Reads the contents of the register"]
- #[inline(always)]
- pub fn read(&self) -> R {
- R {
- bits: self.register.get(),
- }
- }
- #[doc = r" Writes to the register"]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W::reset_value();
- f(&mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Writes the reset value to the register"]
- #[inline(always)]
- pub fn reset(&self) {
- self.write(|w| w)
- }
- }
- #[doc = "Possible values of the field `MODE`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODER {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODER {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- MODER::FUNCTION_0_DEFAULT => 0,
- MODER::FUNCTION_1 => 1,
- MODER::FUNCTION_2 => 2,
- MODER::FUNCTION_3 => 3,
- MODER::FUNCTION_4 => 4,
- MODER::FUNCTION_5 => 5,
- MODER::FUNCTION_6 => 6,
- MODER::FUNCTION_7 => 7,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> MODER {
- match value {
- 0 => MODER::FUNCTION_0_DEFAULT,
- 1 => MODER::FUNCTION_1,
- 2 => MODER::FUNCTION_2,
- 3 => MODER::FUNCTION_3,
- 4 => MODER::FUNCTION_4,
- 5 => MODER::FUNCTION_5,
- 6 => MODER::FUNCTION_6,
- 7 => MODER::FUNCTION_7,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `FUNCTION_0_DEFAULT`"]
- #[inline(always)]
- pub fn is_function_0_default(&self) -> bool {
- *self == MODER::FUNCTION_0_DEFAULT
- }
- #[doc = "Checks if the value of the field is `FUNCTION_1`"]
- #[inline(always)]
- pub fn is_function_1(&self) -> bool {
- *self == MODER::FUNCTION_1
- }
- #[doc = "Checks if the value of the field is `FUNCTION_2`"]
- #[inline(always)]
- pub fn is_function_2(&self) -> bool {
- *self == MODER::FUNCTION_2
- }
- #[doc = "Checks if the value of the field is `FUNCTION_3`"]
- #[inline(always)]
- pub fn is_function_3(&self) -> bool {
- *self == MODER::FUNCTION_3
- }
- #[doc = "Checks if the value of the field is `FUNCTION_4`"]
- #[inline(always)]
- pub fn is_function_4(&self) -> bool {
- *self == MODER::FUNCTION_4
- }
- #[doc = "Checks if the value of the field is `FUNCTION_5`"]
- #[inline(always)]
- pub fn is_function_5(&self) -> bool {
- *self == MODER::FUNCTION_5
- }
- #[doc = "Checks if the value of the field is `FUNCTION_6`"]
- #[inline(always)]
- pub fn is_function_6(&self) -> bool {
- *self == MODER::FUNCTION_6
- }
- #[doc = "Checks if the value of the field is `FUNCTION_7`"]
- #[inline(always)]
- pub fn is_function_7(&self) -> bool {
- *self == MODER::FUNCTION_7
- }
- }
- #[doc = "Possible values of the field `EPD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPDR::DISABLE_PULL_DOWN => false,
- EPDR::ENABLE_PULL_DOWN => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPDR {
- match value {
- false => EPDR::DISABLE_PULL_DOWN,
- true => EPDR::ENABLE_PULL_DOWN,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_disable_pull_down(&self) -> bool {
- *self == EPDR::DISABLE_PULL_DOWN
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_enable_pull_down(&self) -> bool {
- *self == EPDR::ENABLE_PULL_DOWN
- }
- }
- #[doc = "Possible values of the field `EPUN`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPUNR::ENABLE_PULL_UP => false,
- EPUNR::DISABLE_PULL_UP => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPUNR {
- match value {
- false => EPUNR::ENABLE_PULL_UP,
- true => EPUNR::DISABLE_PULL_UP,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_enable_pull_up(&self) -> bool {
- *self == EPUNR::ENABLE_PULL_UP
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_disable_pull_up(&self) -> bool {
- *self == EPUNR::DISABLE_PULL_UP
- }
- }
- #[doc = "Possible values of the field `EHS`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHSR {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EHSR::SLOW_LOW_NOISE_WITH => false,
- EHSR::FAST_MEDIUM_NOISE_W => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EHSR {
- match value {
- false => EHSR::SLOW_LOW_NOISE_WITH,
- true => EHSR::FAST_MEDIUM_NOISE_W,
- }
- }
- #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
- #[inline(always)]
- pub fn is_slow_low_noise_with(&self) -> bool {
- *self == EHSR::SLOW_LOW_NOISE_WITH
- }
- #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
- #[inline(always)]
- pub fn is_fast_medium_noise_w(&self) -> bool {
- *self == EHSR::FAST_MEDIUM_NOISE_W
- }
- }
- #[doc = "Possible values of the field `EZI`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EZIR {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EZIR::DISABLE_INPUT_BUFFER => false,
- EZIR::ENABLE_INPUT_BUFFER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EZIR {
- match value {
- false => EZIR::DISABLE_INPUT_BUFFER,
- true => EZIR::ENABLE_INPUT_BUFFER,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_disable_input_buffer(&self) -> bool {
- *self == EZIR::DISABLE_INPUT_BUFFER
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_enable_input_buffer(&self) -> bool {
- *self == EZIR::ENABLE_INPUT_BUFFER
- }
- }
- #[doc = "Possible values of the field `ZIF`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ZIFR {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- ZIFR::ENABLE_INPUT_GLITCH => false,
- ZIFR::DISABLE_INPUT_GLITCH => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> ZIFR {
- match value {
- false => ZIFR::ENABLE_INPUT_GLITCH,
- true => ZIFR::DISABLE_INPUT_GLITCH,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_enable_input_glitch(&self) -> bool {
- *self == ZIFR::ENABLE_INPUT_GLITCH
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_disable_input_glitch(&self) -> bool {
- *self == ZIFR::DISABLE_INPUT_GLITCH
- }
- }
- #[doc = "Values that can be written to the field `MODE`"]
- pub enum MODEW {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODEW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- MODEW::FUNCTION_0_DEFAULT => 0,
- MODEW::FUNCTION_1 => 1,
- MODEW::FUNCTION_2 => 2,
- MODEW::FUNCTION_3 => 3,
- MODEW::FUNCTION_4 => 4,
- MODEW::FUNCTION_5 => 5,
- MODEW::FUNCTION_6 => 6,
- MODEW::FUNCTION_7 => 7,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _MODEW<'a> {
- w: &'a mut W,
- }
- impl<'a> _MODEW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: MODEW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Function 0 (default)"]
- #[inline(always)]
- pub fn function_0_default(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_0_DEFAULT)
- }
- #[doc = "Function 1"]
- #[inline(always)]
- pub fn function_1(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_1)
- }
- #[doc = "Function 2"]
- #[inline(always)]
- pub fn function_2(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_2)
- }
- #[doc = "Function 3"]
- #[inline(always)]
- pub fn function_3(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_3)
- }
- #[doc = "Function 4"]
- #[inline(always)]
- pub fn function_4(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_4)
- }
- #[doc = "Function 5"]
- #[inline(always)]
- pub fn function_5(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_5)
- }
- #[doc = "Function 6"]
- #[inline(always)]
- pub fn function_6(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_6)
- }
- #[doc = "Function 7"]
- #[inline(always)]
- pub fn function_7(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_7)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPDW::DISABLE_PULL_DOWN => false,
- EPDW::ENABLE_PULL_DOWN => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPDW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable pull-down."]
- #[inline(always)]
- pub fn disable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::DISABLE_PULL_DOWN)
- }
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::ENABLE_PULL_DOWN)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPUNW::ENABLE_PULL_UP => false,
- EPUNW::DISABLE_PULL_UP => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPUNW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPUNW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPUNW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::ENABLE_PULL_UP)
- }
- #[doc = "Disable pull-up."]
- #[inline(always)]
- pub fn disable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::DISABLE_PULL_UP)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EHS`"]
- pub enum EHSW {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EHSW::SLOW_LOW_NOISE_WITH => false,
- EHSW::FAST_MEDIUM_NOISE_W => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EHSW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EHSW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EHSW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Slow (low noise with medium speed)"]
- #[inline(always)]
- pub fn slow_low_noise_with(self) -> &'a mut W {
- self.variant(EHSW::SLOW_LOW_NOISE_WITH)
- }
- #[doc = "Fast (medium noise with fast speed)"]
- #[inline(always)]
- pub fn fast_medium_noise_w(self) -> &'a mut W {
- self.variant(EHSW::FAST_MEDIUM_NOISE_W)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EZI`"]
- pub enum EZIW {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EZIW::DISABLE_INPUT_BUFFER => false,
- EZIW::ENABLE_INPUT_BUFFER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EZIW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EZIW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EZIW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable input buffer"]
- #[inline(always)]
- pub fn disable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::DISABLE_INPUT_BUFFER)
- }
- #[doc = "Enable input buffer"]
- #[inline(always)]
- pub fn enable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::ENABLE_INPUT_BUFFER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `ZIF`"]
- pub enum ZIFW {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- ZIFW::ENABLE_INPUT_GLITCH => false,
- ZIFW::DISABLE_INPUT_GLITCH => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _ZIFW<'a> {
- w: &'a mut W,
- }
- impl<'a> _ZIFW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: ZIFW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable input glitch filter"]
- #[inline(always)]
- pub fn enable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::ENABLE_INPUT_GLITCH)
- }
- #[doc = "Disable input glitch filter"]
- #[inline(always)]
- pub fn disable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::DISABLE_INPUT_GLITCH)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- impl R {
- #[doc = r" Value of the register as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u32 {
- self.bits
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&self) -> MODER {
- MODER::_from({
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&self) -> EPDR {
- EPDR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&self) -> EPUNR {
- EPUNR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&self) -> EHSR {
- EHSR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&self) -> EZIR {
- EZIR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&self) -> ZIFR {
- ZIFR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- }
- impl W {
- #[doc = r" Reset value of the register"]
- #[inline(always)]
- pub fn reset_value() -> W {
- W { bits: 0 }
- }
- #[doc = r" Writes raw bits to the register"]
- #[inline(always)]
- pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.bits = bits;
- self
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&mut self) -> _MODEW {
- _MODEW { w: self }
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&mut self) -> _EPDW {
- _EPDW { w: self }
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&mut self) -> _EPUNW {
- _EPUNW { w: self }
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&mut self) -> _EHSW {
- _EHSW { w: self }
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&mut self) -> _EZIW {
- _EZIW { w: self }
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&mut self) -> _ZIFW {
- _ZIFW { w: self }
- }
- }
- }
- #[doc = "Pin configuration register for pins P5"]
- pub struct SFSP5_ {
- register: VolatileCell<u32>,
- }
- #[doc = "Pin configuration register for pins P5"]
- pub mod sfsp5_ {
- #[doc = r" Value read from the register"]
- pub struct R {
- bits: u32,
- }
- #[doc = r" Value to write to the register"]
- pub struct W {
- bits: u32,
- }
- impl super::SFSP5_ {
- #[doc = r" Modifies the contents of the register"]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
- {
- let bits = self.register.get();
- let r = R { bits: bits };
- let mut w = W { bits: bits };
- f(&r, &mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Reads the contents of the register"]
- #[inline(always)]
- pub fn read(&self) -> R {
- R {
- bits: self.register.get(),
- }
- }
- #[doc = r" Writes to the register"]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W::reset_value();
- f(&mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Writes the reset value to the register"]
- #[inline(always)]
- pub fn reset(&self) {
- self.write(|w| w)
- }
- }
- #[doc = "Possible values of the field `MODE`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODER {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODER {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- MODER::FUNCTION_0_DEFAULT => 0,
- MODER::FUNCTION_1 => 1,
- MODER::FUNCTION_2 => 2,
- MODER::FUNCTION_3 => 3,
- MODER::FUNCTION_4 => 4,
- MODER::FUNCTION_5 => 5,
- MODER::FUNCTION_6 => 6,
- MODER::FUNCTION_7 => 7,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> MODER {
- match value {
- 0 => MODER::FUNCTION_0_DEFAULT,
- 1 => MODER::FUNCTION_1,
- 2 => MODER::FUNCTION_2,
- 3 => MODER::FUNCTION_3,
- 4 => MODER::FUNCTION_4,
- 5 => MODER::FUNCTION_5,
- 6 => MODER::FUNCTION_6,
- 7 => MODER::FUNCTION_7,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `FUNCTION_0_DEFAULT`"]
- #[inline(always)]
- pub fn is_function_0_default(&self) -> bool {
- *self == MODER::FUNCTION_0_DEFAULT
- }
- #[doc = "Checks if the value of the field is `FUNCTION_1`"]
- #[inline(always)]
- pub fn is_function_1(&self) -> bool {
- *self == MODER::FUNCTION_1
- }
- #[doc = "Checks if the value of the field is `FUNCTION_2`"]
- #[inline(always)]
- pub fn is_function_2(&self) -> bool {
- *self == MODER::FUNCTION_2
- }
- #[doc = "Checks if the value of the field is `FUNCTION_3`"]
- #[inline(always)]
- pub fn is_function_3(&self) -> bool {
- *self == MODER::FUNCTION_3
- }
- #[doc = "Checks if the value of the field is `FUNCTION_4`"]
- #[inline(always)]
- pub fn is_function_4(&self) -> bool {
- *self == MODER::FUNCTION_4
- }
- #[doc = "Checks if the value of the field is `FUNCTION_5`"]
- #[inline(always)]
- pub fn is_function_5(&self) -> bool {
- *self == MODER::FUNCTION_5
- }
- #[doc = "Checks if the value of the field is `FUNCTION_6`"]
- #[inline(always)]
- pub fn is_function_6(&self) -> bool {
- *self == MODER::FUNCTION_6
- }
- #[doc = "Checks if the value of the field is `FUNCTION_7`"]
- #[inline(always)]
- pub fn is_function_7(&self) -> bool {
- *self == MODER::FUNCTION_7
- }
- }
- #[doc = "Possible values of the field `EPD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPDR::DISABLE_PULL_DOWN => false,
- EPDR::ENABLE_PULL_DOWN => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPDR {
- match value {
- false => EPDR::DISABLE_PULL_DOWN,
- true => EPDR::ENABLE_PULL_DOWN,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_disable_pull_down(&self) -> bool {
- *self == EPDR::DISABLE_PULL_DOWN
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_enable_pull_down(&self) -> bool {
- *self == EPDR::ENABLE_PULL_DOWN
- }
- }
- #[doc = "Possible values of the field `EPUN`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPUNR::ENABLE_PULL_UP => false,
- EPUNR::DISABLE_PULL_UP => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPUNR {
- match value {
- false => EPUNR::ENABLE_PULL_UP,
- true => EPUNR::DISABLE_PULL_UP,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_enable_pull_up(&self) -> bool {
- *self == EPUNR::ENABLE_PULL_UP
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_disable_pull_up(&self) -> bool {
- *self == EPUNR::DISABLE_PULL_UP
- }
- }
- #[doc = "Possible values of the field `EHS`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHSR {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EHSR::SLOW_LOW_NOISE_WITH => false,
- EHSR::FAST_MEDIUM_NOISE_W => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EHSR {
- match value {
- false => EHSR::SLOW_LOW_NOISE_WITH,
- true => EHSR::FAST_MEDIUM_NOISE_W,
- }
- }
- #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
- #[inline(always)]
- pub fn is_slow_low_noise_with(&self) -> bool {
- *self == EHSR::SLOW_LOW_NOISE_WITH
- }
- #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
- #[inline(always)]
- pub fn is_fast_medium_noise_w(&self) -> bool {
- *self == EHSR::FAST_MEDIUM_NOISE_W
- }
- }
- #[doc = "Possible values of the field `EZI`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EZIR {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EZIR::DISABLE_INPUT_BUFFER => false,
- EZIR::ENABLE_INPUT_BUFFER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EZIR {
- match value {
- false => EZIR::DISABLE_INPUT_BUFFER,
- true => EZIR::ENABLE_INPUT_BUFFER,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_disable_input_buffer(&self) -> bool {
- *self == EZIR::DISABLE_INPUT_BUFFER
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_enable_input_buffer(&self) -> bool {
- *self == EZIR::ENABLE_INPUT_BUFFER
- }
- }
- #[doc = "Possible values of the field `ZIF`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ZIFR {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- ZIFR::ENABLE_INPUT_GLITCH => false,
- ZIFR::DISABLE_INPUT_GLITCH => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> ZIFR {
- match value {
- false => ZIFR::ENABLE_INPUT_GLITCH,
- true => ZIFR::DISABLE_INPUT_GLITCH,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_enable_input_glitch(&self) -> bool {
- *self == ZIFR::ENABLE_INPUT_GLITCH
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_disable_input_glitch(&self) -> bool {
- *self == ZIFR::DISABLE_INPUT_GLITCH
- }
- }
- #[doc = "Values that can be written to the field `MODE`"]
- pub enum MODEW {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODEW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- MODEW::FUNCTION_0_DEFAULT => 0,
- MODEW::FUNCTION_1 => 1,
- MODEW::FUNCTION_2 => 2,
- MODEW::FUNCTION_3 => 3,
- MODEW::FUNCTION_4 => 4,
- MODEW::FUNCTION_5 => 5,
- MODEW::FUNCTION_6 => 6,
- MODEW::FUNCTION_7 => 7,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _MODEW<'a> {
- w: &'a mut W,
- }
- impl<'a> _MODEW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: MODEW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Function 0 (default)"]
- #[inline(always)]
- pub fn function_0_default(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_0_DEFAULT)
- }
- #[doc = "Function 1"]
- #[inline(always)]
- pub fn function_1(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_1)
- }
- #[doc = "Function 2"]
- #[inline(always)]
- pub fn function_2(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_2)
- }
- #[doc = "Function 3"]
- #[inline(always)]
- pub fn function_3(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_3)
- }
- #[doc = "Function 4"]
- #[inline(always)]
- pub fn function_4(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_4)
- }
- #[doc = "Function 5"]
- #[inline(always)]
- pub fn function_5(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_5)
- }
- #[doc = "Function 6"]
- #[inline(always)]
- pub fn function_6(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_6)
- }
- #[doc = "Function 7"]
- #[inline(always)]
- pub fn function_7(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_7)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPDW::DISABLE_PULL_DOWN => false,
- EPDW::ENABLE_PULL_DOWN => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPDW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPDW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPDW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable pull-down."]
- #[inline(always)]
- pub fn disable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::DISABLE_PULL_DOWN)
- }
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_down(self) -> &'a mut W {
- self.variant(EPDW::ENABLE_PULL_DOWN)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EPUNW::ENABLE_PULL_UP => false,
- EPUNW::DISABLE_PULL_UP => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EPUNW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EPUNW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EPUNW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
- pub fn enable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::ENABLE_PULL_UP)
- }
- #[doc = "Disable pull-up."]
- #[inline(always)]
- pub fn disable_pull_up(self) -> &'a mut W {
- self.variant(EPUNW::DISABLE_PULL_UP)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EHS`"]
- pub enum EHSW {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EHSW::SLOW_LOW_NOISE_WITH => false,
- EHSW::FAST_MEDIUM_NOISE_W => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EHSW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EHSW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EHSW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Slow (low noise with medium speed)"]
- #[inline(always)]
- pub fn slow_low_noise_with(self) -> &'a mut W {
- self.variant(EHSW::SLOW_LOW_NOISE_WITH)
- }
- #[doc = "Fast (medium noise with fast speed)"]
- #[inline(always)]
- pub fn fast_medium_noise_w(self) -> &'a mut W {
- self.variant(EHSW::FAST_MEDIUM_NOISE_W)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EZI`"]
- pub enum EZIW {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- EZIW::DISABLE_INPUT_BUFFER => false,
- EZIW::ENABLE_INPUT_BUFFER => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _EZIW<'a> {
- w: &'a mut W,
- }
- impl<'a> _EZIW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: EZIW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Disable input buffer"]
- #[inline(always)]
- pub fn disable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::DISABLE_INPUT_BUFFER)
- }
- #[doc = "Enable input buffer"]
- #[inline(always)]
- pub fn enable_input_buffer(self) -> &'a mut W {
- self.variant(EZIW::ENABLE_INPUT_BUFFER)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `ZIF`"]
- pub enum ZIFW {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> bool {
- match *self {
- ZIFW::ENABLE_INPUT_GLITCH => false,
- ZIFW::DISABLE_INPUT_GLITCH => true,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _ZIFW<'a> {
- w: &'a mut W,
- }
- impl<'a> _ZIFW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: ZIFW) -> &'a mut W {
- {
- self.bit(variant._bits())
- }
- }
- #[doc = "Enable input glitch filter"]
- #[inline(always)]
- pub fn enable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::ENABLE_INPUT_GLITCH)
- }
- #[doc = "Disable input glitch filter"]
- #[inline(always)]
- pub fn disable_input_glitch(self) -> &'a mut W {
- self.variant(ZIFW::DISABLE_INPUT_GLITCH)
- }
- #[doc = r" Sets the field bit"]
- pub fn set_bit(self) -> &'a mut W {
- self.bit(true)
- }
- #[doc = r" Clears the field bit"]
- pub fn clear_bit(self) -> &'a mut W {
- self.bit(false)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bit(self, value: bool) -> &'a mut W {
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- impl R {
- #[doc = r" Value of the register as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u32 {
- self.bits
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&self) -> MODER {
- MODER::_from({
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- ((self.bits >> OFFSET) & MASK as u32) as u8
- })
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&self) -> EPDR {
- EPDR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 3;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&self) -> EPUNR {
- EPUNR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 4;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&self) -> EHSR {
- EHSR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 5;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&self) -> EZIR {
- EZIR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 6;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&self) -> ZIFR {
- ZIFR::_from({
- const MASK: bool = true;
- const OFFSET: u8 = 7;
- ((self.bits >> OFFSET) & MASK as u32) != 0
- })
- }
- }
- impl W {
- #[doc = r" Reset value of the register"]
- #[inline(always)]
- pub fn reset_value() -> W {
- W { bits: 0 }
- }
- #[doc = r" Writes raw bits to the register"]
- #[inline(always)]
- pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.bits = bits;
- self
- }
- #[doc = "Bits 0:2 - Select pin function."]
- #[inline(always)]
- pub fn mode(&mut self) -> _MODEW {
- _MODEW { w: self }
- }
- #[doc = "Bit 3 - Enable pull-down resistor at pad."]
- #[inline(always)]
- pub fn epd(&mut self) -> _EPDW {
- _EPDW { w: self }
- }
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
- pub fn epun(&mut self) -> _EPUNW {
- _EPUNW { w: self }
- }
- #[doc = "Bit 5 - Select Slew rate."]
- #[inline(always)]
- pub fn ehs(&mut self) -> _EHSW {
- _EHSW { w: self }
- }
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
- pub fn ezi(&mut self) -> _EZIW {
- _EZIW { w: self }
- }
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
- pub fn zif(&mut self) -> _ZIFW {
- _ZIFW { w: self }
- }
- }
- }
- #[doc = "Pin configuration register for pins P6"]
- pub struct SFSP6_ {
- register: VolatileCell<u32>,
- }
- #[doc = "Pin configuration register for pins P6"]
- pub mod sfsp6_ {
- #[doc = r" Value read from the register"]
- pub struct R {
- bits: u32,
- }
- #[doc = r" Value to write to the register"]
- pub struct W {
- bits: u32,
- }
- impl super::SFSP6_ {
- #[doc = r" Modifies the contents of the register"]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
- {
- let bits = self.register.get();
- let r = R { bits: bits };
- let mut w = W { bits: bits };
- f(&r, &mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Reads the contents of the register"]
- #[inline(always)]
- pub fn read(&self) -> R {
- R {
- bits: self.register.get(),
- }
- }
- #[doc = r" Writes to the register"]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W::reset_value();
- f(&mut w);
- self.register.set(w.bits);
- }
- #[doc = r" Writes the reset value to the register"]
- #[inline(always)]
- pub fn reset(&self) {
- self.write(|w| w)
- }
- }
- #[doc = "Possible values of the field `MODE`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MODER {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODER {
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bits(&self) -> u8 {
- match *self {
- MODER::FUNCTION_0_DEFAULT => 0,
- MODER::FUNCTION_1 => 1,
- MODER::FUNCTION_2 => 2,
- MODER::FUNCTION_3 => 3,
- MODER::FUNCTION_4 => 4,
- MODER::FUNCTION_5 => 5,
- MODER::FUNCTION_6 => 6,
- MODER::FUNCTION_7 => 7,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: u8) -> MODER {
- match value {
- 0 => MODER::FUNCTION_0_DEFAULT,
- 1 => MODER::FUNCTION_1,
- 2 => MODER::FUNCTION_2,
- 3 => MODER::FUNCTION_3,
- 4 => MODER::FUNCTION_4,
- 5 => MODER::FUNCTION_5,
- 6 => MODER::FUNCTION_6,
- 7 => MODER::FUNCTION_7,
- _ => unreachable!(),
- }
- }
- #[doc = "Checks if the value of the field is `FUNCTION_0_DEFAULT`"]
- #[inline(always)]
- pub fn is_function_0_default(&self) -> bool {
- *self == MODER::FUNCTION_0_DEFAULT
- }
- #[doc = "Checks if the value of the field is `FUNCTION_1`"]
- #[inline(always)]
- pub fn is_function_1(&self) -> bool {
- *self == MODER::FUNCTION_1
- }
- #[doc = "Checks if the value of the field is `FUNCTION_2`"]
- #[inline(always)]
- pub fn is_function_2(&self) -> bool {
- *self == MODER::FUNCTION_2
- }
- #[doc = "Checks if the value of the field is `FUNCTION_3`"]
- #[inline(always)]
- pub fn is_function_3(&self) -> bool {
- *self == MODER::FUNCTION_3
- }
- #[doc = "Checks if the value of the field is `FUNCTION_4`"]
- #[inline(always)]
- pub fn is_function_4(&self) -> bool {
- *self == MODER::FUNCTION_4
- }
- #[doc = "Checks if the value of the field is `FUNCTION_5`"]
- #[inline(always)]
- pub fn is_function_5(&self) -> bool {
- *self == MODER::FUNCTION_5
- }
- #[doc = "Checks if the value of the field is `FUNCTION_6`"]
- #[inline(always)]
- pub fn is_function_6(&self) -> bool {
- *self == MODER::FUNCTION_6
- }
- #[doc = "Checks if the value of the field is `FUNCTION_7`"]
- #[inline(always)]
- pub fn is_function_7(&self) -> bool {
- *self == MODER::FUNCTION_7
- }
- }
- #[doc = "Possible values of the field `EPD`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
- impl EPDR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPDR::DISABLE_PULL_DOWN => false,
- EPDR::ENABLE_PULL_DOWN => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPDR {
- match value {
- false => EPDR::DISABLE_PULL_DOWN,
- true => EPDR::ENABLE_PULL_DOWN,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_disable_pull_down(&self) -> bool {
- *self == EPDR::DISABLE_PULL_DOWN
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_DOWN`"]
- #[inline(always)]
- pub fn is_enable_pull_down(&self) -> bool {
- *self == EPDR::ENABLE_PULL_DOWN
- }
- }
- #[doc = "Possible values of the field `EPUN`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
- impl EPUNR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EPUNR::ENABLE_PULL_UP => false,
- EPUNR::DISABLE_PULL_UP => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EPUNR {
- match value {
- false => EPUNR::ENABLE_PULL_UP,
- true => EPUNR::DISABLE_PULL_UP,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_enable_pull_up(&self) -> bool {
- *self == EPUNR::ENABLE_PULL_UP
- }
- #[doc = "Checks if the value of the field is `DISABLE_PULL_UP`"]
- #[inline(always)]
- pub fn is_disable_pull_up(&self) -> bool {
- *self == EPUNR::DISABLE_PULL_UP
- }
- }
- #[doc = "Possible values of the field `EHS`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EHSR {
- #[doc = "Slow (low noise with medium speed)"] SLOW_LOW_NOISE_WITH,
- #[doc = "Fast (medium noise with fast speed)"] FAST_MEDIUM_NOISE_W,
- }
- impl EHSR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EHSR::SLOW_LOW_NOISE_WITH => false,
- EHSR::FAST_MEDIUM_NOISE_W => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EHSR {
- match value {
- false => EHSR::SLOW_LOW_NOISE_WITH,
- true => EHSR::FAST_MEDIUM_NOISE_W,
- }
- }
- #[doc = "Checks if the value of the field is `SLOW_LOW_NOISE_WITH`"]
- #[inline(always)]
- pub fn is_slow_low_noise_with(&self) -> bool {
- *self == EHSR::SLOW_LOW_NOISE_WITH
- }
- #[doc = "Checks if the value of the field is `FAST_MEDIUM_NOISE_W`"]
- #[inline(always)]
- pub fn is_fast_medium_noise_w(&self) -> bool {
- *self == EHSR::FAST_MEDIUM_NOISE_W
- }
- }
- #[doc = "Possible values of the field `EZI`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EZIR {
- #[doc = "Disable input buffer"] DISABLE_INPUT_BUFFER,
- #[doc = "Enable input buffer"] ENABLE_INPUT_BUFFER,
- }
- impl EZIR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- EZIR::DISABLE_INPUT_BUFFER => false,
- EZIR::ENABLE_INPUT_BUFFER => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> EZIR {
- match value {
- false => EZIR::DISABLE_INPUT_BUFFER,
- true => EZIR::ENABLE_INPUT_BUFFER,
- }
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_disable_input_buffer(&self) -> bool {
- *self == EZIR::DISABLE_INPUT_BUFFER
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_BUFFER`"]
- #[inline(always)]
- pub fn is_enable_input_buffer(&self) -> bool {
- *self == EZIR::ENABLE_INPUT_BUFFER
- }
- }
- #[doc = "Possible values of the field `ZIF`"]
- #[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ZIFR {
- #[doc = "Enable input glitch filter"] ENABLE_INPUT_GLITCH,
- #[doc = "Disable input glitch filter"] DISABLE_INPUT_GLITCH,
- }
- impl ZIFR {
- #[doc = r" Returns `true` if the bit is clear (0)"]
- #[inline(always)]
- pub fn bit_is_clear(&self) -> bool {
- !self.bit()
- }
- #[doc = r" Returns `true` if the bit is set (1)"]
- #[inline(always)]
- pub fn bit_is_set(&self) -> bool {
- self.bit()
- }
- #[doc = r" Value of the field as raw bits"]
- #[inline(always)]
- pub fn bit(&self) -> bool {
- match *self {
- ZIFR::ENABLE_INPUT_GLITCH => false,
- ZIFR::DISABLE_INPUT_GLITCH => true,
- }
- }
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _from(value: bool) -> ZIFR {
- match value {
- false => ZIFR::ENABLE_INPUT_GLITCH,
- true => ZIFR::DISABLE_INPUT_GLITCH,
- }
- }
- #[doc = "Checks if the value of the field is `ENABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_enable_input_glitch(&self) -> bool {
- *self == ZIFR::ENABLE_INPUT_GLITCH
- }
- #[doc = "Checks if the value of the field is `DISABLE_INPUT_GLITCH`"]
- #[inline(always)]
- pub fn is_disable_input_glitch(&self) -> bool {
- *self == ZIFR::DISABLE_INPUT_GLITCH
- }
- }
- #[doc = "Values that can be written to the field `MODE`"]
- pub enum MODEW {
- #[doc = "Function 0 (default)"] FUNCTION_0_DEFAULT,
- #[doc = "Function 1"] FUNCTION_1,
- #[doc = "Function 2"] FUNCTION_2,
- #[doc = "Function 3"] FUNCTION_3,
- #[doc = "Function 4"] FUNCTION_4,
- #[doc = "Function 5"] FUNCTION_5,
- #[doc = "Function 6"] FUNCTION_6,
- #[doc = "Function 7"] FUNCTION_7,
- }
- impl MODEW {
- #[allow(missing_docs)]
- #[doc(hidden)]
- #[inline(always)]
- pub fn _bits(&self) -> u8 {
- match *self {
- MODEW::FUNCTION_0_DEFAULT => 0,
- MODEW::FUNCTION_1 => 1,
- MODEW::FUNCTION_2 => 2,
- MODEW::FUNCTION_3 => 3,
- MODEW::FUNCTION_4 => 4,
- MODEW::FUNCTION_5 => 5,
- MODEW::FUNCTION_6 => 6,
- MODEW::FUNCTION_7 => 7,
- }
- }
- }
- #[doc = r" Proxy"]
- pub struct _MODEW<'a> {
- w: &'a mut W,
- }
- impl<'a> _MODEW<'a> {
- #[doc = r" Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: MODEW) -> &'a mut W {
- {
- self.bits(variant._bits())
- }
- }
- #[doc = "Function 0 (default)"]
- #[inline(always)]
- pub fn function_0_default(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_0_DEFAULT)
- }
- #[doc = "Function 1"]
- #[inline(always)]
- pub fn function_1(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_1)
- }
- #[doc = "Function 2"]
- #[inline(always)]
- pub fn function_2(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_2)
- }
- #[doc = "Function 3"]
- #[inline(always)]
- pub fn function_3(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_3)
- }
- #[doc = "Function 4"]
- #[inline(always)]
- pub fn function_4(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_4)
- }
- #[doc = "Function 5"]
- #[inline(always)]
- pub fn function_5(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_5)
- }
- #[doc = "Function 6"]
- #[inline(always)]
- pub fn function_6(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_6)
- }
- #[doc = "Function 7"]
- #[inline(always)]
- pub fn function_7(self) -> &'a mut W {
- self.variant(MODEW::FUNCTION_7)
- }
- #[doc = r" Writes raw bits to the field"]
- #[inline(always)]
- pub fn bits(self, value: u8) -> &'a mut W {
- const MASK: u8 = 7;
- const OFFSET: u8 = 0;
- self.w.bits &= !((MASK as u32) << OFFSET);
- self.w.bits |= ((value & MASK) as u32) << OFFSET;
- self.w
- }
- }
- #[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -227399,8 +216017,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -227423,11 +216040,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -227451,8 +216064,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -227671,8 +216283,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -227689,8 +216300,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -227698,8 +216308,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -227730,8 +216339,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -227740,24 +216348,22 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
}
}
- #[doc = "Pin configuration register for pins P7"]
- pub struct SFSP7_ {
+ #[doc = "Pin configuration register for pins P6"]
+ pub struct SFSP6_ {
register: VolatileCell<u32>,
}
- #[doc = "Pin configuration register for pins P7"]
- pub mod sfsp7_ {
+ #[doc = "Pin configuration register for pins P6"]
+ pub mod sfsp6_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
@@ -227766,7 +216372,7 @@ pub mod scu {
pub struct W {
bits: u32,
}
- impl super::SFSP7_ {
+ impl super::SFSP6_ {
#[doc = r" Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
@@ -227888,11 +216494,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -227934,11 +216536,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -228204,11 +216802,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -228237,8 +216831,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -228261,11 +216854,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -228289,8 +216878,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -228509,8 +217097,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -228527,8 +217114,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -228536,8 +217122,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -228568,8 +217153,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -228578,24 +217162,22 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
}
}
- #[doc = "Pin configuration register for pins P8"]
- pub struct SFSP8_ {
+ #[doc = "Pin configuration register for pins P7"]
+ pub struct SFSP7_ {
register: VolatileCell<u32>,
}
- #[doc = "Pin configuration register for pins P8"]
- pub mod sfsp8_ {
+ #[doc = "Pin configuration register for pins P7"]
+ pub mod sfsp7_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
@@ -228604,7 +217186,7 @@ pub mod scu {
pub struct W {
bits: u32,
}
- impl super::SFSP8_ {
+ impl super::SFSP7_ {
#[doc = r" Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
@@ -228726,11 +217308,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -228772,11 +217350,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -229042,11 +217616,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -229075,8 +217645,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -229099,11 +217668,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -229127,8 +217692,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -229347,8 +217911,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -229365,8 +217928,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -229374,8 +217936,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -229406,8 +217967,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -229416,13 +217976,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -229564,11 +218122,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -229610,11 +218164,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -229880,11 +218430,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -229913,8 +218459,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -229937,11 +218482,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -229965,8 +218506,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -230185,8 +218725,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -230203,8 +218742,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -230212,8 +218750,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -230244,8 +218781,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -230254,13 +218790,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -230586,8 +219120,7 @@ pub mod scu {
#[doc = "Standard drive: 4 mA drive strength"] STANDARD_DRIVE_4_MA,
#[doc = "Medium drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
#[doc = "High drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra-high drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
+ #[doc = "Ultra-high drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
}
impl EHDR {
#[doc = r" Value of the field as raw bits"]
@@ -230952,8 +219485,7 @@ pub mod scu {
#[doc = "Standard drive: 4 mA drive strength"] STANDARD_DRIVE_4_MA,
#[doc = "Medium drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
#[doc = "High drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra-high drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
+ #[doc = "Ultra-high drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
}
impl EHDW {
#[allow(missing_docs)]
@@ -231034,8 +219566,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -231052,8 +219583,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -231093,8 +219623,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -231103,8 +219632,7 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
@@ -231251,11 +219779,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -231297,11 +219821,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -231567,11 +220087,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -231600,8 +220116,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -231624,11 +220139,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -231652,8 +220163,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -231872,8 +220382,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -231890,8 +220399,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -231899,8 +220407,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -231931,8 +220438,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -231941,13 +220447,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -232089,11 +220593,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -232135,11 +220635,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up"] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up" ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -232275,8 +220771,7 @@ pub mod scu {
#[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
#[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
#[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra high-drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
+ #[doc = "Ultra high-drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
}
impl EHDR {
#[doc = r" Value of the field as raw bits"]
@@ -232413,11 +220908,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -232446,8 +220937,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -232470,11 +220960,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up"] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up" ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -232498,8 +220984,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -232643,8 +221128,7 @@ pub mod scu {
#[doc = "Normal-drive: 4 mA drive strength"] NORMAL_DRIVE_4_MA_D,
#[doc = "Medium-drive: 8 mA drive strength"] MEDIUM_DRIVE_8_MA_D,
#[doc = "High-drive: 14 mA drive strength"] HIGH_DRIVE_14_MA_DR,
- #[doc = "Ultra high-drive: 20 mA drive strength"]
- ULTRA_HIGH_DRIVE_20,
+ #[doc = "Ultra high-drive: 20 mA drive strength"] ULTRA_HIGH_DRIVE_20,
}
impl EHDW {
#[allow(missing_docs)]
@@ -232725,8 +221209,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -232734,8 +221217,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -232743,8 +221225,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -232784,18 +221265,15 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -232942,11 +221420,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -232988,11 +221462,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -233258,11 +221728,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -233291,8 +221757,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -233315,11 +221780,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -233343,8 +221804,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -233563,8 +222023,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -233581,8 +222040,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -233590,8 +222048,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -233622,8 +222079,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -233632,13 +222088,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -233780,11 +222234,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -233826,11 +222276,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -234096,11 +222542,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -234129,8 +222571,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -234153,11 +222594,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -234181,8 +222618,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -234401,8 +222837,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -234419,8 +222854,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -234428,8 +222862,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -234460,8 +222893,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -234470,13 +222902,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -234618,11 +223048,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -234664,11 +223090,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -234934,11 +223356,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -234967,8 +223385,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -234991,11 +223408,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -235019,8 +223432,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -235239,8 +223651,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -235257,8 +223668,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -235266,8 +223676,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -235298,8 +223707,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -235308,13 +223716,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -235456,11 +223862,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -235502,11 +223904,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -235772,11 +224170,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -235805,8 +224199,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -235829,11 +224222,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -235857,8 +224246,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -236077,8 +224465,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -236095,8 +224482,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -236104,8 +224490,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -236136,8 +224521,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -236146,13 +224530,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -236294,11 +224676,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -236340,11 +224718,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -236610,11 +224984,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -236643,8 +225013,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -236667,11 +225036,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -236695,8 +225060,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -236915,8 +225279,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -236933,8 +225296,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -236942,8 +225304,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -236974,8 +225335,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -236984,13 +225344,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -237132,11 +225490,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -237178,11 +225532,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -237448,11 +225798,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -237481,8 +225827,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -237505,11 +225850,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -237533,8 +225874,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -237753,8 +226093,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -237771,8 +226110,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -237780,8 +226118,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -237812,8 +226149,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -237822,13 +226158,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -237970,11 +226304,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPDR {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDR {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -238016,11 +226346,7 @@ pub mod scu {
}
#[doc = "Possible values of the field `EPUN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPUNR {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNR {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -238064,8 +226390,7 @@ pub mod scu {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EHSR {
#[doc = "Fast (low noise with fast speed)"] FAST_LOW_NOISE_WITH,
- #[doc = "High-speed (medium noise with high speed)"]
- HIGH_SPEED_MEDIUM_N,
+ #[doc = "High-speed (medium noise with high speed)"] HIGH_SPEED_MEDIUM_N,
}
impl EHSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -238287,11 +226612,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPD`"]
- pub enum EPDW {
- #[doc = "Disable pull-down."] DISABLE_PULL_DOWN,
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_DOWN,
- }
+ pub enum EPDW {# [ doc = "Disable pull-down." ] DISABLE_PULL_DOWN , # [ doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_DOWN}
impl EPDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -238320,8 +226641,7 @@ pub mod scu {
pub fn disable_pull_down(self) -> &'a mut W {
self.variant(EPDW::DISABLE_PULL_DOWN)
}
- #[doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_down(self) -> &'a mut W {
self.variant(EPDW::ENABLE_PULL_DOWN)
}
@@ -238344,11 +226664,7 @@ pub mod scu {
}
}
#[doc = "Values that can be written to the field `EPUN`"]
- pub enum EPUNW {
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- ENABLE_PULL_UP,
- #[doc = "Disable pull-up."] DISABLE_PULL_UP,
- }
+ pub enum EPUNW {# [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] ENABLE_PULL_UP , # [ doc = "Disable pull-up." ] DISABLE_PULL_UP}
impl EPUNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -238372,8 +226688,7 @@ pub mod scu {
self.bit(variant._bits())
}
}
- #[doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode."]
- #[inline(always)]
+ # [ doc = "Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." ] # [ inline ( always ) ]
pub fn enable_pull_up(self) -> &'a mut W {
self.variant(EPUNW::ENABLE_PULL_UP)
}
@@ -238403,8 +226718,7 @@ pub mod scu {
#[doc = "Values that can be written to the field `EHS`"]
pub enum EHSW {
#[doc = "Fast (low noise with fast speed)"] FAST_LOW_NOISE_WITH,
- #[doc = "High-speed (medium noise with high speed)"]
- HIGH_SPEED_MEDIUM_N,
+ #[doc = "High-speed (medium noise with high speed)"] HIGH_SPEED_MEDIUM_N,
}
impl EHSW {
#[allow(missing_docs)]
@@ -238593,8 +226907,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&self) -> EPUNR {
EPUNR::_from({
const MASK: bool = true;
@@ -238611,8 +226924,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&self) -> EZIR {
EZIR::_from({
const MASK: bool = true;
@@ -238620,8 +226932,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&self) -> ZIFR {
ZIFR::_from({
const MASK: bool = true;
@@ -238652,8 +226963,7 @@ pub mod scu {
pub fn epd(&mut self) -> _EPDW {
_EPDW { w: self }
}
- #[doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset." ] # [ inline ( always ) ]
pub fn epun(&mut self) -> _EPUNW {
_EPUNW { w: self }
}
@@ -238662,13 +226972,11 @@ pub mod scu {
pub fn ehs(&mut self) -> _EHSW {
_EHSW { w: self }
}
- #[doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving." ] # [ inline ( always ) ]
pub fn ezi(&mut self) -> _EZIW {
_EZIW { w: self }
}
- #[doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz." ] # [ inline ( always ) ]
pub fn zif(&mut self) -> _ZIFW {
_ZIFW { w: self }
}
@@ -239259,8 +227567,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 5 - Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register. The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register. The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register." ] # [ inline ( always ) ]
pub fn usb_vbus(&self) -> USB_VBUSR {
USB_VBUSR::_from({
const MASK: bool = true;
@@ -239301,8 +227608,7 @@ pub mod scu {
pub fn usb_epwr(&mut self) -> _USB_EPWRW {
_USB_EPWRW { w: self }
}
- #[doc = "Bit 5 - Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register. The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register. The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register." ] # [ inline ( always ) ]
pub fn usb_vbus(&mut self) -> _USB_VBUSW {
_USB_VBUSW { w: self }
}
@@ -240190,8 +228496,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0." ] # [ inline ( always ) ]
pub fn scl_ezi(&self) -> SCL_EZIR {
SCL_EZIR::_from({
const MASK: bool = true;
@@ -240199,8 +228504,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP." ] # [ inline ( always ) ]
pub fn scl_zif(&self) -> SCL_ZIFR {
SCL_ZIFR::_from({
const MASK: bool = true;
@@ -240226,8 +228530,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 11 - Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0." ] # [ inline ( always ) ]
pub fn sda_ezi(&self) -> SDA_EZIR {
SDA_EZIR::_from({
const MASK: bool = true;
@@ -240235,8 +228538,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 15 - Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP." ] # [ inline ( always ) ]
pub fn sda_zif(&self) -> SDA_ZIFR {
SDA_ZIFR::_from({
const MASK: bool = true;
@@ -240267,13 +228569,11 @@ pub mod scu {
pub fn scl_ehd(&mut self) -> _SCL_EHDW {
_SCL_EHDW { w: self }
}
- #[doc = "Bit 3 - Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0." ] # [ inline ( always ) ]
pub fn scl_ezi(&mut self) -> _SCL_EZIW {
_SCL_EZIW { w: self }
}
- #[doc = "Bit 7 - Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP." ] # [ inline ( always ) ]
pub fn scl_zif(&mut self) -> _SCL_ZIFW {
_SCL_ZIFW { w: self }
}
@@ -240287,13 +228587,11 @@ pub mod scu {
pub fn sda_ehd(&mut self) -> _SDA_EHDW {
_SDA_EHDW { w: self }
}
- #[doc = "Bit 11 - Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0." ] # [ inline ( always ) ]
pub fn sda_ezi(&mut self) -> _SDA_EZIW {
_SDA_EZIW { w: self }
}
- #[doc = "Bit 15 - Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP." ] # [ inline ( always ) ]
pub fn sda_zif(&mut self) -> _SDA_ZIFW {
_SDA_ZIFW { w: self }
}
@@ -240352,10 +228650,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC0_0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_0R {
- #[doc = "Digital function selected on pin P4_3."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_0 selected on pin P4_3"]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P4_3."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_0 selected on pin P4_3"] ANALOG_FUNCTION_ADC0,
}
impl ADC0_0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -240399,10 +228695,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC0_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_1R {
- #[doc = "Digital function selected on pin P4_1."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_1 selected on pin P4_1."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P4_1."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_1 selected on pin P4_1."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -240446,10 +228740,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC0_2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_2R {
- #[doc = "Digital function selected on pin PF_8."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_2 selected on pin PF_8."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin PF_8."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_2 selected on pin PF_8."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -240493,10 +228785,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC0_3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_3R {
- #[doc = "Digital function selected on pin P7_5."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_3 selected on pin P7_5."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P7_5."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_3 selected on pin P7_5."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -240540,10 +228830,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC0_4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_4R {
- #[doc = "Digital function selected on pin P7_4."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_4 selected on pin P7_4."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P7_4."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_4 selected on pin P7_4."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -240587,10 +228875,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC0_5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_5R {
- #[doc = "Digital function selected on pin PF_10."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_5 selected on pin PF_10."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin PF_10."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_5 selected on pin PF_10."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -240634,10 +228920,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC0_6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_6R {
- #[doc = "Digital function selected on pin PB_6."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_6 selected on pin PB_6."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin PB_6."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_6 selected on pin PB_6."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -240680,10 +228964,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC0_0`"]
pub enum ADC0_0W {
- #[doc = "Digital function selected on pin P4_3."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_0 selected on pin P4_3"]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P4_3."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_0 selected on pin P4_3"] ANALOG_FUNCTION_ADC0,
}
impl ADC0_0W {
#[allow(missing_docs)]
@@ -240738,10 +229020,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC0_1`"]
pub enum ADC0_1W {
- #[doc = "Digital function selected on pin P4_1."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_1 selected on pin P4_1."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P4_1."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_1 selected on pin P4_1."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_1W {
#[allow(missing_docs)]
@@ -240796,10 +229076,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC0_2`"]
pub enum ADC0_2W {
- #[doc = "Digital function selected on pin PF_8."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_2 selected on pin PF_8."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin PF_8."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_2 selected on pin PF_8."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_2W {
#[allow(missing_docs)]
@@ -240854,10 +229132,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC0_3`"]
pub enum ADC0_3W {
- #[doc = "Digital function selected on pin P7_5."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_3 selected on pin P7_5."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P7_5."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_3 selected on pin P7_5."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_3W {
#[allow(missing_docs)]
@@ -240912,10 +229188,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC0_4`"]
pub enum ADC0_4W {
- #[doc = "Digital function selected on pin P7_4."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_4 selected on pin P7_4."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin P7_4."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_4 selected on pin P7_4."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_4W {
#[allow(missing_docs)]
@@ -240970,10 +229244,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC0_5`"]
pub enum ADC0_5W {
- #[doc = "Digital function selected on pin PF_10."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_5 selected on pin PF_10."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin PF_10."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_5 selected on pin PF_10."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_5W {
#[allow(missing_docs)]
@@ -241028,10 +229300,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC0_6`"]
pub enum ADC0_6W {
- #[doc = "Digital function selected on pin PB_6."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC0_6 selected on pin PB_6."]
- ANALOG_FUNCTION_ADC0,
+ #[doc = "Digital function selected on pin PB_6."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC0_6 selected on pin PB_6."] ANALOG_FUNCTION_ADC0,
}
impl ADC0_6W {
#[allow(missing_docs)]
@@ -241256,10 +229526,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_0R {
- #[doc = "Digital function selected on pin PC_3."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_0 selected on pin PC_3."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PC_3."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_0 selected on pin PC_3."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241303,10 +229571,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_1R {
- #[doc = "Digital function selected on pin PC_0."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_1 selected on pin PC_0."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PC_0."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_1 selected on pin PC_0."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241350,10 +229616,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_2R {
- #[doc = "Digital function selected on pin PF_9."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_2 selected on pin PF_9."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_9."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_2 selected on pin PF_9."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241397,10 +229661,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_3R {
- #[doc = "Digital function selected on pin PF_6."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_3 selected on pin PF_6."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_6."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_3 selected on pin PF_6."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241444,10 +229706,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_4R {
- #[doc = "Digital function selected on pin PF_5."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_4 selected on pin PF_5."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_5."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_4 selected on pin PF_5."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241491,10 +229751,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_5R {
- #[doc = "Digital function selected on pin PF_11."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_5 selected on pin PF_11."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_11."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_5 selected on pin PF_11."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241538,10 +229796,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_6R {
- #[doc = "Digital function selected on pin P7_7."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_6 selected on pin P7_7."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin P7_7."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_6 selected on pin P7_7."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241585,10 +229841,8 @@ pub mod scu {
#[doc = "Possible values of the field `ADC1_7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1_7R {
- #[doc = "Digital function selected on pin PF_7."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_7 selected on pin PF_7."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_7."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_7 selected on pin PF_7."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_7R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -241631,10 +229885,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_0`"]
pub enum ADC1_0W {
- #[doc = "Digital function selected on pin PC_3."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_0 selected on pin PC_3."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PC_3."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_0 selected on pin PC_3."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_0W {
#[allow(missing_docs)]
@@ -241689,10 +229941,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_1`"]
pub enum ADC1_1W {
- #[doc = "Digital function selected on pin PC_0."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_1 selected on pin PC_0."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PC_0."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_1 selected on pin PC_0."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_1W {
#[allow(missing_docs)]
@@ -241747,10 +229997,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_2`"]
pub enum ADC1_2W {
- #[doc = "Digital function selected on pin PF_9."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_2 selected on pin PF_9."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_9."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_2 selected on pin PF_9."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_2W {
#[allow(missing_docs)]
@@ -241805,10 +230053,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_3`"]
pub enum ADC1_3W {
- #[doc = "Digital function selected on pin PF_6."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_3 selected on pin PF_6."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_6."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_3 selected on pin PF_6."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_3W {
#[allow(missing_docs)]
@@ -241863,10 +230109,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_4`"]
pub enum ADC1_4W {
- #[doc = "Digital function selected on pin PF_5."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_4 selected on pin PF_5."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_5."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_4 selected on pin PF_5."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_4W {
#[allow(missing_docs)]
@@ -241921,10 +230165,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_5`"]
pub enum ADC1_5W {
- #[doc = "Digital function selected on pin PF_11."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_5 selected on pin PF_11."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_11."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_5 selected on pin PF_11."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_5W {
#[allow(missing_docs)]
@@ -241979,10 +230221,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_6`"]
pub enum ADC1_6W {
- #[doc = "Digital function selected on pin P7_7."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_6 selected on pin P7_7."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin P7_7."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_6 selected on pin P7_7."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_6W {
#[allow(missing_docs)]
@@ -242037,10 +230277,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `ADC1_7`"]
pub enum ADC1_7W {
- #[doc = "Digital function selected on pin PF_7."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function ADC1_7 selected on pin PF_7."]
- ANALOG_FUNCTION_ADC1,
+ #[doc = "Digital function selected on pin PF_7."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function ADC1_7 selected on pin PF_7."] ANALOG_FUNCTION_ADC1,
}
impl ADC1_7W {
#[allow(missing_docs)]
@@ -242279,10 +230517,8 @@ pub mod scu {
#[doc = "Possible values of the field `DAC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DACR {
- #[doc = "Digital function selected on pin P4_4."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function DAC selected on pin P4_4."]
- ANALOG_FUNCTION_DAC,
+ #[doc = "Digital function selected on pin P4_4."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function DAC selected on pin P4_4."] ANALOG_FUNCTION_DAC,
}
impl DACR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -242326,10 +230562,8 @@ pub mod scu {
#[doc = "Possible values of the field `BG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BGR {
- #[doc = "Digital function selected on pin PF_7."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Band gap output selected for pin PF_7."]
- BAND_GAP_OUTPUT_SELE,
+ #[doc = "Digital function selected on pin PF_7."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Band gap output selected for pin PF_7."] BAND_GAP_OUTPUT_SELE,
}
impl BGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -242372,10 +230606,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `DAC`"]
pub enum DACW {
- #[doc = "Digital function selected on pin P4_4."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Analog function DAC selected on pin P4_4."]
- ANALOG_FUNCTION_DAC,
+ #[doc = "Digital function selected on pin P4_4."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Analog function DAC selected on pin P4_4."] ANALOG_FUNCTION_DAC,
}
impl DACW {
#[allow(missing_docs)]
@@ -242430,10 +230662,8 @@ pub mod scu {
}
#[doc = "Values that can be written to the field `BG`"]
pub enum BGW {
- #[doc = "Digital function selected on pin PF_7."]
- DIGITAL_FUNCTION_SEL,
- #[doc = "Band gap output selected for pin PF_7."]
- BAND_GAP_OUTPUT_SELE,
+ #[doc = "Digital function selected on pin PF_7."] DIGITAL_FUNCTION_SEL,
+ #[doc = "Band gap output selected for pin PF_7."] BAND_GAP_OUTPUT_SELE,
}
impl BGW {
#[allow(missing_docs)]
@@ -242501,8 +230731,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1)." ] # [ inline ( always ) ]
pub fn bg(&self) -> BGR {
BGR::_from({
const MASK: bool = true;
@@ -242528,8 +230757,7 @@ pub mod scu {
pub fn dac(&mut self) -> _DACW {
_DACW { w: self }
}
- #[doc = "Bit 4 - Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1)." ] # [ inline ( always ) ]
pub fn bg(&mut self) -> _BGW {
_BGW { w: self }
}
@@ -242617,8 +230845,7 @@ pub mod scu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay"]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" ] # [ inline ( always ) ]
pub fn clk_delay(&self) -> CLK_DELAYR {
let bits = {
const MASK: u16 = 65535;
@@ -242640,8 +230867,7 @@ pub mod scu {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay"]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" ] # [ inline ( always ) ]
pub fn clk_delay(&mut self) -> _CLK_DELAYW {
_CLK_DELAYW { w: self }
}
@@ -242765,8 +230991,7 @@ pub mod scu {
};
SAMPLE_DELAYR { bits }
}
- #[doc = "Bits 8:11 - SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed."]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." ] # [ inline ( always ) ]
pub fn drv_delay(&self) -> DRV_DELAYR {
let bits = {
const MASK: u8 = 15;
@@ -242793,8 +231018,7 @@ pub mod scu {
pub fn sample_delay(&mut self) -> _SAMPLE_DELAYW {
_SAMPLE_DELAYW { w: self }
}
- #[doc = "Bits 8:11 - SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed."]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." ] # [ inline ( always ) ]
pub fn drv_delay(&mut self) -> _DRV_DELAYW {
_DRV_DELAYW { w: self }
}
@@ -243656,8 +231880,7 @@ pub mod scu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." ] # [ inline ( always ) ]
pub fn intpin0(&self) -> INTPIN0R {
let bits = {
const MASK: u8 = 31;
@@ -243666,8 +231889,7 @@ pub mod scu {
};
INTPIN0R { bits }
}
- #[doc = "Bits 5:7 - Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 5:7 - Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register." ] # [ inline ( always ) ]
pub fn portsel0(&self) -> PORTSEL0R {
PORTSEL0R::_from({
const MASK: u8 = 7;
@@ -243675,8 +231897,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 8:12 - Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." ] # [ inline ( always ) ]
pub fn intpin1(&self) -> INTPIN1R {
let bits = {
const MASK: u8 = 31;
@@ -243685,8 +231906,7 @@ pub mod scu {
};
INTPIN1R { bits }
}
- #[doc = "Bits 13:15 - Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 13:15 - Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register." ] # [ inline ( always ) ]
pub fn portsel1(&self) -> PORTSEL1R {
PORTSEL1R::_from({
const MASK: u8 = 7;
@@ -243694,8 +231914,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:20 - Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 16:20 - Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." ] # [ inline ( always ) ]
pub fn intpin2(&self) -> INTPIN2R {
let bits = {
const MASK: u8 = 31;
@@ -243704,8 +231923,7 @@ pub mod scu {
};
INTPIN2R { bits }
}
- #[doc = "Bits 21:23 - Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 21:23 - Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register." ] # [ inline ( always ) ]
pub fn portsel2(&self) -> PORTSEL2R {
PORTSEL2R::_from({
const MASK: u8 = 7;
@@ -243713,8 +231931,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 24:28 - Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 24:28 - Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." ] # [ inline ( always ) ]
pub fn intpin3(&self) -> INTPIN3R {
let bits = {
const MASK: u8 = 31;
@@ -243723,8 +231940,7 @@ pub mod scu {
};
INTPIN3R { bits }
}
- #[doc = "Bits 29:31 - Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 29:31 - Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register." ] # [ inline ( always ) ]
pub fn portsel3(&self) -> PORTSEL3R {
PORTSEL3R::_from({
const MASK: u8 = 7;
@@ -243745,43 +231961,35 @@ pub mod scu {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." ] # [ inline ( always ) ]
pub fn intpin0(&mut self) -> _INTPIN0W {
_INTPIN0W { w: self }
}
- #[doc = "Bits 5:7 - Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 5:7 - Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register." ] # [ inline ( always ) ]
pub fn portsel0(&mut self) -> _PORTSEL0W {
_PORTSEL0W { w: self }
}
- #[doc = "Bits 8:12 - Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." ] # [ inline ( always ) ]
pub fn intpin1(&mut self) -> _INTPIN1W {
_INTPIN1W { w: self }
}
- #[doc = "Bits 13:15 - Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 13:15 - Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register." ] # [ inline ( always ) ]
pub fn portsel1(&mut self) -> _PORTSEL1W {
_PORTSEL1W { w: self }
}
- #[doc = "Bits 16:20 - Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 16:20 - Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." ] # [ inline ( always ) ]
pub fn intpin2(&mut self) -> _INTPIN2W {
_INTPIN2W { w: self }
}
- #[doc = "Bits 21:23 - Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 21:23 - Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register." ] # [ inline ( always ) ]
pub fn portsel2(&mut self) -> _PORTSEL2W {
_PORTSEL2W { w: self }
}
- #[doc = "Bits 24:28 - Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 24:28 - Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." ] # [ inline ( always ) ]
pub fn intpin3(&mut self) -> _INTPIN3W {
_INTPIN3W { w: self }
}
- #[doc = "Bits 29:31 - Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 29:31 - Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register." ] # [ inline ( always ) ]
pub fn portsel3(&mut self) -> _PORTSEL3W {
_PORTSEL3W { w: self }
}
@@ -244643,8 +232851,7 @@ pub mod scu {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:4 - Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." ] # [ inline ( always ) ]
pub fn intpin4(&self) -> INTPIN4R {
let bits = {
const MASK: u8 = 31;
@@ -244653,8 +232860,7 @@ pub mod scu {
};
INTPIN4R { bits }
}
- #[doc = "Bits 5:7 - Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 5:7 - Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register." ] # [ inline ( always ) ]
pub fn portsel4(&self) -> PORTSEL4R {
PORTSEL4R::_from({
const MASK: u8 = 7;
@@ -244662,8 +232868,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 8:12 - Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." ] # [ inline ( always ) ]
pub fn intpin5(&self) -> INTPIN5R {
let bits = {
const MASK: u8 = 31;
@@ -244672,8 +232877,7 @@ pub mod scu {
};
INTPIN5R { bits }
}
- #[doc = "Bits 13:15 - Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 13:15 - Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register." ] # [ inline ( always ) ]
pub fn portsel5(&self) -> PORTSEL5R {
PORTSEL5R::_from({
const MASK: u8 = 7;
@@ -244681,8 +232885,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 16:20 - Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 16:20 - Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." ] # [ inline ( always ) ]
pub fn intpin6(&self) -> INTPIN6R {
let bits = {
const MASK: u8 = 31;
@@ -244691,8 +232894,7 @@ pub mod scu {
};
INTPIN6R { bits }
}
- #[doc = "Bits 21:23 - Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 21:23 - Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register." ] # [ inline ( always ) ]
pub fn portsel6(&self) -> PORTSEL6R {
PORTSEL6R::_from({
const MASK: u8 = 7;
@@ -244700,8 +232902,7 @@ pub mod scu {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 24:28 - Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 24:28 - Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." ] # [ inline ( always ) ]
pub fn intpin7(&self) -> INTPIN7R {
let bits = {
const MASK: u8 = 31;
@@ -244710,8 +232911,7 @@ pub mod scu {
};
INTPIN7R { bits }
}
- #[doc = "Bits 29:31 - Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 29:31 - Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register." ] # [ inline ( always ) ]
pub fn portsel7(&self) -> PORTSEL7R {
PORTSEL7R::_from({
const MASK: u8 = 7;
@@ -244732,43 +232932,35 @@ pub mod scu {
self.bits = bits;
self
}
- #[doc = "Bits 0:4 - Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 0:4 - Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." ] # [ inline ( always ) ]
pub fn intpin4(&mut self) -> _INTPIN4W {
_INTPIN4W { w: self }
}
- #[doc = "Bits 5:7 - Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 5:7 - Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register." ] # [ inline ( always ) ]
pub fn portsel4(&mut self) -> _PORTSEL4W {
_PORTSEL4W { w: self }
}
- #[doc = "Bits 8:12 - Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 8:12 - Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." ] # [ inline ( always ) ]
pub fn intpin5(&mut self) -> _INTPIN5W {
_INTPIN5W { w: self }
}
- #[doc = "Bits 13:15 - Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 13:15 - Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register." ] # [ inline ( always ) ]
pub fn portsel5(&mut self) -> _PORTSEL5W {
_PORTSEL5W { w: self }
}
- #[doc = "Bits 16:20 - Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 16:20 - Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." ] # [ inline ( always ) ]
pub fn intpin6(&mut self) -> _INTPIN6W {
_INTPIN6W { w: self }
}
- #[doc = "Bits 21:23 - Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 21:23 - Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register." ] # [ inline ( always ) ]
pub fn portsel6(&mut self) -> _PORTSEL6W {
_PORTSEL6W { w: self }
}
- #[doc = "Bits 24:28 - Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register."]
- #[inline(always)]
+ # [ doc = "Bits 24:28 - Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." ] # [ inline ( always ) ]
pub fn intpin7(&mut self) -> _INTPIN7W {
_INTPIN7W { w: self }
}
- #[doc = "Bits 29:31 - Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register."]
- #[inline(always)]
+ # [ doc = "Bits 29:31 - Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register." ] # [ inline ( always ) ]
pub fn portsel7(&mut self) -> _PORTSEL7W {
_PORTSEL7W { w: self }
}
@@ -244786,8 +232978,7 @@ impl Deref for SCU {
}
}
#[doc = "GPIO pin interrupt"]
-pub const GPIO_PIN_INT: Peripheral<GPIO_PIN_INT> =
- unsafe { Peripheral::new(1074294784) };
+pub const GPIO_PIN_INT: Peripheral<GPIO_PIN_INT> = unsafe { Peripheral::new(1074294784) };
#[doc = "GPIO pin interrupt"]
pub mod gpio_pin_int {
use vcell::VolatileCell;
@@ -245202,8 +233393,7 @@ pub mod gpio_pin_int {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode0(&self) -> PMODE0R {
let bits = {
const MASK: bool = true;
@@ -245212,8 +233402,7 @@ pub mod gpio_pin_int {
};
PMODE0R { bits }
}
- #[doc = "Bit 1 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode1(&self) -> PMODE1R {
let bits = {
const MASK: bool = true;
@@ -245222,8 +233411,7 @@ pub mod gpio_pin_int {
};
PMODE1R { bits }
}
- #[doc = "Bit 2 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode2(&self) -> PMODE2R {
let bits = {
const MASK: bool = true;
@@ -245232,8 +233420,7 @@ pub mod gpio_pin_int {
};
PMODE2R { bits }
}
- #[doc = "Bit 3 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode3(&self) -> PMODE3R {
let bits = {
const MASK: bool = true;
@@ -245242,8 +233429,7 @@ pub mod gpio_pin_int {
};
PMODE3R { bits }
}
- #[doc = "Bit 4 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode4(&self) -> PMODE4R {
let bits = {
const MASK: bool = true;
@@ -245252,8 +233438,7 @@ pub mod gpio_pin_int {
};
PMODE4R { bits }
}
- #[doc = "Bit 5 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode5(&self) -> PMODE5R {
let bits = {
const MASK: bool = true;
@@ -245262,8 +233447,7 @@ pub mod gpio_pin_int {
};
PMODE5R { bits }
}
- #[doc = "Bit 6 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode6(&self) -> PMODE6R {
let bits = {
const MASK: bool = true;
@@ -245272,8 +233456,7 @@ pub mod gpio_pin_int {
};
PMODE6R { bits }
}
- #[doc = "Bit 7 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 7 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode7(&self) -> PMODE7R {
let bits = {
const MASK: bool = true;
@@ -245295,43 +233478,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode0(&mut self) -> _PMODE0W {
_PMODE0W { w: self }
}
- #[doc = "Bit 1 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode1(&mut self) -> _PMODE1W {
_PMODE1W { w: self }
}
- #[doc = "Bit 2 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode2(&mut self) -> _PMODE2W {
_PMODE2W { w: self }
}
- #[doc = "Bit 3 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode3(&mut self) -> _PMODE3W {
_PMODE3W { w: self }
}
- #[doc = "Bit 4 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode4(&mut self) -> _PMODE4W {
_PMODE4W { w: self }
}
- #[doc = "Bit 5 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode5(&mut self) -> _PMODE5W {
_PMODE5W { w: self }
}
- #[doc = "Bit 6 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode6(&mut self) -> _PMODE6W {
_PMODE6W { w: self }
}
- #[doc = "Bit 7 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"]
- #[inline(always)]
+ # [ doc = "Bit 7 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" ] # [ inline ( always ) ]
pub fn pmode7(&mut self) -> _PMODE7W {
_PMODE7W { w: self }
}
@@ -245745,8 +233920,7 @@ pub mod gpio_pin_int {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl0(&self) -> ENRL0R {
let bits = {
const MASK: bool = true;
@@ -245755,8 +233929,7 @@ pub mod gpio_pin_int {
};
ENRL0R { bits }
}
- #[doc = "Bit 1 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl1(&self) -> ENRL1R {
let bits = {
const MASK: bool = true;
@@ -245765,8 +233938,7 @@ pub mod gpio_pin_int {
};
ENRL1R { bits }
}
- #[doc = "Bit 2 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl2(&self) -> ENRL2R {
let bits = {
const MASK: bool = true;
@@ -245775,8 +233947,7 @@ pub mod gpio_pin_int {
};
ENRL2R { bits }
}
- #[doc = "Bit 3 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl3(&self) -> ENRL3R {
let bits = {
const MASK: bool = true;
@@ -245785,8 +233956,7 @@ pub mod gpio_pin_int {
};
ENRL3R { bits }
}
- #[doc = "Bit 4 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl4(&self) -> ENRL4R {
let bits = {
const MASK: bool = true;
@@ -245795,8 +233965,7 @@ pub mod gpio_pin_int {
};
ENRL4R { bits }
}
- #[doc = "Bit 5 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl5(&self) -> ENRL5R {
let bits = {
const MASK: bool = true;
@@ -245805,8 +233974,7 @@ pub mod gpio_pin_int {
};
ENRL5R { bits }
}
- #[doc = "Bit 6 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl6(&self) -> ENRL6R {
let bits = {
const MASK: bool = true;
@@ -245815,8 +233983,7 @@ pub mod gpio_pin_int {
};
ENRL6R { bits }
}
- #[doc = "Bit 7 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl7(&self) -> ENRL7R {
let bits = {
const MASK: bool = true;
@@ -245838,43 +234005,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl0(&mut self) -> _ENRL0W {
_ENRL0W { w: self }
}
- #[doc = "Bit 1 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl1(&mut self) -> _ENRL1W {
_ENRL1W { w: self }
}
- #[doc = "Bit 2 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl2(&mut self) -> _ENRL2W {
_ENRL2W { w: self }
}
- #[doc = "Bit 3 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl3(&mut self) -> _ENRL3W {
_ENRL3W { w: self }
}
- #[doc = "Bit 4 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl4(&mut self) -> _ENRL4W {
_ENRL4W { w: self }
}
- #[doc = "Bit 5 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl5(&mut self) -> _ENRL5W {
_ENRL5W { w: self }
}
- #[doc = "Bit 6 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl6(&mut self) -> _ENRL6W {
_ENRL6W { w: self }
}
- #[doc = "Bit 7 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn enrl7(&mut self) -> _ENRL7W {
_ENRL7W { w: self }
}
@@ -246098,43 +234257,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl0(&mut self) -> _SETENRL0W {
_SETENRL0W { w: self }
}
- #[doc = "Bit 1 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl1(&mut self) -> _SETENRL1W {
_SETENRL1W { w: self }
}
- #[doc = "Bit 2 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl2(&mut self) -> _SETENRL2W {
_SETENRL2W { w: self }
}
- #[doc = "Bit 3 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl3(&mut self) -> _SETENRL3W {
_SETENRL3W { w: self }
}
- #[doc = "Bit 4 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl4(&mut self) -> _SETENRL4W {
_SETENRL4W { w: self }
}
- #[doc = "Bit 5 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl5(&mut self) -> _SETENRL5W {
_SETENRL5W { w: self }
}
- #[doc = "Bit 6 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl6(&mut self) -> _SETENRL6W {
_SETENRL6W { w: self }
}
- #[doc = "Bit 7 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn setenrl7(&mut self) -> _SETENRL7W {
_SETENRL7W { w: self }
}
@@ -246358,43 +234509,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl0(&mut self) -> _CENRL0W {
_CENRL0W { w: self }
}
- #[doc = "Bit 1 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl1(&mut self) -> _CENRL1W {
_CENRL1W { w: self }
}
- #[doc = "Bit 2 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl2(&mut self) -> _CENRL2W {
_CENRL2W { w: self }
}
- #[doc = "Bit 3 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl3(&mut self) -> _CENRL3W {
_CENRL3W { w: self }
}
- #[doc = "Bit 4 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl4(&mut self) -> _CENRL4W {
_CENRL4W { w: self }
}
- #[doc = "Bit 5 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl5(&mut self) -> _CENRL5W {
_CENRL5W { w: self }
}
- #[doc = "Bit 6 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl6(&mut self) -> _CENRL6W {
_CENRL6W { w: self }
}
- #[doc = "Bit 7 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." ] # [ inline ( always ) ]
pub fn cenrl7(&mut self) -> _CENRL7W {
_CENRL7W { w: self }
}
@@ -246808,8 +234951,7 @@ pub mod gpio_pin_int {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf0(&self) -> ENAF0R {
let bits = {
const MASK: bool = true;
@@ -246818,8 +234960,7 @@ pub mod gpio_pin_int {
};
ENAF0R { bits }
}
- #[doc = "Bit 1 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf1(&self) -> ENAF1R {
let bits = {
const MASK: bool = true;
@@ -246828,8 +234969,7 @@ pub mod gpio_pin_int {
};
ENAF1R { bits }
}
- #[doc = "Bit 2 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf2(&self) -> ENAF2R {
let bits = {
const MASK: bool = true;
@@ -246838,8 +234978,7 @@ pub mod gpio_pin_int {
};
ENAF2R { bits }
}
- #[doc = "Bit 3 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf3(&self) -> ENAF3R {
let bits = {
const MASK: bool = true;
@@ -246848,8 +234987,7 @@ pub mod gpio_pin_int {
};
ENAF3R { bits }
}
- #[doc = "Bit 4 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf4(&self) -> ENAF4R {
let bits = {
const MASK: bool = true;
@@ -246858,8 +234996,7 @@ pub mod gpio_pin_int {
};
ENAF4R { bits }
}
- #[doc = "Bit 5 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf5(&self) -> ENAF5R {
let bits = {
const MASK: bool = true;
@@ -246868,8 +235005,7 @@ pub mod gpio_pin_int {
};
ENAF5R { bits }
}
- #[doc = "Bit 6 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf6(&self) -> ENAF6R {
let bits = {
const MASK: bool = true;
@@ -246878,8 +235014,7 @@ pub mod gpio_pin_int {
};
ENAF6R { bits }
}
- #[doc = "Bit 7 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf7(&self) -> ENAF7R {
let bits = {
const MASK: bool = true;
@@ -246901,43 +235036,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf0(&mut self) -> _ENAF0W {
_ENAF0W { w: self }
}
- #[doc = "Bit 1 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf1(&mut self) -> _ENAF1W {
_ENAF1W { w: self }
}
- #[doc = "Bit 2 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf2(&mut self) -> _ENAF2W {
_ENAF2W { w: self }
}
- #[doc = "Bit 3 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf3(&mut self) -> _ENAF3W {
_ENAF3W { w: self }
}
- #[doc = "Bit 4 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf4(&mut self) -> _ENAF4W {
_ENAF4W { w: self }
}
- #[doc = "Bit 5 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf5(&mut self) -> _ENAF5W {
_ENAF5W { w: self }
}
- #[doc = "Bit 6 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf6(&mut self) -> _ENAF6W {
_ENAF6W { w: self }
}
- #[doc = "Bit 7 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." ] # [ inline ( always ) ]
pub fn enaf7(&mut self) -> _ENAF7W {
_ENAF7W { w: self }
}
@@ -247161,43 +235288,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf0(&mut self) -> _SETENAF0W {
_SETENAF0W { w: self }
}
- #[doc = "Bit 1 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf1(&mut self) -> _SETENAF1W {
_SETENAF1W { w: self }
}
- #[doc = "Bit 2 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf2(&mut self) -> _SETENAF2W {
_SETENAF2W { w: self }
}
- #[doc = "Bit 3 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf3(&mut self) -> _SETENAF3W {
_SETENAF3W { w: self }
}
- #[doc = "Bit 4 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf4(&mut self) -> _SETENAF4W {
_SETENAF4W { w: self }
}
- #[doc = "Bit 5 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf5(&mut self) -> _SETENAF5W {
_SETENAF5W { w: self }
}
- #[doc = "Bit 6 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf6(&mut self) -> _SETENAF6W {
_SETENAF6W { w: self }
}
- #[doc = "Bit 7 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." ] # [ inline ( always ) ]
pub fn setenaf7(&mut self) -> _SETENAF7W {
_SETENAF7W { w: self }
}
@@ -247421,43 +235540,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf0(&mut self) -> _CENAF0W {
_CENAF0W { w: self }
}
- #[doc = "Bit 1 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf1(&mut self) -> _CENAF1W {
_CENAF1W { w: self }
}
- #[doc = "Bit 2 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf2(&mut self) -> _CENAF2W {
_CENAF2W { w: self }
}
- #[doc = "Bit 3 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf3(&mut self) -> _CENAF3W {
_CENAF3W { w: self }
}
- #[doc = "Bit 4 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf4(&mut self) -> _CENAF4W {
_CENAF4W { w: self }
}
- #[doc = "Bit 5 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf5(&mut self) -> _CENAF5W {
_CENAF5W { w: self }
}
- #[doc = "Bit 6 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf6(&mut self) -> _CENAF6W {
_CENAF6W { w: self }
}
- #[doc = "Bit 7 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." ] # [ inline ( always ) ]
pub fn cenaf7(&mut self) -> _CENAF7W {
_CENAF7W { w: self }
}
@@ -247871,8 +235982,7 @@ pub mod gpio_pin_int {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet0(&self) -> RDET0R {
let bits = {
const MASK: bool = true;
@@ -247881,8 +235991,7 @@ pub mod gpio_pin_int {
};
RDET0R { bits }
}
- #[doc = "Bit 1 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet1(&self) -> RDET1R {
let bits = {
const MASK: bool = true;
@@ -247891,8 +236000,7 @@ pub mod gpio_pin_int {
};
RDET1R { bits }
}
- #[doc = "Bit 2 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet2(&self) -> RDET2R {
let bits = {
const MASK: bool = true;
@@ -247901,8 +236009,7 @@ pub mod gpio_pin_int {
};
RDET2R { bits }
}
- #[doc = "Bit 3 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet3(&self) -> RDET3R {
let bits = {
const MASK: bool = true;
@@ -247911,8 +236018,7 @@ pub mod gpio_pin_int {
};
RDET3R { bits }
}
- #[doc = "Bit 4 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet4(&self) -> RDET4R {
let bits = {
const MASK: bool = true;
@@ -247921,8 +236027,7 @@ pub mod gpio_pin_int {
};
RDET4R { bits }
}
- #[doc = "Bit 5 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet5(&self) -> RDET5R {
let bits = {
const MASK: bool = true;
@@ -247931,8 +236036,7 @@ pub mod gpio_pin_int {
};
RDET5R { bits }
}
- #[doc = "Bit 6 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet6(&self) -> RDET6R {
let bits = {
const MASK: bool = true;
@@ -247941,8 +236045,7 @@ pub mod gpio_pin_int {
};
RDET6R { bits }
}
- #[doc = "Bit 7 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet7(&self) -> RDET7R {
let bits = {
const MASK: bool = true;
@@ -247964,43 +236067,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet0(&mut self) -> _RDET0W {
_RDET0W { w: self }
}
- #[doc = "Bit 1 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet1(&mut self) -> _RDET1W {
_RDET1W { w: self }
}
- #[doc = "Bit 2 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet2(&mut self) -> _RDET2W {
_RDET2W { w: self }
}
- #[doc = "Bit 3 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet3(&mut self) -> _RDET3W {
_RDET3W { w: self }
}
- #[doc = "Bit 4 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet4(&mut self) -> _RDET4W {
_RDET4W { w: self }
}
- #[doc = "Bit 5 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet5(&mut self) -> _RDET5W {
_RDET5W { w: self }
}
- #[doc = "Bit 6 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet6(&mut self) -> _RDET6W {
_RDET6W { w: self }
}
- #[doc = "Bit 7 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." ] # [ inline ( always ) ]
pub fn rdet7(&mut self) -> _RDET7W {
_RDET7W { w: self }
}
@@ -248414,8 +236509,7 @@ pub mod gpio_pin_int {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet0(&self) -> FDET0R {
let bits = {
const MASK: bool = true;
@@ -248424,8 +236518,7 @@ pub mod gpio_pin_int {
};
FDET0R { bits }
}
- #[doc = "Bit 1 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet1(&self) -> FDET1R {
let bits = {
const MASK: bool = true;
@@ -248434,8 +236527,7 @@ pub mod gpio_pin_int {
};
FDET1R { bits }
}
- #[doc = "Bit 2 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet2(&self) -> FDET2R {
let bits = {
const MASK: bool = true;
@@ -248444,8 +236536,7 @@ pub mod gpio_pin_int {
};
FDET2R { bits }
}
- #[doc = "Bit 3 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet3(&self) -> FDET3R {
let bits = {
const MASK: bool = true;
@@ -248454,8 +236545,7 @@ pub mod gpio_pin_int {
};
FDET3R { bits }
}
- #[doc = "Bit 4 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet4(&self) -> FDET4R {
let bits = {
const MASK: bool = true;
@@ -248464,8 +236554,7 @@ pub mod gpio_pin_int {
};
FDET4R { bits }
}
- #[doc = "Bit 5 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet5(&self) -> FDET5R {
let bits = {
const MASK: bool = true;
@@ -248474,8 +236563,7 @@ pub mod gpio_pin_int {
};
FDET5R { bits }
}
- #[doc = "Bit 6 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet6(&self) -> FDET6R {
let bits = {
const MASK: bool = true;
@@ -248484,8 +236572,7 @@ pub mod gpio_pin_int {
};
FDET6R { bits }
}
- #[doc = "Bit 7 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet7(&self) -> FDET7R {
let bits = {
const MASK: bool = true;
@@ -248507,43 +236594,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet0(&mut self) -> _FDET0W {
_FDET0W { w: self }
}
- #[doc = "Bit 1 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet1(&mut self) -> _FDET1W {
_FDET1W { w: self }
}
- #[doc = "Bit 2 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet2(&mut self) -> _FDET2W {
_FDET2W { w: self }
}
- #[doc = "Bit 3 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet3(&mut self) -> _FDET3W {
_FDET3W { w: self }
}
- #[doc = "Bit 4 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet4(&mut self) -> _FDET4W {
_FDET4W { w: self }
}
- #[doc = "Bit 5 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet5(&mut self) -> _FDET5W {
_FDET5W { w: self }
}
- #[doc = "Bit 6 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet6(&mut self) -> _FDET6W {
_FDET6W { w: self }
}
- #[doc = "Bit 7 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." ] # [ inline ( always ) ]
pub fn fdet7(&mut self) -> _FDET7W {
_FDET7W { w: self }
}
@@ -248957,8 +237036,7 @@ pub mod gpio_pin_int {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat0(&self) -> PSTAT0R {
let bits = {
const MASK: bool = true;
@@ -248967,8 +237045,7 @@ pub mod gpio_pin_int {
};
PSTAT0R { bits }
}
- #[doc = "Bit 1 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat1(&self) -> PSTAT1R {
let bits = {
const MASK: bool = true;
@@ -248977,8 +237054,7 @@ pub mod gpio_pin_int {
};
PSTAT1R { bits }
}
- #[doc = "Bit 2 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat2(&self) -> PSTAT2R {
let bits = {
const MASK: bool = true;
@@ -248987,8 +237063,7 @@ pub mod gpio_pin_int {
};
PSTAT2R { bits }
}
- #[doc = "Bit 3 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat3(&self) -> PSTAT3R {
let bits = {
const MASK: bool = true;
@@ -248997,8 +237072,7 @@ pub mod gpio_pin_int {
};
PSTAT3R { bits }
}
- #[doc = "Bit 4 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat4(&self) -> PSTAT4R {
let bits = {
const MASK: bool = true;
@@ -249007,8 +237081,7 @@ pub mod gpio_pin_int {
};
PSTAT4R { bits }
}
- #[doc = "Bit 5 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat5(&self) -> PSTAT5R {
let bits = {
const MASK: bool = true;
@@ -249017,8 +237090,7 @@ pub mod gpio_pin_int {
};
PSTAT5R { bits }
}
- #[doc = "Bit 6 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat6(&self) -> PSTAT6R {
let bits = {
const MASK: bool = true;
@@ -249027,8 +237099,7 @@ pub mod gpio_pin_int {
};
PSTAT6R { bits }
}
- #[doc = "Bit 7 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat7(&self) -> PSTAT7R {
let bits = {
const MASK: bool = true;
@@ -249050,43 +237121,35 @@ pub mod gpio_pin_int {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat0(&mut self) -> _PSTAT0W {
_PSTAT0W { w: self }
}
- #[doc = "Bit 1 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat1(&mut self) -> _PSTAT1W {
_PSTAT1W { w: self }
}
- #[doc = "Bit 2 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat2(&mut self) -> _PSTAT2W {
_PSTAT2W { w: self }
}
- #[doc = "Bit 3 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat3(&mut self) -> _PSTAT3W {
_PSTAT3W { w: self }
}
- #[doc = "Bit 4 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat4(&mut self) -> _PSTAT4W {
_PSTAT4W { w: self }
}
- #[doc = "Bit 5 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat5(&mut self) -> _PSTAT5W {
_PSTAT5W { w: self }
}
- #[doc = "Bit 6 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat6(&mut self) -> _PSTAT6W {
_PSTAT6W { w: self }
}
- #[doc = "Bit 7 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." ] # [ inline ( always ) ]
pub fn pstat7(&mut self) -> _PSTAT7W {
_PSTAT7W { w: self }
}
@@ -249112,41 +237175,24 @@ pub mod gpio_group_int0 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
- #[doc = "0x00 - GPIO grouped interrupt control register"]
- pub ctrl: CTRL,
+ #[doc = "0x00 - GPIO grouped interrupt control register"] pub ctrl: CTRL,
_reserved0: [u8; 28usize],
- #[doc = "0x20 - GPIO grouped interrupt port polarity register"]
- pub port_pol0: PORT_POL,
- #[doc = "0x24 - GPIO grouped interrupt port polarity register"]
- pub port_pol1: PORT_POL,
- #[doc = "0x28 - GPIO grouped interrupt port polarity register"]
- pub port_pol2: PORT_POL,
- #[doc = "0x2c - GPIO grouped interrupt port polarity register"]
- pub port_pol3: PORT_POL,
- #[doc = "0x30 - GPIO grouped interrupt port polarity register"]
- pub port_pol4: PORT_POL,
- #[doc = "0x34 - GPIO grouped interrupt port polarity register"]
- pub port_pol5: PORT_POL,
- #[doc = "0x38 - GPIO grouped interrupt port polarity register"]
- pub port_pol6: PORT_POL,
- #[doc = "0x3c - GPIO grouped interrupt port polarity register"]
- pub port_pol7: PORT_POL,
- #[doc = "0x40 - GPIO grouped interrupt port m enable register"]
- pub port_ena0: PORT_ENA,
- #[doc = "0x44 - GPIO grouped interrupt port m enable register"]
- pub port_ena1: PORT_ENA,
- #[doc = "0x48 - GPIO grouped interrupt port m enable register"]
- pub port_ena2: PORT_ENA,
- #[doc = "0x4c - GPIO grouped interrupt port m enable register"]
- pub port_ena3: PORT_ENA,
- #[doc = "0x50 - GPIO grouped interrupt port m enable register"]
- pub port_ena4: PORT_ENA,
- #[doc = "0x54 - GPIO grouped interrupt port m enable register"]
- pub port_ena5: PORT_ENA,
- #[doc = "0x58 - GPIO grouped interrupt port m enable register"]
- pub port_ena6: PORT_ENA,
- #[doc = "0x5c - GPIO grouped interrupt port m enable register"]
- pub port_ena7: PORT_ENA,
+ #[doc = "0x20 - GPIO grouped interrupt port polarity register"] pub port_pol0: PORT_POL,
+ #[doc = "0x24 - GPIO grouped interrupt port polarity register"] pub port_pol1: PORT_POL,
+ #[doc = "0x28 - GPIO grouped interrupt port polarity register"] pub port_pol2: PORT_POL,
+ #[doc = "0x2c - GPIO grouped interrupt port polarity register"] pub port_pol3: PORT_POL,
+ #[doc = "0x30 - GPIO grouped interrupt port polarity register"] pub port_pol4: PORT_POL,
+ #[doc = "0x34 - GPIO grouped interrupt port polarity register"] pub port_pol5: PORT_POL,
+ #[doc = "0x38 - GPIO grouped interrupt port polarity register"] pub port_pol6: PORT_POL,
+ #[doc = "0x3c - GPIO grouped interrupt port polarity register"] pub port_pol7: PORT_POL,
+ #[doc = "0x40 - GPIO grouped interrupt port m enable register"] pub port_ena0: PORT_ENA,
+ #[doc = "0x44 - GPIO grouped interrupt port m enable register"] pub port_ena1: PORT_ENA,
+ #[doc = "0x48 - GPIO grouped interrupt port m enable register"] pub port_ena2: PORT_ENA,
+ #[doc = "0x4c - GPIO grouped interrupt port m enable register"] pub port_ena3: PORT_ENA,
+ #[doc = "0x50 - GPIO grouped interrupt port m enable register"] pub port_ena4: PORT_ENA,
+ #[doc = "0x54 - GPIO grouped interrupt port m enable register"] pub port_ena5: PORT_ENA,
+ #[doc = "0x58 - GPIO grouped interrupt port m enable register"] pub port_ena6: PORT_ENA,
+ #[doc = "0x5c - GPIO grouped interrupt port m enable register"] pub port_ena7: PORT_ENA,
}
#[doc = "GPIO grouped interrupt control register"]
pub struct CTRL {
@@ -249245,12 +237291,7 @@ pub mod gpio_group_int0 {
}
#[doc = "Possible values of the field `COMB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum COMBR {
- #[doc = "OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)."]
- OR_FUNCTIONALITY_A_,
- #[doc = "AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)."]
- AND_FUNCTIONALITY_A,
- }
+ pub enum COMBR {# [ doc = "OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." ] OR_FUNCTIONALITY_A_ , # [ doc = "AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." ] AND_FUNCTIONALITY_A}
impl COMBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -249392,12 +237433,7 @@ pub mod gpio_group_int0 {
}
}
#[doc = "Values that can be written to the field `COMB`"]
- pub enum COMBW {
- #[doc = "OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)."]
- OR_FUNCTIONALITY_A_,
- #[doc = "AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)."]
- AND_FUNCTIONALITY_A,
- }
+ pub enum COMBW {# [ doc = "OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." ] OR_FUNCTIONALITY_A_ , # [ doc = "AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." ] AND_FUNCTIONALITY_A}
impl COMBW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -249421,13 +237457,11 @@ pub mod gpio_group_int0 {
self.bit(variant._bits())
}
}
- #[doc = "OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)."]
- #[inline(always)]
+ # [ doc = "OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." ] # [ inline ( always ) ]
pub fn or_functionality_a_(self) -> &'a mut W {
self.variant(COMBW::OR_FUNCTIONALITY_A_)
}
- #[doc = "AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)."]
- #[inline(always)]
+ # [ doc = "AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." ] # [ inline ( always ) ]
pub fn and_functionality_a(self) -> &'a mut W {
self.variant(COMBW::AND_FUNCTIONALITY_A)
}
@@ -249511,8 +237545,7 @@ pub mod gpio_group_int0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." ] # [ inline ( always ) ]
pub fn int(&self) -> INTR {
INTR::_from({
const MASK: bool = true;
@@ -249551,8 +237584,7 @@ pub mod gpio_group_int0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." ] # [ inline ( always ) ]
pub fn int(&mut self) -> _INTW {
_INTW { w: self }
}
@@ -251032,8 +239064,7 @@ pub mod gpio_group_int0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_0(&self) -> POL_0R {
let bits = {
const MASK: bool = true;
@@ -251042,8 +239073,7 @@ pub mod gpio_group_int0 {
};
POL_0R { bits }
}
- #[doc = "Bit 1 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_1(&self) -> POL_1R {
let bits = {
const MASK: bool = true;
@@ -251052,8 +239082,7 @@ pub mod gpio_group_int0 {
};
POL_1R { bits }
}
- #[doc = "Bit 2 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_2(&self) -> POL_2R {
let bits = {
const MASK: bool = true;
@@ -251062,8 +239091,7 @@ pub mod gpio_group_int0 {
};
POL_2R { bits }
}
- #[doc = "Bit 3 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_3(&self) -> POL_3R {
let bits = {
const MASK: bool = true;
@@ -251072,8 +239100,7 @@ pub mod gpio_group_int0 {
};
POL_3R { bits }
}
- #[doc = "Bit 4 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_4(&self) -> POL_4R {
let bits = {
const MASK: bool = true;
@@ -251082,8 +239109,7 @@ pub mod gpio_group_int0 {
};
POL_4R { bits }
}
- #[doc = "Bit 5 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_5(&self) -> POL_5R {
let bits = {
const MASK: bool = true;
@@ -251092,8 +239118,7 @@ pub mod gpio_group_int0 {
};
POL_5R { bits }
}
- #[doc = "Bit 6 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_6(&self) -> POL_6R {
let bits = {
const MASK: bool = true;
@@ -251102,8 +239127,7 @@ pub mod gpio_group_int0 {
};
POL_6R { bits }
}
- #[doc = "Bit 7 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_7(&self) -> POL_7R {
let bits = {
const MASK: bool = true;
@@ -251112,8 +239136,7 @@ pub mod gpio_group_int0 {
};
POL_7R { bits }
}
- #[doc = "Bit 8 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_8(&self) -> POL_8R {
let bits = {
const MASK: bool = true;
@@ -251122,8 +239145,7 @@ pub mod gpio_group_int0 {
};
POL_8R { bits }
}
- #[doc = "Bit 9 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_9(&self) -> POL_9R {
let bits = {
const MASK: bool = true;
@@ -251132,8 +239154,7 @@ pub mod gpio_group_int0 {
};
POL_9R { bits }
}
- #[doc = "Bit 10 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_10(&self) -> POL_10R {
let bits = {
const MASK: bool = true;
@@ -251142,8 +239163,7 @@ pub mod gpio_group_int0 {
};
POL_10R { bits }
}
- #[doc = "Bit 11 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_11(&self) -> POL_11R {
let bits = {
const MASK: bool = true;
@@ -251152,8 +239172,7 @@ pub mod gpio_group_int0 {
};
POL_11R { bits }
}
- #[doc = "Bit 12 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_12(&self) -> POL_12R {
let bits = {
const MASK: bool = true;
@@ -251162,8 +239181,7 @@ pub mod gpio_group_int0 {
};
POL_12R { bits }
}
- #[doc = "Bit 13 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_13(&self) -> POL_13R {
let bits = {
const MASK: bool = true;
@@ -251172,8 +239190,7 @@ pub mod gpio_group_int0 {
};
POL_13R { bits }
}
- #[doc = "Bit 14 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_14(&self) -> POL_14R {
let bits = {
const MASK: bool = true;
@@ -251182,8 +239199,7 @@ pub mod gpio_group_int0 {
};
POL_14R { bits }
}
- #[doc = "Bit 15 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_15(&self) -> POL_15R {
let bits = {
const MASK: bool = true;
@@ -251192,8 +239208,7 @@ pub mod gpio_group_int0 {
};
POL_15R { bits }
}
- #[doc = "Bit 16 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_16(&self) -> POL_16R {
let bits = {
const MASK: bool = true;
@@ -251202,8 +239217,7 @@ pub mod gpio_group_int0 {
};
POL_16R { bits }
}
- #[doc = "Bit 17 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_17(&self) -> POL_17R {
let bits = {
const MASK: bool = true;
@@ -251212,8 +239226,7 @@ pub mod gpio_group_int0 {
};
POL_17R { bits }
}
- #[doc = "Bit 18 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_18(&self) -> POL_18R {
let bits = {
const MASK: bool = true;
@@ -251222,8 +239235,7 @@ pub mod gpio_group_int0 {
};
POL_18R { bits }
}
- #[doc = "Bit 19 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_19(&self) -> POL_19R {
let bits = {
const MASK: bool = true;
@@ -251232,8 +239244,7 @@ pub mod gpio_group_int0 {
};
POL_19R { bits }
}
- #[doc = "Bit 20 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_20(&self) -> POL_20R {
let bits = {
const MASK: bool = true;
@@ -251242,8 +239253,7 @@ pub mod gpio_group_int0 {
};
POL_20R { bits }
}
- #[doc = "Bit 21 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_21(&self) -> POL_21R {
let bits = {
const MASK: bool = true;
@@ -251252,8 +239262,7 @@ pub mod gpio_group_int0 {
};
POL_21R { bits }
}
- #[doc = "Bit 22 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_22(&self) -> POL_22R {
let bits = {
const MASK: bool = true;
@@ -251262,8 +239271,7 @@ pub mod gpio_group_int0 {
};
POL_22R { bits }
}
- #[doc = "Bit 23 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_23(&self) -> POL_23R {
let bits = {
const MASK: bool = true;
@@ -251272,8 +239280,7 @@ pub mod gpio_group_int0 {
};
POL_23R { bits }
}
- #[doc = "Bit 24 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_24(&self) -> POL_24R {
let bits = {
const MASK: bool = true;
@@ -251282,8 +239289,7 @@ pub mod gpio_group_int0 {
};
POL_24R { bits }
}
- #[doc = "Bit 25 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_25(&self) -> POL_25R {
let bits = {
const MASK: bool = true;
@@ -251292,8 +239298,7 @@ pub mod gpio_group_int0 {
};
POL_25R { bits }
}
- #[doc = "Bit 26 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_26(&self) -> POL_26R {
let bits = {
const MASK: bool = true;
@@ -251302,8 +239307,7 @@ pub mod gpio_group_int0 {
};
POL_26R { bits }
}
- #[doc = "Bit 27 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_27(&self) -> POL_27R {
let bits = {
const MASK: bool = true;
@@ -251312,8 +239316,7 @@ pub mod gpio_group_int0 {
};
POL_27R { bits }
}
- #[doc = "Bit 28 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_28(&self) -> POL_28R {
let bits = {
const MASK: bool = true;
@@ -251322,8 +239325,7 @@ pub mod gpio_group_int0 {
};
POL_28R { bits }
}
- #[doc = "Bit 29 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_29(&self) -> POL_29R {
let bits = {
const MASK: bool = true;
@@ -251332,8 +239334,7 @@ pub mod gpio_group_int0 {
};
POL_29R { bits }
}
- #[doc = "Bit 30 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_30(&self) -> POL_30R {
let bits = {
const MASK: bool = true;
@@ -251342,8 +239343,7 @@ pub mod gpio_group_int0 {
};
POL_30R { bits }
}
- #[doc = "Bit 31 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_31(&self) -> POL_31R {
let bits = {
const MASK: bool = true;
@@ -251365,163 +239365,131 @@ pub mod gpio_group_int0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_0(&mut self) -> _POL_0W {
_POL_0W { w: self }
}
- #[doc = "Bit 1 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_1(&mut self) -> _POL_1W {
_POL_1W { w: self }
}
- #[doc = "Bit 2 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_2(&mut self) -> _POL_2W {
_POL_2W { w: self }
}
- #[doc = "Bit 3 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_3(&mut self) -> _POL_3W {
_POL_3W { w: self }
}
- #[doc = "Bit 4 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_4(&mut self) -> _POL_4W {
_POL_4W { w: self }
}
- #[doc = "Bit 5 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_5(&mut self) -> _POL_5W {
_POL_5W { w: self }
}
- #[doc = "Bit 6 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_6(&mut self) -> _POL_6W {
_POL_6W { w: self }
}
- #[doc = "Bit 7 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_7(&mut self) -> _POL_7W {
_POL_7W { w: self }
}
- #[doc = "Bit 8 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_8(&mut self) -> _POL_8W {
_POL_8W { w: self }
}
- #[doc = "Bit 9 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_9(&mut self) -> _POL_9W {
_POL_9W { w: self }
}
- #[doc = "Bit 10 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_10(&mut self) -> _POL_10W {
_POL_10W { w: self }
}
- #[doc = "Bit 11 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_11(&mut self) -> _POL_11W {
_POL_11W { w: self }
}
- #[doc = "Bit 12 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_12(&mut self) -> _POL_12W {
_POL_12W { w: self }
}
- #[doc = "Bit 13 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_13(&mut self) -> _POL_13W {
_POL_13W { w: self }
}
- #[doc = "Bit 14 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_14(&mut self) -> _POL_14W {
_POL_14W { w: self }
}
- #[doc = "Bit 15 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_15(&mut self) -> _POL_15W {
_POL_15W { w: self }
}
- #[doc = "Bit 16 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_16(&mut self) -> _POL_16W {
_POL_16W { w: self }
}
- #[doc = "Bit 17 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_17(&mut self) -> _POL_17W {
_POL_17W { w: self }
}
- #[doc = "Bit 18 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_18(&mut self) -> _POL_18W {
_POL_18W { w: self }
}
- #[doc = "Bit 19 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_19(&mut self) -> _POL_19W {
_POL_19W { w: self }
}
- #[doc = "Bit 20 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_20(&mut self) -> _POL_20W {
_POL_20W { w: self }
}
- #[doc = "Bit 21 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_21(&mut self) -> _POL_21W {
_POL_21W { w: self }
}
- #[doc = "Bit 22 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_22(&mut self) -> _POL_22W {
_POL_22W { w: self }
}
- #[doc = "Bit 23 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_23(&mut self) -> _POL_23W {
_POL_23W { w: self }
}
- #[doc = "Bit 24 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_24(&mut self) -> _POL_24W {
_POL_24W { w: self }
}
- #[doc = "Bit 25 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_25(&mut self) -> _POL_25W {
_POL_25W { w: self }
}
- #[doc = "Bit 26 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_26(&mut self) -> _POL_26W {
_POL_26W { w: self }
}
- #[doc = "Bit 27 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_27(&mut self) -> _POL_27W {
_POL_27W { w: self }
}
- #[doc = "Bit 28 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_28(&mut self) -> _POL_28W {
_POL_28W { w: self }
}
- #[doc = "Bit 29 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_29(&mut self) -> _POL_29W {
_POL_29W { w: self }
}
- #[doc = "Bit 30 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_30(&mut self) -> _POL_30W {
_POL_30W { w: self }
}
- #[doc = "Bit 31 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." ] # [ inline ( always ) ]
pub fn pol_31(&mut self) -> _POL_31W {
_POL_31W { w: self }
}
@@ -252991,8 +240959,7 @@ pub mod gpio_group_int0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_0(&self) -> ENA_0R {
let bits = {
const MASK: bool = true;
@@ -253001,8 +240968,7 @@ pub mod gpio_group_int0 {
};
ENA_0R { bits }
}
- #[doc = "Bit 1 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_1(&self) -> ENA_1R {
let bits = {
const MASK: bool = true;
@@ -253011,8 +240977,7 @@ pub mod gpio_group_int0 {
};
ENA_1R { bits }
}
- #[doc = "Bit 2 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_2(&self) -> ENA_2R {
let bits = {
const MASK: bool = true;
@@ -253021,8 +240986,7 @@ pub mod gpio_group_int0 {
};
ENA_2R { bits }
}
- #[doc = "Bit 3 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_3(&self) -> ENA_3R {
let bits = {
const MASK: bool = true;
@@ -253031,8 +240995,7 @@ pub mod gpio_group_int0 {
};
ENA_3R { bits }
}
- #[doc = "Bit 4 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_4(&self) -> ENA_4R {
let bits = {
const MASK: bool = true;
@@ -253041,8 +241004,7 @@ pub mod gpio_group_int0 {
};
ENA_4R { bits }
}
- #[doc = "Bit 5 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_5(&self) -> ENA_5R {
let bits = {
const MASK: bool = true;
@@ -253051,8 +241013,7 @@ pub mod gpio_group_int0 {
};
ENA_5R { bits }
}
- #[doc = "Bit 6 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_6(&self) -> ENA_6R {
let bits = {
const MASK: bool = true;
@@ -253061,8 +241022,7 @@ pub mod gpio_group_int0 {
};
ENA_6R { bits }
}
- #[doc = "Bit 7 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_7(&self) -> ENA_7R {
let bits = {
const MASK: bool = true;
@@ -253071,8 +241031,7 @@ pub mod gpio_group_int0 {
};
ENA_7R { bits }
}
- #[doc = "Bit 8 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_8(&self) -> ENA_8R {
let bits = {
const MASK: bool = true;
@@ -253081,8 +241040,7 @@ pub mod gpio_group_int0 {
};
ENA_8R { bits }
}
- #[doc = "Bit 9 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_9(&self) -> ENA_9R {
let bits = {
const MASK: bool = true;
@@ -253091,8 +241049,7 @@ pub mod gpio_group_int0 {
};
ENA_9R { bits }
}
- #[doc = "Bit 10 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_10(&self) -> ENA_10R {
let bits = {
const MASK: bool = true;
@@ -253101,8 +241058,7 @@ pub mod gpio_group_int0 {
};
ENA_10R { bits }
}
- #[doc = "Bit 11 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_11(&self) -> ENA_11R {
let bits = {
const MASK: bool = true;
@@ -253111,8 +241067,7 @@ pub mod gpio_group_int0 {
};
ENA_11R { bits }
}
- #[doc = "Bit 12 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_12(&self) -> ENA_12R {
let bits = {
const MASK: bool = true;
@@ -253121,8 +241076,7 @@ pub mod gpio_group_int0 {
};
ENA_12R { bits }
}
- #[doc = "Bit 13 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_13(&self) -> ENA_13R {
let bits = {
const MASK: bool = true;
@@ -253131,8 +241085,7 @@ pub mod gpio_group_int0 {
};
ENA_13R { bits }
}
- #[doc = "Bit 14 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_14(&self) -> ENA_14R {
let bits = {
const MASK: bool = true;
@@ -253141,8 +241094,7 @@ pub mod gpio_group_int0 {
};
ENA_14R { bits }
}
- #[doc = "Bit 15 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_15(&self) -> ENA_15R {
let bits = {
const MASK: bool = true;
@@ -253151,8 +241103,7 @@ pub mod gpio_group_int0 {
};
ENA_15R { bits }
}
- #[doc = "Bit 16 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_16(&self) -> ENA_16R {
let bits = {
const MASK: bool = true;
@@ -253161,8 +241112,7 @@ pub mod gpio_group_int0 {
};
ENA_16R { bits }
}
- #[doc = "Bit 17 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_17(&self) -> ENA_17R {
let bits = {
const MASK: bool = true;
@@ -253171,8 +241121,7 @@ pub mod gpio_group_int0 {
};
ENA_17R { bits }
}
- #[doc = "Bit 18 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_18(&self) -> ENA_18R {
let bits = {
const MASK: bool = true;
@@ -253181,8 +241130,7 @@ pub mod gpio_group_int0 {
};
ENA_18R { bits }
}
- #[doc = "Bit 19 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_19(&self) -> ENA_19R {
let bits = {
const MASK: bool = true;
@@ -253191,8 +241139,7 @@ pub mod gpio_group_int0 {
};
ENA_19R { bits }
}
- #[doc = "Bit 20 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_20(&self) -> ENA_20R {
let bits = {
const MASK: bool = true;
@@ -253201,8 +241148,7 @@ pub mod gpio_group_int0 {
};
ENA_20R { bits }
}
- #[doc = "Bit 21 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_21(&self) -> ENA_21R {
let bits = {
const MASK: bool = true;
@@ -253211,8 +241157,7 @@ pub mod gpio_group_int0 {
};
ENA_21R { bits }
}
- #[doc = "Bit 22 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_22(&self) -> ENA_22R {
let bits = {
const MASK: bool = true;
@@ -253221,8 +241166,7 @@ pub mod gpio_group_int0 {
};
ENA_22R { bits }
}
- #[doc = "Bit 23 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_23(&self) -> ENA_23R {
let bits = {
const MASK: bool = true;
@@ -253231,8 +241175,7 @@ pub mod gpio_group_int0 {
};
ENA_23R { bits }
}
- #[doc = "Bit 24 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_24(&self) -> ENA_24R {
let bits = {
const MASK: bool = true;
@@ -253241,8 +241184,7 @@ pub mod gpio_group_int0 {
};
ENA_24R { bits }
}
- #[doc = "Bit 25 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_25(&self) -> ENA_25R {
let bits = {
const MASK: bool = true;
@@ -253251,8 +241193,7 @@ pub mod gpio_group_int0 {
};
ENA_25R { bits }
}
- #[doc = "Bit 26 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_26(&self) -> ENA_26R {
let bits = {
const MASK: bool = true;
@@ -253261,8 +241202,7 @@ pub mod gpio_group_int0 {
};
ENA_26R { bits }
}
- #[doc = "Bit 27 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_27(&self) -> ENA_27R {
let bits = {
const MASK: bool = true;
@@ -253271,8 +241211,7 @@ pub mod gpio_group_int0 {
};
ENA_27R { bits }
}
- #[doc = "Bit 28 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_28(&self) -> ENA_28R {
let bits = {
const MASK: bool = true;
@@ -253281,8 +241220,7 @@ pub mod gpio_group_int0 {
};
ENA_28R { bits }
}
- #[doc = "Bit 29 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_29(&self) -> ENA_29R {
let bits = {
const MASK: bool = true;
@@ -253291,8 +241229,7 @@ pub mod gpio_group_int0 {
};
ENA_29R { bits }
}
- #[doc = "Bit 30 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_30(&self) -> ENA_30R {
let bits = {
const MASK: bool = true;
@@ -253301,8 +241238,7 @@ pub mod gpio_group_int0 {
};
ENA_30R { bits }
}
- #[doc = "Bit 31 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_31(&self) -> ENA_31R {
let bits = {
const MASK: bool = true;
@@ -253324,163 +241260,131 @@ pub mod gpio_group_int0 {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_0(&mut self) -> _ENA_0W {
_ENA_0W { w: self }
}
- #[doc = "Bit 1 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_1(&mut self) -> _ENA_1W {
_ENA_1W { w: self }
}
- #[doc = "Bit 2 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_2(&mut self) -> _ENA_2W {
_ENA_2W { w: self }
}
- #[doc = "Bit 3 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_3(&mut self) -> _ENA_3W {
_ENA_3W { w: self }
}
- #[doc = "Bit 4 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_4(&mut self) -> _ENA_4W {
_ENA_4W { w: self }
}
- #[doc = "Bit 5 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_5(&mut self) -> _ENA_5W {
_ENA_5W { w: self }
}
- #[doc = "Bit 6 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_6(&mut self) -> _ENA_6W {
_ENA_6W { w: self }
}
- #[doc = "Bit 7 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_7(&mut self) -> _ENA_7W {
_ENA_7W { w: self }
}
- #[doc = "Bit 8 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_8(&mut self) -> _ENA_8W {
_ENA_8W { w: self }
}
- #[doc = "Bit 9 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_9(&mut self) -> _ENA_9W {
_ENA_9W { w: self }
}
- #[doc = "Bit 10 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_10(&mut self) -> _ENA_10W {
_ENA_10W { w: self }
}
- #[doc = "Bit 11 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_11(&mut self) -> _ENA_11W {
_ENA_11W { w: self }
}
- #[doc = "Bit 12 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_12(&mut self) -> _ENA_12W {
_ENA_12W { w: self }
}
- #[doc = "Bit 13 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_13(&mut self) -> _ENA_13W {
_ENA_13W { w: self }
}
- #[doc = "Bit 14 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_14(&mut self) -> _ENA_14W {
_ENA_14W { w: self }
}
- #[doc = "Bit 15 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_15(&mut self) -> _ENA_15W {
_ENA_15W { w: self }
}
- #[doc = "Bit 16 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_16(&mut self) -> _ENA_16W {
_ENA_16W { w: self }
}
- #[doc = "Bit 17 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_17(&mut self) -> _ENA_17W {
_ENA_17W { w: self }
}
- #[doc = "Bit 18 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_18(&mut self) -> _ENA_18W {
_ENA_18W { w: self }
}
- #[doc = "Bit 19 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_19(&mut self) -> _ENA_19W {
_ENA_19W { w: self }
}
- #[doc = "Bit 20 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_20(&mut self) -> _ENA_20W {
_ENA_20W { w: self }
}
- #[doc = "Bit 21 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_21(&mut self) -> _ENA_21W {
_ENA_21W { w: self }
}
- #[doc = "Bit 22 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_22(&mut self) -> _ENA_22W {
_ENA_22W { w: self }
}
- #[doc = "Bit 23 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_23(&mut self) -> _ENA_23W {
_ENA_23W { w: self }
}
- #[doc = "Bit 24 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_24(&mut self) -> _ENA_24W {
_ENA_24W { w: self }
}
- #[doc = "Bit 25 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_25(&mut self) -> _ENA_25W {
_ENA_25W { w: self }
}
- #[doc = "Bit 26 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_26(&mut self) -> _ENA_26W {
_ENA_26W { w: self }
}
- #[doc = "Bit 27 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_27(&mut self) -> _ENA_27W {
_ENA_27W { w: self }
}
- #[doc = "Bit 28 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_28(&mut self) -> _ENA_28W {
_ENA_28W { w: self }
}
- #[doc = "Bit 29 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_29(&mut self) -> _ENA_29W {
_ENA_29W { w: self }
}
- #[doc = "Bit 30 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_30(&mut self) -> _ENA_30W {
_ENA_30W { w: self }
}
- #[doc = "Bit 31 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." ] # [ inline ( always ) ]
pub fn ena_31(&mut self) -> _ENA_31W {
_ENA_31W { w: self }
}
@@ -253522,10 +241426,8 @@ pub mod mcpwm {
#[doc = "0x04 - PWM Control set address"] pub con_set: CON_SET,
#[doc = "0x08 - PWM Control clear address"] pub con_clr: CON_CLR,
#[doc = "0x0c - Capture Control read address"] pub capcon: CAPCON,
- #[doc = "0x10 - Capture Control set address"]
- pub capcon_set: CAPCON_SET,
- #[doc = "0x14 - Event Control clear address"]
- pub capcon_clr: CAPCON_CLR,
+ #[doc = "0x10 - Capture Control set address"] pub capcon_set: CAPCON_SET,
+ #[doc = "0x14 - Event Control clear address"] pub capcon_clr: CAPCON_CLR,
#[doc = "0x18 - Timer Counter register"] pub tc0: TC,
#[doc = "0x1c - Timer Counter register"] pub tc1: TC,
#[doc = "0x20 - Timer Counter register"] pub tc2: TC,
@@ -253542,12 +241444,10 @@ pub mod mcpwm {
#[doc = "0x4c - Capture register"] pub cap2: CAP,
#[doc = "0x50 - Interrupt Enable read address"] pub inten: INTEN,
#[doc = "0x54 - Interrupt Enable set address"] pub inten_set: INTEN_SET,
- #[doc = "0x58 - Interrupt Enable clear address"]
- pub inten_clr: INTEN_CLR,
+ #[doc = "0x58 - Interrupt Enable clear address"] pub inten_clr: INTEN_CLR,
#[doc = "0x5c - Count Control read address"] pub cntcon: CNTCON,
#[doc = "0x60 - Count Control set address"] pub cntcon_set: CNTCON_SET,
- #[doc = "0x64 - Count Control clear address"]
- pub cntcon_clr: CNTCON_CLR,
+ #[doc = "0x64 - Count Control clear address"] pub cntcon_clr: CNTCON_CLR,
#[doc = "0x68 - Interrupt flags read address"] pub intf: INTF,
#[doc = "0x6c - Interrupt flags set address"] pub intf_set: INTF_SET,
#[doc = "0x70 - Interrupt flags clear address"] pub intf_clr: INTF_CLR,
@@ -253665,10 +241565,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `POLA0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POLA0R {
- #[doc = "Passive state is LOW, active state is HIGH."]
- PASSIVE_STATE_IS_LOW,
- #[doc = "Passive state is HIGH, active state is LOW."]
- PASSIVE_STATE_IS_HIG,
+ #[doc = "Passive state is LOW, active state is HIGH."] PASSIVE_STATE_IS_LOW,
+ #[doc = "Passive state is HIGH, active state is LOW."] PASSIVE_STATE_IS_HIG,
}
impl POLA0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -253756,12 +241654,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `DISUP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DISUP0R {
- #[doc = "Functional registers are updated from the write registers at the end of each PWM cycle."]
- UPDATE,
- #[doc = "Functional registers remain the same as long as the timer is running."]
- NOUPDATE,
- }
+ pub enum DISUP0R {# [ doc = "Functional registers are updated from the write registers at the end of each PWM cycle." ] UPDATE , # [ doc = "Functional registers remain the same as long as the timer is running." ] NOUPDATE}
impl DISUP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -253894,10 +241787,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `POLA1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POLA1R {
- #[doc = "Passive state is LOW, active state is HIGH."]
- PASSIVE_STATE_IS_LOW,
- #[doc = "Passive state is HIGH, active state is LOW."]
- PASSIVE_STATE_IS_HIG,
+ #[doc = "Passive state is LOW, active state is HIGH."] PASSIVE_STATE_IS_LOW,
+ #[doc = "Passive state is HIGH, active state is LOW."] PASSIVE_STATE_IS_HIG,
}
impl POLA1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -253985,12 +241876,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `DISUP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DISUP1R {
- #[doc = "Functional registers are updated from the write registers at the end of each PWM cycle."]
- UPDATE,
- #[doc = "Functional registers remain the same as long as the timer is running."]
- NOUPDATE,
- }
+ pub enum DISUP1R {# [ doc = "Functional registers are updated from the write registers at the end of each PWM cycle." ] UPDATE , # [ doc = "Functional registers remain the same as long as the timer is running." ] NOUPDATE}
impl DISUP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -254123,10 +242009,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `POLA2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POLA2R {
- #[doc = "Passive state is LOW, active state is HIGH."]
- PASSIVE_STATE_IS_LOW,
- #[doc = "Passive state is HIGH, active state is LOW."]
- PASSIVE_STATE_IS_HIG,
+ #[doc = "Passive state is LOW, active state is HIGH."] PASSIVE_STATE_IS_LOW,
+ #[doc = "Passive state is HIGH, active state is LOW."] PASSIVE_STATE_IS_HIG,
}
impl POLA2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -254214,12 +242098,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `DISUP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DISUP2R {
- #[doc = "Functional registers are updated from the write registers at the end of each PWM cycle."]
- UPDATE,
- #[doc = "Functional registers remain the same as long as the timer is running."]
- NOUPDATE,
- }
+ pub enum DISUP2R {# [ doc = "Functional registers are updated from the write registers at the end of each PWM cycle." ] UPDATE , # [ doc = "Functional registers remain the same as long as the timer is running." ] NOUPDATE}
impl DISUP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -254261,12 +242140,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `INVBDC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum INVBDCR {
- #[doc = "The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)."]
- OPPOSITE,
- #[doc = "The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)"]
- SAME,
- }
+ pub enum INVBDCR {# [ doc = "The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." ] OPPOSITE , # [ doc = "The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" ] SAME}
impl INVBDCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -254308,12 +242182,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ACMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ACMODER {
- #[doc = "3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register."]
- _3_PHASE_AC_MODE_OFF,
- #[doc = "3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0."]
- _3_PHASE_AC_MODE_ON_,
- }
+ pub enum ACMODER {# [ doc = "3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." ] _3_PHASE_AC_MODE_OFF , # [ doc = "3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." ] _3_PHASE_AC_MODE_ON_}
impl ACMODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -254355,12 +242224,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `DCMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DCMODER {
- #[doc = "3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)"]
- _3_PHASE_DC_MODE_OFF,
- #[doc = "3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs."]
- _3_PHASE_DC_MODE_ON_,
- }
+ pub enum DCMODER {# [ doc = "3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" ] _3_PHASE_DC_MODE_OFF , # [ doc = "3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." ] _3_PHASE_DC_MODE_ON_}
impl DCMODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -254442,8 +242306,7 @@ pub mod mcpwm {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Enable/disable updates of functional registers for channel 0 (see Section 24.8.2)."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Enable/disable updates of functional registers for channel 0 (see Section 24.8.2)." ] # [ inline ( always ) ]
pub fn disup0(&self) -> DISUP0R {
DISUP0R::_from({
const MASK: bool = true;
@@ -254487,8 +242350,7 @@ pub mod mcpwm {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 12 - Enable/disable updates of functional registers for channel 1 (see Section 24.8.2)."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Enable/disable updates of functional registers for channel 1 (see Section 24.8.2)." ] # [ inline ( always ) ]
pub fn disup1(&self) -> DISUP1R {
DISUP1R::_from({
const MASK: bool = true;
@@ -254532,8 +242394,7 @@ pub mod mcpwm {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 20 - Enable/disable updates of functional registers for channel 2 (see Section 24.8.2)."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Enable/disable updates of functional registers for channel 2 (see Section 24.8.2)." ] # [ inline ( always ) ]
pub fn disup2(&self) -> DISUP2R {
DISUP2R::_from({
const MASK: bool = true;
@@ -254541,8 +242402,7 @@ pub mod mcpwm {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 29 - Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode." ] # [ inline ( always ) ]
pub fn invbdc(&self) -> INVBDCR {
INVBDCR::_from({
const MASK: bool = true;
@@ -256116,8 +243976,7 @@ pub mod mcpwm {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." ] # [ inline ( always ) ]
pub fn cap0mci0_re(&self) -> CAP0MCI0_RER {
let bits = {
const MASK: bool = true;
@@ -256126,8 +243985,7 @@ pub mod mcpwm {
};
CAP0MCI0_RER { bits }
}
- #[doc = "Bit 1 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." ] # [ inline ( always ) ]
pub fn cap0mci0_fe(&self) -> CAP0MCI0_FER {
let bits = {
const MASK: bool = true;
@@ -256136,8 +243994,7 @@ pub mod mcpwm {
};
CAP0MCI0_FER { bits }
}
- #[doc = "Bit 2 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1."]
- #[inline(always)]
+ # [ doc = "Bit 2 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." ] # [ inline ( always ) ]
pub fn cap0mci1_re(&self) -> CAP0MCI1_RER {
let bits = {
const MASK: bool = true;
@@ -256146,8 +244003,7 @@ pub mod mcpwm {
};
CAP0MCI1_RER { bits }
}
- #[doc = "Bit 3 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1."]
- #[inline(always)]
+ # [ doc = "Bit 3 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." ] # [ inline ( always ) ]
pub fn cap0mci1_fe(&self) -> CAP0MCI1_FER {
let bits = {
const MASK: bool = true;
@@ -256156,8 +244012,7 @@ pub mod mcpwm {
};
CAP0MCI1_FER { bits }
}
- #[doc = "Bit 4 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2."]
- #[inline(always)]
+ # [ doc = "Bit 4 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." ] # [ inline ( always ) ]
pub fn cap0mci2_re(&self) -> CAP0MCI2_RER {
let bits = {
const MASK: bool = true;
@@ -256166,8 +244021,7 @@ pub mod mcpwm {
};
CAP0MCI2_RER { bits }
}
- #[doc = "Bit 5 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2."]
- #[inline(always)]
+ # [ doc = "Bit 5 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." ] # [ inline ( always ) ]
pub fn cap0mci2_fe(&self) -> CAP0MCI2_FER {
let bits = {
const MASK: bool = true;
@@ -256176,8 +244030,7 @@ pub mod mcpwm {
};
CAP0MCI2_FER { bits }
}
- #[doc = "Bit 6 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." ] # [ inline ( always ) ]
pub fn cap1mci0_re(&self) -> CAP1MCI0_RER {
let bits = {
const MASK: bool = true;
@@ -256186,8 +244039,7 @@ pub mod mcpwm {
};
CAP1MCI0_RER { bits }
}
- #[doc = "Bit 7 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." ] # [ inline ( always ) ]
pub fn cap1mci0_fe(&self) -> CAP1MCI0_FER {
let bits = {
const MASK: bool = true;
@@ -256196,8 +244048,7 @@ pub mod mcpwm {
};
CAP1MCI0_FER { bits }
}
- #[doc = "Bit 8 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1."]
- #[inline(always)]
+ # [ doc = "Bit 8 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." ] # [ inline ( always ) ]
pub fn cap1mci1_re(&self) -> CAP1MCI1_RER {
let bits = {
const MASK: bool = true;
@@ -256206,8 +244057,7 @@ pub mod mcpwm {
};
CAP1MCI1_RER { bits }
}
- #[doc = "Bit 9 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1."]
- #[inline(always)]
+ # [ doc = "Bit 9 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." ] # [ inline ( always ) ]
pub fn cap1mci1_fe(&self) -> CAP1MCI1_FER {
let bits = {
const MASK: bool = true;
@@ -256216,8 +244066,7 @@ pub mod mcpwm {
};
CAP1MCI1_FER { bits }
}
- #[doc = "Bit 10 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2."]
- #[inline(always)]
+ # [ doc = "Bit 10 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." ] # [ inline ( always ) ]
pub fn cap1mci2_re(&self) -> CAP1MCI2_RER {
let bits = {
const MASK: bool = true;
@@ -256226,8 +244075,7 @@ pub mod mcpwm {
};
CAP1MCI2_RER { bits }
}
- #[doc = "Bit 11 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2."]
- #[inline(always)]
+ # [ doc = "Bit 11 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." ] # [ inline ( always ) ]
pub fn cap1mci2_fe(&self) -> CAP1MCI2_FER {
let bits = {
const MASK: bool = true;
@@ -256236,8 +244084,7 @@ pub mod mcpwm {
};
CAP1MCI2_FER { bits }
}
- #[doc = "Bit 12 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0."]
- #[inline(always)]
+ # [ doc = "Bit 12 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." ] # [ inline ( always ) ]
pub fn cap2mci0_re(&self) -> CAP2MCI0_RER {
let bits = {
const MASK: bool = true;
@@ -256246,8 +244093,7 @@ pub mod mcpwm {
};
CAP2MCI0_RER { bits }
}
- #[doc = "Bit 13 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0."]
- #[inline(always)]
+ # [ doc = "Bit 13 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." ] # [ inline ( always ) ]
pub fn cap2mci0_fe(&self) -> CAP2MCI0_FER {
let bits = {
const MASK: bool = true;
@@ -256256,8 +244102,7 @@ pub mod mcpwm {
};
CAP2MCI0_FER { bits }
}
- #[doc = "Bit 14 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1."]
- #[inline(always)]
+ # [ doc = "Bit 14 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." ] # [ inline ( always ) ]
pub fn cap2mci1_re(&self) -> CAP2MCI1_RER {
let bits = {
const MASK: bool = true;
@@ -256266,8 +244111,7 @@ pub mod mcpwm {
};
CAP2MCI1_RER { bits }
}
- #[doc = "Bit 15 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1."]
- #[inline(always)]
+ # [ doc = "Bit 15 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." ] # [ inline ( always ) ]
pub fn cap2mci1_fe(&self) -> CAP2MCI1_FER {
let bits = {
const MASK: bool = true;
@@ -256276,8 +244120,7 @@ pub mod mcpwm {
};
CAP2MCI1_FER { bits }
}
- #[doc = "Bit 16 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2."]
- #[inline(always)]
+ # [ doc = "Bit 16 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." ] # [ inline ( always ) ]
pub fn cap2mci2_re(&self) -> CAP2MCI2_RER {
let bits = {
const MASK: bool = true;
@@ -256286,8 +244129,7 @@ pub mod mcpwm {
};
CAP2MCI2_RER { bits }
}
- #[doc = "Bit 17 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2."]
- #[inline(always)]
+ # [ doc = "Bit 17 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." ] # [ inline ( always ) ]
pub fn cap2mci2_fe(&self) -> CAP2MCI2_FER {
let bits = {
const MASK: bool = true;
@@ -259746,53 +247588,43 @@ pub mod mcpwm {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim0_set(&mut self) -> _ILIM0_SETW {
_ILIM0_SETW { w: self }
}
- #[doc = "Bit 1 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn imat0_set(&mut self) -> _IMAT0_SETW {
_IMAT0_SETW { w: self }
}
- #[doc = "Bit 2 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn icap0_set(&mut self) -> _ICAP0_SETW {
_ICAP0_SETW { w: self }
}
- #[doc = "Bit 4 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim1_set(&mut self) -> _ILIM1_SETW {
_ILIM1_SETW { w: self }
}
- #[doc = "Bit 5 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn imat1_set(&mut self) -> _IMAT1_SETW {
_IMAT1_SETW { w: self }
}
- #[doc = "Bit 6 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn icap1_set(&mut self) -> _ICAP1_SETW {
_ICAP1_SETW { w: self }
}
- #[doc = "Bit 9 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim2_set(&mut self) -> _ILIM2_SETW {
_ILIM2_SETW { w: self }
}
- #[doc = "Bit 10 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn imat2_set(&mut self) -> _IMAT2_SETW {
_IMAT2_SETW { w: self }
}
- #[doc = "Bit 11 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn icap2_set(&mut self) -> _ICAP2_SETW {
_ICAP2_SETW { w: self }
}
- #[doc = "Bit 15 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." ] # [ inline ( always ) ]
pub fn abort_set(&mut self) -> _ABORT_SETW {
_ABORT_SETW { w: self }
}
@@ -260062,53 +247894,43 @@ pub mod mcpwm {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim0_clr(&mut self) -> _ILIM0_CLRW {
_ILIM0_CLRW { w: self }
}
- #[doc = "Bit 1 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn imat0_clr(&mut self) -> _IMAT0_CLRW {
_IMAT0_CLRW { w: self }
}
- #[doc = "Bit 2 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn icap0_clr(&mut self) -> _ICAP0_CLRW {
_ICAP0_CLRW { w: self }
}
- #[doc = "Bit 4 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim1_clr(&mut self) -> _ILIM1_CLRW {
_ILIM1_CLRW { w: self }
}
- #[doc = "Bit 5 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn imat1_clr(&mut self) -> _IMAT1_CLRW {
_IMAT1_CLRW { w: self }
}
- #[doc = "Bit 6 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn icap1_clr(&mut self) -> _ICAP1_CLRW {
_ICAP1_CLRW { w: self }
}
- #[doc = "Bit 8 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim2_clr(&mut self) -> _ILIM2_CLRW {
_ILIM2_CLRW { w: self }
}
- #[doc = "Bit 9 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn imat2_clr(&mut self) -> _IMAT2_CLRW {
_IMAT2_CLRW { w: self }
}
- #[doc = "Bit 10 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn icap2_clr(&mut self) -> _ICAP2_CLRW {
_ICAP2_CLRW { w: self }
}
- #[doc = "Bit 15 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn abort_clr(&mut self) -> _ABORT_CLRW {
_ABORT_CLRW { w: self }
}
@@ -260135,12 +247957,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ILIM0_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ILIM0_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum ILIM0_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl ILIM0_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260182,12 +247999,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `IMAT0_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum IMAT0_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum IMAT0_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl IMAT0_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260229,12 +248041,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ICAP0_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ICAP0_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum ICAP0_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl ICAP0_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260276,12 +248083,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ILIM1_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ILIM1_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum ILIM1_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl ILIM1_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260323,12 +248125,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `IMAT1_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum IMAT1_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum IMAT1_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl IMAT1_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260370,12 +248167,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ICAP1_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ICAP1_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum ICAP1_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl ICAP1_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260417,12 +248209,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ILIM2_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ILIM2_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum ILIM2_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl ILIM2_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260464,12 +248251,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `IMAT2_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum IMAT2_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum IMAT2_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl IMAT2_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260511,12 +248293,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ICAP2_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ICAP2_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum ICAP2_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl ICAP2_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260558,12 +248335,7 @@ pub mod mcpwm {
}
#[doc = "Possible values of the field `ABORT_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ABORT_FR {
- #[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
- THIS_INTERRUPT_SOURC,
- #[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
- IF_THE_CORRESPONDING,
- }
+ pub enum ABORT_FR {# [ doc = "This interrupt source is not contributing to the MCPWM interrupt request." ] THIS_INTERRUPT_SOURC , # [ doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." ] IF_THE_CORRESPONDING}
impl ABORT_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -260965,53 +248737,43 @@ pub mod mcpwm {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn ilim0_f_set(&mut self) -> _ILIM0_F_SETW {
_ILIM0_F_SETW { w: self }
}
- #[doc = "Bit 1 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn imat0_f_set(&mut self) -> _IMAT0_F_SETW {
_IMAT0_F_SETW { w: self }
}
- #[doc = "Bit 2 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn icap0_f_set(&mut self) -> _ICAP0_F_SETW {
_ICAP0_F_SETW { w: self }
}
- #[doc = "Bit 4 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn ilim1_f_set(&mut self) -> _ILIM1_F_SETW {
_ILIM1_F_SETW { w: self }
}
- #[doc = "Bit 5 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn imat1_f_set(&mut self) -> _IMAT1_F_SETW {
_IMAT1_F_SETW { w: self }
}
- #[doc = "Bit 6 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn icap1_f_set(&mut self) -> _ICAP1_F_SETW {
_ICAP1_F_SETW { w: self }
}
- #[doc = "Bit 8 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn ilim2_f_set(&mut self) -> _ILIM2_F_SETW {
_ILIM2_F_SETW { w: self }
}
- #[doc = "Bit 9 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn imat2_f_set(&mut self) -> _IMAT2_F_SETW {
_IMAT2_F_SETW { w: self }
}
- #[doc = "Bit 10 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn icap2_f_set(&mut self) -> _ICAP2_F_SETW {
_ICAP2_F_SETW { w: self }
}
- #[doc = "Bit 15 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." ] # [ inline ( always ) ]
pub fn abort_f_set(&mut self) -> _ABORT_F_SETW {
_ABORT_F_SETW { w: self }
}
@@ -261281,53 +249043,43 @@ pub mod mcpwm {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." ] # [ inline ( always ) ]
pub fn ilim0_f_clr(&mut self) -> _ILIM0_F_CLRW {
_ILIM0_F_CLRW { w: self }
}
- #[doc = "Bit 1 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn imat0_f_clr(&mut self) -> _IMAT0_F_CLRW {
_IMAT0_F_CLRW { w: self }
}
- #[doc = "Bit 2 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn icap0_f_clr(&mut self) -> _ICAP0_F_CLRW {
_ICAP0_F_CLRW { w: self }
}
- #[doc = "Bit 4 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim1_f_clr(&mut self) -> _ILIM1_F_CLRW {
_ILIM1_F_CLRW { w: self }
}
- #[doc = "Bit 5 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn imat1_f_clr(&mut self) -> _IMAT1_F_CLRW {
_IMAT1_F_CLRW { w: self }
}
- #[doc = "Bit 6 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn icap1_f_clr(&mut self) -> _ICAP1_F_CLRW {
_ICAP1_F_CLRW { w: self }
}
- #[doc = "Bit 8 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn ilim2_f_clr(&mut self) -> _ILIM2_F_CLRW {
_ILIM2_F_CLRW { w: self }
}
- #[doc = "Bit 9 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn imat2_f_clr(&mut self) -> _IMAT2_F_CLRW {
_IMAT2_F_CLRW { w: self }
}
- #[doc = "Bit 10 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn icap2_f_clr(&mut self) -> _ICAP2_F_CLRW {
_ICAP2_F_CLRW { w: self }
}
- #[doc = "Bit 15 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." ] # [ inline ( always ) ]
pub fn abort_f_clr(&mut self) -> _ABORT_F_CLRW {
_ABORT_F_CLRW { w: self }
}
@@ -261356,8 +249108,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI0_RER {
#[doc = "A rising edge on MCI0 does not affect counter 0."] NOEFFECT,
- #[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI0."]
- RISING,
+ #[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI0."] RISING,
}
impl TC0MCI0_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261402,8 +249153,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI0_FER {
#[doc = "A falling edge on MCI0 does not affect counter 0."] NOEFECT,
- #[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI0."]
- FALLING,
+ #[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI0."] FALLING,
}
impl TC0MCI0_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261448,8 +249198,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI1_RER {
#[doc = "A rising edge on MCI1 does not affect counter 0."] NOEFFECT,
- #[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI1."]
- RISING,
+ #[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI1."] RISING,
}
impl TC0MCI1_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261493,10 +249242,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `TC0MCI1_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI1_FER {
- #[doc = "A falling edge on MCI1 does not affect counter 0."]
- NOEFFECT,
- #[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI1."]
- FALLING,
+ #[doc = "A falling edge on MCI1 does not affect counter 0."] NOEFFECT,
+ #[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI1."] FALLING,
}
impl TC0MCI1_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261541,8 +249288,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI2_RER {
#[doc = "A rising edge on MCI0 does not affect counter 0."] NOEFFECT,
- #[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI2."]
- RISING,
+ #[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI2."] RISING,
}
impl TC0MCI2_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261586,10 +249332,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `TC0MCI2_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI2_FER {
- #[doc = "A falling edge on MCI0 does not affect counter 0."]
- NOEFFECT,
- #[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI2."]
- FALLING,
+ #[doc = "A falling edge on MCI0 does not affect counter 0."] NOEFFECT,
+ #[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI2."] FALLING,
}
impl TC0MCI2_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261634,8 +249378,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI0_RER {
#[doc = "A rising edge on MCI0 does not affect counter 1."] NOEFFECT,
- #[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI0."]
- RISING,
+ #[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI0."] RISING,
}
impl TC1MCI0_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261680,8 +249423,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI0_FER {
#[doc = "A falling edge on MCI0 does not affect counter 1."] RISING,
- #[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI0."]
- FALLING,
+ #[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI0."] FALLING,
}
impl TC1MCI0_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261726,8 +249468,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI1_RER {
#[doc = "A rising edge on MCI1 does not affect counter 1."] NOEFFECT,
- #[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI1."]
- RISING,
+ #[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI1."] RISING,
}
impl TC1MCI1_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261771,10 +249512,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `TC1MCI1_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI1_FER {
- #[doc = "A falling edge on MCI0 does not affect counter 1."]
- NOEFFECT,
- #[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI1."]
- FALLING,
+ #[doc = "A falling edge on MCI0 does not affect counter 1."] NOEFFECT,
+ #[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI1."] FALLING,
}
impl TC1MCI1_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261819,8 +249558,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI2_RER {
#[doc = "A rising edge on MCI2 does not affect counter 1."] NOEFFECT,
- #[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI2."]
- RISING,
+ #[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI2."] RISING,
}
impl TC1MCI2_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261864,10 +249602,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `TC1MCI2_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI2_FER {
- #[doc = "A falling edge on MCI2 does not affect counter 1."]
- NOEFFECT,
- #[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI2."]
- RISING,
+ #[doc = "A falling edge on MCI2 does not affect counter 1."] NOEFFECT,
+ #[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI2."] RISING,
}
impl TC1MCI2_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261912,8 +249648,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI0_RER {
#[doc = "A rising edge on MCI0 does not affect counter 2."] NOEFFECT,
- #[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI0."]
- FALLING,
+ #[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI0."] FALLING,
}
impl TC2MCI0_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -261957,10 +249692,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `TC2MCI0_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI0_FER {
- #[doc = "A falling edge on MCI0 does not affect counter 2."]
- NOEFFECT,
- #[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI0."]
- FALLING,
+ #[doc = "A falling edge on MCI0 does not affect counter 2."] NOEFFECT,
+ #[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI0."] FALLING,
}
impl TC2MCI0_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -262005,8 +249738,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI1_RER {
#[doc = "A rising edge on MCI1 does not affect counter 2."] NOEFFECT,
- #[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI1."]
- FALLING,
+ #[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI1."] FALLING,
}
impl TC2MCI1_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -262050,10 +249782,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `TC2MCI1_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI1_FER {
- #[doc = "A falling edge on MCI1 does not affect counter 2."]
- NOEFFECT,
- #[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI1."]
- FALLING,
+ #[doc = "A falling edge on MCI1 does not affect counter 2."] NOEFFECT,
+ #[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI1."] FALLING,
}
impl TC2MCI1_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -262098,8 +249828,7 @@ pub mod mcpwm {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI2_RER {
#[doc = "A rising edge on MCI2 does not affect counter 2."] NOEFFECT,
- #[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI2."]
- FALLING,
+ #[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI2."] FALLING,
}
impl TC2MCI2_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -262143,10 +249872,8 @@ pub mod mcpwm {
#[doc = "Possible values of the field `TC2MCI2_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI2_FER {
- #[doc = "A falling edge on MCI2 does not affect counter 2."]
- NOEFFECT,
- #[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI2."]
- FALLING,
+ #[doc = "A falling edge on MCI2 does not affect counter 2."] NOEFFECT,
+ #[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI2."] FALLING,
}
impl TC2MCI2_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -263905,40 +251632,12 @@ pub mod i2c0 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
- pub conset: CONSET,
- #[doc = "0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
- pub stat: STAT,
- #[doc = "0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
- pub dat: DAT,
- #[doc = "0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
- pub adr0: ADR0,
- #[doc = "0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
- pub sclh: SCLH,
- #[doc = "0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
- pub scll: SCLL,
- #[doc = "0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
- pub conclr: CONCLR,
- #[doc = "0x1c - Monitor mode control register."] pub mmctrl: MMCTRL,
- #[doc = "0x20 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
- pub adr1: ADR,
- #[doc = "0x24 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
- pub adr2: ADR,
- #[doc = "0x28 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
- pub adr3: ADR,
- #[doc = "0x2c - Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
- pub data_buffer: DATA_BUFFER,
- #[doc = "0x30 - I2C Slave address mask register"] pub mask0: MASK,
- #[doc = "0x34 - I2C Slave address mask register"] pub mask1: MASK,
- #[doc = "0x38 - I2C Slave address mask register"] pub mask2: MASK,
- #[doc = "0x3c - I2C Slave address mask register"] pub mask3: MASK,
- }
- #[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
+ pub struct RegisterBlock { # [ doc = "0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." ] pub conset : CONSET , # [ doc = "0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." ] pub stat : STAT , # [ doc = "0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." ] pub dat : DAT , # [ doc = "0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ] pub adr0 : ADR0 , # [ doc = "0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." ] pub sclh : SCLH , # [ doc = "0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." ] pub scll : SCLL , # [ doc = "0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." ] pub conclr : CONCLR , # [ doc = "0x1c - Monitor mode control register." ] pub mmctrl : MMCTRL , # [ doc = "0x20 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ] pub adr1 : ADR , # [ doc = "0x24 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ] pub adr2 : ADR , # [ doc = "0x28 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ] pub adr3 : ADR , # [ doc = "0x2c - Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." ] pub data_buffer : DATA_BUFFER , # [ doc = "0x30 - I2C Slave address mask register" ] pub mask0 : MASK , # [ doc = "0x34 - I2C Slave address mask register" ] pub mask1 : MASK , # [ doc = "0x38 - I2C Slave address mask register" ] pub mask2 : MASK , # [ doc = "0x3c - I2C Slave address mask register" ] pub mask3 : MASK , }
+ # [ doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." ]
pub struct CONSET {
register: VolatileCell<u32>,
}
- #[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
+ # [ doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." ]
pub mod conset {
#[doc = r" Value read from the register"]
pub struct R {
@@ -264300,11 +251999,11 @@ pub mod i2c0 {
}
}
}
- #[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
+ # [ doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." ]
pub struct STAT {
register: VolatileCell<u32>,
}
- #[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
+ # [ doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." ]
pub mod stat {
#[doc = r" Value read from the register"]
pub struct R {
@@ -264336,8 +252035,7 @@ pub mod i2c0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 3:7 - These bits give the actual status information about the I 2C interface."]
- #[inline(always)]
+ # [ doc = "Bits 3:7 - These bits give the actual status information about the I 2C interface." ] # [ inline ( always ) ]
pub fn status(&self) -> STATUSR {
let bits = {
const MASK: u8 = 31;
@@ -264348,11 +252046,11 @@ pub mod i2c0 {
}
}
}
- #[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
+ # [ doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." ]
pub struct DAT {
register: VolatileCell<u32>,
}
- #[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
+ # [ doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." ]
pub mod dat {
#[doc = r" Value read from the register"]
pub struct R {
@@ -264430,8 +252128,7 @@ pub mod i2c0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted." ] # [ inline ( always ) ]
pub fn data(&self) -> DATAR {
let bits = {
const MASK: u8 = 255;
@@ -264453,18 +252150,17 @@ pub mod i2c0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted." ] # [ inline ( always ) ]
pub fn data(&mut self) -> _DATAW {
_DATAW { w: self }
}
}
}
- #[doc = "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
+ # [ doc = "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ]
pub struct ADR0 {
register: VolatileCell<u32>,
}
- #[doc = "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
+ # [ doc = "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ]
pub mod adr0 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -264743,11 +252439,11 @@ pub mod i2c0 {
}
}
}
- #[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
+ # [ doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." ]
pub struct SCLL {
register: VolatileCell<u32>,
}
- #[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
+ # [ doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." ]
pub mod scll {
#[doc = r" Value read from the register"]
pub struct R {
@@ -264855,11 +252551,11 @@ pub mod i2c0 {
}
}
}
- #[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
+ # [ doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." ]
pub struct CONCLR {
register: VolatileCell<u32>,
}
- #[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
+ # [ doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." ]
pub mod conclr {
#[doc = r" Value to write to the register"]
pub struct W {
@@ -265055,11 +252751,7 @@ pub mod i2c0 {
}
#[doc = "Possible values of the field `MM_ENA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MM_ENAR {
- #[doc = "Monitor mode disabled."] MONITOR_MODE_DISABLE,
- #[doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
- THE_I_2C_MODULE_WILL,
- }
+ pub enum MM_ENAR {# [ doc = "Monitor mode disabled." ] MONITOR_MODE_DISABLE , # [ doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." ] THE_I_2C_MODULE_WILL}
impl MM_ENAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -265101,12 +252793,7 @@ pub mod i2c0 {
}
#[doc = "Possible values of the field `ENA_SCL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ENA_SCLR {
- #[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
- WHEN_THIS_BIT_IS_CLE,
- #[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]"]
- WHEN_THIS_BIT_IS_SET,
- }
+ pub enum ENA_SCLR {# [ doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." ] WHEN_THIS_BIT_IS_CLE , # [ doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" ] WHEN_THIS_BIT_IS_SET}
impl ENA_SCLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -265148,12 +252835,7 @@ pub mod i2c0 {
}
#[doc = "Possible values of the field `MATCH_ALL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MATCH_ALLR {
- #[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
- WHEN_THIS_BIT_IS_CLE,
- #[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
- WHEN_THIS_BIT_IS_SET,
- }
+ pub enum MATCH_ALLR {# [ doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." ] WHEN_THIS_BIT_IS_CLE , # [ doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." ] WHEN_THIS_BIT_IS_SET}
impl MATCH_ALLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -265194,11 +252876,7 @@ pub mod i2c0 {
}
}
#[doc = "Values that can be written to the field `MM_ENA`"]
- pub enum MM_ENAW {
- #[doc = "Monitor mode disabled."] MONITOR_MODE_DISABLE,
- #[doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
- THE_I_2C_MODULE_WILL,
- }
+ pub enum MM_ENAW {# [ doc = "Monitor mode disabled." ] MONITOR_MODE_DISABLE , # [ doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." ] THE_I_2C_MODULE_WILL}
impl MM_ENAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -265227,8 +252905,7 @@ pub mod i2c0 {
pub fn monitor_mode_disable(self) -> &'a mut W {
self.variant(MM_ENAW::MONITOR_MODE_DISABLE)
}
- #[doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
- #[inline(always)]
+ # [ doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." ] # [ inline ( always ) ]
pub fn the_i_2c_module_will(self) -> &'a mut W {
self.variant(MM_ENAW::THE_I_2C_MODULE_WILL)
}
@@ -265251,12 +252928,7 @@ pub mod i2c0 {
}
}
#[doc = "Values that can be written to the field `ENA_SCL`"]
- pub enum ENA_SCLW {
- #[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
- WHEN_THIS_BIT_IS_CLE,
- #[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]"]
- WHEN_THIS_BIT_IS_SET,
- }
+ pub enum ENA_SCLW {# [ doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." ] WHEN_THIS_BIT_IS_CLE , # [ doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" ] WHEN_THIS_BIT_IS_SET}
impl ENA_SCLW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -265280,13 +252952,11 @@ pub mod i2c0 {
self.bit(variant._bits())
}
}
- #[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
- #[inline(always)]
+ # [ doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." ] # [ inline ( always ) ]
pub fn when_this_bit_is_cle(self) -> &'a mut W {
self.variant(ENA_SCLW::WHEN_THIS_BIT_IS_CLE)
}
- #[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]"]
- #[inline(always)]
+ # [ doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" ] # [ inline ( always ) ]
pub fn when_this_bit_is_set(self) -> &'a mut W {
self.variant(ENA_SCLW::WHEN_THIS_BIT_IS_SET)
}
@@ -265309,12 +252979,7 @@ pub mod i2c0 {
}
}
#[doc = "Values that can be written to the field `MATCH_ALL`"]
- pub enum MATCH_ALLW {
- #[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
- WHEN_THIS_BIT_IS_CLE,
- #[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
- WHEN_THIS_BIT_IS_SET,
- }
+ pub enum MATCH_ALLW {# [ doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." ] WHEN_THIS_BIT_IS_CLE , # [ doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." ] WHEN_THIS_BIT_IS_SET}
impl MATCH_ALLW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -265338,13 +253003,11 @@ pub mod i2c0 {
self.bit(variant._bits())
}
}
- #[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
- #[inline(always)]
+ # [ doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned." ] # [ inline ( always ) ]
pub fn when_this_bit_is_cle(self) -> &'a mut W {
self.variant(MATCH_ALLW::WHEN_THIS_BIT_IS_CLE)
}
- #[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
- #[inline(always)]
+ # [ doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." ] # [ inline ( always ) ]
pub fn when_this_bit_is_set(self) -> &'a mut W {
self.variant(MATCH_ALLW::WHEN_THIS_BIT_IS_SET)
}
@@ -265429,11 +253092,11 @@ pub mod i2c0 {
}
}
}
- #[doc = "I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
+ # [ doc = "I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ]
pub struct ADR {
register: VolatileCell<u32>,
}
- #[doc = "I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
+ # [ doc = "I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." ]
pub mod adr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -265600,11 +253263,11 @@ pub mod i2c0 {
}
}
}
- #[doc = "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
+ # [ doc = "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." ]
pub struct DATA_BUFFER {
register: VolatileCell<u32>,
}
- #[doc = "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
+ # [ doc = "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." ]
pub mod data_buffer {
#[doc = r" Value read from the register"]
pub struct R {
@@ -265636,8 +253299,7 @@ pub mod i2c0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - This register holds contents of the 8 MSBs of the DAT shift register."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - This register holds contents of the 8 MSBs of the DAT shift register." ] # [ inline ( always ) ]
pub fn data(&self) -> DATAR {
let bits = {
const MASK: u8 = 255;
@@ -265790,34 +253452,7 @@ pub mod i2s0 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel."]
- pub dao: DAO,
- #[doc = "0x04 - I2S Digital Audio Input Register. Contains control bits for the I2S receive channel."]
- pub dai: DAI,
- #[doc = "0x08 - I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO."]
- pub txfifo: TXFIFO,
- #[doc = "0x0c - I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO."]
- pub rxfifo: RXFIFO,
- #[doc = "0x10 - I2S Status Feedback Register. Contains status information about the I2S interface."]
- pub state: STATE,
- #[doc = "0x14 - I2S DMA Configuration Register 1. Contains control information for DMA request 1."]
- pub dma1: DMA1,
- #[doc = "0x18 - I2S DMA Configuration Register 2. Contains control information for DMA request 2."]
- pub dma2: DMA2,
- #[doc = "0x1c - I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated."]
- pub irq: IRQ,
- #[doc = "0x20 - I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
- pub txrate: TXRATE,
- #[doc = "0x24 - I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
- pub rxrate: RXRATE,
- #[doc = "0x28 - I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock."]
- pub txbitrate: TXBITRATE,
- #[doc = "0x2c - I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock."]
- pub rxbitrate: RXBITRATE,
- #[doc = "0x30 - I2S Transmit mode control."] pub txmode: TXMODE,
- #[doc = "0x34 - I2S Receive mode control."] pub rxmode: RXMODE,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." ] pub dao : DAO , # [ doc = "0x04 - I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." ] pub dai : DAI , # [ doc = "0x08 - I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." ] pub txfifo : TXFIFO , # [ doc = "0x0c - I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." ] pub rxfifo : RXFIFO , # [ doc = "0x10 - I2S Status Feedback Register. Contains status information about the I2S interface." ] pub state : STATE , # [ doc = "0x14 - I2S DMA Configuration Register 1. Contains control information for DMA request 1." ] pub dma1 : DMA1 , # [ doc = "0x18 - I2S DMA Configuration Register 2. Contains control information for DMA request 2." ] pub dma2 : DMA2 , # [ doc = "0x1c - I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." ] pub irq : IRQ , # [ doc = "0x20 - I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." ] pub txrate : TXRATE , # [ doc = "0x24 - I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." ] pub rxrate : RXRATE , # [ doc = "0x28 - I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." ] pub txbitrate : TXBITRATE , # [ doc = "0x2c - I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." ] pub rxbitrate : RXBITRATE , # [ doc = "0x30 - I2S Transmit mode control." ] pub txmode : TXMODE , # [ doc = "0x34 - I2S Receive mode control." ] pub rxmode : RXMODE , }
#[doc = "I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel."]
pub struct DAO {
register: VolatileCell<u32>,
@@ -266226,8 +253861,7 @@ pub mod i2s0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
- #[inline(always)]
+ # [ doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format." ] # [ inline ( always ) ]
pub fn mono(&self) -> MONOR {
let bits = {
const MASK: bool = true;
@@ -266236,8 +253870,7 @@ pub mod i2s0 {
};
MONOR { bits }
}
- #[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
- #[inline(always)]
+ # [ doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode." ] # [ inline ( always ) ]
pub fn stop(&self) -> STOPR {
let bits = {
const MASK: bool = true;
@@ -266256,8 +253889,7 @@ pub mod i2s0 {
};
RESETR { bits }
}
- #[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE."]
- #[inline(always)]
+ # [ doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." ] # [ inline ( always ) ]
pub fn ws_sel(&self) -> WS_SELR {
let bits = {
const MASK: bool = true;
@@ -266266,8 +253898,7 @@ pub mod i2s0 {
};
WS_SELR { bits }
}
- #[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
- #[inline(always)]
+ # [ doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." ] # [ inline ( always ) ]
pub fn ws_halfperiod(&self) -> WS_HALFPERIODR {
let bits = {
const MASK: u16 = 511;
@@ -266304,13 +253935,11 @@ pub mod i2s0 {
pub fn wordwidth(&mut self) -> _WORDWIDTHW {
_WORDWIDTHW { w: self }
}
- #[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
- #[inline(always)]
+ # [ doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format." ] # [ inline ( always ) ]
pub fn mono(&mut self) -> _MONOW {
_MONOW { w: self }
}
- #[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
- #[inline(always)]
+ # [ doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode." ] # [ inline ( always ) ]
pub fn stop(&mut self) -> _STOPW {
_STOPW { w: self }
}
@@ -266319,13 +253948,11 @@ pub mod i2s0 {
pub fn reset(&mut self) -> _RESETW {
_RESETW { w: self }
}
- #[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE."]
- #[inline(always)]
+ # [ doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." ] # [ inline ( always ) ]
pub fn ws_sel(&mut self) -> _WS_SELW {
_WS_SELW { w: self }
}
- #[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
- #[inline(always)]
+ # [ doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." ] # [ inline ( always ) ]
pub fn ws_halfperiod(&mut self) -> _WS_HALFPERIODW {
_WS_HALFPERIODW { w: self }
}
@@ -266700,8 +254327,7 @@ pub mod i2s0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
- #[inline(always)]
+ # [ doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format." ] # [ inline ( always ) ]
pub fn mono(&self) -> MONOR {
let bits = {
const MASK: bool = true;
@@ -266710,8 +254336,7 @@ pub mod i2s0 {
};
MONOR { bits }
}
- #[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
- #[inline(always)]
+ # [ doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode." ] # [ inline ( always ) ]
pub fn stop(&self) -> STOPR {
let bits = {
const MASK: bool = true;
@@ -266730,8 +254355,7 @@ pub mod i2s0 {
};
RESETR { bits }
}
- #[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE."]
- #[inline(always)]
+ # [ doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." ] # [ inline ( always ) ]
pub fn ws_sel(&self) -> WS_SELR {
let bits = {
const MASK: bool = true;
@@ -266740,8 +254364,7 @@ pub mod i2s0 {
};
WS_SELR { bits }
}
- #[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
- #[inline(always)]
+ # [ doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." ] # [ inline ( always ) ]
pub fn ws_halfperiod(&self) -> WS_HALFPERIODR {
let bits = {
const MASK: u16 = 511;
@@ -266768,13 +254391,11 @@ pub mod i2s0 {
pub fn wordwidth(&mut self) -> _WORDWIDTHW {
_WORDWIDTHW { w: self }
}
- #[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
- #[inline(always)]
+ # [ doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format." ] # [ inline ( always ) ]
pub fn mono(&mut self) -> _MONOW {
_MONOW { w: self }
}
- #[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
- #[inline(always)]
+ # [ doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode." ] # [ inline ( always ) ]
pub fn stop(&mut self) -> _STOPW {
_STOPW { w: self }
}
@@ -266783,13 +254404,11 @@ pub mod i2s0 {
pub fn reset(&mut self) -> _RESETW {
_RESETW { w: self }
}
- #[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE."]
- #[inline(always)]
+ # [ doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." ] # [ inline ( always ) ]
pub fn ws_sel(&mut self) -> _WS_SELW {
_WS_SELW { w: self }
}
- #[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
- #[inline(always)]
+ # [ doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31." ] # [ inline ( always ) ]
pub fn ws_halfperiod(&mut self) -> _WS_HALFPERIODW {
_WS_HALFPERIODW { w: self }
}
@@ -267009,8 +254628,7 @@ pub mod i2s0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." ] # [ inline ( always ) ]
pub fn irq(&self) -> IRQR {
let bits = {
const MASK: bool = true;
@@ -267019,8 +254637,7 @@ pub mod i2s0 {
};
IRQR { bits }
}
- #[doc = "Bit 1 - This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register."]
- #[inline(always)]
+ # [ doc = "Bit 1 - This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." ] # [ inline ( always ) ]
pub fn dmareq1(&self) -> DMAREQ1R {
let bits = {
const MASK: bool = true;
@@ -267029,8 +254646,7 @@ pub mod i2s0 {
};
DMAREQ1R { bits }
}
- #[doc = "Bit 2 - This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register."]
- #[inline(always)]
+ # [ doc = "Bit 2 - This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." ] # [ inline ( always ) ]
pub fn dmareq2(&self) -> DMAREQ2R {
let bits = {
const MASK: bool = true;
@@ -267603,11 +255219,11 @@ pub mod i2s0 {
}
}
}
- #[doc = "I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated."]
+ # [ doc = "I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." ]
pub struct IRQ {
register: VolatileCell<u32>,
}
- #[doc = "I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated."]
+ # [ doc = "I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." ]
pub mod irq {
#[doc = r" Value read from the register"]
pub struct R {
@@ -267874,11 +255490,11 @@ pub mod i2s0 {
}
}
}
- #[doc = "I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
+ # [ doc = "I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." ]
pub struct TXRATE {
register: VolatileCell<u32>,
}
- #[doc = "I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
+ # [ doc = "I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." ]
pub mod txrate {
#[doc = r" Value read from the register"]
pub struct R {
@@ -267982,8 +255598,7 @@ pub mod i2s0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." ] # [ inline ( always ) ]
pub fn y_divider(&self) -> Y_DIVIDERR {
let bits = {
const MASK: u8 = 255;
@@ -267992,8 +255607,7 @@ pub mod i2s0 {
};
Y_DIVIDERR { bits }
}
- #[doc = "Bits 8:15 - I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." ] # [ inline ( always ) ]
pub fn x_divider(&self) -> X_DIVIDERR {
let bits = {
const MASK: u8 = 255;
@@ -268015,23 +255629,21 @@ pub mod i2s0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." ] # [ inline ( always ) ]
pub fn y_divider(&mut self) -> _Y_DIVIDERW {
_Y_DIVIDERW { w: self }
}
- #[doc = "Bits 8:15 - I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." ] # [ inline ( always ) ]
pub fn x_divider(&mut self) -> _X_DIVIDERW {
_X_DIVIDERW { w: self }
}
}
}
- #[doc = "I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
+ # [ doc = "I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." ]
pub struct RXRATE {
register: VolatileCell<u32>,
}
- #[doc = "I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
+ # [ doc = "I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." ]
pub mod rxrate {
#[doc = r" Value read from the register"]
pub struct R {
@@ -268135,8 +255747,7 @@ pub mod i2s0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." ] # [ inline ( always ) ]
pub fn y_divider(&self) -> Y_DIVIDERR {
let bits = {
const MASK: u8 = 255;
@@ -268145,8 +255756,7 @@ pub mod i2s0 {
};
Y_DIVIDERR { bits }
}
- #[doc = "Bits 8:15 - I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." ] # [ inline ( always ) ]
pub fn x_divider(&self) -> X_DIVIDERR {
let bits = {
const MASK: u8 = 255;
@@ -268168,23 +255778,21 @@ pub mod i2s0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." ] # [ inline ( always ) ]
pub fn y_divider(&mut self) -> _Y_DIVIDERW {
_Y_DIVIDERW { w: self }
}
- #[doc = "Bits 8:15 - I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." ] # [ inline ( always ) ]
pub fn x_divider(&mut self) -> _X_DIVIDERW {
_X_DIVIDERW { w: self }
}
}
}
- #[doc = "I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock."]
+ # [ doc = "I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." ]
pub struct TXBITRATE {
register: VolatileCell<u32>,
}
- #[doc = "I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock."]
+ # [ doc = "I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." ]
pub mod txbitrate {
#[doc = r" Value read from the register"]
pub struct R {
@@ -268262,8 +255870,7 @@ pub mod i2s0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." ] # [ inline ( always ) ]
pub fn tx_bitrate(&self) -> TX_BITRATER {
let bits = {
const MASK: u8 = 63;
@@ -268285,18 +255892,17 @@ pub mod i2s0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." ] # [ inline ( always ) ]
pub fn tx_bitrate(&mut self) -> _TX_BITRATEW {
_TX_BITRATEW { w: self }
}
}
}
- #[doc = "I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock."]
+ # [ doc = "I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." ]
pub struct RXBITRATE {
register: VolatileCell<u32>,
}
- #[doc = "I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock."]
+ # [ doc = "I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." ]
pub mod rxbitrate {
#[doc = r" Value read from the register"]
pub struct R {
@@ -268374,8 +255980,7 @@ pub mod i2s0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." ] # [ inline ( always ) ]
pub fn rx_bitrate(&self) -> RX_BITRATER {
let bits = {
const MASK: u8 = 63;
@@ -268397,8 +256002,7 @@ pub mod i2s0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." ] # [ inline ( always ) ]
pub fn rx_bitrate(&mut self) -> _RX_BITRATEW {
_RX_BITRATEW { w: self }
}
@@ -268459,8 +256063,7 @@ pub mod i2s0 {
pub enum TXCLKSELR {
#[doc = "Select the TX fractional rate divider clock output as the source"]
SELECT_THE_TX_FRACTI,
- #[doc = "Select the RX_MCLK signal as the TX_MCLK clock source"]
- SELECT_THE_RX_MCLK_S,
+ #[doc = "Select the RX_MCLK signal as the TX_MCLK clock source"] SELECT_THE_RX_MCLK_S,
}
impl TXCLKSELR {
#[doc = r" Value of the field as raw bits"]
@@ -268538,8 +256141,7 @@ pub mod i2s0 {
pub enum TXCLKSELW {
#[doc = "Select the TX fractional rate divider clock output as the source"]
SELECT_THE_TX_FRACTI,
- #[doc = "Select the RX_MCLK signal as the TX_MCLK clock source"]
- SELECT_THE_RX_MCLK_S,
+ #[doc = "Select the RX_MCLK signal as the TX_MCLK clock source"] SELECT_THE_RX_MCLK_S,
}
impl TXCLKSELW {
#[allow(missing_docs)]
@@ -268653,8 +256255,7 @@ pub mod i2s0 {
};
TX4PINR { bits }
}
- #[doc = "Bit 3 - Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." ] # [ inline ( always ) ]
pub fn txmcena(&self) -> TXMCENAR {
let bits = {
const MASK: bool = true;
@@ -268686,8 +256287,7 @@ pub mod i2s0 {
pub fn tx4pin(&mut self) -> _TX4PINW {
_TX4PINW { w: self }
}
- #[doc = "Bit 3 - Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." ] # [ inline ( always ) ]
pub fn txmcena(&mut self) -> _TXMCENAW {
_TXMCENAW { w: self }
}
@@ -268748,8 +256348,7 @@ pub mod i2s0 {
pub enum RXCLKSELR {
#[doc = "Select the RX fractional rate divider clock output as the source"]
SELECT_THE_RX_FRACTI,
- #[doc = "Select the TX_MCLK signal as the RX_MCLK clock source"]
- SELECT_THE_TX_MCLK_S,
+ #[doc = "Select the TX_MCLK signal as the RX_MCLK clock source"] SELECT_THE_TX_MCLK_S,
}
impl RXCLKSELR {
#[doc = r" Value of the field as raw bits"]
@@ -268827,8 +256426,7 @@ pub mod i2s0 {
pub enum RXCLKSELW {
#[doc = "Select the RX fractional rate divider clock output as the source"]
SELECT_THE_RX_FRACTI,
- #[doc = "Select the TX_MCLK signal as the RX_MCLK clock source"]
- SELECT_THE_TX_MCLK_S,
+ #[doc = "Select the TX_MCLK signal as the RX_MCLK clock source"] SELECT_THE_TX_MCLK_S,
}
impl RXCLKSELW {
#[allow(missing_docs)]
@@ -268942,8 +256540,7 @@ pub mod i2s0 {
};
RX4PINR { bits }
}
- #[doc = "Bit 3 - Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." ] # [ inline ( always ) ]
pub fn rxmcena(&self) -> RXMCENAR {
let bits = {
const MASK: bool = true;
@@ -268975,8 +256572,7 @@ pub mod i2s0 {
pub fn rx4pin(&mut self) -> _RX4PINW {
_RX4PINW { w: self }
}
- #[doc = "Bit 3 - Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." ] # [ inline ( always ) ]
pub fn rxmcena(&mut self) -> _RXMCENAW {
_RXMCENAW { w: self }
}
@@ -269021,35 +256617,27 @@ pub mod c_can1 {
#[doc = "0x14 - Test register"] pub test: TEST,
#[doc = "0x18 - Baud rate prescaler extension register"] pub brpe: BRPE,
_reserved0: [u8; 4usize],
- #[doc = "0x20 - Message interface command request"]
- pub if1_cmdreq: IF_CMDREQ,
+ #[doc = "0x20 - Message interface command request"] pub if1_cmdreq: IF_CMDREQ,
#[doc = "0x24 - Message interface command mask (write direction)"]
pub if1_cmdmsk_w: IF_CMDMSK_W,
#[doc = "0x28 - Message interface mask 1"] pub if1_msk1: IF_MSK1,
#[doc = "0x2c - Message interface 1 mask 2"] pub if1_msk2: IF_MSK2,
- #[doc = "0x30 - Message interface 1 arbitration 1"]
- pub if1_arb1: IF_ARB1,
- #[doc = "0x34 - Message interface 1 arbitration 2"]
- pub if1_arb2: IF_ARB2,
- #[doc = "0x38 - Message interface 1 message control"]
- pub if1_mctrl: IF_MCTRL,
+ #[doc = "0x30 - Message interface 1 arbitration 1"] pub if1_arb1: IF_ARB1,
+ #[doc = "0x34 - Message interface 1 arbitration 2"] pub if1_arb2: IF_ARB2,
+ #[doc = "0x38 - Message interface 1 message control"] pub if1_mctrl: IF_MCTRL,
#[doc = "0x3c - Message interface data A1"] pub if1_da1: IF_DA1,
#[doc = "0x40 - Message interface 1 data A2"] pub if1_da2: IF_DA2,
#[doc = "0x44 - Message interface 1 data B1"] pub if1_db1: IF_DB1,
#[doc = "0x48 - Message interface 1 data B2"] pub if1_db2: IF_DB2,
_reserved1: [u8; 52usize],
- #[doc = "0x80 - Message interface command request"]
- pub if2_cmdreq: IF_CMDREQ,
+ #[doc = "0x80 - Message interface command request"] pub if2_cmdreq: IF_CMDREQ,
#[doc = "0x84 - Message interface command mask (write direction)"]
pub if2_cmdmsk_w: IF_CMDMSK_W,
#[doc = "0x88 - Message interface mask 1"] pub if2_msk1: IF_MSK1,
#[doc = "0x8c - Message interface 1 mask 2"] pub if2_msk2: IF_MSK2,
- #[doc = "0x90 - Message interface 1 arbitration 1"]
- pub if2_arb1: IF_ARB1,
- #[doc = "0x94 - Message interface 1 arbitration 2"]
- pub if2_arb2: IF_ARB2,
- #[doc = "0x98 - Message interface 1 message control"]
- pub if2_mctrl: IF_MCTRL,
+ #[doc = "0x90 - Message interface 1 arbitration 1"] pub if2_arb1: IF_ARB1,
+ #[doc = "0x94 - Message interface 1 arbitration 2"] pub if2_arb2: IF_ARB2,
+ #[doc = "0x98 - Message interface 1 message control"] pub if2_mctrl: IF_MCTRL,
#[doc = "0x9c - Message interface data A1"] pub if2_da1: IF_DA1,
#[doc = "0xa0 - Message interface 1 data A2"] pub if2_da2: IF_DA2,
#[doc = "0xa4 - Message interface 1 data B1"] pub if2_db1: IF_DB1,
@@ -269121,11 +256709,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `INIT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum INITR {
- #[doc = "Initialization is started. On reset, software needs to initialize the CAN controller."]
- INITIALIZATION_IS_ST,
- #[doc = "Normal operation."] NORMAL_OPERATION_,
- }
+ pub enum INITR {# [ doc = "Initialization is started. On reset, software needs to initialize the CAN controller." ] INITIALIZATION_IS_ST , # [ doc = "Normal operation." ] NORMAL_OPERATION_}
impl INITR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -269167,12 +256751,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `IE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum IER {
- #[doc = "Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared."]
- ENABLE_CAN_INTERRUPT,
- #[doc = "Disable CAN interrupts. The interrupt line is always HIGH."]
- DISABLE_CAN_INTERRUP,
- }
+ pub enum IER {# [ doc = "Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." ] ENABLE_CAN_INTERRUPT , # [ doc = "Disable CAN interrupts. The interrupt line is always HIGH." ] DISABLE_CAN_INTERRUP}
impl IER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -269214,12 +256793,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `SIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SIER {
- #[doc = "Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected."]
- ENABLE_STATUS_CHANGE,
- #[doc = "Disable status change interrupts. No status change interrupt will be generated."]
- DISABLE_STATUS_CHANG,
- }
+ pub enum SIER {# [ doc = "Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." ] ENABLE_STATUS_CHANGE , # [ doc = "Disable status change interrupts. No status change interrupt will be generated." ] DISABLE_STATUS_CHANG}
impl SIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -269261,12 +256835,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `EIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EIER {
- #[doc = "Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt."]
- ENABLE_ERROR_INTERRU,
- #[doc = "Disable error interrupt. No error status interrupt will be generated."]
- DISABLE_ERROR_INTERR,
- }
+ pub enum EIER {# [ doc = "Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." ] ENABLE_ERROR_INTERRU , # [ doc = "Disable error interrupt. No error status interrupt will be generated." ] DISABLE_ERROR_INTERR}
impl EIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -269310,8 +256879,7 @@ pub mod c_can1 {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DARR {
#[doc = "Automatic retransmission disabled."] DISABLED,
- #[doc = "Automatic retransmission of disturbed messages enabled."]
- ENABLED,
+ #[doc = "Automatic retransmission of disturbed messages enabled."] ENABLED,
}
impl DARR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -269357,8 +256925,7 @@ pub mod c_can1 {
pub enum CCER {
#[doc = "The CPU has write access to the CANBT register while the INIT bit is one."]
THE_CPU_HAS_WRITE_AC,
- #[doc = "The CPU has no write access to the bit timing register."]
- THE_CPU_HAS_NO_WRITE,
+ #[doc = "The CPU has no write access to the bit timing register."] THE_CPU_HAS_NO_WRITE,
}
impl CCER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -269445,11 +257012,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `INIT`"]
- pub enum INITW {
- #[doc = "Initialization is started. On reset, software needs to initialize the CAN controller."]
- INITIALIZATION_IS_ST,
- #[doc = "Normal operation."] NORMAL_OPERATION_,
- }
+ pub enum INITW {# [ doc = "Initialization is started. On reset, software needs to initialize the CAN controller." ] INITIALIZATION_IS_ST , # [ doc = "Normal operation." ] NORMAL_OPERATION_}
impl INITW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -269473,8 +257036,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "Initialization is started. On reset, software needs to initialize the CAN controller."]
- #[inline(always)]
+ # [ doc = "Initialization is started. On reset, software needs to initialize the CAN controller." ] # [ inline ( always ) ]
pub fn initialization_is_st(self) -> &'a mut W {
self.variant(INITW::INITIALIZATION_IS_ST)
}
@@ -269502,12 +257064,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `IE`"]
- pub enum IEW {
- #[doc = "Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared."]
- ENABLE_CAN_INTERRUPT,
- #[doc = "Disable CAN interrupts. The interrupt line is always HIGH."]
- DISABLE_CAN_INTERRUP,
- }
+ pub enum IEW {# [ doc = "Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." ] ENABLE_CAN_INTERRUPT , # [ doc = "Disable CAN interrupts. The interrupt line is always HIGH." ] DISABLE_CAN_INTERRUP}
impl IEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -269531,8 +257088,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared."]
- #[inline(always)]
+ # [ doc = "Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." ] # [ inline ( always ) ]
pub fn enable_can_interrupt(self) -> &'a mut W {
self.variant(IEW::ENABLE_CAN_INTERRUPT)
}
@@ -269560,12 +257116,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `SIE`"]
- pub enum SIEW {
- #[doc = "Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected."]
- ENABLE_STATUS_CHANGE,
- #[doc = "Disable status change interrupts. No status change interrupt will be generated."]
- DISABLE_STATUS_CHANG,
- }
+ pub enum SIEW {# [ doc = "Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." ] ENABLE_STATUS_CHANGE , # [ doc = "Disable status change interrupts. No status change interrupt will be generated." ] DISABLE_STATUS_CHANG}
impl SIEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -269589,13 +257140,11 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected."]
- #[inline(always)]
+ # [ doc = "Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." ] # [ inline ( always ) ]
pub fn enable_status_change(self) -> &'a mut W {
self.variant(SIEW::ENABLE_STATUS_CHANGE)
}
- #[doc = "Disable status change interrupts. No status change interrupt will be generated."]
- #[inline(always)]
+ # [ doc = "Disable status change interrupts. No status change interrupt will be generated." ] # [ inline ( always ) ]
pub fn disable_status_chang(self) -> &'a mut W {
self.variant(SIEW::DISABLE_STATUS_CHANG)
}
@@ -269618,12 +257167,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `EIE`"]
- pub enum EIEW {
- #[doc = "Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt."]
- ENABLE_ERROR_INTERRU,
- #[doc = "Disable error interrupt. No error status interrupt will be generated."]
- DISABLE_ERROR_INTERR,
- }
+ pub enum EIEW {# [ doc = "Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." ] ENABLE_ERROR_INTERRU , # [ doc = "Disable error interrupt. No error status interrupt will be generated." ] DISABLE_ERROR_INTERR}
impl EIEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -269647,8 +257191,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt."]
- #[inline(always)]
+ # [ doc = "Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." ] # [ inline ( always ) ]
pub fn enable_error_interru(self) -> &'a mut W {
self.variant(EIEW::ENABLE_ERROR_INTERRU)
}
@@ -269678,8 +257221,7 @@ pub mod c_can1 {
#[doc = "Values that can be written to the field `DAR`"]
pub enum DARW {
#[doc = "Automatic retransmission disabled."] DISABLED,
- #[doc = "Automatic retransmission of disturbed messages enabled."]
- ENABLED,
+ #[doc = "Automatic retransmission of disturbed messages enabled."] ENABLED,
}
impl DARW {
#[allow(missing_docs)]
@@ -269736,8 +257278,7 @@ pub mod c_can1 {
pub enum CCEW {
#[doc = "The CPU has write access to the CANBT register while the INIT bit is one."]
THE_CPU_HAS_WRITE_AC,
- #[doc = "The CPU has no write access to the bit timing register."]
- THE_CPU_HAS_NO_WRITE,
+ #[doc = "The CPU has no write access to the bit timing register."] THE_CPU_HAS_NO_WRITE,
}
impl CCEW {
#[allow(missing_docs)]
@@ -270017,23 +257558,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `LEC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum LECR {
- #[doc = "No error."] NO_ERROR_,
- #[doc = "Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed."]
- STUFF_ERROR_MORE_TH,
- #[doc = "Form error: A fixed format part of a received frame has the wrong format."]
- FORM_ERROR_A_FIXED_,
- #[doc = "AckError: The message this CAN core transmitted was not acknowledged."]
- ACKERROR_THE_MESSAG,
- #[doc = "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant."]
- BIT1ERROR_DURING_TH,
- #[doc = "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)."]
- BIT0ERROR_DURING_TH,
- #[doc = "CRCError: The CRC checksum was incorrect in the message received."]
- CRCERROR_THE_CRC_CH,
- #[doc = "Unused: No CAN bus event was detected (written by the CPU)."]
- UNUSED_NO_CAN_BUS_E,
- }
+ pub enum LECR {# [ doc = "No error." ] NO_ERROR_ , # [ doc = "Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." ] STUFF_ERROR_MORE_TH , # [ doc = "Form error: A fixed format part of a received frame has the wrong format." ] FORM_ERROR_A_FIXED_ , # [ doc = "AckError: The message this CAN core transmitted was not acknowledged." ] ACKERROR_THE_MESSAG , # [ doc = "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." ] BIT1ERROR_DURING_TH , # [ doc = "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." ] BIT0ERROR_DURING_TH , # [ doc = "CRCError: The CRC checksum was incorrect in the message received." ] CRCERROR_THE_CRC_CH , # [ doc = "Unused: No CAN bus event was detected (written by the CPU)." ] UNUSED_NO_CAN_BUS_E}
impl LECR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -270108,12 +257633,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `TXOK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TXOKR {
- #[doc = "Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)."]
- MSGTRANSFER,
- #[doc = "Since this bit was reset by the CPU, no message has been successfully transmitted."]
- NOMSGTRANSFER,
- }
+ pub enum TXOKR {# [ doc = "Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." ] MSGTRANSFER , # [ doc = "Since this bit was reset by the CPU, no message has been successfully transmitted." ] NOMSGTRANSFER}
impl TXOKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -270155,12 +257675,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `RXOK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RXOKR {
- #[doc = "Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering."]
- MSGTRANSFER,
- #[doc = "Since this bit was last reset by the CPU, no message has been successfully transmitted."]
- NOMSGTRANSFER,
- }
+ pub enum RXOKR {# [ doc = "Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." ] MSGTRANSFER , # [ doc = "Since this bit was last reset by the CPU, no message has been successfully transmitted." ] NOMSGTRANSFER}
impl RXOKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -270202,11 +257717,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `EPASS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EPASSR {
- #[doc = "The CAN controller is in the error passive state as defined in the CAN 2.0 specification."]
- PASSIVE,
- #[doc = "The CAN controller is in the error active state."] ACTIVE,
- }
+ pub enum EPASSR {# [ doc = "The CAN controller is in the error passive state as defined in the CAN 2.0 specification." ] PASSIVE , # [ doc = "The CAN controller is in the error active state." ] ACTIVE}
impl EPASSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -270248,12 +257759,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `EWARN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EWARNR {
- #[doc = "At least one of the error counters in the EML has reached the error warning limit of 96."]
- AT_LEAST_ONE_OF_THE_,
- #[doc = "Both error counters are below the error warning limit of 96."]
- BOTH_ERROR_COUNTERS_,
- }
+ pub enum EWARNR {# [ doc = "At least one of the error counters in the EML has reached the error warning limit of 96." ] AT_LEAST_ONE_OF_THE_ , # [ doc = "Both error counters are below the error warning limit of 96." ] BOTH_ERROR_COUNTERS_}
impl EWARNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -270339,23 +257845,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `LEC`"]
- pub enum LECW {
- #[doc = "No error."] NO_ERROR_,
- #[doc = "Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed."]
- STUFF_ERROR_MORE_TH,
- #[doc = "Form error: A fixed format part of a received frame has the wrong format."]
- FORM_ERROR_A_FIXED_,
- #[doc = "AckError: The message this CAN core transmitted was not acknowledged."]
- ACKERROR_THE_MESSAG,
- #[doc = "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant."]
- BIT1ERROR_DURING_TH,
- #[doc = "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)."]
- BIT0ERROR_DURING_TH,
- #[doc = "CRCError: The CRC checksum was incorrect in the message received."]
- CRCERROR_THE_CRC_CH,
- #[doc = "Unused: No CAN bus event was detected (written by the CPU)."]
- UNUSED_NO_CAN_BUS_E,
- }
+ pub enum LECW {# [ doc = "No error." ] NO_ERROR_ , # [ doc = "Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." ] STUFF_ERROR_MORE_TH , # [ doc = "Form error: A fixed format part of a received frame has the wrong format." ] FORM_ERROR_A_FIXED_ , # [ doc = "AckError: The message this CAN core transmitted was not acknowledged." ] ACKERROR_THE_MESSAG , # [ doc = "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." ] BIT1ERROR_DURING_TH , # [ doc = "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." ] BIT0ERROR_DURING_TH , # [ doc = "CRCError: The CRC checksum was incorrect in the message received." ] CRCERROR_THE_CRC_CH , # [ doc = "Unused: No CAN bus event was detected (written by the CPU)." ] UNUSED_NO_CAN_BUS_E}
impl LECW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -270390,8 +257880,7 @@ pub mod c_can1 {
pub fn no_error_(self) -> &'a mut W {
self.variant(LECW::NO_ERROR_)
}
- #[doc = "Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed."]
- #[inline(always)]
+ # [ doc = "Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." ] # [ inline ( always ) ]
pub fn stuff_error_more_th(self) -> &'a mut W {
self.variant(LECW::STUFF_ERROR_MORE_TH)
}
@@ -270405,13 +257894,11 @@ pub mod c_can1 {
pub fn ackerror_the_messag(self) -> &'a mut W {
self.variant(LECW::ACKERROR_THE_MESSAG)
}
- #[doc = "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant."]
- #[inline(always)]
+ # [ doc = "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." ] # [ inline ( always ) ]
pub fn bit1error_during_th(self) -> &'a mut W {
self.variant(LECW::BIT1ERROR_DURING_TH)
}
- #[doc = "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)."]
- #[inline(always)]
+ # [ doc = "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." ] # [ inline ( always ) ]
pub fn bit0error_during_th(self) -> &'a mut W {
self.variant(LECW::BIT0ERROR_DURING_TH)
}
@@ -270436,12 +257923,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `TXOK`"]
- pub enum TXOKW {
- #[doc = "Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)."]
- MSGTRANSFER,
- #[doc = "Since this bit was reset by the CPU, no message has been successfully transmitted."]
- NOMSGTRANSFER,
- }
+ pub enum TXOKW {# [ doc = "Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." ] MSGTRANSFER , # [ doc = "Since this bit was reset by the CPU, no message has been successfully transmitted." ] NOMSGTRANSFER}
impl TXOKW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -270465,13 +257947,11 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)."]
- #[inline(always)]
+ # [ doc = "Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." ] # [ inline ( always ) ]
pub fn msgtransfer(self) -> &'a mut W {
self.variant(TXOKW::MSGTRANSFER)
}
- #[doc = "Since this bit was reset by the CPU, no message has been successfully transmitted."]
- #[inline(always)]
+ # [ doc = "Since this bit was reset by the CPU, no message has been successfully transmitted." ] # [ inline ( always ) ]
pub fn nomsgtransfer(self) -> &'a mut W {
self.variant(TXOKW::NOMSGTRANSFER)
}
@@ -270494,12 +257974,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `RXOK`"]
- pub enum RXOKW {
- #[doc = "Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering."]
- MSGTRANSFER,
- #[doc = "Since this bit was last reset by the CPU, no message has been successfully transmitted."]
- NOMSGTRANSFER,
- }
+ pub enum RXOKW {# [ doc = "Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." ] MSGTRANSFER , # [ doc = "Since this bit was last reset by the CPU, no message has been successfully transmitted." ] NOMSGTRANSFER}
impl RXOKW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -270523,13 +257998,11 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering."]
- #[inline(always)]
+ # [ doc = "Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." ] # [ inline ( always ) ]
pub fn msgtransfer(self) -> &'a mut W {
self.variant(RXOKW::MSGTRANSFER)
}
- #[doc = "Since this bit was last reset by the CPU, no message has been successfully transmitted."]
- #[inline(always)]
+ # [ doc = "Since this bit was last reset by the CPU, no message has been successfully transmitted." ] # [ inline ( always ) ]
pub fn nomsgtransfer(self) -> &'a mut W {
self.variant(RXOKW::NOMSGTRANSFER)
}
@@ -270552,11 +258025,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `EPASS`"]
- pub enum EPASSW {
- #[doc = "The CAN controller is in the error passive state as defined in the CAN 2.0 specification."]
- PASSIVE,
- #[doc = "The CAN controller is in the error active state."] ACTIVE,
- }
+ pub enum EPASSW {# [ doc = "The CAN controller is in the error passive state as defined in the CAN 2.0 specification." ] PASSIVE , # [ doc = "The CAN controller is in the error active state." ] ACTIVE}
impl EPASSW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -270580,8 +258049,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "The CAN controller is in the error passive state as defined in the CAN 2.0 specification."]
- #[inline(always)]
+ # [ doc = "The CAN controller is in the error passive state as defined in the CAN 2.0 specification." ] # [ inline ( always ) ]
pub fn passive(self) -> &'a mut W {
self.variant(EPASSW::PASSIVE)
}
@@ -270609,12 +258077,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `EWARN`"]
- pub enum EWARNW {
- #[doc = "At least one of the error counters in the EML has reached the error warning limit of 96."]
- AT_LEAST_ONE_OF_THE_,
- #[doc = "Both error counters are below the error warning limit of 96."]
- BOTH_ERROR_COUNTERS_,
- }
+ pub enum EWARNW {# [ doc = "At least one of the error counters in the EML has reached the error warning limit of 96." ] AT_LEAST_ONE_OF_THE_ , # [ doc = "Both error counters are below the error warning limit of 96." ] BOTH_ERROR_COUNTERS_}
impl EWARNW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -270638,8 +258101,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "At least one of the error counters in the EML has reached the error warning limit of 96."]
- #[inline(always)]
+ # [ doc = "At least one of the error counters in the EML has reached the error warning limit of 96." ] # [ inline ( always ) ]
pub fn at_least_one_of_the_(self) -> &'a mut W {
self.variant(EWARNW::AT_LEAST_ONE_OF_THE_)
}
@@ -270728,8 +258190,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:2 - Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates."]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates." ] # [ inline ( always ) ]
pub fn lec(&self) -> LECR {
LECR::_from({
const MASK: u8 = 7;
@@ -270737,8 +258198,7 @@ pub mod c_can1 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 3 - Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller." ] # [ inline ( always ) ]
pub fn txok(&self) -> TXOKR {
TXOKR::_from({
const MASK: bool = true;
@@ -270746,8 +258206,7 @@ pub mod c_can1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 4 - Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller." ] # [ inline ( always ) ]
pub fn rxok(&self) -> RXOKR {
RXOKR::_from({
const MASK: bool = true;
@@ -270795,18 +258254,15 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:2 - Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates."]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates." ] # [ inline ( always ) ]
pub fn lec(&mut self) -> _LECW {
_LECW { w: self }
}
- #[doc = "Bit 3 - Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller." ] # [ inline ( always ) ]
pub fn txok(&mut self) -> _TXOKW {
_TXOKW { w: self }
}
- #[doc = "Bit 4 - Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller." ] # [ inline ( always ) ]
pub fn rxok(&mut self) -> _RXOKW {
_RXOKW { w: self }
}
@@ -270870,12 +258326,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `RP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RPR {
- #[doc = "The receive counter has reached the error passive level as defined in the CAN2.0 specification."]
- PASSIVE,
- #[doc = "The receive counter is below the error passive level."]
- BELOWPASSIVE,
- }
+ pub enum RPR {# [ doc = "The receive counter has reached the error passive level as defined in the CAN2.0 specification." ] PASSIVE , # [ doc = "The receive counter is below the error passive level." ] BELOWPASSIVE}
impl RPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -270921,8 +258372,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Transmit error counter Current value of the transmit error counter (maximum value 127)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Transmit error counter Current value of the transmit error counter (maximum value 127)" ] # [ inline ( always ) ]
pub fn tec_7_0(&self) -> TEC_7_0R {
let bits = {
const MASK: u8 = 255;
@@ -270931,8 +258381,7 @@ pub mod c_can1 {
};
TEC_7_0R { bits }
}
- #[doc = "Bits 8:14 - Receive error counter Current value of the receive error counter (maximum value 255)."]
- #[inline(always)]
+ # [ doc = "Bits 8:14 - Receive error counter Current value of the receive error counter (maximum value 255)." ] # [ inline ( always ) ]
pub fn rec_6_0(&self) -> REC_6_0R {
let bits = {
const MASK: u8 = 127;
@@ -271112,8 +258561,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1]. Valid programmed values are 0x01 - 0x3F[1]."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1]. Valid programmed values are 0x01 - 0x3F[1]." ] # [ inline ( always ) ]
pub fn brp(&self) -> BRPR {
let bits = {
const MASK: u8 = 63;
@@ -271122,8 +258570,7 @@ pub mod c_can1 {
};
BRPR { bits }
}
- #[doc = "Bits 6:7 - (Re)synchronization jump width Valid programmed values are 0 to 3[1]."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - (Re)synchronization jump width Valid programmed values are 0 to 3[1]." ] # [ inline ( always ) ]
pub fn sjw(&self) -> SJWR {
let bits = {
const MASK: u8 = 3;
@@ -271165,13 +258612,11 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1]. Valid programmed values are 0x01 - 0x3F[1]."]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1]. Valid programmed values are 0x01 - 0x3F[1]." ] # [ inline ( always ) ]
pub fn brp(&mut self) -> _BRPW {
_BRPW { w: self }
}
- #[doc = "Bits 6:7 - (Re)synchronization jump width Valid programmed values are 0 to 3[1]."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - (Re)synchronization jump width Valid programmed values are 0 to 3[1]." ] # [ inline ( always ) ]
pub fn sjw(&mut self) -> _SJWW {
_SJWW { w: self }
}
@@ -271223,8 +258668,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - 0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused"]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - 0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" ] # [ inline ( always ) ]
pub fn intid15_0(&self) -> INTID15_0R {
let bits = {
const MASK: u16 = 65535;
@@ -271423,14 +258867,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `TX1_0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TX1_0R {
- #[doc = "Level at the TD pin is controlled by the CAN controller. This is the value at reset."]
- LEVEL_AT_THE_TD_PIN_,
- #[doc = "The sample point can be monitored at the TD pin."]
- THE_SAMPLE_POINT_CAN,
- #[doc = "TD pin is driven LOW/dominant."] TD_PIN_IS_DRIVEN_LOW,
- #[doc = "TD pin is driven HIGH/recessive."] TD_PIN_IS_DRIVEN_HIG,
- }
+ pub enum TX1_0R {# [ doc = "Level at the TD pin is controlled by the CAN controller. This is the value at reset." ] LEVEL_AT_THE_TD_PIN_ , # [ doc = "The sample point can be monitored at the TD pin." ] THE_SAMPLE_POINT_CAN , # [ doc = "TD pin is driven LOW/dominant." ] TD_PIN_IS_DRIVEN_LOW , # [ doc = "TD pin is driven HIGH/recessive." ] TD_PIN_IS_DRIVEN_HIG}
impl TX1_0R {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -271690,14 +259127,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `TX1_0`"]
- pub enum TX1_0W {
- #[doc = "Level at the TD pin is controlled by the CAN controller. This is the value at reset."]
- LEVEL_AT_THE_TD_PIN_,
- #[doc = "The sample point can be monitored at the TD pin."]
- THE_SAMPLE_POINT_CAN,
- #[doc = "TD pin is driven LOW/dominant."] TD_PIN_IS_DRIVEN_LOW,
- #[doc = "TD pin is driven HIGH/recessive."] TD_PIN_IS_DRIVEN_HIG,
- }
+ pub enum TX1_0W {# [ doc = "Level at the TD pin is controlled by the CAN controller. This is the value at reset." ] LEVEL_AT_THE_TD_PIN_ , # [ doc = "The sample point can be monitored at the TD pin." ] THE_SAMPLE_POINT_CAN , # [ doc = "TD pin is driven LOW/dominant." ] TD_PIN_IS_DRIVEN_LOW , # [ doc = "TD pin is driven HIGH/recessive." ] TD_PIN_IS_DRIVEN_HIG}
impl TX1_0W {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -271723,8 +259153,7 @@ pub mod c_can1 {
self.bits(variant._bits())
}
}
- #[doc = "Level at the TD pin is controlled by the CAN controller. This is the value at reset."]
- #[inline(always)]
+ # [ doc = "Level at the TD pin is controlled by the CAN controller. This is the value at reset." ] # [ inline ( always ) ]
pub fn level_at_the_td_pin_(self) -> &'a mut W {
self.variant(TX1_0W::LEVEL_AT_THE_TD_PIN_)
}
@@ -271982,8 +259411,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" ] # [ inline ( always ) ]
pub fn brpe(&self) -> BRPER {
let bits = {
const MASK: u8 = 15;
@@ -272005,8 +259433,7 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" ] # [ inline ( always ) ]
pub fn brpe(&mut self) -> _BRPEW {
_BRPEW { w: self }
}
@@ -272138,8 +259565,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" ] # [ inline ( always ) ]
pub fn messnum(&self) -> MESSNUMR {
let bits = {
const MASK: u8 = 63;
@@ -272148,8 +259574,7 @@ pub mod c_can1 {
};
MESSNUMR { bits }
}
- #[doc = "Bit 15 - BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished."]
- #[inline(always)]
+ # [ doc = "Bit 15 - BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." ] # [ inline ( always ) ]
pub fn busy(&self) -> BUSYR {
let bits = {
const MASK: bool = true;
@@ -272171,13 +259596,11 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" ] # [ inline ( always ) ]
pub fn messnum(&mut self) -> _MESSNUMW {
_MESSNUMW { w: self }
}
- #[doc = "Bit 15 - BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished."]
- #[inline(always)]
+ # [ doc = "Bit 15 - BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." ] # [ inline ( always ) ]
pub fn busy(&mut self) -> _BUSYW {
_BUSYW { w: self }
}
@@ -272236,8 +259659,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `DATA_B`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATA_BR {
- #[doc = "Transfer data bytes 4-7 to message object."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 4-7 to message object."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 4-7 unchanged."] DATA_BYTES_4_7_UNCHA,
}
impl DATA_BR {
@@ -272282,8 +259704,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `DATA_A`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATA_AR {
- #[doc = "Transfer data bytes 0-3 to message object."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 0-3 to message object."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 0-3 unchanged."] DATA_BYTES_0_3_UNCHA,
}
impl DATA_AR {
@@ -272327,12 +259748,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `TXRQST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TXRQSTR {
- #[doc = "Request a transmission. Set the TXRQST bit IF1/2_MCTRL."]
- REQUEST_A_TRANSMISSI,
- #[doc = "No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored."]
- NO_TRANSMISSION_REQU,
- }
+ pub enum TXRQSTR {# [ doc = "Request a transmission. Set the TXRQST bit IF1/2_MCTRL." ] REQUEST_A_TRANSMISSI , # [ doc = "No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." ] NO_TRANSMISSION_REQU}
impl TXRQSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -272396,8 +259812,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `CTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CTRLR {
- #[doc = "Transfer control bits to message object"]
- TRANSFER_CONTROL_BIT,
+ #[doc = "Transfer control bits to message object"] TRANSFER_CONTROL_BIT,
#[doc = "Control bits unchanged."] CONTROL_BITS_UNCHANG,
}
impl CTRLR {
@@ -272554,8 +259969,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `DATA_B`"]
pub enum DATA_BW {
- #[doc = "Transfer data bytes 4-7 to message object."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 4-7 to message object."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 4-7 unchanged."] DATA_BYTES_4_7_UNCHA,
}
impl DATA_BW {
@@ -272611,8 +260025,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `DATA_A`"]
pub enum DATA_AW {
- #[doc = "Transfer data bytes 0-3 to message object."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 0-3 to message object."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 0-3 unchanged."] DATA_BYTES_0_3_UNCHA,
}
impl DATA_AW {
@@ -272667,12 +260080,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `TXRQST`"]
- pub enum TXRQSTW {
- #[doc = "Request a transmission. Set the TXRQST bit IF1/2_MCTRL."]
- REQUEST_A_TRANSMISSI,
- #[doc = "No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored."]
- NO_TRANSMISSION_REQU,
- }
+ pub enum TXRQSTW {# [ doc = "Request a transmission. Set the TXRQST bit IF1/2_MCTRL." ] REQUEST_A_TRANSMISSI , # [ doc = "No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." ] NO_TRANSMISSION_REQU}
impl TXRQSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -272701,8 +260109,7 @@ pub mod c_can1 {
pub fn request_a_transmissi(self) -> &'a mut W {
self.variant(TXRQSTW::REQUEST_A_TRANSMISSI)
}
- #[doc = "No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored."]
- #[inline(always)]
+ # [ doc = "No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." ] # [ inline ( always ) ]
pub fn no_transmission_requ(self) -> &'a mut W {
self.variant(TXRQSTW::NO_TRANSMISSION_REQU)
}
@@ -272749,8 +260156,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `CTRL`"]
pub enum CTRLW {
- #[doc = "Transfer control bits to message object"]
- TRANSFER_CONTROL_BIT,
+ #[doc = "Transfer control bits to message object"] TRANSFER_CONTROL_BIT,
#[doc = "Control bits unchanged."] CONTROL_BITS_UNCHANG,
}
impl CTRLW {
@@ -273011,8 +260417,7 @@ pub mod c_can1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." ] # [ inline ( always ) ]
pub fn wr_rd(&self) -> WR_RDR {
let bits = {
const MASK: bool = true;
@@ -273069,8 +260474,7 @@ pub mod c_can1 {
pub fn mask(&mut self) -> _MASKW {
_MASKW { w: self }
}
- #[doc = "Bit 7 - Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." ] # [ inline ( always ) ]
pub fn wr_rd(&mut self) -> _WR_RDW {
_WR_RDW { w: self }
}
@@ -273129,8 +260533,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `DATA_B`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATA_BR {
- #[doc = "Transfer data bytes 4-7 to IFx message buffer register."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 4-7 to IFx message buffer register."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 4-7 unchanged."] DATA_BYTES_4_7_UNCHA,
}
impl DATA_BR {
@@ -273175,8 +260578,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `DATA_A`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATA_AR {
- #[doc = "Transfer data bytes 0-3 to IFx message buffer."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 0-3 to IFx message buffer."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 0-3 unchanged."] DATA_BYTES_0_3_UNCHA,
}
impl DATA_AR {
@@ -273220,12 +260622,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `NEWDAT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum NEWDATR {
- #[doc = "Clear NEWDAT bit in the message object."]
- CLEAR_NEWDAT_BIT_IN_,
- #[doc = "NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits."]
- NEWDAT_BIT_REMAINS_U,
- }
+ pub enum NEWDATR {# [ doc = "Clear NEWDAT bit in the message object." ] CLEAR_NEWDAT_BIT_IN_ , # [ doc = "NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." ] NEWDAT_BIT_REMAINS_U}
impl NEWDATR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -273268,8 +260665,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `CLRINTPND`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLRINTPNDR {
- #[doc = "Clear INTPND bit in the message object."]
- CLEAR_INTPND_BIT_IN_,
+ #[doc = "Clear INTPND bit in the message object."] CLEAR_INTPND_BIT_IN_,
#[doc = "INTPND bit remains unchanged."] INTPND_BIT_REMAINS_U,
}
impl CLRINTPNDR {
@@ -273314,8 +260710,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `CTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CTRLR {
- #[doc = "Transfer control bits to IFx message buffer."]
- TRANSFER_CONTROL_BIT,
+ #[doc = "Transfer control bits to IFx message buffer."] TRANSFER_CONTROL_BIT,
#[doc = "Control bits unchanged."] CONTROL_BITS_UNCHANG,
}
impl CTRLR {
@@ -273359,11 +260754,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `ARB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum ARBR {
- #[doc = "Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register."]
- TRANSFER_IDENTIFIER,
- #[doc = "Arbitration bits unchanged."] ARBITRATION_BITS_UNC,
- }
+ pub enum ARBR {# [ doc = "Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." ] TRANSFER_IDENTIFIER , # [ doc = "Arbitration bits unchanged." ] ARBITRATION_BITS_UNC}
impl ARBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -273472,8 +260863,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `DATA_B`"]
pub enum DATA_BW {
- #[doc = "Transfer data bytes 4-7 to IFx message buffer register."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 4-7 to IFx message buffer register."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 4-7 unchanged."] DATA_BYTES_4_7_UNCHA,
}
impl DATA_BW {
@@ -273529,8 +260919,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `DATA_A`"]
pub enum DATA_AW {
- #[doc = "Transfer data bytes 0-3 to IFx message buffer."]
- TRANSFER_DATA_BYTES_,
+ #[doc = "Transfer data bytes 0-3 to IFx message buffer."] TRANSFER_DATA_BYTES_,
#[doc = "data bytes 0-3 unchanged."] DATA_BYTES_0_3_UNCHA,
}
impl DATA_AW {
@@ -273585,12 +260974,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `NEWDAT`"]
- pub enum NEWDATW {
- #[doc = "Clear NEWDAT bit in the message object."]
- CLEAR_NEWDAT_BIT_IN_,
- #[doc = "NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits."]
- NEWDAT_BIT_REMAINS_U,
- }
+ pub enum NEWDATW {# [ doc = "Clear NEWDAT bit in the message object." ] CLEAR_NEWDAT_BIT_IN_ , # [ doc = "NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." ] NEWDAT_BIT_REMAINS_U}
impl NEWDATW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -273619,8 +261003,7 @@ pub mod c_can1 {
pub fn clear_newdat_bit_in_(self) -> &'a mut W {
self.variant(NEWDATW::CLEAR_NEWDAT_BIT_IN_)
}
- #[doc = "NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits."]
- #[inline(always)]
+ # [ doc = "NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." ] # [ inline ( always ) ]
pub fn newdat_bit_remains_u(self) -> &'a mut W {
self.variant(NEWDATW::NEWDAT_BIT_REMAINS_U)
}
@@ -273644,8 +261027,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `CLRINTPND`"]
pub enum CLRINTPNDW {
- #[doc = "Clear INTPND bit in the message object."]
- CLEAR_INTPND_BIT_IN_,
+ #[doc = "Clear INTPND bit in the message object."] CLEAR_INTPND_BIT_IN_,
#[doc = "INTPND bit remains unchanged."] INTPND_BIT_REMAINS_U,
}
impl CLRINTPNDW {
@@ -273701,8 +261083,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `CTRL`"]
pub enum CTRLW {
- #[doc = "Transfer control bits to IFx message buffer."]
- TRANSFER_CONTROL_BIT,
+ #[doc = "Transfer control bits to IFx message buffer."] TRANSFER_CONTROL_BIT,
#[doc = "Control bits unchanged."] CONTROL_BITS_UNCHANG,
}
impl CTRLW {
@@ -273757,11 +261138,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `ARB`"]
- pub enum ARBW {
- #[doc = "Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register."]
- TRANSFER_IDENTIFIER,
- #[doc = "Arbitration bits unchanged."] ARBITRATION_BITS_UNC,
- }
+ pub enum ARBW {# [ doc = "Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." ] TRANSFER_IDENTIFIER , # [ doc = "Arbitration bits unchanged." ] ARBITRATION_BITS_UNC}
impl ARBW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -273962,8 +261339,7 @@ pub mod c_can1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 7 - Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." ] # [ inline ( always ) ]
pub fn wr_rd(&self) -> WR_RDR {
let bits = {
const MASK: bool = true;
@@ -274020,8 +261396,7 @@ pub mod c_can1 {
pub fn mask(&mut self) -> _MASKW {
_MASKW { w: self }
}
- #[doc = "Bit 7 - Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." ] # [ inline ( always ) ]
pub fn wr_rd(&mut self) -> _WR_RDW {
_WR_RDW { w: self }
}
@@ -274109,8 +261484,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." ] # [ inline ( always ) ]
pub fn msk15_0(&self) -> MSK15_0R {
let bits = {
const MASK: u16 = 65535;
@@ -274132,8 +261506,7 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." ] # [ inline ( always ) ]
pub fn msk15_0(&mut self) -> _MSK15_0W {
_MSK15_0W { w: self }
}
@@ -274203,8 +261576,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `MDIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MDIRR {
- #[doc = "The message direction bit (DIR) is used for acceptance filtering."]
- USED,
+ #[doc = "The message direction bit (DIR) is used for acceptance filtering."] USED,
#[doc = "The message direction bit (DIR) has no effect on acceptance filtering."]
IGNORED,
}
@@ -274250,8 +261622,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `MXTD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MXTDR {
- #[doc = "The extended identifier bit (IDE) is used for acceptance filtering."]
- USED,
+ #[doc = "The extended identifier bit (IDE) is used for acceptance filtering."] USED,
#[doc = "The extended identifier bit (IDE) has no effect on acceptance filtering."]
IGNORED,
}
@@ -274311,8 +261682,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `MDIR`"]
pub enum MDIRW {
- #[doc = "The message direction bit (DIR) is used for acceptance filtering."]
- USED,
+ #[doc = "The message direction bit (DIR) is used for acceptance filtering."] USED,
#[doc = "The message direction bit (DIR) has no effect on acceptance filtering."]
IGNORED,
}
@@ -274369,8 +261739,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `MXTD`"]
pub enum MXTDW {
- #[doc = "The extended identifier bit (IDE) is used for acceptance filtering."]
- USED,
+ #[doc = "The extended identifier bit (IDE) is used for acceptance filtering."] USED,
#[doc = "The extended identifier bit (IDE) has no effect on acceptance filtering."]
IGNORED,
}
@@ -274431,8 +261800,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:12 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering."]
- #[inline(always)]
+ # [ doc = "Bits 0:12 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." ] # [ inline ( always ) ]
pub fn msk28_16(&self) -> MSK28_16R {
let bits = {
const MASK: u16 = 8191;
@@ -274472,8 +261840,7 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:12 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering."]
- #[inline(always)]
+ # [ doc = "Bits 0:12 - Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." ] # [ inline ( always ) ]
pub fn msk28_16(&mut self) -> _MSK28_16W {
_MSK28_16W { w: self }
}
@@ -274571,8 +261938,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)"]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)" ] # [ inline ( always ) ]
pub fn id15_0(&self) -> ID15_0R {
let bits = {
const MASK: u16 = 65535;
@@ -274594,8 +261960,7 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)"]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)" ] # [ inline ( always ) ]
pub fn id15_0(&mut self) -> _ID15_0W {
_ID15_0W { w: self }
}
@@ -274664,12 +262029,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `DIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DIRR {
- #[doc = "Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)."]
- DIRECTION_EQ_TRANSMIT,
- #[doc = "Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object."]
- DIRECTION_EQ_RECEIVE_,
- }
+ pub enum DIRR {# [ doc = "Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." ] DIRECTION_EQ_TRANSMIT , # [ doc = "Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." ] DIRECTION_EQ_RECEIVE_}
impl DIRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -274758,12 +262118,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `MSGVAL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MSGVALR {
- #[doc = "The message object is configured and should be considered by the message handler."]
- CONFIGURED,
- #[doc = "The message object is ignored by the message handler."]
- IGNORED,
- }
+ pub enum MSGVALR {# [ doc = "The message object is configured and should be considered by the message handler." ] CONFIGURED , # [ doc = "The message object is ignored by the message handler." ] IGNORED}
impl MSGVALR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -274819,12 +262174,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `DIR`"]
- pub enum DIRW {
- #[doc = "Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)."]
- DIRECTION_EQ_TRANSMIT,
- #[doc = "Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object."]
- DIRECTION_EQ_RECEIVE_,
- }
+ pub enum DIRW {# [ doc = "Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." ] DIRECTION_EQ_TRANSMIT , # [ doc = "Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." ] DIRECTION_EQ_RECEIVE_}
impl DIRW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -274848,13 +262198,11 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)."]
- #[inline(always)]
+ # [ doc = "Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." ] # [ inline ( always ) ]
pub fn direction_eq_transmit(self) -> &'a mut W {
self.variant(DIRW::DIRECTION_EQ_TRANSMIT)
}
- #[doc = "Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object."]
- #[inline(always)]
+ # [ doc = "Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." ] # [ inline ( always ) ]
pub fn direction_eq_receive_(self) -> &'a mut W {
self.variant(DIRW::DIRECTION_EQ_RECEIVE_)
}
@@ -274935,12 +262283,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `MSGVAL`"]
- pub enum MSGVALW {
- #[doc = "The message object is configured and should be considered by the message handler."]
- CONFIGURED,
- #[doc = "The message object is ignored by the message handler."]
- IGNORED,
- }
+ pub enum MSGVALW {# [ doc = "The message object is configured and should be considered by the message handler." ] CONFIGURED , # [ doc = "The message object is ignored by the message handler." ] IGNORED}
impl MSGVALW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -274964,8 +262307,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "The message object is configured and should be considered by the message handler."]
- #[inline(always)]
+ # [ doc = "The message object is configured and should be considered by the message handler." ] # [ inline ( always ) ]
pub fn configured(self) -> &'a mut W {
self.variant(MSGVALW::CONFIGURED)
}
@@ -274998,8 +262340,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:12 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)"]
- #[inline(always)]
+ # [ doc = "Bits 0:12 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)" ] # [ inline ( always ) ]
pub fn id28_16(&self) -> ID28_16R {
let bits = {
const MASK: u16 = 8191;
@@ -275026,8 +262367,7 @@ pub mod c_can1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 15 - Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required." ] # [ inline ( always ) ]
pub fn msgval(&self) -> MSGVALR {
MSGVALR::_from({
const MASK: bool = true;
@@ -275048,8 +262388,7 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:12 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)"]
- #[inline(always)]
+ # [ doc = "Bits 0:12 - Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)" ] # [ inline ( always ) ]
pub fn id28_16(&mut self) -> _ID28_16W {
_ID28_16W { w: self }
}
@@ -275063,8 +262402,7 @@ pub mod c_can1 {
pub fn xtd(&mut self) -> _XTDW {
_XTDW { w: self }
}
- #[doc = "Bit 15 - Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required." ] # [ inline ( always ) ]
pub fn msgval(&mut self) -> _MSGVALW {
_MSGVALW { w: self }
}
@@ -275133,12 +262471,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `EOB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum EOBR {
- #[doc = "Single message object or last message object of a FIFO buffer."]
- SINGLE_MESSAGE_OBJEC,
- #[doc = "Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer."]
- MESSAGE_OBJECT_BELON,
- }
+ pub enum EOBR {# [ doc = "Single message object or last message object of a FIFO buffer." ] SINGLE_MESSAGE_OBJEC , # [ doc = "Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." ] MESSAGE_OBJECT_BELON}
impl EOBR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -275227,10 +262560,8 @@ pub mod c_can1 {
#[doc = "Possible values of the field `RMTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RMTENR {
- #[doc = "At the reception of a remote frame, TXRQST is set."]
- TXRQSTSET,
- #[doc = "At the reception of a remote frame, TXRQST is left unchanged."]
- UNCHANGED,
+ #[doc = "At the reception of a remote frame, TXRQST is set."] TXRQSTSET,
+ #[doc = "At the reception of a remote frame, TXRQST is left unchanged."] UNCHANGED,
}
impl RMTENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -275274,8 +262605,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `RXIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXIER {
- #[doc = "INTPND will be set after successful reception of a frame."]
- INTPNDSET,
+ #[doc = "INTPND will be set after successful reception of a frame."] INTPNDSET,
#[doc = "INTPND will be left unchanged after successful reception of a frame."]
UNCHANGED,
}
@@ -275320,12 +262650,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `TXIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum TXIER {
- #[doc = "INTPND will be set after a successful reception of a frame."]
- INTPNDSET,
- #[doc = "The INTPND bit will be left unchanged after a successful reception of a frame."]
- UNCHANGED,
- }
+ pub enum TXIER {# [ doc = "INTPND will be set after a successful reception of a frame." ] INTPNDSET , # [ doc = "The INTPND bit will be left unchanged after a successful reception of a frame." ] UNCHANGED}
impl TXIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -275368,8 +262693,7 @@ pub mod c_can1 {
#[doc = "Possible values of the field `UMASK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UMASKR {
- #[doc = "Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering."]
- USE_MASK,
+ #[doc = "Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering."] USE_MASK,
#[doc = "Mask ignored."] MASK_IGNORED_,
}
impl UMASKR {
@@ -275413,12 +262737,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `INTPND`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum INTPNDR {
- #[doc = "This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority."]
- INTSOURCE,
- #[doc = "This message object is not the source of an interrupt."]
- NOINTSOURCE,
- }
+ pub enum INTPNDR {# [ doc = "This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." ] INTSOURCE , # [ doc = "This message object is not the source of an interrupt." ] NOINTSOURCE}
impl INTPNDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -275460,12 +262779,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `MSGLST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum MSGLSTR {
- #[doc = "The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message."]
- THE_MESSAGE_HANDLER_,
- #[doc = "No message lost since this bit was reset last by the CPU."]
- NO_MESSAGE_LOST_SINC,
- }
+ pub enum MSGLSTR {# [ doc = "The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." ] THE_MESSAGE_HANDLER_ , # [ doc = "No message lost since this bit was reset last by the CPU." ] NO_MESSAGE_LOST_SINC}
impl MSGLSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -275507,12 +262821,7 @@ pub mod c_can1 {
}
#[doc = "Possible values of the field `NEWDAT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum NEWDATR {
- #[doc = "The message handler or the CPU has written new data into the data portion of this message object."]
- THE_MESSAGE_HANDLER_,
- #[doc = "No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU."]
- NO_NEW_DATA_HAS_BEEN,
- }
+ pub enum NEWDATR {# [ doc = "The message handler or the CPU has written new data into the data portion of this message object." ] THE_MESSAGE_HANDLER_ , # [ doc = "No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." ] NO_NEW_DATA_HAS_BEEN}
impl NEWDATR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -275568,12 +262877,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `EOB`"]
- pub enum EOBW {
- #[doc = "Single message object or last message object of a FIFO buffer."]
- SINGLE_MESSAGE_OBJEC,
- #[doc = "Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer."]
- MESSAGE_OBJECT_BELON,
- }
+ pub enum EOBW {# [ doc = "Single message object or last message object of a FIFO buffer." ] SINGLE_MESSAGE_OBJEC , # [ doc = "Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." ] MESSAGE_OBJECT_BELON}
impl EOBW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -275602,8 +262906,7 @@ pub mod c_can1 {
pub fn single_message_objec(self) -> &'a mut W {
self.variant(EOBW::SINGLE_MESSAGE_OBJEC)
}
- #[doc = "Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer."]
- #[inline(always)]
+ # [ doc = "Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." ] # [ inline ( always ) ]
pub fn message_object_belon(self) -> &'a mut W {
self.variant(EOBW::MESSAGE_OBJECT_BELON)
}
@@ -275684,10 +262987,8 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `RMTEN`"]
pub enum RMTENW {
- #[doc = "At the reception of a remote frame, TXRQST is set."]
- TXRQSTSET,
- #[doc = "At the reception of a remote frame, TXRQST is left unchanged."]
- UNCHANGED,
+ #[doc = "At the reception of a remote frame, TXRQST is set."] TXRQSTSET,
+ #[doc = "At the reception of a remote frame, TXRQST is left unchanged."] UNCHANGED,
}
impl RMTENW {
#[allow(missing_docs)]
@@ -275742,8 +263043,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `RXIE`"]
pub enum RXIEW {
- #[doc = "INTPND will be set after successful reception of a frame."]
- INTPNDSET,
+ #[doc = "INTPND will be set after successful reception of a frame."] INTPNDSET,
#[doc = "INTPND will be left unchanged after successful reception of a frame."]
UNCHANGED,
}
@@ -275799,12 +263099,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `TXIE`"]
- pub enum TXIEW {
- #[doc = "INTPND will be set after a successful reception of a frame."]
- INTPNDSET,
- #[doc = "The INTPND bit will be left unchanged after a successful reception of a frame."]
- UNCHANGED,
- }
+ pub enum TXIEW {# [ doc = "INTPND will be set after a successful reception of a frame." ] INTPNDSET , # [ doc = "The INTPND bit will be left unchanged after a successful reception of a frame." ] UNCHANGED}
impl TXIEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -275858,8 +263153,7 @@ pub mod c_can1 {
}
#[doc = "Values that can be written to the field `UMASK`"]
pub enum UMASKW {
- #[doc = "Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering."]
- USE_MASK,
+ #[doc = "Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering."] USE_MASK,
#[doc = "Mask ignored."] MASK_IGNORED_,
}
impl UMASKW {
@@ -275914,12 +263208,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `INTPND`"]
- pub enum INTPNDW {
- #[doc = "This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority."]
- INTSOURCE,
- #[doc = "This message object is not the source of an interrupt."]
- NOINTSOURCE,
- }
+ pub enum INTPNDW {# [ doc = "This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." ] INTSOURCE , # [ doc = "This message object is not the source of an interrupt." ] NOINTSOURCE}
impl INTPNDW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -275943,8 +263232,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority."]
- #[inline(always)]
+ # [ doc = "This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." ] # [ inline ( always ) ]
pub fn intsource(self) -> &'a mut W {
self.variant(INTPNDW::INTSOURCE)
}
@@ -275972,12 +263260,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `MSGLST`"]
- pub enum MSGLSTW {
- #[doc = "The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message."]
- THE_MESSAGE_HANDLER_,
- #[doc = "No message lost since this bit was reset last by the CPU."]
- NO_MESSAGE_LOST_SINC,
- }
+ pub enum MSGLSTW {# [ doc = "The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." ] THE_MESSAGE_HANDLER_ , # [ doc = "No message lost since this bit was reset last by the CPU." ] NO_MESSAGE_LOST_SINC}
impl MSGLSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -276001,8 +263284,7 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message."]
- #[inline(always)]
+ # [ doc = "The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." ] # [ inline ( always ) ]
pub fn the_message_handler_(self) -> &'a mut W {
self.variant(MSGLSTW::THE_MESSAGE_HANDLER_)
}
@@ -276030,12 +263312,7 @@ pub mod c_can1 {
}
}
#[doc = "Values that can be written to the field `NEWDAT`"]
- pub enum NEWDATW {
- #[doc = "The message handler or the CPU has written new data into the data portion of this message object."]
- THE_MESSAGE_HANDLER_,
- #[doc = "No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU."]
- NO_NEW_DATA_HAS_BEEN,
- }
+ pub enum NEWDATW {# [ doc = "The message handler or the CPU has written new data into the data portion of this message object." ] THE_MESSAGE_HANDLER_ , # [ doc = "No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." ] NO_NEW_DATA_HAS_BEEN}
impl NEWDATW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -276059,13 +263336,11 @@ pub mod c_can1 {
self.bit(variant._bits())
}
}
- #[doc = "The message handler or the CPU has written new data into the data portion of this message object."]
- #[inline(always)]
+ # [ doc = "The message handler or the CPU has written new data into the data portion of this message object." ] # [ inline ( always ) ]
pub fn the_message_handler_(self) -> &'a mut W {
self.variant(NEWDATW::THE_MESSAGE_HANDLER_)
}
- #[doc = "No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU."]
- #[inline(always)]
+ # [ doc = "No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." ] # [ inline ( always ) ]
pub fn no_new_data_has_been(self) -> &'a mut W {
self.variant(NEWDATW::NO_NEW_DATA_HAS_BEEN)
}
@@ -276093,8 +263368,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." ] # [ inline ( always ) ]
pub fn dlc3_0(&self) -> DLC3_0R {
let bits = {
const MASK: u8 = 15;
@@ -276148,8 +263422,7 @@ pub mod c_can1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 12 - Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1." ] # [ inline ( always ) ]
pub fn umask(&self) -> UMASKR {
UMASKR::_from({
const MASK: bool = true;
@@ -276166,8 +263439,7 @@ pub mod c_can1 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 14 - Message lost (only valid for message objects in the direction receive)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Message lost (only valid for message objects in the direction receive)." ] # [ inline ( always ) ]
pub fn msglst(&self) -> MSGLSTR {
MSGLSTR::_from({
const MASK: bool = true;
@@ -276197,8 +263469,7 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." ] # [ inline ( always ) ]
pub fn dlc3_0(&mut self) -> _DLC3_0W {
_DLC3_0W { w: self }
}
@@ -276227,8 +263498,7 @@ pub mod c_can1 {
pub fn txie(&mut self) -> _TXIEW {
_TXIEW { w: self }
}
- #[doc = "Bit 12 - Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1." ] # [ inline ( always ) ]
pub fn umask(&mut self) -> _UMASKW {
_UMASKW { w: self }
}
@@ -276237,8 +263507,7 @@ pub mod c_can1 {
pub fn intpnd(&mut self) -> _INTPNDW {
_INTPNDW { w: self }
}
- #[doc = "Bit 14 - Message lost (only valid for message objects in the direction receive)."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Message lost (only valid for message objects in the direction receive)." ] # [ inline ( always ) ]
pub fn msglst(&mut self) -> _MSGLSTW {
_MSGLSTW { w: self }
}
@@ -276897,8 +264166,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." ] # [ inline ( always ) ]
pub fn txrqst16_1(&self) -> TXRQST16_1R {
let bits = {
const MASK: u16 = 65535;
@@ -276945,8 +264213,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." ] # [ inline ( always ) ]
pub fn txrqst32_17(&self) -> TXRQST32_17R {
let bits = {
const MASK: u16 = 65535;
@@ -276993,8 +264260,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." ] # [ inline ( always ) ]
pub fn newdat16_1(&self) -> NEWDAT16_1R {
let bits = {
const MASK: u16 = 65535;
@@ -277041,8 +264307,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." ] # [ inline ( always ) ]
pub fn newdat32_17(&self) -> NEWDAT32_17R {
let bits = {
const MASK: u16 = 65535;
@@ -277089,8 +264354,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." ] # [ inline ( always ) ]
pub fn intpnd16_1(&self) -> INTPND16_1R {
let bits = {
const MASK: u16 = 65535;
@@ -277137,8 +264401,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." ] # [ inline ( always ) ]
pub fn intpnd32_17(&self) -> INTPND32_17R {
let bits = {
const MASK: u16 = 65535;
@@ -277185,8 +264448,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." ] # [ inline ( always ) ]
pub fn msgval16_1(&self) -> MSGVAL16_1R {
let bits = {
const MASK: u16 = 65535;
@@ -277233,8 +264495,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." ] # [ inline ( always ) ]
pub fn msgval32_17(&self) -> MSGVAL32_17R {
let bits = {
const MASK: u16 = 65535;
@@ -277327,8 +264588,7 @@ pub mod c_can1 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:3 - Clock divider value CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3. 0011: CAN_CLK = PCLK divided by 4. 0100: CAN_CLK = PCLK divided by 5. ... 1111: CAN_CLK = PCLK divided by 16."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Clock divider value CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3. 0011: CAN_CLK = PCLK divided by 4. 0100: CAN_CLK = PCLK divided by 5. ... 1111: CAN_CLK = PCLK divided by 16." ] # [ inline ( always ) ]
pub fn clkdivval(&self) -> CLKDIVVALR {
let bits = {
const MASK: u8 = 15;
@@ -277350,8 +264610,7 @@ pub mod c_can1 {
self.bits = bits;
self
}
- #[doc = "Bits 0:3 - Clock divider value CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3. 0011: CAN_CLK = PCLK divided by 4. 0100: CAN_CLK = PCLK divided by 5. ... 1111: CAN_CLK = PCLK divided by 16."]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Clock divider value CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3. 0011: CAN_CLK = PCLK divided by 4. 0100: CAN_CLK = PCLK divided by 5. ... 1111: CAN_CLK = PCLK divided by 16." ] # [ inline ( always ) ]
pub fn clkdivval(&mut self) -> _CLKDIVVALW {
_CLKDIVVALW { w: self }
}
@@ -277375,13 +264634,7 @@ pub mod ritimer {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Compare register"] pub compval: COMPVAL,
- #[doc = "0x04 - Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register."]
- pub mask: MASK,
- #[doc = "0x08 - Control register."] pub ctrl: CTRL,
- #[doc = "0x0c - 32-bit counter"] pub counter: COUNTER,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - Compare register" ] pub compval : COMPVAL , # [ doc = "0x04 - Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." ] pub mask : MASK , # [ doc = "0x08 - Control register." ] pub ctrl : CTRL , # [ doc = "0x0c - 32-bit counter" ] pub counter : COUNTER , }
#[doc = "Compare register"]
pub struct COMPVAL {
register: VolatileCell<u32>,
@@ -277464,8 +264717,7 @@ pub mod ritimer {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Compare register. Holds the compare value which is compared to the counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Compare register. Holds the compare value which is compared to the counter." ] # [ inline ( always ) ]
pub fn ricomp(&self) -> RICOMPR {
let bits = {
const MASK: u32 = 4294967295;
@@ -277487,18 +264739,17 @@ pub mod ritimer {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Compare register. Holds the compare value which is compared to the counter."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Compare register. Holds the compare value which is compared to the counter." ] # [ inline ( always ) ]
pub fn ricomp(&mut self) -> _RICOMPW {
_RICOMPW { w: self }
}
}
}
- #[doc = "Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register."]
+ # [ doc = "Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." ]
pub struct MASK {
register: VolatileCell<u32>,
}
- #[doc = "Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register."]
+ # [ doc = "Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." ]
pub mod mask {
#[doc = r" Value read from the register"]
pub struct R {
@@ -277576,8 +264827,7 @@ pub mod ritimer {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." ] # [ inline ( always ) ]
pub fn rimask(&self) -> RIMASKR {
let bits = {
const MASK: u32 = 4294967295;
@@ -277599,8 +264849,7 @@ pub mod ritimer {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." ] # [ inline ( always ) ]
pub fn rimask(&mut self) -> _RIMASKW {
_RIMASKW { w: self }
}
@@ -277658,12 +264907,7 @@ pub mod ritimer {
}
#[doc = "Possible values of the field `RITINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RITINTR {
- #[doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect."]
- THIS_BIT_IS_SET_TO_1,
- #[doc = "The counter value does not equal the masked compare value."]
- THE_COUNTER_VALUE_DO,
- }
+ pub enum RITINTR {# [ doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." ] THIS_BIT_IS_SET_TO_1 , # [ doc = "The counter value does not equal the masked compare value." ] THE_COUNTER_VALUE_DO}
impl RITINTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -277705,11 +264949,7 @@ pub mod ritimer {
}
#[doc = "Possible values of the field `RITENCLR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum RITENCLRR {
- #[doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag."]
- THE_TIMER_WILL_BE_CL,
- #[doc = "The timer will not be cleared to 0."] THE_TIMER_WILL_NOT_B,
- }
+ pub enum RITENCLRR {# [ doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." ] THE_TIMER_WILL_BE_CL , # [ doc = "The timer will not be cleared to 0." ] THE_TIMER_WILL_NOT_B}
impl RITENCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -277754,8 +264994,7 @@ pub mod ritimer {
pub enum RITENBRR {
#[doc = "The timer is halted when the processor is halted for debugging."]
THE_TIMER_IS_HALTED_,
- #[doc = "Debug has no effect on the timer operation."]
- DEBUG_HAS_NO_EFFECT_,
+ #[doc = "Debug has no effect on the timer operation."] DEBUG_HAS_NO_EFFECT_,
}
impl RITENBRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -277843,12 +265082,7 @@ pub mod ritimer {
}
}
#[doc = "Values that can be written to the field `RITINT`"]
- pub enum RITINTW {
- #[doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect."]
- THIS_BIT_IS_SET_TO_1,
- #[doc = "The counter value does not equal the masked compare value."]
- THE_COUNTER_VALUE_DO,
- }
+ pub enum RITINTW {# [ doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." ] THIS_BIT_IS_SET_TO_1 , # [ doc = "The counter value does not equal the masked compare value." ] THE_COUNTER_VALUE_DO}
impl RITINTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -277872,8 +265106,7 @@ pub mod ritimer {
self.bit(variant._bits())
}
}
- #[doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect."]
- #[inline(always)]
+ # [ doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." ] # [ inline ( always ) ]
pub fn this_bit_is_set_to_1(self) -> &'a mut W {
self.variant(RITINTW::THIS_BIT_IS_SET_TO_1)
}
@@ -277901,11 +265134,7 @@ pub mod ritimer {
}
}
#[doc = "Values that can be written to the field `RITENCLR`"]
- pub enum RITENCLRW {
- #[doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag."]
- THE_TIMER_WILL_BE_CL,
- #[doc = "The timer will not be cleared to 0."] THE_TIMER_WILL_NOT_B,
- }
+ pub enum RITENCLRW {# [ doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." ] THE_TIMER_WILL_BE_CL , # [ doc = "The timer will not be cleared to 0." ] THE_TIMER_WILL_NOT_B}
impl RITENCLRW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -277929,8 +265158,7 @@ pub mod ritimer {
self.bit(variant._bits())
}
}
- #[doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag."]
- #[inline(always)]
+ # [ doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." ] # [ inline ( always ) ]
pub fn the_timer_will_be_cl(self) -> &'a mut W {
self.variant(RITENCLRW::THE_TIMER_WILL_BE_CL)
}
@@ -277961,8 +265189,7 @@ pub mod ritimer {
pub enum RITENBRW {
#[doc = "The timer is halted when the processor is halted for debugging."]
THE_TIMER_IS_HALTED_,
- #[doc = "Debug has no effect on the timer operation."]
- DEBUG_HAS_NO_EFFECT_,
+ #[doc = "Debug has no effect on the timer operation."] DEBUG_HAS_NO_EFFECT_,
}
impl RITENBRW {
#[allow(missing_docs)]
@@ -278231,8 +265458,7 @@ pub mod ritimer {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." ] # [ inline ( always ) ]
pub fn ricounter(&self) -> RICOUNTERR {
let bits = {
const MASK: u32 = 4294967295;
@@ -278254,8 +265480,7 @@ pub mod ritimer {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." ] # [ inline ( always ) ]
pub fn ricounter(&mut self) -> _RICOUNTERW {
_RICOUNTERW { w: self }
}
@@ -278295,12 +265520,9 @@ pub mod qei {
#[doc = "0x30 - Velocity counter register"] pub vel: VEL,
#[doc = "0x34 - Velocity capture register"] pub cap: CAP,
#[doc = "0x38 - Velocity compare register"] pub velcomp: VELCOMP,
- #[doc = "0x3c - Digital filter register on input phase A (QEI_A)"]
- pub filterpha: FILTERPHA,
- #[doc = "0x40 - Digital filter register on input phase B (QEI_B)"]
- pub filterphb: FILTERPHB,
- #[doc = "0x44 - Digital filter register on input index (QEI_IDX)"]
- pub filterinx: FILTERINX,
+ #[doc = "0x3c - Digital filter register on input phase A (QEI_A)"] pub filterpha: FILTERPHA,
+ #[doc = "0x40 - Digital filter register on input phase B (QEI_B)"] pub filterphb: FILTERPHB,
+ #[doc = "0x44 - Digital filter register on input index (QEI_IDX)"] pub filterinx: FILTERINX,
#[doc = "0x48 - Index acceptance window register"] pub window: WINDOW,
#[doc = "0x4c - Index compare register 1"] pub inxcmp1: INXCMP1,
#[doc = "0x50 - Index compare register 2"] pub inxcmp2: INXCMP2,
@@ -278438,23 +265660,19 @@ pub mod qei {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." ] # [ inline ( always ) ]
pub fn resp(&mut self) -> _RESPW {
_RESPW { w: self }
}
- #[doc = "Bit 1 - Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." ] # [ inline ( always ) ]
pub fn respi(&mut self) -> _RESPIW {
_RESPIW { w: self }
}
- #[doc = "Bit 2 - Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." ] # [ inline ( always ) ]
pub fn resv(&mut self) -> _RESVW {
_RESVW { w: self }
}
- #[doc = "Bit 3 - Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." ] # [ inline ( always ) ]
pub fn resi(&mut self) -> _RESIW {
_RESIW { w: self }
}
@@ -278772,8 +265990,7 @@ pub mod qei {
};
DIRINVR { bits }
}
- #[doc = "Bit 1 - Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." ] # [ inline ( always ) ]
pub fn sigmode(&self) -> SIGMODER {
let bits = {
const MASK: bool = true;
@@ -278782,8 +265999,7 @@ pub mod qei {
};
SIGMODER { bits }
}
- #[doc = "Bit 2 - Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." ] # [ inline ( always ) ]
pub fn capmode(&self) -> CAPMODER {
let bits = {
const MASK: bool = true;
@@ -278802,8 +266018,7 @@ pub mod qei {
};
INVINXR { bits }
}
- #[doc = "Bit 4 - Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." ] # [ inline ( always ) ]
pub fn crespi(&self) -> CRESPIR {
let bits = {
const MASK: bool = true;
@@ -278812,8 +266027,7 @@ pub mod qei {
};
CRESPIR { bits }
}
- #[doc = "Bits 16:19 - Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." ] # [ inline ( always ) ]
pub fn inxgate(&self) -> INXGATER {
let bits = {
const MASK: u8 = 15;
@@ -278840,13 +266054,11 @@ pub mod qei {
pub fn dirinv(&mut self) -> _DIRINVW {
_DIRINVW { w: self }
}
- #[doc = "Bit 1 - Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." ] # [ inline ( always ) ]
pub fn sigmode(&mut self) -> _SIGMODEW {
_SIGMODEW { w: self }
}
- #[doc = "Bit 2 - Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." ] # [ inline ( always ) ]
pub fn capmode(&mut self) -> _CAPMODEW {
_CAPMODEW { w: self }
}
@@ -278855,13 +266067,11 @@ pub mod qei {
pub fn invinx(&mut self) -> _INVINXW {
_INVINXW { w: self }
}
- #[doc = "Bit 4 - Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." ] # [ inline ( always ) ]
pub fn crespi(&mut self) -> _CRESPIW {
_CRESPIW { w: self }
}
- #[doc = "Bits 16:19 - Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block."]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." ] # [ inline ( always ) ]
pub fn inxgate(&mut self) -> _INXGATEW {
_INXGATEW { w: self }
}
@@ -278913,8 +266123,7 @@ pub mod qei {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." ] # [ inline ( always ) ]
pub fn dir(&self) -> DIRR {
let bits = {
const MASK: bool = true;
@@ -281053,53 +268262,43 @@ pub mod qei {
pub fn enclk_en(&mut self) -> _ENCLK_ENW {
_ENCLK_ENW { w: self }
}
- #[doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
- #[doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
- #[doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
- #[doc = "Bit 9 - Indicates that the index compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Indicates that the index compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev_int(&mut self) -> _REV_INTW {
_REV_INTW { w: self }
}
- #[doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
- #[doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
- #[doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos2rev_int(&mut self) -> _POS2REV_INTW {
_POS2REV_INTW { w: self }
}
- #[doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
- #[doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
- #[doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." ] # [ inline ( always ) ]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
@@ -281537,53 +268736,43 @@ pub mod qei {
pub fn enclk_en(&mut self) -> _ENCLK_ENW {
_ENCLK_ENW { w: self }
}
- #[doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
- #[doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
- #[doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
- #[doc = "Bit 9 - Indicates that the index compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Indicates that the index compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev_int(&mut self) -> _REV_INTW {
_REV_INTW { w: self }
}
- #[doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
- #[doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
- #[doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos2rev_int(&mut self) -> _POS2REV_INTW {
_POS2REV_INTW { w: self }
}
- #[doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
- #[doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
- #[doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." ] # [ inline ( always ) ]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
@@ -282010,8 +269199,7 @@ pub mod qei {
};
ENCLK_INTR { bits }
}
- #[doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos0_int(&self) -> POS0_INTR {
let bits = {
const MASK: bool = true;
@@ -282020,8 +269208,7 @@ pub mod qei {
};
POS0_INTR { bits }
}
- #[doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos1_int(&self) -> POS1_INTR {
let bits = {
const MASK: bool = true;
@@ -282030,8 +269217,7 @@ pub mod qei {
};
POS1_INTR { bits }
}
- #[doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos2_int(&self) -> POS2_INTR {
let bits = {
const MASK: bool = true;
@@ -282040,8 +269226,7 @@ pub mod qei {
};
POS2_INTR { bits }
}
- #[doc = "Bit 9 - Indicates that the index compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Indicates that the index compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev_int(&self) -> REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282050,8 +269235,7 @@ pub mod qei {
};
REV_INTR { bits }
}
- #[doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos0rev_int(&self) -> POS0REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282060,8 +269244,7 @@ pub mod qei {
};
POS0REV_INTR { bits }
}
- #[doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos1rev_int(&self) -> POS1REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282070,8 +269253,7 @@ pub mod qei {
};
POS1REV_INTR { bits }
}
- #[doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos2rev_int(&self) -> POS2REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282080,8 +269262,7 @@ pub mod qei {
};
POS2REV_INTR { bits }
}
- #[doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev1_int(&self) -> REV1_INTR {
let bits = {
const MASK: bool = true;
@@ -282090,8 +269271,7 @@ pub mod qei {
};
REV1_INTR { bits }
}
- #[doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev2_int(&self) -> REV2_INTR {
let bits = {
const MASK: bool = true;
@@ -282100,8 +269280,7 @@ pub mod qei {
};
REV2_INTR { bits }
}
- #[doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." ] # [ inline ( always ) ]
pub fn maxpos_int(&self) -> MAXPOS_INTR {
let bits = {
const MASK: bool = true;
@@ -282533,8 +269712,7 @@ pub mod qei {
};
ENCLK_INTR { bits }
}
- #[doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos0_int(&self) -> POS0_INTR {
let bits = {
const MASK: bool = true;
@@ -282543,8 +269721,7 @@ pub mod qei {
};
POS0_INTR { bits }
}
- #[doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos1_int(&self) -> POS1_INTR {
let bits = {
const MASK: bool = true;
@@ -282553,8 +269730,7 @@ pub mod qei {
};
POS1_INTR { bits }
}
- #[doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos2_int(&self) -> POS2_INTR {
let bits = {
const MASK: bool = true;
@@ -282563,8 +269739,7 @@ pub mod qei {
};
POS2_INTR { bits }
}
- #[doc = "Bit 9 - Indicates that the index compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Indicates that the index compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev_int(&self) -> REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282573,8 +269748,7 @@ pub mod qei {
};
REV_INTR { bits }
}
- #[doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos0rev_int(&self) -> POS0REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282583,8 +269757,7 @@ pub mod qei {
};
POS0REV_INTR { bits }
}
- #[doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos1rev_int(&self) -> POS1REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282593,8 +269766,7 @@ pub mod qei {
};
POS1REV_INTR { bits }
}
- #[doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos2rev_int(&self) -> POS2REV_INTR {
let bits = {
const MASK: bool = true;
@@ -282603,8 +269775,7 @@ pub mod qei {
};
POS2REV_INTR { bits }
}
- #[doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev1_int(&self) -> REV1_INTR {
let bits = {
const MASK: bool = true;
@@ -282613,8 +269784,7 @@ pub mod qei {
};
REV1_INTR { bits }
}
- #[doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev2_int(&self) -> REV2_INTR {
let bits = {
const MASK: bool = true;
@@ -282623,8 +269793,7 @@ pub mod qei {
};
REV2_INTR { bits }
}
- #[doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." ] # [ inline ( always ) ]
pub fn maxpos_int(&self) -> MAXPOS_INTR {
let bits = {
const MASK: bool = true;
@@ -283044,48 +270213,39 @@ pub mod qei {
pub fn enclk_int(&mut self) -> _ENCLK_INTW {
_ENCLK_INTW { w: self }
}
- #[doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
- #[doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
- #[doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
- #[doc = "Bit 9 - Indicates that the index compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Indicates that the index compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev_int(&mut self) -> _REV_INTW {
_REV_INTW { w: self }
}
- #[doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
- #[doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
- #[doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
- #[doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
- #[doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." ] # [ inline ( always ) ]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
@@ -283523,53 +270683,43 @@ pub mod qei {
pub fn enclk_int(&mut self) -> _ENCLK_INTW {
_ENCLK_INTW { w: self }
}
- #[doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
- #[doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
- #[doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position." ] # [ inline ( always ) ]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
- #[doc = "Bit 9 - Indicates that the index compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Indicates that the index compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev_int(&mut self) -> _REV_INTW {
_REV_INTW { w: self }
}
- #[doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
- #[doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
- #[doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." ] # [ inline ( always ) ]
pub fn pos2rev_int(&mut self) -> _POS2REV_INTW {
_POS2REV_INTW { w: self }
}
- #[doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Indicates that the index 1 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
- #[doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Indicates that the index 2 compare value is equal to the current index count." ] # [ inline ( always ) ]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
- #[doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." ] # [ inline ( always ) ]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
@@ -283593,68 +270743,7 @@ pub mod gima {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)"]
- pub cap0_0_in: CAP0_0_IN,
- #[doc = "0x04 - Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)"]
- pub cap0_1_in: CAP0_1_IN,
- #[doc = "0x08 - Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)"]
- pub cap0_2_in: CAP0_2_IN,
- #[doc = "0x0c - Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)"]
- pub cap0_3_in: CAP0_3_IN,
- #[doc = "0x10 - Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)"]
- pub cap1_0_in: CAP1_0_IN,
- #[doc = "0x14 - Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)"]
- pub cap1_1_in: CAP1_1_IN,
- #[doc = "0x18 - Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)"]
- pub cap1_2_in: CAP1_2_IN,
- #[doc = "0x1c - Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)"]
- pub cap1_3_in: CAP1_3_IN,
- #[doc = "0x20 - Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)"]
- pub cap2_0_in: CAP2_0_IN,
- #[doc = "0x24 - Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)"]
- pub cap2_1_in: CAP2_1_IN,
- #[doc = "0x28 - Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)"]
- pub cap2_2_in: CAP2_2_IN,
- #[doc = "0x2c - Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)"]
- pub cap2_3_in: CAP2_3_IN,
- #[doc = "0x30 - Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)"]
- pub cap3_0_in: CAP3_0_IN,
- #[doc = "0x34 - Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)"]
- pub cap3_1_in: CAP3_1_IN,
- #[doc = "0x38 - Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)"]
- pub cap3_2_in: CAP3_2_IN,
- #[doc = "0x3c - Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)"]
- pub cap3_3_in: CAP3_3_IN,
- #[doc = "0x40 - SCT CTIN_0 capture input multiplexer (GIMA output 16)"]
- pub ctin_0_in: CTIN_0_IN,
- #[doc = "0x44 - SCT CTIN_1 capture input multiplexer (GIMA output 17)"]
- pub ctin_1_in: CTIN_1_IN,
- #[doc = "0x48 - SCT CTIN_2 capture input multiplexer (GIMA output 18)"]
- pub ctin_2_in: CTIN_2_IN,
- #[doc = "0x4c - SCT CTIN_3 capture input multiplexer (GIMA output 19)"]
- pub ctin_3_in: CTIN_3_IN,
- #[doc = "0x50 - SCT CTIN_4 capture input multiplexer (GIMA output 20)"]
- pub ctin_4_in: CTIN_4_IN,
- #[doc = "0x54 - SCT CTIN_5 capture input multiplexer (GIMA output 21)"]
- pub ctin_5_in: CTIN_5_IN,
- #[doc = "0x58 - SCT CTIN_6 capture input multiplexer (GIMA output 22)"]
- pub ctin_6_in: CTIN_6_IN,
- #[doc = "0x5c - SCT CTIN_7 capture input multiplexer (GIMA output 23)"]
- pub ctin_7_in: CTIN_7_IN,
- #[doc = "0x60 - ADCHS trigger input multiplexer (GIMA output 24)"]
- pub adchs_trigger_in: ADCHS_TRIGGER_IN,
- #[doc = "0x64 - Event router input 13 multiplexer (GIMA output 25)"]
- pub eventrouter_13_in: EVENTROUTER_13_IN,
- #[doc = "0x68 - Event router input 14 multiplexer (GIMA output 26)"]
- pub eventrouter_14_in: EVENTROUTER_14_IN,
- #[doc = "0x6c - Event router input 16 multiplexer (GIMA output 27)"]
- pub eventrouter_16_in: EVENTROUTER_16_IN,
- #[doc = "0x70 - ADC start0 input multiplexer (GIMA output 28)"]
- pub adcstart0_in: ADCSTART0_IN,
- #[doc = "0x74 - ADC start1 input multiplexer (GIMA output 29)"]
- pub adcstart1_in: ADCSTART1_IN,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" ] pub cap0_0_in : CAP0_0_IN , # [ doc = "0x04 - Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" ] pub cap0_1_in : CAP0_1_IN , # [ doc = "0x08 - Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" ] pub cap0_2_in : CAP0_2_IN , # [ doc = "0x0c - Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" ] pub cap0_3_in : CAP0_3_IN , # [ doc = "0x10 - Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" ] pub cap1_0_in : CAP1_0_IN , # [ doc = "0x14 - Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" ] pub cap1_1_in : CAP1_1_IN , # [ doc = "0x18 - Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" ] pub cap1_2_in : CAP1_2_IN , # [ doc = "0x1c - Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" ] pub cap1_3_in : CAP1_3_IN , # [ doc = "0x20 - Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" ] pub cap2_0_in : CAP2_0_IN , # [ doc = "0x24 - Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" ] pub cap2_1_in : CAP2_1_IN , # [ doc = "0x28 - Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" ] pub cap2_2_in : CAP2_2_IN , # [ doc = "0x2c - Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" ] pub cap2_3_in : CAP2_3_IN , # [ doc = "0x30 - Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" ] pub cap3_0_in : CAP3_0_IN , # [ doc = "0x34 - Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" ] pub cap3_1_in : CAP3_1_IN , # [ doc = "0x38 - Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" ] pub cap3_2_in : CAP3_2_IN , # [ doc = "0x3c - Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" ] pub cap3_3_in : CAP3_3_IN , # [ doc = "0x40 - SCT CTIN_0 capture input multiplexer (GIMA output 16)" ] pub ctin_0_in : CTIN_0_IN , # [ doc = "0x44 - SCT CTIN_1 capture input multiplexer (GIMA output 17)" ] pub ctin_1_in : CTIN_1_IN , # [ doc = "0x48 - SCT CTIN_2 capture input multiplexer (GIMA output 18)" ] pub ctin_2_in : CTIN_2_IN , # [ doc = "0x4c - SCT CTIN_3 capture input multiplexer (GIMA output 19)" ] pub ctin_3_in : CTIN_3_IN , # [ doc = "0x50 - SCT CTIN_4 capture input multiplexer (GIMA output 20)" ] pub ctin_4_in : CTIN_4_IN , # [ doc = "0x54 - SCT CTIN_5 capture input multiplexer (GIMA output 21)" ] pub ctin_5_in : CTIN_5_IN , # [ doc = "0x58 - SCT CTIN_6 capture input multiplexer (GIMA output 22)" ] pub ctin_6_in : CTIN_6_IN , # [ doc = "0x5c - SCT CTIN_7 capture input multiplexer (GIMA output 23)" ] pub ctin_7_in : CTIN_7_IN , # [ doc = "0x60 - ADCHS trigger input multiplexer (GIMA output 24)" ] pub adchs_trigger_in : ADCHS_TRIGGER_IN , # [ doc = "0x64 - Event router input 13 multiplexer (GIMA output 25)" ] pub eventrouter_13_in : EVENTROUTER_13_IN , # [ doc = "0x68 - Event router input 14 multiplexer (GIMA output 26)" ] pub eventrouter_14_in : EVENTROUTER_14_IN , # [ doc = "0x6c - Event router input 16 multiplexer (GIMA output 27)" ] pub eventrouter_16_in : EVENTROUTER_16_IN , # [ doc = "0x70 - ADC start0 input multiplexer (GIMA output 28)" ] pub adcstart0_in : ADCSTART0_IN , # [ doc = "0x74 - ADC start1 input multiplexer (GIMA output 29)" ] pub adcstart1_in : ADCSTART1_IN , }
#[doc = "Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)"]
pub struct CAP0_0_IN {
register: VolatileCell<u32>,
@@ -303211,12 +290300,7 @@ pub mod dac {
}
#[doc = "Possible values of the field `BIAS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BIASR {
- #[doc = "The settling time of the DAC is 1 micros max, and the maximum current is 700 microA."]
- SHORT,
- #[doc = "The settling time of the DAC is 2.5 micros and the maximum current is 350 microA."]
- LONG,
- }
+ pub enum BIASR {# [ doc = "The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." ] SHORT , # [ doc = "The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." ] LONG}
impl BIASR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -303272,12 +290356,7 @@ pub mod dac {
}
}
#[doc = "Values that can be written to the field `BIAS`"]
- pub enum BIASW {
- #[doc = "The settling time of the DAC is 1 micros max, and the maximum current is 700 microA."]
- SHORT,
- #[doc = "The settling time of the DAC is 2.5 micros and the maximum current is 350 microA."]
- LONG,
- }
+ pub enum BIASW {# [ doc = "The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." ] SHORT , # [ doc = "The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." ] LONG}
impl BIASW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -303301,13 +290380,11 @@ pub mod dac {
self.bit(variant._bits())
}
}
- #[doc = "The settling time of the DAC is 1 micros max, and the maximum current is 700 microA."]
- #[inline(always)]
+ # [ doc = "The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." ] # [ inline ( always ) ]
pub fn short(self) -> &'a mut W {
self.variant(BIASW::SHORT)
}
- #[doc = "The settling time of the DAC is 2.5 micros and the maximum current is 350 microA."]
- #[inline(always)]
+ # [ doc = "The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." ] # [ inline ( always ) ]
pub fn long(self) -> &'a mut W {
self.variant(BIASW::LONG)
}
@@ -303335,8 +290412,7 @@ pub mod dac {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 6:15 - After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA."]
- #[inline(always)]
+ # [ doc = "Bits 6:15 - After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." ] # [ inline ( always ) ]
pub fn value(&self) -> VALUER {
let bits = {
const MASK: u16 = 1023;
@@ -303367,8 +290443,7 @@ pub mod dac {
self.bits = bits;
self
}
- #[doc = "Bits 6:15 - After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA."]
- #[inline(always)]
+ # [ doc = "Bits 6:15 - After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." ] # [ inline ( always ) ]
pub fn value(&mut self) -> _VALUEW {
_VALUEW { w: self }
}
@@ -303432,8 +290507,7 @@ pub mod dac {
#[doc = "Possible values of the field `INT_DMA_REQ`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INT_DMA_REQR {
- #[doc = "This bit is cleared on any write to the DACR register."]
- CLR,
+ #[doc = "This bit is cleared on any write to the DACR register."] CLR,
#[doc = "This bit is set by hardware when the timer times out."] SET,
}
impl INT_DMA_REQR {
@@ -303477,11 +290551,7 @@ pub mod dac {
}
#[doc = "Possible values of the field `DBLBUF_ENA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum DBLBUF_ENAR {
- #[doc = "DACR double-buffering is disabled."] DISABLED,
- #[doc = "When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter."]
- ENABLED,
- }
+ pub enum DBLBUF_ENAR {# [ doc = "DACR double-buffering is disabled." ] DISABLED , # [ doc = "When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." ] ENABLED}
impl DBLBUF_ENAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -303570,8 +290640,7 @@ pub mod dac {
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMA_ENAR {
#[doc = "DMA access is disabled."] DISABLED,
- #[doc = "DMA Burst Request Input 15 is enabled for the DAC (see Table 136)."]
- ENABLED,
+ #[doc = "DMA Burst Request Input 15 is enabled for the DAC (see Table 136)."] ENABLED,
}
impl DMA_ENAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -303614,8 +290683,7 @@ pub mod dac {
}
#[doc = "Values that can be written to the field `INT_DMA_REQ`"]
pub enum INT_DMA_REQW {
- #[doc = "This bit is cleared on any write to the DACR register."]
- CLR,
+ #[doc = "This bit is cleared on any write to the DACR register."] CLR,
#[doc = "This bit is set by hardware when the timer times out."] SET,
}
impl INT_DMA_REQW {
@@ -303670,11 +290738,7 @@ pub mod dac {
}
}
#[doc = "Values that can be written to the field `DBLBUF_ENA`"]
- pub enum DBLBUF_ENAW {
- #[doc = "DACR double-buffering is disabled."] DISABLED,
- #[doc = "When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter."]
- ENABLED,
- }
+ pub enum DBLBUF_ENAW {# [ doc = "DACR double-buffering is disabled." ] DISABLED , # [ doc = "When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." ] ENABLED}
impl DBLBUF_ENAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -303703,8 +290767,7 @@ pub mod dac {
pub fn disabled(self) -> &'a mut W {
self.variant(DBLBUF_ENAW::DISABLED)
}
- #[doc = "When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter."]
- #[inline(always)]
+ # [ doc = "When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." ] # [ inline ( always ) ]
pub fn enabled(self) -> &'a mut W {
self.variant(DBLBUF_ENAW::ENABLED)
}
@@ -303785,8 +290848,7 @@ pub mod dac {
#[doc = "Values that can be written to the field `DMA_ENA`"]
pub enum DMA_ENAW {
#[doc = "DMA access is disabled."] DISABLED,
- #[doc = "DMA Burst Request Input 15 is enabled for the DAC (see Table 136)."]
- ENABLED,
+ #[doc = "DMA Burst Request Input 15 is enabled for the DAC (see Table 136)."] ENABLED,
}
impl DMA_ENAW {
#[allow(missing_docs)]
@@ -304058,38 +291120,12 @@ pub mod adc0 {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur."]
- pub cr: CR,
- #[doc = "0x04 - A/D Global Data Register. Contains the result of the most recent A/D conversion."]
- pub gdr: GDR,
- _reserved0: [u8; 4usize],
- #[doc = "0x0c - A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
- pub inten: INTEN,
- #[doc = "0x10 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr0: DR,
- #[doc = "0x14 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr1: DR,
- #[doc = "0x18 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr2: DR,
- #[doc = "0x1c - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr3: DR,
- #[doc = "0x20 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr4: DR,
- #[doc = "0x24 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr5: DR,
- #[doc = "0x28 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr6: DR,
- #[doc = "0x2c - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
- pub dr7: DR,
- #[doc = "0x30 - A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."]
- pub stat: STAT,
- }
- #[doc = "A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur."]
+ pub struct RegisterBlock { # [ doc = "0x00 - A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." ] pub cr : CR , # [ doc = "0x04 - A/D Global Data Register. Contains the result of the most recent A/D conversion." ] pub gdr : GDR , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x0c - A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." ] pub inten : INTEN , # [ doc = "0x10 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr0 : DR , # [ doc = "0x14 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr1 : DR , # [ doc = "0x18 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr2 : DR , # [ doc = "0x1c - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr3 : DR , # [ doc = "0x20 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr4 : DR , # [ doc = "0x24 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr5 : DR , # [ doc = "0x28 - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr6 : DR , # [ doc = "0x2c - A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ] pub dr7 : DR , # [ doc = "0x30 - A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." ] pub stat : STAT , }
+ # [ doc = "A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." ]
pub struct CR {
register: VolatileCell<u32>,
}
- #[doc = "A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur."]
+ # [ doc = "A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." ]
pub mod cr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -304159,12 +291195,7 @@ pub mod adc0 {
}
#[doc = "Possible values of the field `BURST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BURSTR {
- #[doc = "Conversions are software controlled and require 11 clocks."]
- SOFTWARE,
- #[doc = "The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
- BURST,
- }
+ pub enum BURSTR {# [ doc = "Conversions are software controlled and require 11 clocks." ] SOFTWARE , # [ doc = "The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." ] BURST}
impl BURSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -304335,22 +291366,7 @@ pub mod adc0 {
}
#[doc = "Possible values of the field `START`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum STARTR {
- #[doc = "No start (this value should be used when clearing PDN to 0)."]
- NO_START,
- #[doc = "Start conversion now."] START_CONVERSION_NOW,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)."]
- CTOUT_15,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)."]
- CTOUT_8,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input."]
- ADCTRIG0,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input."]
- ADCTRIG1,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2."]
- MCOA2,
- #[doc = "Reserved."] RESERVED_,
- }
+ pub enum STARTR {# [ doc = "No start (this value should be used when clearing PDN to 0)." ] NO_START , # [ doc = "Start conversion now." ] START_CONVERSION_NOW , # [ doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." ] CTOUT_15 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." ] CTOUT_8 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." ] ADCTRIG0 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." ] ADCTRIG1 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." ] MCOA2 , # [ doc = "Reserved." ] RESERVED_}
impl STARTR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
@@ -304426,10 +291442,8 @@ pub mod adc0 {
#[doc = "Possible values of the field `EDGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EDGER {
- #[doc = "Start conversion on a rising edge on the selected signal."]
- RISING,
- #[doc = "Start conversion on a falling edge on the selected signal."]
- FALLING,
+ #[doc = "Start conversion on a rising edge on the selected signal."] RISING,
+ #[doc = "Start conversion on a falling edge on the selected signal."] FALLING,
}
impl EDGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -304501,12 +291515,7 @@ pub mod adc0 {
}
}
#[doc = "Values that can be written to the field `BURST`"]
- pub enum BURSTW {
- #[doc = "Conversions are software controlled and require 11 clocks."]
- SOFTWARE,
- #[doc = "The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
- BURST,
- }
+ pub enum BURSTW {# [ doc = "Conversions are software controlled and require 11 clocks." ] SOFTWARE , # [ doc = "The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." ] BURST}
impl BURSTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -304535,8 +291544,7 @@ pub mod adc0 {
pub fn software(self) -> &'a mut W {
self.variant(BURSTW::SOFTWARE)
}
- #[doc = "The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
- #[inline(always)]
+ # [ doc = "The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." ] # [ inline ( always ) ]
pub fn burst(self) -> &'a mut W {
self.variant(BURSTW::BURST)
}
@@ -304705,22 +291713,7 @@ pub mod adc0 {
}
}
#[doc = "Values that can be written to the field `START`"]
- pub enum STARTW {
- #[doc = "No start (this value should be used when clearing PDN to 0)."]
- NO_START,
- #[doc = "Start conversion now."] START_CONVERSION_NOW,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)."]
- CTOUT_15,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)."]
- CTOUT_8,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input."]
- ADCTRIG0,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input."]
- ADCTRIG1,
- #[doc = "Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2."]
- MCOA2,
- #[doc = "Reserved."] RESERVED_,
- }
+ pub enum STARTW {# [ doc = "No start (this value should be used when clearing PDN to 0)." ] NO_START , # [ doc = "Start conversion now." ] START_CONVERSION_NOW , # [ doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." ] CTOUT_15 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." ] CTOUT_8 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." ] ADCTRIG0 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." ] ADCTRIG1 , # [ doc = "Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." ] MCOA2 , # [ doc = "Reserved." ] RESERVED_}
impl STARTW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -304760,13 +291753,11 @@ pub mod adc0 {
pub fn start_conversion_now(self) -> &'a mut W {
self.variant(STARTW::START_CONVERSION_NOW)
}
- #[doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)."]
- #[inline(always)]
+ # [ doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." ] # [ inline ( always ) ]
pub fn ctout_15(self) -> &'a mut W {
self.variant(STARTW::CTOUT_15)
}
- #[doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)."]
- #[inline(always)]
+ # [ doc = "Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." ] # [ inline ( always ) ]
pub fn ctout_8(self) -> &'a mut W {
self.variant(STARTW::CTOUT_8)
}
@@ -304780,8 +291771,7 @@ pub mod adc0 {
pub fn adctrig1(self) -> &'a mut W {
self.variant(STARTW::ADCTRIG1)
}
- #[doc = "Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2."]
- #[inline(always)]
+ # [ doc = "Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." ] # [ inline ( always ) ]
pub fn mcoa2(self) -> &'a mut W {
self.variant(STARTW::MCOA2)
}
@@ -304802,10 +291792,8 @@ pub mod adc0 {
}
#[doc = "Values that can be written to the field `EDGE`"]
pub enum EDGEW {
- #[doc = "Start conversion on a rising edge on the selected signal."]
- RISING,
- #[doc = "Start conversion on a falling edge on the selected signal."]
- FALLING,
+ #[doc = "Start conversion on a rising edge on the selected signal."] RISING,
+ #[doc = "Start conversion on a falling edge on the selected signal."] FALLING,
}
impl EDGEW {
#[allow(missing_docs)]
@@ -304864,8 +291852,7 @@ pub mod adc0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." ] # [ inline ( always ) ]
pub fn sel(&self) -> SELR {
let bits = {
const MASK: u8 = 255;
@@ -304874,8 +291861,7 @@ pub mod adc0 {
};
SELR { bits }
}
- #[doc = "Bits 8:15 - The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." ] # [ inline ( always ) ]
pub fn clkdiv(&self) -> CLKDIVR {
let bits = {
const MASK: u8 = 255;
@@ -304893,8 +291879,7 @@ pub mod adc0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
- #[inline(always)]
+ # [ doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)." ] # [ inline ( always ) ]
pub fn clks(&self) -> CLKSR {
CLKSR::_from({
const MASK: u8 = 7;
@@ -304911,8 +291896,7 @@ pub mod adc0 {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):"]
- #[inline(always)]
+ # [ doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):" ] # [ inline ( always ) ]
pub fn start(&self) -> STARTR {
STARTR::_from({
const MASK: u8 = 7;
@@ -304920,8 +291904,7 @@ pub mod adc0 {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bit 27 - This bit is significant only when the START field contains 0x2 -0x6. In these cases:"]
- #[inline(always)]
+ # [ doc = "Bit 27 - This bit is significant only when the START field contains 0x2 -0x6. In these cases:" ] # [ inline ( always ) ]
pub fn edge(&self) -> EDGER {
EDGER::_from({
const MASK: bool = true;
@@ -304942,13 +291925,11 @@ pub mod adc0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." ] # [ inline ( always ) ]
pub fn sel(&mut self) -> _SELW {
_SELW { w: self }
}
- #[doc = "Bits 8:15 - The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." ] # [ inline ( always ) ]
pub fn clkdiv(&mut self) -> _CLKDIVW {
_CLKDIVW { w: self }
}
@@ -304957,8 +291938,7 @@ pub mod adc0 {
pub fn burst(&mut self) -> _BURSTW {
_BURSTW { w: self }
}
- #[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
- #[inline(always)]
+ # [ doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)." ] # [ inline ( always ) ]
pub fn clks(&mut self) -> _CLKSW {
_CLKSW { w: self }
}
@@ -304967,13 +291947,11 @@ pub mod adc0 {
pub fn pdn(&mut self) -> _PDNW {
_PDNW { w: self }
}
- #[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):"]
- #[inline(always)]
+ # [ doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):" ] # [ inline ( always ) ]
pub fn start(&mut self) -> _STARTW {
_STARTW { w: self }
}
- #[doc = "Bit 27 - This bit is significant only when the START field contains 0x2 -0x6. In these cases:"]
- #[inline(always)]
+ # [ doc = "Bit 27 - This bit is significant only when the START field contains 0x2 -0x6. In these cases:" ] # [ inline ( always ) ]
pub fn edge(&mut self) -> _EDGEW {
_EDGEW { w: self }
}
@@ -305068,8 +292046,7 @@ pub mod adc0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA."]
- #[inline(always)]
+ # [ doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." ] # [ inline ( always ) ]
pub fn v_vref(&self) -> V_VREFR {
let bits = {
const MASK: u16 = 1023;
@@ -305078,8 +292055,7 @@ pub mod adc0 {
};
V_VREFR { bits }
}
- #[doc = "Bits 24:26 - These bits contain the channel from which the LS bits were converted."]
- #[inline(always)]
+ # [ doc = "Bits 24:26 - These bits contain the channel from which the LS bits were converted." ] # [ inline ( always ) ]
pub fn chn(&self) -> CHNR {
let bits = {
const MASK: u8 = 7;
@@ -305088,8 +292064,7 @@ pub mod adc0 {
};
CHNR { bits }
}
- #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
- #[inline(always)]
+ # [ doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." ] # [ inline ( always ) ]
pub fn overrun(&self) -> OVERRUNR {
let bits = {
const MASK: bool = true;
@@ -305098,8 +292073,7 @@ pub mod adc0 {
};
OVERRUNR { bits }
}
- #[doc = "Bit 31 - This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
- #[inline(always)]
+ # [ doc = "Bit 31 - This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." ] # [ inline ( always ) ]
pub fn done(&self) -> DONER {
let bits = {
const MASK: bool = true;
@@ -305110,11 +292084,11 @@ pub mod adc0 {
}
}
}
- #[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
+ # [ doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." ]
pub struct INTEN {
register: VolatileCell<u32>,
}
- #[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
+ # [ doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." ]
pub mod inten {
#[doc = r" Value read from the register"]
pub struct R {
@@ -305236,8 +292210,7 @@ pub mod adc0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." ] # [ inline ( always ) ]
pub fn adinten(&self) -> ADINTENR {
let bits = {
const MASK: u8 = 255;
@@ -305246,8 +292219,7 @@ pub mod adc0 {
};
ADINTENR { bits }
}
- #[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
- #[inline(always)]
+ # [ doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." ] # [ inline ( always ) ]
pub fn adginten(&self) -> ADGINTENR {
let bits = {
const MASK: bool = true;
@@ -305269,23 +292241,21 @@ pub mod adc0 {
self.bits = bits;
self
}
- #[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." ] # [ inline ( always ) ]
pub fn adinten(&mut self) -> _ADINTENW {
_ADINTENW { w: self }
}
- #[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
- #[inline(always)]
+ # [ doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." ] # [ inline ( always ) ]
pub fn adginten(&mut self) -> _ADGINTENW {
_ADGINTENW { w: self }
}
}
}
- #[doc = "A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
+ # [ doc = "A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ]
pub struct DR {
register: VolatileCell<u32>,
}
- #[doc = "A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n."]
+ # [ doc = "A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." ]
pub mod dr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -305359,8 +292329,7 @@ pub mod adc0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA."]
- #[inline(always)]
+ # [ doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." ] # [ inline ( always ) ]
pub fn v_vref(&self) -> V_VREFR {
let bits = {
const MASK: u16 = 1023;
@@ -305369,8 +292338,7 @@ pub mod adc0 {
};
V_VREFR { bits }
}
- #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register."]
- #[inline(always)]
+ # [ doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." ] # [ inline ( always ) ]
pub fn overrun(&self) -> OVERRUNR {
let bits = {
const MASK: bool = true;
@@ -305379,8 +292347,7 @@ pub mod adc0 {
};
OVERRUNR { bits }
}
- #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
- #[inline(always)]
+ # [ doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." ] # [ inline ( always ) ]
pub fn done(&self) -> DONER {
let bits = {
const MASK: bool = true;
@@ -305391,11 +292358,11 @@ pub mod adc0 {
}
}
}
- #[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."]
+ # [ doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." ]
pub struct STAT {
register: VolatileCell<u32>,
}
- #[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."]
+ # [ doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." ]
pub mod stat {
#[doc = r" Value read from the register"]
pub struct R {
@@ -305459,8 +292426,7 @@ pub mod adc0 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:7 - These bits mirror the DONE status flags that appear in the result register for each A/D channel."]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - These bits mirror the DONE status flags that appear in the result register for each A/D channel." ] # [ inline ( always ) ]
pub fn done(&self) -> DONER {
let bits = {
const MASK: u8 = 255;
@@ -305469,8 +292435,7 @@ pub mod adc0 {
};
DONER { bits }
}
- #[doc = "Bits 8:15 - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." ] # [ inline ( always ) ]
pub fn overun(&self) -> OVERUNR {
let bits = {
const MASK: u8 = 255;
@@ -305479,8 +292444,7 @@ pub mod adc0 {
};
OVERUNR { bits }
}
- #[doc = "Bit 16 - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."]
- #[inline(always)]
+ # [ doc = "Bit 16 - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." ] # [ inline ( always ) ]
pub fn adint(&self) -> ADINTR {
let bits = {
const MASK: bool = true;
@@ -305521,124 +292485,7 @@ pub mod adchs {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - Flushes FIFO"] pub flush: FLUSH,
- #[doc = "0x04 - Set or clear DMA write request"] pub dma_req: DMA_REQ,
- #[doc = "0x08 - Indicates FIFO fill level status"]
- pub fifo_sts: FIFO_STS,
- #[doc = "0x0c - Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word."]
- pub fifo_cfg: FIFO_CFG,
- #[doc = "0x10 - Enable software trigger to start descriptor processing"]
- pub trigger: TRIGGER,
- #[doc = "0x14 - Indicates active descriptor table and descriptor entry"]
- pub dscr_sts: DSCR_STS,
- #[doc = "0x18 - Set or clear power down mode"]
- pub power_down: POWER_DOWN,
- #[doc = "0x1c - Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down."]
- pub config: CONFIG,
- #[doc = "0x20 - Configures window comparator A levels."]
- pub thr_a: THR_A,
- #[doc = "0x24 - Configures window comparator B levels."]
- pub thr_b: THR_B,
- #[doc = "0x28 - Contains last converted sample of input M [M=0..5) and result of window comparator."]
- pub last_sample0: LAST_SAMPLE,
- #[doc = "0x2c - Contains last converted sample of input M [M=0..5) and result of window comparator."]
- pub last_sample1: LAST_SAMPLE,
- #[doc = "0x30 - Contains last converted sample of input M [M=0..5) and result of window comparator."]
- pub last_sample2: LAST_SAMPLE,
- #[doc = "0x34 - Contains last converted sample of input M [M=0..5) and result of window comparator."]
- pub last_sample3: LAST_SAMPLE,
- #[doc = "0x38 - Contains last converted sample of input M [M=0..5) and result of window comparator."]
- pub last_sample4: LAST_SAMPLE,
- #[doc = "0x3c - Contains last converted sample of input M [M=0..5) and result of window comparator."]
- pub last_sample5: LAST_SAMPLE,
- _reserved0: [u8; 196usize],
- #[doc = "0x104 - ADC speed control"] pub adc_speed: ADC_SPEED,
- #[doc = "0x108 - Configures ADC power vs. speed, DC-in biasing, output format and power gating."]
- pub power_control: POWER_CONTROL,
- _reserved1: [u8; 244usize],
- #[doc = "0x200 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output0: FIFO_OUTPUT,
- #[doc = "0x204 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output1: FIFO_OUTPUT,
- #[doc = "0x208 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output2: FIFO_OUTPUT,
- #[doc = "0x20c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output3: FIFO_OUTPUT,
- #[doc = "0x210 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output4: FIFO_OUTPUT,
- #[doc = "0x214 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output5: FIFO_OUTPUT,
- #[doc = "0x218 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output6: FIFO_OUTPUT,
- #[doc = "0x21c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output7: FIFO_OUTPUT,
- #[doc = "0x220 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output8: FIFO_OUTPUT,
- #[doc = "0x224 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output9: FIFO_OUTPUT,
- #[doc = "0x228 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output10: FIFO_OUTPUT,
- #[doc = "0x22c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output11: FIFO_OUTPUT,
- #[doc = "0x230 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output12: FIFO_OUTPUT,
- #[doc = "0x234 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output13: FIFO_OUTPUT,
- #[doc = "0x238 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output14: FIFO_OUTPUT,
- #[doc = "0x23c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
- pub fifo_output15: FIFO_OUTPUT,
- _reserved2: [u8; 192usize],
- #[doc = "0x300 - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_0: DESCRIPTOR0_,
- #[doc = "0x304 - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_1: DESCRIPTOR0_,
- #[doc = "0x308 - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_2: DESCRIPTOR0_,
- #[doc = "0x30c - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_3: DESCRIPTOR0_,
- #[doc = "0x310 - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_4: DESCRIPTOR0_,
- #[doc = "0x314 - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_5: DESCRIPTOR0_,
- #[doc = "0x318 - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_6: DESCRIPTOR0_,
- #[doc = "0x31c - Table 0 descriptor n, n= 0 to 7"]
- pub descriptor0_7: DESCRIPTOR0_,
- #[doc = "0x320 - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_0: DESCRIPTOR1_,
- #[doc = "0x324 - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_1: DESCRIPTOR1_,
- #[doc = "0x328 - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_2: DESCRIPTOR1_,
- #[doc = "0x32c - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_3: DESCRIPTOR1_,
- #[doc = "0x330 - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_4: DESCRIPTOR1_,
- #[doc = "0x334 - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_5: DESCRIPTOR1_,
- #[doc = "0x338 - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_6: DESCRIPTOR1_,
- #[doc = "0x33c - Table 1 descriptors n, n=0 to 7"]
- pub descriptor1_7: DESCRIPTOR1_,
- _reserved3: [u8; 3008usize],
- #[doc = "0xf00 - Interrupt 0 clear mask"] pub clr_en0: CLR_EN0,
- #[doc = "0xf04 - Interrupt 0 set mask"] pub set_en0: SET_EN0,
- #[doc = "0xf08 - Interrupt 0 mask"] pub mask0: MASK0,
- #[doc = "0xf0c - Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow"]
- pub status0: STATUS0,
- #[doc = "0xf10 - Interrupt 0 clear status"] pub clr_stat0: CLR_STAT0,
- #[doc = "0xf14 - Interrupt 0 set status"] pub set_stat0: SET_STAT0,
- _reserved4: [u8; 8usize],
- #[doc = "0xf20 - Interrupt 1 mask clear enable."] pub clr_en1: CLR_EN1,
- #[doc = "0xf24 - Interrupt 1 mask set enable"] pub set_en1: SET_EN1,
- #[doc = "0xf28 - Interrupt 1 mask"] pub mask1: MASK1,
- #[doc = "0xf2c - Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun."]
- pub status1: STATUS1,
- #[doc = "0xf30 - Interrupt 1 clear status"] pub clr_stat1: CLR_STAT1,
- #[doc = "0xf34 - Interrupt 1 set status"] pub set_stat1: SET_STAT1,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - Flushes FIFO" ] pub flush : FLUSH , # [ doc = "0x04 - Set or clear DMA write request" ] pub dma_req : DMA_REQ , # [ doc = "0x08 - Indicates FIFO fill level status" ] pub fifo_sts : FIFO_STS , # [ doc = "0x0c - Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." ] pub fifo_cfg : FIFO_CFG , # [ doc = "0x10 - Enable software trigger to start descriptor processing" ] pub trigger : TRIGGER , # [ doc = "0x14 - Indicates active descriptor table and descriptor entry" ] pub dscr_sts : DSCR_STS , # [ doc = "0x18 - Set or clear power down mode" ] pub power_down : POWER_DOWN , # [ doc = "0x1c - Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." ] pub config : CONFIG , # [ doc = "0x20 - Configures window comparator A levels." ] pub thr_a : THR_A , # [ doc = "0x24 - Configures window comparator B levels." ] pub thr_b : THR_B , # [ doc = "0x28 - Contains last converted sample of input M [M=0..5) and result of window comparator." ] pub last_sample0 : LAST_SAMPLE , # [ doc = "0x2c - Contains last converted sample of input M [M=0..5) and result of window comparator." ] pub last_sample1 : LAST_SAMPLE , # [ doc = "0x30 - Contains last converted sample of input M [M=0..5) and result of window comparator." ] pub last_sample2 : LAST_SAMPLE , # [ doc = "0x34 - Contains last converted sample of input M [M=0..5) and result of window comparator." ] pub last_sample3 : LAST_SAMPLE , # [ doc = "0x38 - Contains last converted sample of input M [M=0..5) and result of window comparator." ] pub last_sample4 : LAST_SAMPLE , # [ doc = "0x3c - Contains last converted sample of input M [M=0..5) and result of window comparator." ] pub last_sample5 : LAST_SAMPLE , _reserved0 : [ u8 ; 196usize ] , # [ doc = "0x104 - ADC speed control" ] pub adc_speed : ADC_SPEED , # [ doc = "0x108 - Configures ADC power vs. speed, DC-in biasing, output format and power gating." ] pub power_control : POWER_CONTROL , _reserved1 : [ u8 ; 244usize ] , # [ doc = "0x200 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output0 : FIFO_OUTPUT , # [ doc = "0x204 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output1 : FIFO_OUTPUT , # [ doc = "0x208 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output2 : FIFO_OUTPUT , # [ doc = "0x20c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output3 : FIFO_OUTPUT , # [ doc = "0x210 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output4 : FIFO_OUTPUT , # [ doc = "0x214 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output5 : FIFO_OUTPUT , # [ doc = "0x218 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output6 : FIFO_OUTPUT , # [ doc = "0x21c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output7 : FIFO_OUTPUT , # [ doc = "0x220 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output8 : FIFO_OUTPUT , # [ doc = "0x224 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output9 : FIFO_OUTPUT , # [ doc = "0x228 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output10 : FIFO_OUTPUT , # [ doc = "0x22c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output11 : FIFO_OUTPUT , # [ doc = "0x230 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output12 : FIFO_OUTPUT , # [ doc = "0x234 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output13 : FIFO_OUTPUT , # [ doc = "0x238 - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output14 : FIFO_OUTPUT , # [ doc = "0x23c - FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ] pub fifo_output15 : FIFO_OUTPUT , _reserved2 : [ u8 ; 192usize ] , # [ doc = "0x300 - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_0 : DESCRIPTOR0_ , # [ doc = "0x304 - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_1 : DESCRIPTOR0_ , # [ doc = "0x308 - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_2 : DESCRIPTOR0_ , # [ doc = "0x30c - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_3 : DESCRIPTOR0_ , # [ doc = "0x310 - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_4 : DESCRIPTOR0_ , # [ doc = "0x314 - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_5 : DESCRIPTOR0_ , # [ doc = "0x318 - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_6 : DESCRIPTOR0_ , # [ doc = "0x31c - Table 0 descriptor n, n= 0 to 7" ] pub descriptor0_7 : DESCRIPTOR0_ , # [ doc = "0x320 - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_0 : DESCRIPTOR1_ , # [ doc = "0x324 - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_1 : DESCRIPTOR1_ , # [ doc = "0x328 - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_2 : DESCRIPTOR1_ , # [ doc = "0x32c - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_3 : DESCRIPTOR1_ , # [ doc = "0x330 - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_4 : DESCRIPTOR1_ , # [ doc = "0x334 - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_5 : DESCRIPTOR1_ , # [ doc = "0x338 - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_6 : DESCRIPTOR1_ , # [ doc = "0x33c - Table 1 descriptors n, n=0 to 7" ] pub descriptor1_7 : DESCRIPTOR1_ , _reserved3 : [ u8 ; 3008usize ] , # [ doc = "0xf00 - Interrupt 0 clear mask" ] pub clr_en0 : CLR_EN0 , # [ doc = "0xf04 - Interrupt 0 set mask" ] pub set_en0 : SET_EN0 , # [ doc = "0xf08 - Interrupt 0 mask" ] pub mask0 : MASK0 , # [ doc = "0xf0c - Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" ] pub status0 : STATUS0 , # [ doc = "0xf10 - Interrupt 0 clear status" ] pub clr_stat0 : CLR_STAT0 , # [ doc = "0xf14 - Interrupt 0 set status" ] pub set_stat0 : SET_STAT0 , _reserved4 : [ u8 ; 8usize ] , # [ doc = "0xf20 - Interrupt 1 mask clear enable." ] pub clr_en1 : CLR_EN1 , # [ doc = "0xf24 - Interrupt 1 mask set enable" ] pub set_en1 : SET_EN1 , # [ doc = "0xf28 - Interrupt 1 mask" ] pub mask1 : MASK1 , # [ doc = "0xf2c - Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." ] pub status1 : STATUS1 , # [ doc = "0xf30 - Interrupt 1 clear status" ] pub clr_stat1 : CLR_STAT1 , # [ doc = "0xf34 - Interrupt 1 set status" ] pub set_stat1 : SET_STAT1 , }
#[doc = "Flushes FIFO"]
pub struct FLUSH {
register: VolatileCell<u32>,
@@ -305803,8 +292650,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - 1 = Dma_req_wr is set (initially used to fill second table), 0 = Dma_req_wr is cleared"]
- #[inline(always)]
+ # [ doc = "Bit 0 - 1 = Dma_req_wr is set (initially used to fill second table), 0 = Dma_req_wr is cleared" ] # [ inline ( always ) ]
pub fn dma_req_wr(&self) -> DMA_REQ_WRR {
let bits = {
const MASK: bool = true;
@@ -305826,8 +292672,7 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bit 0 - 1 = Dma_req_wr is set (initially used to fill second table), 0 = Dma_req_wr is cleared"]
- #[inline(always)]
+ # [ doc = "Bit 0 - 1 = Dma_req_wr is set (initially used to fill second table), 0 = Dma_req_wr is cleared" ] # [ inline ( always ) ]
pub fn dma_req_wr(&mut self) -> _DMA_REQ_WRW {
_DMA_REQ_WRW { w: self }
}
@@ -305881,11 +292726,11 @@ pub mod adchs {
}
}
}
- #[doc = "Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word."]
+ # [ doc = "Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." ]
pub struct FIFO_CFG {
register: VolatileCell<u32>,
}
- #[doc = "Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word."]
+ # [ doc = "Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." ]
pub mod fifo_cfg {
#[doc = r" Value read from the register"]
pub struct R {
@@ -306007,8 +292852,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - 0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle"]
- #[inline(always)]
+ # [ doc = "Bit 0 - 0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle" ] # [ inline ( always ) ]
pub fn packed_read(&self) -> PACKED_READR {
let bits = {
const MASK: bool = true;
@@ -306017,8 +292861,7 @@ pub mod adchs {
};
PACKED_READR { bits }
}
- #[doc = "Bits 1:5 - When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised."]
- #[inline(always)]
+ # [ doc = "Bits 1:5 - When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised." ] # [ inline ( always ) ]
pub fn level(&self) -> LEVELR {
let bits = {
const MASK: u8 = 31;
@@ -306040,13 +292883,11 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bit 0 - 0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle"]
- #[inline(always)]
+ # [ doc = "Bit 0 - 0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle" ] # [ inline ( always ) ]
pub fn packed_read(&mut self) -> _PACKED_READW {
_PACKED_READW { w: self }
}
- #[doc = "Bits 1:5 - When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised."]
- #[inline(always)]
+ # [ doc = "Bits 1:5 - When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised." ] # [ inline ( always ) ]
pub fn level(&mut self) -> _LEVELW {
_LEVELW { w: self }
}
@@ -306387,8 +293228,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - 0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - 0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion." ] # [ inline ( always ) ]
pub fn pd_ctrl(&self) -> PD_CTRLR {
let bits = {
const MASK: bool = true;
@@ -306410,18 +293250,17 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bit 0 - 0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion."]
- #[inline(always)]
+ # [ doc = "Bit 0 - 0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion." ] # [ inline ( always ) ]
pub fn pd_ctrl(&mut self) -> _PD_CTRLW {
_PD_CTRLW { w: self }
}
}
}
- #[doc = "Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down."]
+ # [ doc = "Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." ]
pub struct CONFIG {
register: VolatileCell<u32>,
}
- #[doc = "Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down."]
+ # [ doc = "Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." ]
pub mod config {
#[doc = r" Value read from the register"]
pub struct R {
@@ -306639,8 +293478,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:1 - 00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - 00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed" ] # [ inline ( always ) ]
pub fn trigger__mask(&self) -> TRIGGER__MASKR {
let bits = {
const MASK: u8 = 3;
@@ -306649,8 +293487,7 @@ pub mod adchs {
};
TRIGGER__MASKR { bits }
}
- #[doc = "Bits 2:3 - 00 = rising external trigger 01 = falling external trigger 10 = low external trigger 11 = high external trigger"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - 00 = rising external trigger 01 = falling external trigger 10 = low external trigger 11 = high external trigger" ] # [ inline ( always ) ]
pub fn trigger_mode(&self) -> TRIGGER_MODER {
let bits = {
const MASK: u8 = 3;
@@ -306659,8 +293496,7 @@ pub mod adchs {
};
TRIGGER_MODER { bits }
}
- #[doc = "Bit 4 - 0 = do not synchronize external trigger input 1 = synchronize external trigger input"]
- #[inline(always)]
+ # [ doc = "Bit 4 - 0 = do not synchronize external trigger input 1 = synchronize external trigger input" ] # [ inline ( always ) ]
pub fn trigger_sync(&self) -> TRIGGER_SYNCR {
let bits = {
const MASK: bool = true;
@@ -306669,8 +293505,7 @@ pub mod adchs {
};
TRIGGER_SYNCR { bits }
}
- #[doc = "Bit 5 - 0 = do not add channel ID to FIFO output data 1 = add channel ID to FIFO output data"]
- #[inline(always)]
+ # [ doc = "Bit 5 - 0 = do not add channel ID to FIFO output data 1 = add channel ID to FIFO output data" ] # [ inline ( always ) ]
pub fn channel_id_en(&self) -> CHANNEL_ID_ENR {
let bits = {
const MASK: bool = true;
@@ -306702,23 +293537,19 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bits 0:1 - 00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed"]
- #[inline(always)]
+ # [ doc = "Bits 0:1 - 00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed" ] # [ inline ( always ) ]
pub fn trigger__mask(&mut self) -> _TRIGGER__MASKW {
_TRIGGER__MASKW { w: self }
}
- #[doc = "Bits 2:3 - 00 = rising external trigger 01 = falling external trigger 10 = low external trigger 11 = high external trigger"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - 00 = rising external trigger 01 = falling external trigger 10 = low external trigger 11 = high external trigger" ] # [ inline ( always ) ]
pub fn trigger_mode(&mut self) -> _TRIGGER_MODEW {
_TRIGGER_MODEW { w: self }
}
- #[doc = "Bit 4 - 0 = do not synchronize external trigger input 1 = synchronize external trigger input"]
- #[inline(always)]
+ # [ doc = "Bit 4 - 0 = do not synchronize external trigger input 1 = synchronize external trigger input" ] # [ inline ( always ) ]
pub fn trigger_sync(&mut self) -> _TRIGGER_SYNCW {
_TRIGGER_SYNCW { w: self }
}
- #[doc = "Bit 5 - 0 = do not add channel ID to FIFO output data 1 = add channel ID to FIFO output data"]
- #[inline(always)]
+ # [ doc = "Bit 5 - 0 = do not add channel ID to FIFO output data 1 = add channel ID to FIFO output data" ] # [ inline ( always ) ]
pub fn channel_id_en(&mut self) -> _CHANNEL_ID_ENW {
_CHANNEL_ID_ENW { w: self }
}
@@ -306837,8 +293668,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:11 - Low Compare Threshold Register A: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Low Compare Threshold Register A: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_low_a(&self) -> THR_LOW_AR {
let bits = {
const MASK: u16 = 4095;
@@ -306847,8 +293677,7 @@ pub mod adchs {
};
THR_LOW_AR { bits }
}
- #[doc = "Bits 16:27 - High Compare Threshold Register A: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 16:27 - High Compare Threshold Register A: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_high_a(&self) -> THR_HIGH_AR {
let bits = {
const MASK: u16 = 4095;
@@ -306870,13 +293699,11 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bits 0:11 - Low Compare Threshold Register A: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Low Compare Threshold Register A: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_low_a(&mut self) -> _THR_LOW_AW {
_THR_LOW_AW { w: self }
}
- #[doc = "Bits 16:27 - High Compare Threshold Register A: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 16:27 - High Compare Threshold Register A: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_high_a(&mut self) -> _THR_HIGH_AW {
_THR_HIGH_AW { w: self }
}
@@ -306990,8 +293817,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:11 - Low Compare Threshold Register B: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Low Compare Threshold Register B: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_low_b(&self) -> THR_LOW_BR {
let bits = {
const MASK: u16 = 4095;
@@ -307000,8 +293826,7 @@ pub mod adchs {
};
THR_LOW_BR { bits }
}
- #[doc = "Bits 16:27 - High Compare Threshold Register B: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 16:27 - High Compare Threshold Register B: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_high_b(&self) -> THR_HIGH_BR {
let bits = {
const MASK: u16 = 4095;
@@ -307023,13 +293848,11 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bits 0:11 - Low Compare Threshold Register B: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Low Compare Threshold Register B: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_low_b(&mut self) -> _THR_LOW_BW {
_THR_LOW_BW { w: self }
}
- #[doc = "Bits 16:27 - High Compare Threshold Register B: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A."]
- #[inline(always)]
+ # [ doc = "Bits 16:27 - High Compare Threshold Register B: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A." ] # [ inline ( always ) ]
pub fn thr_high_b(&mut self) -> _THR_HIGH_BW {
_THR_HIGH_BW { w: self }
}
@@ -307135,8 +293958,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read."]
- #[inline(always)]
+ # [ doc = "Bit 0 - This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read." ] # [ inline ( always ) ]
pub fn done(&self) -> DONER {
let bits = {
const MASK: bool = true;
@@ -307145,8 +293967,7 @@ pub mod adchs {
};
DONER { bits }
}
- #[doc = "Bit 1 - This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled."]
- #[inline(always)]
+ # [ doc = "Bit 1 - This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." ] # [ inline ( always ) ]
pub fn overrun(&self) -> OVERRUNR {
let bits = {
const MASK: bool = true;
@@ -307155,8 +293976,7 @@ pub mod adchs {
};
OVERRUNR { bits }
}
- #[doc = "Bits 2:3 - Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 2:3 - Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved" ] # [ inline ( always ) ]
pub fn thcmp_range(&self) -> THCMP_RANGER {
let bits = {
const MASK: u8 = 3;
@@ -307165,8 +293985,7 @@ pub mod adchs {
};
THCMP_RANGER { bits }
}
- #[doc = "Bits 4:5 - Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 4:5 - Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved" ] # [ inline ( always ) ]
pub fn thcmp_cross(&self) -> THCMP_CROSSR {
let bits = {
const MASK: u8 = 3;
@@ -307790,8 +294609,7 @@ pub mod adchs {
};
DCINNEGR { bits }
}
- #[doc = "Bits 10:15 - AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side"]
- #[inline(always)]
+ # [ doc = "Bits 10:15 - AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side" ] # [ inline ( always ) ]
pub fn dcinpos(&self) -> DCINPOSR {
let bits = {
const MASK: u8 = 63;
@@ -307820,8 +294638,7 @@ pub mod adchs {
};
POWER_SWITCHR { bits }
}
- #[doc = "Bit 18 - 0 = ADC band gap reference is powered down 1 = ADC band gap reference is active"]
- #[inline(always)]
+ # [ doc = "Bit 18 - 0 = ADC band gap reference is powered down 1 = ADC band gap reference is active" ] # [ inline ( always ) ]
pub fn bgap_switch(&self) -> BGAP_SWITCHR {
let bits = {
const MASK: bool = true;
@@ -307853,8 +294670,7 @@ pub mod adchs {
pub fn dcinneg(&mut self) -> _DCINNEGW {
_DCINNEGW { w: self }
}
- #[doc = "Bits 10:15 - AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side"]
- #[inline(always)]
+ # [ doc = "Bits 10:15 - AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side" ] # [ inline ( always ) ]
pub fn dcinpos(&mut self) -> _DCINPOSW {
_DCINPOSW { w: self }
}
@@ -307868,18 +294684,17 @@ pub mod adchs {
pub fn power_switch(&mut self) -> _POWER_SWITCHW {
_POWER_SWITCHW { w: self }
}
- #[doc = "Bit 18 - 0 = ADC band gap reference is powered down 1 = ADC band gap reference is active"]
- #[inline(always)]
+ # [ doc = "Bit 18 - 0 = ADC band gap reference is powered down 1 = ADC band gap reference is active" ] # [ inline ( always ) ]
pub fn bgap_switch(&mut self) -> _BGAP_SWITCHW {
_BGAP_SWITCHW { w: self }
}
}
}
- #[doc = "FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
+ # [ doc = "FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ]
pub struct FIFO_OUTPUT {
register: VolatileCell<u32>,
}
- #[doc = "FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples"]
+ # [ doc = "FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" ]
pub mod fifo_output {
#[doc = r" Value read from the register"]
pub struct R {
@@ -307996,8 +294811,7 @@ pub mod adchs {
};
SAMPLER { bits }
}
- #[doc = "Bits 12:14 - Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error"]
- #[inline(always)]
+ # [ doc = "Bits 12:14 - Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error" ] # [ inline ( always ) ]
pub fn chan_id(&self) -> CHAN_IDR {
let bits = {
const MASK: u8 = 7;
@@ -308016,8 +294830,7 @@ pub mod adchs {
};
EMPTYR { bits }
}
- #[doc = "Bits 16:27 - Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0"]
- #[inline(always)]
+ # [ doc = "Bits 16:27 - Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0" ] # [ inline ( always ) ]
pub fn sample2(&self) -> SAMPLE2R {
let bits = {
const MASK: u16 = 4095;
@@ -308026,8 +294839,7 @@ pub mod adchs {
};
SAMPLE2R { bits }
}
- #[doc = "Bits 28:30 - Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0"]
- #[inline(always)]
+ # [ doc = "Bits 28:30 - Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" ] # [ inline ( always ) ]
pub fn chan_id2(&self) -> CHAN_ID2R {
let bits = {
const MASK: u8 = 7;
@@ -308428,8 +295240,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved"]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" ] # [ inline ( always ) ]
pub fn channel_nr(&self) -> CHANNEL_NRR {
let bits = {
const MASK: u8 = 7;
@@ -308438,8 +295249,7 @@ pub mod adchs {
};
CHANNEL_NRR { bits }
}
- #[doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger."]
- #[inline(always)]
+ # [ doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." ] # [ inline ( always ) ]
pub fn halt(&self) -> HALTR {
let bits = {
const MASK: bool = true;
@@ -308468,8 +295278,7 @@ pub mod adchs {
};
POWER_DOWNR { bits }
}
- #[doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." ] # [ inline ( always ) ]
pub fn branch(&self) -> BRANCHR {
let bits = {
const MASK: u8 = 3;
@@ -308478,8 +295287,7 @@ pub mod adchs {
};
BRANCHR { bits }
}
- #[doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value."]
- #[inline(always)]
+ # [ doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value." ] # [ inline ( always ) ]
pub fn match_value(&self) -> MATCH_VALUER {
let bits = {
const MASK: u16 = 16383;
@@ -308488,8 +295296,7 @@ pub mod adchs {
};
MATCH_VALUER { bits }
}
- #[doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" ] # [ inline ( always ) ]
pub fn threshold_sel(&self) -> THRESHOLD_SELR {
let bits = {
const MASK: u8 = 3;
@@ -308508,8 +295315,7 @@ pub mod adchs {
};
RESET_TIMERR { bits }
}
- #[doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0."]
- #[inline(always)]
+ # [ doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." ] # [ inline ( always ) ]
pub fn update_table(&self) -> UPDATE_TABLER {
let bits = {
const MASK: bool = true;
@@ -308531,13 +295337,11 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved"]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" ] # [ inline ( always ) ]
pub fn channel_nr(&mut self) -> _CHANNEL_NRW {
_CHANNEL_NRW { w: self }
}
- #[doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger."]
- #[inline(always)]
+ # [ doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." ] # [ inline ( always ) ]
pub fn halt(&mut self) -> _HALTW {
_HALTW { w: self }
}
@@ -308551,18 +295355,15 @@ pub mod adchs {
pub fn power_down(&mut self) -> _POWER_DOWNW {
_POWER_DOWNW { w: self }
}
- #[doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." ] # [ inline ( always ) ]
pub fn branch(&mut self) -> _BRANCHW {
_BRANCHW { w: self }
}
- #[doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value."]
- #[inline(always)]
+ # [ doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value." ] # [ inline ( always ) ]
pub fn match_value(&mut self) -> _MATCH_VALUEW {
_MATCH_VALUEW { w: self }
}
- #[doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" ] # [ inline ( always ) ]
pub fn threshold_sel(&mut self) -> _THRESHOLD_SELW {
_THRESHOLD_SELW { w: self }
}
@@ -308571,8 +295372,7 @@ pub mod adchs {
pub fn reset_timer(&mut self) -> _RESET_TIMERW {
_RESET_TIMERW { w: self }
}
- #[doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0."]
- #[inline(always)]
+ # [ doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." ] # [ inline ( always ) ]
pub fn update_table(&mut self) -> _UPDATE_TABLEW {
_UPDATE_TABLEW { w: self }
}
@@ -308958,8 +295758,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved"]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" ] # [ inline ( always ) ]
pub fn channel_nr(&self) -> CHANNEL_NRR {
let bits = {
const MASK: u8 = 7;
@@ -308968,8 +295767,7 @@ pub mod adchs {
};
CHANNEL_NRR { bits }
}
- #[doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger."]
- #[inline(always)]
+ # [ doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." ] # [ inline ( always ) ]
pub fn halt(&self) -> HALTR {
let bits = {
const MASK: bool = true;
@@ -308998,8 +295796,7 @@ pub mod adchs {
};
POWER_DOWNR { bits }
}
- #[doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." ] # [ inline ( always ) ]
pub fn branch(&self) -> BRANCHR {
let bits = {
const MASK: u8 = 3;
@@ -309008,8 +295805,7 @@ pub mod adchs {
};
BRANCHR { bits }
}
- #[doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value."]
- #[inline(always)]
+ # [ doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value." ] # [ inline ( always ) ]
pub fn match_value(&self) -> MATCH_VALUER {
let bits = {
const MASK: u16 = 16383;
@@ -309018,8 +295814,7 @@ pub mod adchs {
};
MATCH_VALUER { bits }
}
- #[doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" ] # [ inline ( always ) ]
pub fn threshold_sel(&self) -> THRESHOLD_SELR {
let bits = {
const MASK: u8 = 3;
@@ -309038,8 +295833,7 @@ pub mod adchs {
};
RESET_TIMERR { bits }
}
- #[doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0."]
- #[inline(always)]
+ # [ doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." ] # [ inline ( always ) ]
pub fn update_table(&self) -> UPDATE_TABLER {
let bits = {
const MASK: bool = true;
@@ -309061,13 +295855,11 @@ pub mod adchs {
self.bits = bits;
self
}
- #[doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved"]
- #[inline(always)]
+ # [ doc = "Bits 0:2 - 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved" ] # [ inline ( always ) ]
pub fn channel_nr(&mut self) -> _CHANNEL_NRW {
_CHANNEL_NRW { w: self }
}
- #[doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger."]
- #[inline(always)]
+ # [ doc = "Bit 3 - 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger." ] # [ inline ( always ) ]
pub fn halt(&mut self) -> _HALTW {
_HALTW { w: self }
}
@@ -309081,18 +295873,15 @@ pub mod adchs {
pub fn power_down(&mut self) -> _POWER_DOWNW {
_POWER_DOWNW { w: self }
}
- #[doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)."]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." ] # [ inline ( always ) ]
pub fn branch(&mut self) -> _BRANCHW {
_BRANCHW { w: self }
}
- #[doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value."]
- #[inline(always)]
+ # [ doc = "Bits 8:21 - Evaluate this descriptor when descriptor timer value is equal to match value." ] # [ inline ( always ) ]
pub fn match_value(&mut self) -> _MATCH_VALUEW {
_MATCH_VALUEW { w: self }
}
- #[doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved" ] # [ inline ( always ) ]
pub fn threshold_sel(&mut self) -> _THRESHOLD_SELW {
_THRESHOLD_SELW { w: self }
}
@@ -309101,8 +295890,7 @@ pub mod adchs {
pub fn reset_timer(&mut self) -> _RESET_TIMERW {
_RESET_TIMERW { w: self }
}
- #[doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0."]
- #[inline(always)]
+ # [ doc = "Bit 31 - 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0." ] # [ inline ( always ) ]
pub fn update_table(&mut self) -> _UPDATE_TABLEW {
_UPDATE_TABLEW { w: self }
}
@@ -309268,11 +296056,11 @@ pub mod adchs {
}
}
}
- #[doc = "Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow"]
+ # [ doc = "Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" ]
pub struct STATUS0 {
register: VolatileCell<u32>,
}
- #[doc = "Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow"]
+ # [ doc = "Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" ]
pub mod status0 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -309440,8 +296228,7 @@ pub mod adchs {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - 0: number of samples in FIFO less than or equal to FIFO_LEVEL 1: number of samples in FIFO is more than FIFO_LEVEL"]
- #[inline(always)]
+ # [ doc = "Bit 0 - 0: number of samples in FIFO less than or equal to FIFO_LEVEL 1: number of samples in FIFO is more than FIFO_LEVEL" ] # [ inline ( always ) ]
pub fn fifo_full(&self) -> FIFO_FULLR {
let bits = {
const MASK: bool = true;
@@ -309470,8 +296257,7 @@ pub mod adchs {
};
FIFO_OVERFLOWR { bits }
}
- #[doc = "Bit 3 - The descriptor INTERRUPT field was enabled and its sample is converted."]
- #[inline(always)]
+ # [ doc = "Bit 3 - The descriptor INTERRUPT field was enabled and its sample is converted." ] # [ inline ( always ) ]
pub fn dscr_done(&self) -> DSCR_DONER {
let bits = {
const MASK: bool = true;
@@ -309480,8 +296266,7 @@ pub mod adchs {
};
DSCR_DONER { bits }
}
- #[doc = "Bit 4 - The ADC was not fully woken up when a sample was converted and the conversion results is unreliable"]
- #[inline(always)]
+ # [ doc = "Bit 4 - The ADC was not fully woken up when a sample was converted and the conversion results is unreliable" ] # [ inline ( always ) ]
pub fn dscr_error(&self) -> DSCR_ERRORR {
let bits = {
const MASK: bool = true;
@@ -309784,11 +296569,11 @@ pub mod adchs {
}
}
}
- #[doc = "Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun."]
+ # [ doc = "Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." ]
pub struct STATUS1 {
register: VolatileCell<u32>,
}
- #[doc = "Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun."]
+ # [ doc = "Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." ]
pub mod status1 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -310479,8 +297264,7 @@ pub mod adchs {
};
THCMP_UCROSS0R { bits }
}
- #[doc = "Bit 4 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [0] before it has been read"]
- #[inline(always)]
+ # [ doc = "Bit 4 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [0] before it has been read" ] # [ inline ( always ) ]
pub fn overrun_0(&self) -> OVERRUN_0R {
let bits = {
const MASK: bool = true;
@@ -310529,8 +297313,7 @@ pub mod adchs {
};
THCMP_UCROSS1R { bits }
}
- #[doc = "Bit 9 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [1] before it has been read"]
- #[inline(always)]
+ # [ doc = "Bit 9 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [1] before it has been read" ] # [ inline ( always ) ]
pub fn overrun_1(&self) -> OVERRUN_1R {
let bits = {
const MASK: bool = true;
@@ -310579,8 +297362,7 @@ pub mod adchs {
};
THCMP_UCROSS2R { bits }
}
- #[doc = "Bit 14 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [2] before it has been read"]
- #[inline(always)]
+ # [ doc = "Bit 14 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [2] before it has been read" ] # [ inline ( always ) ]
pub fn overrun_2(&self) -> OVERRUN_2R {
let bits = {
const MASK: bool = true;
@@ -310629,8 +297411,7 @@ pub mod adchs {
};
THCMP_UCROSS3R { bits }
}
- #[doc = "Bit 19 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [3] before it has been read"]
- #[inline(always)]
+ # [ doc = "Bit 19 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [3] before it has been read" ] # [ inline ( always ) ]
pub fn overrun_3(&self) -> OVERRUN_3R {
let bits = {
const MASK: bool = true;
@@ -310679,8 +297460,7 @@ pub mod adchs {
};
THCMP_UCROSS4R { bits }
}
- #[doc = "Bit 24 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [4] before it has been read"]
- #[inline(always)]
+ # [ doc = "Bit 24 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [4] before it has been read" ] # [ inline ( always ) ]
pub fn overrun_4(&self) -> OVERRUN_4R {
let bits = {
const MASK: bool = true;
@@ -310729,8 +297509,7 @@ pub mod adchs {
};
THCMP_UCROSS5R { bits }
}
- #[doc = "Bit 29 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [5] before it has been read"]
- #[inline(always)]
+ # [ doc = "Bit 29 - A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [5] before it has been read" ] # [ inline ( always ) ]
pub fn overrun_5(&self) -> OVERRUN_5R {
let bits = {
const MASK: bool = true;
@@ -310865,526 +297644,269 @@ impl Deref for ADCHS {
}
}
#[doc = "GPIO port"]
-pub const GPIO_PORT: Peripheral<GPIO_PORT> =
- unsafe { Peripheral::new(1074741248) };
+pub const GPIO_PORT: Peripheral<GPIO_PORT> = unsafe { Peripheral::new(1074741248) };
#[doc = "GPIO port"]
pub mod gpio_port {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
- #[doc = "0x00 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b0: B,
- #[doc = "0x01 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b1: B,
- #[doc = "0x02 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b2: B,
- #[doc = "0x03 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b3: B,
- #[doc = "0x04 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b4: B,
- #[doc = "0x05 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b5: B,
- #[doc = "0x06 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b6: B,
- #[doc = "0x07 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b7: B,
- #[doc = "0x08 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b8: B,
- #[doc = "0x09 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b9: B,
- #[doc = "0x0a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b10: B,
- #[doc = "0x0b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b11: B,
- #[doc = "0x0c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b12: B,
- #[doc = "0x0d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b13: B,
- #[doc = "0x0e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b14: B,
- #[doc = "0x0f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b15: B,
- #[doc = "0x10 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b16: B,
- #[doc = "0x11 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b17: B,
- #[doc = "0x12 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b18: B,
- #[doc = "0x13 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b19: B,
- #[doc = "0x14 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b20: B,
- #[doc = "0x15 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b21: B,
- #[doc = "0x16 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b22: B,
- #[doc = "0x17 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b23: B,
- #[doc = "0x18 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b24: B,
- #[doc = "0x19 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b25: B,
- #[doc = "0x1a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b26: B,
- #[doc = "0x1b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b27: B,
- #[doc = "0x1c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b28: B,
- #[doc = "0x1d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b29: B,
- #[doc = "0x1e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b30: B,
- #[doc = "0x1f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b31: B,
- #[doc = "0x20 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b32: B,
- #[doc = "0x21 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b33: B,
- #[doc = "0x22 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b34: B,
- #[doc = "0x23 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b35: B,
- #[doc = "0x24 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b36: B,
- #[doc = "0x25 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b37: B,
- #[doc = "0x26 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b38: B,
- #[doc = "0x27 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b39: B,
- #[doc = "0x28 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b40: B,
- #[doc = "0x29 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b41: B,
- #[doc = "0x2a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b42: B,
- #[doc = "0x2b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b43: B,
- #[doc = "0x2c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b44: B,
- #[doc = "0x2d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b45: B,
- #[doc = "0x2e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b46: B,
- #[doc = "0x2f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b47: B,
- #[doc = "0x30 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b48: B,
- #[doc = "0x31 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b49: B,
- #[doc = "0x32 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b50: B,
- #[doc = "0x33 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b51: B,
- #[doc = "0x34 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b52: B,
- #[doc = "0x35 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b53: B,
- #[doc = "0x36 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b54: B,
- #[doc = "0x37 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b55: B,
- #[doc = "0x38 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b56: B,
- #[doc = "0x39 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b57: B,
- #[doc = "0x3a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b58: B,
- #[doc = "0x3b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b59: B,
- #[doc = "0x3c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b60: B,
- #[doc = "0x3d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b61: B,
- #[doc = "0x3e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b62: B,
- #[doc = "0x3f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b63: B,
- #[doc = "0x40 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b64: B,
- #[doc = "0x41 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b65: B,
- #[doc = "0x42 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b66: B,
- #[doc = "0x43 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b67: B,
- #[doc = "0x44 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b68: B,
- #[doc = "0x45 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b69: B,
- #[doc = "0x46 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b70: B,
- #[doc = "0x47 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b71: B,
- #[doc = "0x48 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b72: B,
- #[doc = "0x49 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b73: B,
- #[doc = "0x4a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b74: B,
- #[doc = "0x4b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b75: B,
- #[doc = "0x4c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b76: B,
- #[doc = "0x4d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b77: B,
- #[doc = "0x4e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b78: B,
- #[doc = "0x4f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b79: B,
- #[doc = "0x50 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b80: B,
- #[doc = "0x51 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b81: B,
- #[doc = "0x52 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b82: B,
- #[doc = "0x53 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b83: B,
- #[doc = "0x54 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b84: B,
- #[doc = "0x55 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b85: B,
- #[doc = "0x56 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b86: B,
- #[doc = "0x57 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b87: B,
- #[doc = "0x58 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b88: B,
- #[doc = "0x59 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b89: B,
- #[doc = "0x5a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b90: B,
- #[doc = "0x5b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b91: B,
- #[doc = "0x5c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b92: B,
- #[doc = "0x5d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b93: B,
- #[doc = "0x5e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b94: B,
- #[doc = "0x5f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b95: B,
- #[doc = "0x60 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b96: B,
- #[doc = "0x61 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b97: B,
- #[doc = "0x62 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b98: B,
- #[doc = "0x63 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b99: B,
- #[doc = "0x64 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b100: B,
- #[doc = "0x65 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b101: B,
- #[doc = "0x66 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b102: B,
- #[doc = "0x67 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b103: B,
- #[doc = "0x68 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b104: B,
- #[doc = "0x69 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b105: B,
- #[doc = "0x6a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b106: B,
- #[doc = "0x6b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b107: B,
- #[doc = "0x6c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b108: B,
- #[doc = "0x6d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b109: B,
- #[doc = "0x6e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b110: B,
- #[doc = "0x6f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b111: B,
- #[doc = "0x70 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b112: B,
- #[doc = "0x71 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b113: B,
- #[doc = "0x72 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b114: B,
- #[doc = "0x73 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b115: B,
- #[doc = "0x74 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b116: B,
- #[doc = "0x75 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b117: B,
- #[doc = "0x76 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b118: B,
- #[doc = "0x77 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b119: B,
- #[doc = "0x78 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b120: B,
- #[doc = "0x79 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b121: B,
- #[doc = "0x7a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b122: B,
- #[doc = "0x7b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b123: B,
- #[doc = "0x7c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b124: B,
- #[doc = "0x7d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b125: B,
- #[doc = "0x7e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b126: B,
- #[doc = "0x7f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b127: B,
- #[doc = "0x80 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b128: B,
- #[doc = "0x81 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b129: B,
- #[doc = "0x82 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b130: B,
- #[doc = "0x83 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b131: B,
- #[doc = "0x84 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b132: B,
- #[doc = "0x85 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b133: B,
- #[doc = "0x86 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b134: B,
- #[doc = "0x87 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b135: B,
- #[doc = "0x88 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b136: B,
- #[doc = "0x89 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b137: B,
- #[doc = "0x8a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b138: B,
- #[doc = "0x8b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b139: B,
- #[doc = "0x8c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b140: B,
- #[doc = "0x8d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b141: B,
- #[doc = "0x8e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b142: B,
- #[doc = "0x8f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b143: B,
- #[doc = "0x90 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b144: B,
- #[doc = "0x91 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b145: B,
- #[doc = "0x92 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b146: B,
- #[doc = "0x93 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b147: B,
- #[doc = "0x94 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b148: B,
- #[doc = "0x95 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b149: B,
- #[doc = "0x96 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b150: B,
- #[doc = "0x97 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b151: B,
- #[doc = "0x98 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b152: B,
- #[doc = "0x99 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b153: B,
- #[doc = "0x9a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b154: B,
- #[doc = "0x9b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b155: B,
- #[doc = "0x9c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b156: B,
- #[doc = "0x9d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b157: B,
- #[doc = "0x9e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b158: B,
- #[doc = "0x9f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b159: B,
- #[doc = "0xa0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b160: B,
- #[doc = "0xa1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b161: B,
- #[doc = "0xa2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b162: B,
- #[doc = "0xa3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b163: B,
- #[doc = "0xa4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b164: B,
- #[doc = "0xa5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b165: B,
- #[doc = "0xa6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b166: B,
- #[doc = "0xa7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b167: B,
- #[doc = "0xa8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b168: B,
- #[doc = "0xa9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b169: B,
- #[doc = "0xaa - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b170: B,
- #[doc = "0xab - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b171: B,
- #[doc = "0xac - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b172: B,
- #[doc = "0xad - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b173: B,
- #[doc = "0xae - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b174: B,
- #[doc = "0xaf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b175: B,
- #[doc = "0xb0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b176: B,
- #[doc = "0xb1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b177: B,
- #[doc = "0xb2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b178: B,
- #[doc = "0xb3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b179: B,
- #[doc = "0xb4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b180: B,
- #[doc = "0xb5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b181: B,
- #[doc = "0xb6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b182: B,
- #[doc = "0xb7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b183: B,
- #[doc = "0xb8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b184: B,
- #[doc = "0xb9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b185: B,
- #[doc = "0xba - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b186: B,
- #[doc = "0xbb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b187: B,
- #[doc = "0xbc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b188: B,
- #[doc = "0xbd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b189: B,
- #[doc = "0xbe - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b190: B,
- #[doc = "0xbf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b191: B,
- #[doc = "0xc0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b192: B,
- #[doc = "0xc1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b193: B,
- #[doc = "0xc2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b194: B,
- #[doc = "0xc3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b195: B,
- #[doc = "0xc4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b196: B,
- #[doc = "0xc5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b197: B,
- #[doc = "0xc6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b198: B,
- #[doc = "0xc7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b199: B,
- #[doc = "0xc8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b200: B,
- #[doc = "0xc9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b201: B,
- #[doc = "0xca - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b202: B,
- #[doc = "0xcb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b203: B,
- #[doc = "0xcc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b204: B,
- #[doc = "0xcd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b205: B,
- #[doc = "0xce - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b206: B,
- #[doc = "0xcf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b207: B,
- #[doc = "0xd0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b208: B,
- #[doc = "0xd1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b209: B,
- #[doc = "0xd2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b210: B,
- #[doc = "0xd3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b211: B,
- #[doc = "0xd4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b212: B,
- #[doc = "0xd5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b213: B,
- #[doc = "0xd6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b214: B,
- #[doc = "0xd7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b215: B,
- #[doc = "0xd8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b216: B,
- #[doc = "0xd9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b217: B,
- #[doc = "0xda - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b218: B,
- #[doc = "0xdb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b219: B,
- #[doc = "0xdc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b220: B,
- #[doc = "0xdd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b221: B,
- #[doc = "0xde - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b222: B,
- #[doc = "0xdf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b223: B,
- #[doc = "0xe0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b224: B,
- #[doc = "0xe1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b225: B,
- #[doc = "0xe2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b226: B,
- #[doc = "0xe3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b227: B,
- #[doc = "0xe4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b228: B,
- #[doc = "0xe5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b229: B,
- #[doc = "0xe6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b230: B,
- #[doc = "0xe7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b231: B,
- #[doc = "0xe8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b232: B,
- #[doc = "0xe9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b233: B,
- #[doc = "0xea - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b234: B,
- #[doc = "0xeb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b235: B,
- #[doc = "0xec - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b236: B,
- #[doc = "0xed - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b237: B,
- #[doc = "0xee - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b238: B,
- #[doc = "0xef - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b239: B,
- #[doc = "0xf0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b240: B,
- #[doc = "0xf1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b241: B,
- #[doc = "0xf2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b242: B,
- #[doc = "0xf3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b243: B,
- #[doc = "0xf4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b244: B,
- #[doc = "0xf5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b245: B,
- #[doc = "0xf6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b246: B,
- #[doc = "0xf7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b247: B,
- #[doc = "0xf8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b248: B,
- #[doc = "0xf9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b249: B,
- #[doc = "0xfa - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b250: B,
- #[doc = "0xfb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b251: B,
- #[doc = "0xfc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b252: B,
- #[doc = "0xfd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b253: B,
- #[doc = "0xfe - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b254: B,
- #[doc = "0xff - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"]
- pub b255: B,
+ #[doc = "0x00 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b0: B,
+ #[doc = "0x01 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b1: B,
+ #[doc = "0x02 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b2: B,
+ #[doc = "0x03 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b3: B,
+ #[doc = "0x04 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b4: B,
+ #[doc = "0x05 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b5: B,
+ #[doc = "0x06 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b6: B,
+ #[doc = "0x07 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b7: B,
+ #[doc = "0x08 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b8: B,
+ #[doc = "0x09 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b9: B,
+ #[doc = "0x0a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b10: B,
+ #[doc = "0x0b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b11: B,
+ #[doc = "0x0c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b12: B,
+ #[doc = "0x0d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b13: B,
+ #[doc = "0x0e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b14: B,
+ #[doc = "0x0f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b15: B,
+ #[doc = "0x10 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b16: B,
+ #[doc = "0x11 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b17: B,
+ #[doc = "0x12 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b18: B,
+ #[doc = "0x13 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b19: B,
+ #[doc = "0x14 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b20: B,
+ #[doc = "0x15 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b21: B,
+ #[doc = "0x16 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b22: B,
+ #[doc = "0x17 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b23: B,
+ #[doc = "0x18 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b24: B,
+ #[doc = "0x19 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b25: B,
+ #[doc = "0x1a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b26: B,
+ #[doc = "0x1b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b27: B,
+ #[doc = "0x1c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b28: B,
+ #[doc = "0x1d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b29: B,
+ #[doc = "0x1e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b30: B,
+ #[doc = "0x1f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b31: B,
+ #[doc = "0x20 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b32: B,
+ #[doc = "0x21 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b33: B,
+ #[doc = "0x22 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b34: B,
+ #[doc = "0x23 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b35: B,
+ #[doc = "0x24 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b36: B,
+ #[doc = "0x25 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b37: B,
+ #[doc = "0x26 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b38: B,
+ #[doc = "0x27 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b39: B,
+ #[doc = "0x28 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b40: B,
+ #[doc = "0x29 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b41: B,
+ #[doc = "0x2a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b42: B,
+ #[doc = "0x2b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b43: B,
+ #[doc = "0x2c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b44: B,
+ #[doc = "0x2d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b45: B,
+ #[doc = "0x2e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b46: B,
+ #[doc = "0x2f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b47: B,
+ #[doc = "0x30 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b48: B,
+ #[doc = "0x31 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b49: B,
+ #[doc = "0x32 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b50: B,
+ #[doc = "0x33 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b51: B,
+ #[doc = "0x34 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b52: B,
+ #[doc = "0x35 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b53: B,
+ #[doc = "0x36 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b54: B,
+ #[doc = "0x37 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b55: B,
+ #[doc = "0x38 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b56: B,
+ #[doc = "0x39 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b57: B,
+ #[doc = "0x3a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b58: B,
+ #[doc = "0x3b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b59: B,
+ #[doc = "0x3c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b60: B,
+ #[doc = "0x3d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b61: B,
+ #[doc = "0x3e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b62: B,
+ #[doc = "0x3f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b63: B,
+ #[doc = "0x40 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b64: B,
+ #[doc = "0x41 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b65: B,
+ #[doc = "0x42 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b66: B,
+ #[doc = "0x43 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b67: B,
+ #[doc = "0x44 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b68: B,
+ #[doc = "0x45 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b69: B,
+ #[doc = "0x46 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b70: B,
+ #[doc = "0x47 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b71: B,
+ #[doc = "0x48 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b72: B,
+ #[doc = "0x49 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b73: B,
+ #[doc = "0x4a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b74: B,
+ #[doc = "0x4b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b75: B,
+ #[doc = "0x4c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b76: B,
+ #[doc = "0x4d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b77: B,
+ #[doc = "0x4e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b78: B,
+ #[doc = "0x4f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b79: B,
+ #[doc = "0x50 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b80: B,
+ #[doc = "0x51 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b81: B,
+ #[doc = "0x52 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b82: B,
+ #[doc = "0x53 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b83: B,
+ #[doc = "0x54 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b84: B,
+ #[doc = "0x55 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b85: B,
+ #[doc = "0x56 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b86: B,
+ #[doc = "0x57 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b87: B,
+ #[doc = "0x58 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b88: B,
+ #[doc = "0x59 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b89: B,
+ #[doc = "0x5a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b90: B,
+ #[doc = "0x5b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b91: B,
+ #[doc = "0x5c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b92: B,
+ #[doc = "0x5d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b93: B,
+ #[doc = "0x5e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b94: B,
+ #[doc = "0x5f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b95: B,
+ #[doc = "0x60 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b96: B,
+ #[doc = "0x61 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b97: B,
+ #[doc = "0x62 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b98: B,
+ #[doc = "0x63 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b99: B,
+ #[doc = "0x64 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b100: B,
+ #[doc = "0x65 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b101: B,
+ #[doc = "0x66 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b102: B,
+ #[doc = "0x67 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b103: B,
+ #[doc = "0x68 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b104: B,
+ #[doc = "0x69 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b105: B,
+ #[doc = "0x6a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b106: B,
+ #[doc = "0x6b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b107: B,
+ #[doc = "0x6c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b108: B,
+ #[doc = "0x6d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b109: B,
+ #[doc = "0x6e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b110: B,
+ #[doc = "0x6f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b111: B,
+ #[doc = "0x70 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b112: B,
+ #[doc = "0x71 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b113: B,
+ #[doc = "0x72 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b114: B,
+ #[doc = "0x73 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b115: B,
+ #[doc = "0x74 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b116: B,
+ #[doc = "0x75 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b117: B,
+ #[doc = "0x76 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b118: B,
+ #[doc = "0x77 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b119: B,
+ #[doc = "0x78 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b120: B,
+ #[doc = "0x79 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b121: B,
+ #[doc = "0x7a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b122: B,
+ #[doc = "0x7b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b123: B,
+ #[doc = "0x7c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b124: B,
+ #[doc = "0x7d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b125: B,
+ #[doc = "0x7e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b126: B,
+ #[doc = "0x7f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b127: B,
+ #[doc = "0x80 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b128: B,
+ #[doc = "0x81 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b129: B,
+ #[doc = "0x82 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b130: B,
+ #[doc = "0x83 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b131: B,
+ #[doc = "0x84 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b132: B,
+ #[doc = "0x85 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b133: B,
+ #[doc = "0x86 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b134: B,
+ #[doc = "0x87 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b135: B,
+ #[doc = "0x88 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b136: B,
+ #[doc = "0x89 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b137: B,
+ #[doc = "0x8a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b138: B,
+ #[doc = "0x8b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b139: B,
+ #[doc = "0x8c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b140: B,
+ #[doc = "0x8d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b141: B,
+ #[doc = "0x8e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b142: B,
+ #[doc = "0x8f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b143: B,
+ #[doc = "0x90 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b144: B,
+ #[doc = "0x91 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b145: B,
+ #[doc = "0x92 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b146: B,
+ #[doc = "0x93 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b147: B,
+ #[doc = "0x94 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b148: B,
+ #[doc = "0x95 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b149: B,
+ #[doc = "0x96 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b150: B,
+ #[doc = "0x97 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b151: B,
+ #[doc = "0x98 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b152: B,
+ #[doc = "0x99 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b153: B,
+ #[doc = "0x9a - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b154: B,
+ #[doc = "0x9b - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b155: B,
+ #[doc = "0x9c - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b156: B,
+ #[doc = "0x9d - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b157: B,
+ #[doc = "0x9e - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b158: B,
+ #[doc = "0x9f - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b159: B,
+ #[doc = "0xa0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b160: B,
+ #[doc = "0xa1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b161: B,
+ #[doc = "0xa2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b162: B,
+ #[doc = "0xa3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b163: B,
+ #[doc = "0xa4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b164: B,
+ #[doc = "0xa5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b165: B,
+ #[doc = "0xa6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b166: B,
+ #[doc = "0xa7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b167: B,
+ #[doc = "0xa8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b168: B,
+ #[doc = "0xa9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b169: B,
+ #[doc = "0xaa - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b170: B,
+ #[doc = "0xab - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b171: B,
+ #[doc = "0xac - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b172: B,
+ #[doc = "0xad - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b173: B,
+ #[doc = "0xae - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b174: B,
+ #[doc = "0xaf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b175: B,
+ #[doc = "0xb0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b176: B,
+ #[doc = "0xb1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b177: B,
+ #[doc = "0xb2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b178: B,
+ #[doc = "0xb3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b179: B,
+ #[doc = "0xb4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b180: B,
+ #[doc = "0xb5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b181: B,
+ #[doc = "0xb6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b182: B,
+ #[doc = "0xb7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b183: B,
+ #[doc = "0xb8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b184: B,
+ #[doc = "0xb9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b185: B,
+ #[doc = "0xba - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b186: B,
+ #[doc = "0xbb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b187: B,
+ #[doc = "0xbc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b188: B,
+ #[doc = "0xbd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b189: B,
+ #[doc = "0xbe - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b190: B,
+ #[doc = "0xbf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b191: B,
+ #[doc = "0xc0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b192: B,
+ #[doc = "0xc1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b193: B,
+ #[doc = "0xc2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b194: B,
+ #[doc = "0xc3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b195: B,
+ #[doc = "0xc4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b196: B,
+ #[doc = "0xc5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b197: B,
+ #[doc = "0xc6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b198: B,
+ #[doc = "0xc7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b199: B,
+ #[doc = "0xc8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b200: B,
+ #[doc = "0xc9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b201: B,
+ #[doc = "0xca - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b202: B,
+ #[doc = "0xcb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b203: B,
+ #[doc = "0xcc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b204: B,
+ #[doc = "0xcd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b205: B,
+ #[doc = "0xce - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b206: B,
+ #[doc = "0xcf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b207: B,
+ #[doc = "0xd0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b208: B,
+ #[doc = "0xd1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b209: B,
+ #[doc = "0xd2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b210: B,
+ #[doc = "0xd3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b211: B,
+ #[doc = "0xd4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b212: B,
+ #[doc = "0xd5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b213: B,
+ #[doc = "0xd6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b214: B,
+ #[doc = "0xd7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b215: B,
+ #[doc = "0xd8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b216: B,
+ #[doc = "0xd9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b217: B,
+ #[doc = "0xda - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b218: B,
+ #[doc = "0xdb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b219: B,
+ #[doc = "0xdc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b220: B,
+ #[doc = "0xdd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b221: B,
+ #[doc = "0xde - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b222: B,
+ #[doc = "0xdf - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b223: B,
+ #[doc = "0xe0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b224: B,
+ #[doc = "0xe1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b225: B,
+ #[doc = "0xe2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b226: B,
+ #[doc = "0xe3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b227: B,
+ #[doc = "0xe4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b228: B,
+ #[doc = "0xe5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b229: B,
+ #[doc = "0xe6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b230: B,
+ #[doc = "0xe7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b231: B,
+ #[doc = "0xe8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b232: B,
+ #[doc = "0xe9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b233: B,
+ #[doc = "0xea - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b234: B,
+ #[doc = "0xeb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b235: B,
+ #[doc = "0xec - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b236: B,
+ #[doc = "0xed - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b237: B,
+ #[doc = "0xee - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b238: B,
+ #[doc = "0xef - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b239: B,
+ #[doc = "0xf0 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b240: B,
+ #[doc = "0xf1 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b241: B,
+ #[doc = "0xf2 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b242: B,
+ #[doc = "0xf3 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b243: B,
+ #[doc = "0xf4 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b244: B,
+ #[doc = "0xf5 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b245: B,
+ #[doc = "0xf6 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b246: B,
+ #[doc = "0xf7 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b247: B,
+ #[doc = "0xf8 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b248: B,
+ #[doc = "0xf9 - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b249: B,
+ #[doc = "0xfa - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b250: B,
+ #[doc = "0xfb - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b251: B,
+ #[doc = "0xfc - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b252: B,
+ #[doc = "0xfd - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b253: B,
+ #[doc = "0xfe - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b254: B,
+ #[doc = "0xff - Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31"] pub b255: B,
_reserved0: [u8; 3840usize],
#[doc = "0x1000 - Word pin registers port 0 to 5"] pub w0: W,
#[doc = "0x1004 - Word pin registers port 0 to 5"] pub w1: W,
@@ -311814,8 +298336,7 @@ pub mod gpio_port {
pub fn bits(&self) -> u8 {
self.bits
}
- #[doc = "Bit 0 - Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." ] # [ inline ( always ) ]
pub fn pbyte(&self) -> PBYTER {
let bits = {
const MASK: bool = true;
@@ -311837,8 +298358,7 @@ pub mod gpio_port {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." ] # [ inline ( always ) ]
pub fn pbyte(&mut self) -> _PBYTEW {
_PBYTEW { w: self }
}
@@ -311926,8 +298446,7 @@ pub mod gpio_port {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." ] # [ inline ( always ) ]
pub fn pword(&self) -> PWORDR {
let bits = {
const MASK: u32 = 4294967295;
@@ -311949,8 +298468,7 @@ pub mod gpio_port {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." ] # [ inline ( always ) ]
pub fn pword(&mut self) -> _PWORDW {
_PWORDW { w: self }
}
@@ -313420,8 +299938,7 @@ pub mod gpio_port {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp0(&self) -> DIRP0R {
let bits = {
const MASK: bool = true;
@@ -313430,8 +299947,7 @@ pub mod gpio_port {
};
DIRP0R { bits }
}
- #[doc = "Bit 1 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp1(&self) -> DIRP1R {
let bits = {
const MASK: bool = true;
@@ -313440,8 +299956,7 @@ pub mod gpio_port {
};
DIRP1R { bits }
}
- #[doc = "Bit 2 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp2(&self) -> DIRP2R {
let bits = {
const MASK: bool = true;
@@ -313450,8 +299965,7 @@ pub mod gpio_port {
};
DIRP2R { bits }
}
- #[doc = "Bit 3 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp3(&self) -> DIRP3R {
let bits = {
const MASK: bool = true;
@@ -313460,8 +299974,7 @@ pub mod gpio_port {
};
DIRP3R { bits }
}
- #[doc = "Bit 4 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp4(&self) -> DIRP4R {
let bits = {
const MASK: bool = true;
@@ -313470,8 +299983,7 @@ pub mod gpio_port {
};
DIRP4R { bits }
}
- #[doc = "Bit 5 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp5(&self) -> DIRP5R {
let bits = {
const MASK: bool = true;
@@ -313480,8 +299992,7 @@ pub mod gpio_port {
};
DIRP5R { bits }
}
- #[doc = "Bit 6 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp6(&self) -> DIRP6R {
let bits = {
const MASK: bool = true;
@@ -313490,8 +300001,7 @@ pub mod gpio_port {
};
DIRP6R { bits }
}
- #[doc = "Bit 7 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp7(&self) -> DIRP7R {
let bits = {
const MASK: bool = true;
@@ -313500,8 +300010,7 @@ pub mod gpio_port {
};
DIRP7R { bits }
}
- #[doc = "Bit 8 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp8(&self) -> DIRP8R {
let bits = {
const MASK: bool = true;
@@ -313510,8 +300019,7 @@ pub mod gpio_port {
};
DIRP8R { bits }
}
- #[doc = "Bit 9 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp9(&self) -> DIRP9R {
let bits = {
const MASK: bool = true;
@@ -313520,8 +300028,7 @@ pub mod gpio_port {
};
DIRP9R { bits }
}
- #[doc = "Bit 10 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp10(&self) -> DIRP10R {
let bits = {
const MASK: bool = true;
@@ -313530,8 +300037,7 @@ pub mod gpio_port {
};
DIRP10R { bits }
}
- #[doc = "Bit 11 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp11(&self) -> DIRP11R {
let bits = {
const MASK: bool = true;
@@ -313540,8 +300046,7 @@ pub mod gpio_port {
};
DIRP11R { bits }
}
- #[doc = "Bit 12 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp12(&self) -> DIRP12R {
let bits = {
const MASK: bool = true;
@@ -313550,8 +300055,7 @@ pub mod gpio_port {
};
DIRP12R { bits }
}
- #[doc = "Bit 13 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp13(&self) -> DIRP13R {
let bits = {
const MASK: bool = true;
@@ -313560,8 +300064,7 @@ pub mod gpio_port {
};
DIRP13R { bits }
}
- #[doc = "Bit 14 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp14(&self) -> DIRP14R {
let bits = {
const MASK: bool = true;
@@ -313570,8 +300073,7 @@ pub mod gpio_port {
};
DIRP14R { bits }
}
- #[doc = "Bit 15 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp15(&self) -> DIRP15R {
let bits = {
const MASK: bool = true;
@@ -313580,8 +300082,7 @@ pub mod gpio_port {
};
DIRP15R { bits }
}
- #[doc = "Bit 16 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp16(&self) -> DIRP16R {
let bits = {
const MASK: bool = true;
@@ -313590,8 +300091,7 @@ pub mod gpio_port {
};
DIRP16R { bits }
}
- #[doc = "Bit 17 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp17(&self) -> DIRP17R {
let bits = {
const MASK: bool = true;
@@ -313600,8 +300100,7 @@ pub mod gpio_port {
};
DIRP17R { bits }
}
- #[doc = "Bit 18 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp18(&self) -> DIRP18R {
let bits = {
const MASK: bool = true;
@@ -313610,8 +300109,7 @@ pub mod gpio_port {
};
DIRP18R { bits }
}
- #[doc = "Bit 19 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp19(&self) -> DIRP19R {
let bits = {
const MASK: bool = true;
@@ -313620,8 +300118,7 @@ pub mod gpio_port {
};
DIRP19R { bits }
}
- #[doc = "Bit 20 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp20(&self) -> DIRP20R {
let bits = {
const MASK: bool = true;
@@ -313630,8 +300127,7 @@ pub mod gpio_port {
};
DIRP20R { bits }
}
- #[doc = "Bit 21 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp21(&self) -> DIRP21R {
let bits = {
const MASK: bool = true;
@@ -313640,8 +300136,7 @@ pub mod gpio_port {
};
DIRP21R { bits }
}
- #[doc = "Bit 22 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp22(&self) -> DIRP22R {
let bits = {
const MASK: bool = true;
@@ -313650,8 +300145,7 @@ pub mod gpio_port {
};
DIRP22R { bits }
}
- #[doc = "Bit 23 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp23(&self) -> DIRP23R {
let bits = {
const MASK: bool = true;
@@ -313660,8 +300154,7 @@ pub mod gpio_port {
};
DIRP23R { bits }
}
- #[doc = "Bit 24 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp24(&self) -> DIRP24R {
let bits = {
const MASK: bool = true;
@@ -313670,8 +300163,7 @@ pub mod gpio_port {
};
DIRP24R { bits }
}
- #[doc = "Bit 25 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp25(&self) -> DIRP25R {
let bits = {
const MASK: bool = true;
@@ -313680,8 +300172,7 @@ pub mod gpio_port {
};
DIRP25R { bits }
}
- #[doc = "Bit 26 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp26(&self) -> DIRP26R {
let bits = {
const MASK: bool = true;
@@ -313690,8 +300181,7 @@ pub mod gpio_port {
};
DIRP26R { bits }
}
- #[doc = "Bit 27 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp27(&self) -> DIRP27R {
let bits = {
const MASK: bool = true;
@@ -313700,8 +300190,7 @@ pub mod gpio_port {
};
DIRP27R { bits }
}
- #[doc = "Bit 28 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp28(&self) -> DIRP28R {
let bits = {
const MASK: bool = true;
@@ -313710,8 +300199,7 @@ pub mod gpio_port {
};
DIRP28R { bits }
}
- #[doc = "Bit 29 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp29(&self) -> DIRP29R {
let bits = {
const MASK: bool = true;
@@ -313720,8 +300208,7 @@ pub mod gpio_port {
};
DIRP29R { bits }
}
- #[doc = "Bit 30 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp30(&self) -> DIRP30R {
let bits = {
const MASK: bool = true;
@@ -313730,8 +300217,7 @@ pub mod gpio_port {
};
DIRP30R { bits }
}
- #[doc = "Bit 31 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp31(&self) -> DIRP31R {
let bits = {
const MASK: bool = true;
@@ -313753,163 +300239,131 @@ pub mod gpio_port {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp0(&mut self) -> _DIRP0W {
_DIRP0W { w: self }
}
- #[doc = "Bit 1 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp1(&mut self) -> _DIRP1W {
_DIRP1W { w: self }
}
- #[doc = "Bit 2 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp2(&mut self) -> _DIRP2W {
_DIRP2W { w: self }
}
- #[doc = "Bit 3 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp3(&mut self) -> _DIRP3W {
_DIRP3W { w: self }
}
- #[doc = "Bit 4 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp4(&mut self) -> _DIRP4W {
_DIRP4W { w: self }
}
- #[doc = "Bit 5 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp5(&mut self) -> _DIRP5W {
_DIRP5W { w: self }
}
- #[doc = "Bit 6 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp6(&mut self) -> _DIRP6W {
_DIRP6W { w: self }
}
- #[doc = "Bit 7 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp7(&mut self) -> _DIRP7W {
_DIRP7W { w: self }
}
- #[doc = "Bit 8 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp8(&mut self) -> _DIRP8W {
_DIRP8W { w: self }
}
- #[doc = "Bit 9 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp9(&mut self) -> _DIRP9W {
_DIRP9W { w: self }
}
- #[doc = "Bit 10 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp10(&mut self) -> _DIRP10W {
_DIRP10W { w: self }
}
- #[doc = "Bit 11 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp11(&mut self) -> _DIRP11W {
_DIRP11W { w: self }
}
- #[doc = "Bit 12 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp12(&mut self) -> _DIRP12W {
_DIRP12W { w: self }
}
- #[doc = "Bit 13 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp13(&mut self) -> _DIRP13W {
_DIRP13W { w: self }
}
- #[doc = "Bit 14 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp14(&mut self) -> _DIRP14W {
_DIRP14W { w: self }
}
- #[doc = "Bit 15 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp15(&mut self) -> _DIRP15W {
_DIRP15W { w: self }
}
- #[doc = "Bit 16 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp16(&mut self) -> _DIRP16W {
_DIRP16W { w: self }
}
- #[doc = "Bit 17 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp17(&mut self) -> _DIRP17W {
_DIRP17W { w: self }
}
- #[doc = "Bit 18 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp18(&mut self) -> _DIRP18W {
_DIRP18W { w: self }
}
- #[doc = "Bit 19 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp19(&mut self) -> _DIRP19W {
_DIRP19W { w: self }
}
- #[doc = "Bit 20 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp20(&mut self) -> _DIRP20W {
_DIRP20W { w: self }
}
- #[doc = "Bit 21 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp21(&mut self) -> _DIRP21W {
_DIRP21W { w: self }
}
- #[doc = "Bit 22 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp22(&mut self) -> _DIRP22W {
_DIRP22W { w: self }
}
- #[doc = "Bit 23 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp23(&mut self) -> _DIRP23W {
_DIRP23W { w: self }
}
- #[doc = "Bit 24 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp24(&mut self) -> _DIRP24W {
_DIRP24W { w: self }
}
- #[doc = "Bit 25 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp25(&mut self) -> _DIRP25W {
_DIRP25W { w: self }
}
- #[doc = "Bit 26 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp26(&mut self) -> _DIRP26W {
_DIRP26W { w: self }
}
- #[doc = "Bit 27 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp27(&mut self) -> _DIRP27W {
_DIRP27W { w: self }
}
- #[doc = "Bit 28 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp28(&mut self) -> _DIRP28W {
_DIRP28W { w: self }
}
- #[doc = "Bit 29 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp29(&mut self) -> _DIRP29W {
_DIRP29W { w: self }
}
- #[doc = "Bit 30 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp30(&mut self) -> _DIRP30W {
_DIRP30W { w: self }
}
- #[doc = "Bit 31 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." ] # [ inline ( always ) ]
pub fn dirp31(&mut self) -> _DIRP31W {
_DIRP31W { w: self }
}
@@ -315379,8 +301833,7 @@ pub mod gpio_port {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp0(&self) -> MASKP0R {
let bits = {
const MASK: bool = true;
@@ -315389,8 +301842,7 @@ pub mod gpio_port {
};
MASKP0R { bits }
}
- #[doc = "Bit 1 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp1(&self) -> MASKP1R {
let bits = {
const MASK: bool = true;
@@ -315399,8 +301851,7 @@ pub mod gpio_port {
};
MASKP1R { bits }
}
- #[doc = "Bit 2 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp2(&self) -> MASKP2R {
let bits = {
const MASK: bool = true;
@@ -315409,8 +301860,7 @@ pub mod gpio_port {
};
MASKP2R { bits }
}
- #[doc = "Bit 3 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp3(&self) -> MASKP3R {
let bits = {
const MASK: bool = true;
@@ -315419,8 +301869,7 @@ pub mod gpio_port {
};
MASKP3R { bits }
}
- #[doc = "Bit 4 - Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp4(&self) -> MASKP4R {
let bits = {
const MASK: bool = true;
@@ -315429,8 +301878,7 @@ pub mod gpio_port {
};
MASKP4R { bits }
}
- #[doc = "Bit 5 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp5(&self) -> MASKP5R {
let bits = {
const MASK: bool = true;
@@ -315439,8 +301887,7 @@ pub mod gpio_port {
};
MASKP5R { bits }
}
- #[doc = "Bit 6 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp6(&self) -> MASKP6R {
let bits = {
const MASK: bool = true;
@@ -315449,8 +301896,7 @@ pub mod gpio_port {
};
MASKP6R { bits }
}
- #[doc = "Bit 7 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp7(&self) -> MASKP7R {
let bits = {
const MASK: bool = true;
@@ -315459,8 +301905,7 @@ pub mod gpio_port {
};
MASKP7R { bits }
}
- #[doc = "Bit 8 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp8(&self) -> MASKP8R {
let bits = {
const MASK: bool = true;
@@ -315469,8 +301914,7 @@ pub mod gpio_port {
};
MASKP8R { bits }
}
- #[doc = "Bit 9 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp9(&self) -> MASKP9R {
let bits = {
const MASK: bool = true;
@@ -315479,8 +301923,7 @@ pub mod gpio_port {
};
MASKP9R { bits }
}
- #[doc = "Bit 10 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp10(&self) -> MASKP10R {
let bits = {
const MASK: bool = true;
@@ -315489,8 +301932,7 @@ pub mod gpio_port {
};
MASKP10R { bits }
}
- #[doc = "Bit 11 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp11(&self) -> MASKP11R {
let bits = {
const MASK: bool = true;
@@ -315499,8 +301941,7 @@ pub mod gpio_port {
};
MASKP11R { bits }
}
- #[doc = "Bit 12 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp12(&self) -> MASKP12R {
let bits = {
const MASK: bool = true;
@@ -315509,8 +301950,7 @@ pub mod gpio_port {
};
MASKP12R { bits }
}
- #[doc = "Bit 13 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp13(&self) -> MASKP13R {
let bits = {
const MASK: bool = true;
@@ -315519,8 +301959,7 @@ pub mod gpio_port {
};
MASKP13R { bits }
}
- #[doc = "Bit 14 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp14(&self) -> MASKP14R {
let bits = {
const MASK: bool = true;
@@ -315529,8 +301968,7 @@ pub mod gpio_port {
};
MASKP14R { bits }
}
- #[doc = "Bit 15 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp15(&self) -> MASKP15R {
let bits = {
const MASK: bool = true;
@@ -315539,8 +301977,7 @@ pub mod gpio_port {
};
MASKP15R { bits }
}
- #[doc = "Bit 16 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp16(&self) -> MASKP16R {
let bits = {
const MASK: bool = true;
@@ -315549,8 +301986,7 @@ pub mod gpio_port {
};
MASKP16R { bits }
}
- #[doc = "Bit 17 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp17(&self) -> MASKP17R {
let bits = {
const MASK: bool = true;
@@ -315559,8 +301995,7 @@ pub mod gpio_port {
};
MASKP17R { bits }
}
- #[doc = "Bit 18 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp18(&self) -> MASKP18R {
let bits = {
const MASK: bool = true;
@@ -315569,8 +302004,7 @@ pub mod gpio_port {
};
MASKP18R { bits }
}
- #[doc = "Bit 19 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp19(&self) -> MASKP19R {
let bits = {
const MASK: bool = true;
@@ -315579,8 +302013,7 @@ pub mod gpio_port {
};
MASKP19R { bits }
}
- #[doc = "Bit 20 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp20(&self) -> MASKP20R {
let bits = {
const MASK: bool = true;
@@ -315589,8 +302022,7 @@ pub mod gpio_port {
};
MASKP20R { bits }
}
- #[doc = "Bit 21 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp21(&self) -> MASKP21R {
let bits = {
const MASK: bool = true;
@@ -315599,8 +302031,7 @@ pub mod gpio_port {
};
MASKP21R { bits }
}
- #[doc = "Bit 22 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp22(&self) -> MASKP22R {
let bits = {
const MASK: bool = true;
@@ -315609,8 +302040,7 @@ pub mod gpio_port {
};
MASKP22R { bits }
}
- #[doc = "Bit 23 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp23(&self) -> MASKP23R {
let bits = {
const MASK: bool = true;
@@ -315619,8 +302049,7 @@ pub mod gpio_port {
};
MASKP23R { bits }
}
- #[doc = "Bit 24 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp24(&self) -> MASKP24R {
let bits = {
const MASK: bool = true;
@@ -315629,8 +302058,7 @@ pub mod gpio_port {
};
MASKP24R { bits }
}
- #[doc = "Bit 25 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp25(&self) -> MASKP25R {
let bits = {
const MASK: bool = true;
@@ -315639,8 +302067,7 @@ pub mod gpio_port {
};
MASKP25R { bits }
}
- #[doc = "Bit 26 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp26(&self) -> MASKP26R {
let bits = {
const MASK: bool = true;
@@ -315649,8 +302076,7 @@ pub mod gpio_port {
};
MASKP26R { bits }
}
- #[doc = "Bit 27 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp27(&self) -> MASKP27R {
let bits = {
const MASK: bool = true;
@@ -315659,8 +302085,7 @@ pub mod gpio_port {
};
MASKP27R { bits }
}
- #[doc = "Bit 28 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp28(&self) -> MASKP28R {
let bits = {
const MASK: bool = true;
@@ -315669,8 +302094,7 @@ pub mod gpio_port {
};
MASKP28R { bits }
}
- #[doc = "Bit 29 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp29(&self) -> MASKP29R {
let bits = {
const MASK: bool = true;
@@ -315679,8 +302103,7 @@ pub mod gpio_port {
};
MASKP29R { bits }
}
- #[doc = "Bit 30 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp30(&self) -> MASKP30R {
let bits = {
const MASK: bool = true;
@@ -315689,8 +302112,7 @@ pub mod gpio_port {
};
MASKP30R { bits }
}
- #[doc = "Bit 31 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp31(&self) -> MASKP31R {
let bits = {
const MASK: bool = true;
@@ -315712,163 +302134,131 @@ pub mod gpio_port {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp0(&mut self) -> _MASKP0W {
_MASKP0W { w: self }
}
- #[doc = "Bit 1 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp1(&mut self) -> _MASKP1W {
_MASKP1W { w: self }
}
- #[doc = "Bit 2 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp2(&mut self) -> _MASKP2W {
_MASKP2W { w: self }
}
- #[doc = "Bit 3 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp3(&mut self) -> _MASKP3W {
_MASKP3W { w: self }
}
- #[doc = "Bit 4 - Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp4(&mut self) -> _MASKP4W {
_MASKP4W { w: self }
}
- #[doc = "Bit 5 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp5(&mut self) -> _MASKP5W {
_MASKP5W { w: self }
}
- #[doc = "Bit 6 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp6(&mut self) -> _MASKP6W {
_MASKP6W { w: self }
}
- #[doc = "Bit 7 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp7(&mut self) -> _MASKP7W {
_MASKP7W { w: self }
}
- #[doc = "Bit 8 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp8(&mut self) -> _MASKP8W {
_MASKP8W { w: self }
}
- #[doc = "Bit 9 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp9(&mut self) -> _MASKP9W {
_MASKP9W { w: self }
}
- #[doc = "Bit 10 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp10(&mut self) -> _MASKP10W {
_MASKP10W { w: self }
}
- #[doc = "Bit 11 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp11(&mut self) -> _MASKP11W {
_MASKP11W { w: self }
}
- #[doc = "Bit 12 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp12(&mut self) -> _MASKP12W {
_MASKP12W { w: self }
}
- #[doc = "Bit 13 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp13(&mut self) -> _MASKP13W {
_MASKP13W { w: self }
}
- #[doc = "Bit 14 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp14(&mut self) -> _MASKP14W {
_MASKP14W { w: self }
}
- #[doc = "Bit 15 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp15(&mut self) -> _MASKP15W {
_MASKP15W { w: self }
}
- #[doc = "Bit 16 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp16(&mut self) -> _MASKP16W {
_MASKP16W { w: self }
}
- #[doc = "Bit 17 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp17(&mut self) -> _MASKP17W {
_MASKP17W { w: self }
}
- #[doc = "Bit 18 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp18(&mut self) -> _MASKP18W {
_MASKP18W { w: self }
}
- #[doc = "Bit 19 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp19(&mut self) -> _MASKP19W {
_MASKP19W { w: self }
}
- #[doc = "Bit 20 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp20(&mut self) -> _MASKP20W {
_MASKP20W { w: self }
}
- #[doc = "Bit 21 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp21(&mut self) -> _MASKP21W {
_MASKP21W { w: self }
}
- #[doc = "Bit 22 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp22(&mut self) -> _MASKP22W {
_MASKP22W { w: self }
}
- #[doc = "Bit 23 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp23(&mut self) -> _MASKP23W {
_MASKP23W { w: self }
}
- #[doc = "Bit 24 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp24(&mut self) -> _MASKP24W {
_MASKP24W { w: self }
}
- #[doc = "Bit 25 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp25(&mut self) -> _MASKP25W {
_MASKP25W { w: self }
}
- #[doc = "Bit 26 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp26(&mut self) -> _MASKP26W {
_MASKP26W { w: self }
}
- #[doc = "Bit 27 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp27(&mut self) -> _MASKP27W {
_MASKP27W { w: self }
}
- #[doc = "Bit 28 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp28(&mut self) -> _MASKP28W {
_MASKP28W { w: self }
}
- #[doc = "Bit 29 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp29(&mut self) -> _MASKP29W {
_MASKP29W { w: self }
}
- #[doc = "Bit 30 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp30(&mut self) -> _MASKP30W {
_MASKP30W { w: self }
}
- #[doc = "Bit 31 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." ] # [ inline ( always ) ]
pub fn maskp31(&mut self) -> _MASKP31W {
_MASKP31W { w: self }
}
@@ -317338,8 +303728,7 @@ pub mod gpio_port {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port0(&self) -> PORT0R {
let bits = {
const MASK: bool = true;
@@ -317348,8 +303737,7 @@ pub mod gpio_port {
};
PORT0R { bits }
}
- #[doc = "Bit 1 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port1(&self) -> PORT1R {
let bits = {
const MASK: bool = true;
@@ -317358,8 +303746,7 @@ pub mod gpio_port {
};
PORT1R { bits }
}
- #[doc = "Bit 2 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port2(&self) -> PORT2R {
let bits = {
const MASK: bool = true;
@@ -317368,8 +303755,7 @@ pub mod gpio_port {
};
PORT2R { bits }
}
- #[doc = "Bit 3 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port3(&self) -> PORT3R {
let bits = {
const MASK: bool = true;
@@ -317378,8 +303764,7 @@ pub mod gpio_port {
};
PORT3R { bits }
}
- #[doc = "Bit 4 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port4(&self) -> PORT4R {
let bits = {
const MASK: bool = true;
@@ -317388,8 +303773,7 @@ pub mod gpio_port {
};
PORT4R { bits }
}
- #[doc = "Bit 5 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port5(&self) -> PORT5R {
let bits = {
const MASK: bool = true;
@@ -317398,8 +303782,7 @@ pub mod gpio_port {
};
PORT5R { bits }
}
- #[doc = "Bit 6 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port6(&self) -> PORT6R {
let bits = {
const MASK: bool = true;
@@ -317408,8 +303791,7 @@ pub mod gpio_port {
};
PORT6R { bits }
}
- #[doc = "Bit 7 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port7(&self) -> PORT7R {
let bits = {
const MASK: bool = true;
@@ -317418,8 +303800,7 @@ pub mod gpio_port {
};
PORT7R { bits }
}
- #[doc = "Bit 8 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port8(&self) -> PORT8R {
let bits = {
const MASK: bool = true;
@@ -317428,8 +303809,7 @@ pub mod gpio_port {
};
PORT8R { bits }
}
- #[doc = "Bit 9 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port9(&self) -> PORT9R {
let bits = {
const MASK: bool = true;
@@ -317438,8 +303818,7 @@ pub mod gpio_port {
};
PORT9R { bits }
}
- #[doc = "Bit 10 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port10(&self) -> PORT10R {
let bits = {
const MASK: bool = true;
@@ -317448,8 +303827,7 @@ pub mod gpio_port {
};
PORT10R { bits }
}
- #[doc = "Bit 11 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port11(&self) -> PORT11R {
let bits = {
const MASK: bool = true;
@@ -317458,8 +303836,7 @@ pub mod gpio_port {
};
PORT11R { bits }
}
- #[doc = "Bit 12 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port12(&self) -> PORT12R {
let bits = {
const MASK: bool = true;
@@ -317468,8 +303845,7 @@ pub mod gpio_port {
};
PORT12R { bits }
}
- #[doc = "Bit 13 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port13(&self) -> PORT13R {
let bits = {
const MASK: bool = true;
@@ -317478,8 +303854,7 @@ pub mod gpio_port {
};
PORT13R { bits }
}
- #[doc = "Bit 14 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port14(&self) -> PORT14R {
let bits = {
const MASK: bool = true;
@@ -317488,8 +303863,7 @@ pub mod gpio_port {
};
PORT14R { bits }
}
- #[doc = "Bit 15 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port15(&self) -> PORT15R {
let bits = {
const MASK: bool = true;
@@ -317498,8 +303872,7 @@ pub mod gpio_port {
};
PORT15R { bits }
}
- #[doc = "Bit 16 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port16(&self) -> PORT16R {
let bits = {
const MASK: bool = true;
@@ -317508,8 +303881,7 @@ pub mod gpio_port {
};
PORT16R { bits }
}
- #[doc = "Bit 17 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port17(&self) -> PORT17R {
let bits = {
const MASK: bool = true;
@@ -317518,8 +303890,7 @@ pub mod gpio_port {
};
PORT17R { bits }
}
- #[doc = "Bit 18 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port18(&self) -> PORT18R {
let bits = {
const MASK: bool = true;
@@ -317528,8 +303899,7 @@ pub mod gpio_port {
};
PORT18R { bits }
}
- #[doc = "Bit 19 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port19(&self) -> PORT19R {
let bits = {
const MASK: bool = true;
@@ -317538,8 +303908,7 @@ pub mod gpio_port {
};
PORT19R { bits }
}
- #[doc = "Bit 20 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port20(&self) -> PORT20R {
let bits = {
const MASK: bool = true;
@@ -317548,8 +303917,7 @@ pub mod gpio_port {
};
PORT20R { bits }
}
- #[doc = "Bit 21 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port21(&self) -> PORT21R {
let bits = {
const MASK: bool = true;
@@ -317558,8 +303926,7 @@ pub mod gpio_port {
};
PORT21R { bits }
}
- #[doc = "Bit 22 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port22(&self) -> PORT22R {
let bits = {
const MASK: bool = true;
@@ -317568,8 +303935,7 @@ pub mod gpio_port {
};
PORT22R { bits }
}
- #[doc = "Bit 23 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port23(&self) -> PORT23R {
let bits = {
const MASK: bool = true;
@@ -317578,8 +303944,7 @@ pub mod gpio_port {
};
PORT23R { bits }
}
- #[doc = "Bit 24 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port24(&self) -> PORT24R {
let bits = {
const MASK: bool = true;
@@ -317588,8 +303953,7 @@ pub mod gpio_port {
};
PORT24R { bits }
}
- #[doc = "Bit 25 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port25(&self) -> PORT25R {
let bits = {
const MASK: bool = true;
@@ -317598,8 +303962,7 @@ pub mod gpio_port {
};
PORT25R { bits }
}
- #[doc = "Bit 26 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port26(&self) -> PORT26R {
let bits = {
const MASK: bool = true;
@@ -317608,8 +303971,7 @@ pub mod gpio_port {
};
PORT26R { bits }
}
- #[doc = "Bit 27 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port27(&self) -> PORT27R {
let bits = {
const MASK: bool = true;
@@ -317618,8 +303980,7 @@ pub mod gpio_port {
};
PORT27R { bits }
}
- #[doc = "Bit 28 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port28(&self) -> PORT28R {
let bits = {
const MASK: bool = true;
@@ -317628,8 +303989,7 @@ pub mod gpio_port {
};
PORT28R { bits }
}
- #[doc = "Bit 29 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port29(&self) -> PORT29R {
let bits = {
const MASK: bool = true;
@@ -317638,8 +303998,7 @@ pub mod gpio_port {
};
PORT29R { bits }
}
- #[doc = "Bit 30 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port30(&self) -> PORT30R {
let bits = {
const MASK: bool = true;
@@ -317648,8 +304007,7 @@ pub mod gpio_port {
};
PORT30R { bits }
}
- #[doc = "Bit 31 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port31(&self) -> PORT31R {
let bits = {
const MASK: bool = true;
@@ -317671,163 +304029,131 @@ pub mod gpio_port {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port0(&mut self) -> _PORT0W {
_PORT0W { w: self }
}
- #[doc = "Bit 1 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port1(&mut self) -> _PORT1W {
_PORT1W { w: self }
}
- #[doc = "Bit 2 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port2(&mut self) -> _PORT2W {
_PORT2W { w: self }
}
- #[doc = "Bit 3 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port3(&mut self) -> _PORT3W {
_PORT3W { w: self }
}
- #[doc = "Bit 4 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port4(&mut self) -> _PORT4W {
_PORT4W { w: self }
}
- #[doc = "Bit 5 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port5(&mut self) -> _PORT5W {
_PORT5W { w: self }
}
- #[doc = "Bit 6 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port6(&mut self) -> _PORT6W {
_PORT6W { w: self }
}
- #[doc = "Bit 7 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port7(&mut self) -> _PORT7W {
_PORT7W { w: self }
}
- #[doc = "Bit 8 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port8(&mut self) -> _PORT8W {
_PORT8W { w: self }
}
- #[doc = "Bit 9 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port9(&mut self) -> _PORT9W {
_PORT9W { w: self }
}
- #[doc = "Bit 10 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port10(&mut self) -> _PORT10W {
_PORT10W { w: self }
}
- #[doc = "Bit 11 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port11(&mut self) -> _PORT11W {
_PORT11W { w: self }
}
- #[doc = "Bit 12 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port12(&mut self) -> _PORT12W {
_PORT12W { w: self }
}
- #[doc = "Bit 13 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port13(&mut self) -> _PORT13W {
_PORT13W { w: self }
}
- #[doc = "Bit 14 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port14(&mut self) -> _PORT14W {
_PORT14W { w: self }
}
- #[doc = "Bit 15 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port15(&mut self) -> _PORT15W {
_PORT15W { w: self }
}
- #[doc = "Bit 16 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port16(&mut self) -> _PORT16W {
_PORT16W { w: self }
}
- #[doc = "Bit 17 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port17(&mut self) -> _PORT17W {
_PORT17W { w: self }
}
- #[doc = "Bit 18 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port18(&mut self) -> _PORT18W {
_PORT18W { w: self }
}
- #[doc = "Bit 19 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port19(&mut self) -> _PORT19W {
_PORT19W { w: self }
}
- #[doc = "Bit 20 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port20(&mut self) -> _PORT20W {
_PORT20W { w: self }
}
- #[doc = "Bit 21 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port21(&mut self) -> _PORT21W {
_PORT21W { w: self }
}
- #[doc = "Bit 22 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port22(&mut self) -> _PORT22W {
_PORT22W { w: self }
}
- #[doc = "Bit 23 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port23(&mut self) -> _PORT23W {
_PORT23W { w: self }
}
- #[doc = "Bit 24 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port24(&mut self) -> _PORT24W {
_PORT24W { w: self }
}
- #[doc = "Bit 25 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port25(&mut self) -> _PORT25W {
_PORT25W { w: self }
}
- #[doc = "Bit 26 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port26(&mut self) -> _PORT26W {
_PORT26W { w: self }
}
- #[doc = "Bit 27 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port27(&mut self) -> _PORT27W {
_PORT27W { w: self }
}
- #[doc = "Bit 28 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port28(&mut self) -> _PORT28W {
_PORT28W { w: self }
}
- #[doc = "Bit 29 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port29(&mut self) -> _PORT29W {
_PORT29W { w: self }
}
- #[doc = "Bit 30 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port30(&mut self) -> _PORT30W {
_PORT30W { w: self }
}
- #[doc = "Bit 31 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." ] # [ inline ( always ) ]
pub fn port31(&mut self) -> _PORT31W {
_PORT31W { w: self }
}
@@ -319297,8 +305623,7 @@ pub mod gpio_port {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp0(&self) -> MPORTP0R {
let bits = {
const MASK: bool = true;
@@ -319307,8 +305632,7 @@ pub mod gpio_port {
};
MPORTP0R { bits }
}
- #[doc = "Bit 1 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp1(&self) -> MPORTP1R {
let bits = {
const MASK: bool = true;
@@ -319317,8 +305641,7 @@ pub mod gpio_port {
};
MPORTP1R { bits }
}
- #[doc = "Bit 2 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp2(&self) -> MPORTP2R {
let bits = {
const MASK: bool = true;
@@ -319327,8 +305650,7 @@ pub mod gpio_port {
};
MPORTP2R { bits }
}
- #[doc = "Bit 3 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp3(&self) -> MPORTP3R {
let bits = {
const MASK: bool = true;
@@ -319337,8 +305659,7 @@ pub mod gpio_port {
};
MPORTP3R { bits }
}
- #[doc = "Bit 4 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp4(&self) -> MPORTP4R {
let bits = {
const MASK: bool = true;
@@ -319347,8 +305668,7 @@ pub mod gpio_port {
};
MPORTP4R { bits }
}
- #[doc = "Bit 5 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp5(&self) -> MPORTP5R {
let bits = {
const MASK: bool = true;
@@ -319357,8 +305677,7 @@ pub mod gpio_port {
};
MPORTP5R { bits }
}
- #[doc = "Bit 6 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp6(&self) -> MPORTP6R {
let bits = {
const MASK: bool = true;
@@ -319367,8 +305686,7 @@ pub mod gpio_port {
};
MPORTP6R { bits }
}
- #[doc = "Bit 7 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp7(&self) -> MPORTP7R {
let bits = {
const MASK: bool = true;
@@ -319377,8 +305695,7 @@ pub mod gpio_port {
};
MPORTP7R { bits }
}
- #[doc = "Bit 8 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp8(&self) -> MPORTP8R {
let bits = {
const MASK: bool = true;
@@ -319387,8 +305704,7 @@ pub mod gpio_port {
};
MPORTP8R { bits }
}
- #[doc = "Bit 9 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp9(&self) -> MPORTP9R {
let bits = {
const MASK: bool = true;
@@ -319397,8 +305713,7 @@ pub mod gpio_port {
};
MPORTP9R { bits }
}
- #[doc = "Bit 10 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp10(&self) -> MPORTP10R {
let bits = {
const MASK: bool = true;
@@ -319407,8 +305722,7 @@ pub mod gpio_port {
};
MPORTP10R { bits }
}
- #[doc = "Bit 11 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp11(&self) -> MPORTP11R {
let bits = {
const MASK: bool = true;
@@ -319417,8 +305731,7 @@ pub mod gpio_port {
};
MPORTP11R { bits }
}
- #[doc = "Bit 12 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp12(&self) -> MPORTP12R {
let bits = {
const MASK: bool = true;
@@ -319427,8 +305740,7 @@ pub mod gpio_port {
};
MPORTP12R { bits }
}
- #[doc = "Bit 13 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp13(&self) -> MPORTP13R {
let bits = {
const MASK: bool = true;
@@ -319437,8 +305749,7 @@ pub mod gpio_port {
};
MPORTP13R { bits }
}
- #[doc = "Bit 14 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp14(&self) -> MPORTP14R {
let bits = {
const MASK: bool = true;
@@ -319447,8 +305758,7 @@ pub mod gpio_port {
};
MPORTP14R { bits }
}
- #[doc = "Bit 15 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp15(&self) -> MPORTP15R {
let bits = {
const MASK: bool = true;
@@ -319457,8 +305767,7 @@ pub mod gpio_port {
};
MPORTP15R { bits }
}
- #[doc = "Bit 16 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp16(&self) -> MPORTP16R {
let bits = {
const MASK: bool = true;
@@ -319467,8 +305776,7 @@ pub mod gpio_port {
};
MPORTP16R { bits }
}
- #[doc = "Bit 17 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp17(&self) -> MPORTP17R {
let bits = {
const MASK: bool = true;
@@ -319477,8 +305785,7 @@ pub mod gpio_port {
};
MPORTP17R { bits }
}
- #[doc = "Bit 18 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp18(&self) -> MPORTP18R {
let bits = {
const MASK: bool = true;
@@ -319487,8 +305794,7 @@ pub mod gpio_port {
};
MPORTP18R { bits }
}
- #[doc = "Bit 19 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp19(&self) -> MPORTP19R {
let bits = {
const MASK: bool = true;
@@ -319497,8 +305803,7 @@ pub mod gpio_port {
};
MPORTP19R { bits }
}
- #[doc = "Bit 20 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp20(&self) -> MPORTP20R {
let bits = {
const MASK: bool = true;
@@ -319507,8 +305812,7 @@ pub mod gpio_port {
};
MPORTP20R { bits }
}
- #[doc = "Bit 21 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp21(&self) -> MPORTP21R {
let bits = {
const MASK: bool = true;
@@ -319517,8 +305821,7 @@ pub mod gpio_port {
};
MPORTP21R { bits }
}
- #[doc = "Bit 22 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp22(&self) -> MPORTP22R {
let bits = {
const MASK: bool = true;
@@ -319527,8 +305830,7 @@ pub mod gpio_port {
};
MPORTP22R { bits }
}
- #[doc = "Bit 23 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp23(&self) -> MPORTP23R {
let bits = {
const MASK: bool = true;
@@ -319537,8 +305839,7 @@ pub mod gpio_port {
};
MPORTP23R { bits }
}
- #[doc = "Bit 24 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp24(&self) -> MPORTP24R {
let bits = {
const MASK: bool = true;
@@ -319547,8 +305848,7 @@ pub mod gpio_port {
};
MPORTP24R { bits }
}
- #[doc = "Bit 25 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp25(&self) -> MPORTP25R {
let bits = {
const MASK: bool = true;
@@ -319557,8 +305857,7 @@ pub mod gpio_port {
};
MPORTP25R { bits }
}
- #[doc = "Bit 26 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp26(&self) -> MPORTP26R {
let bits = {
const MASK: bool = true;
@@ -319567,8 +305866,7 @@ pub mod gpio_port {
};
MPORTP26R { bits }
}
- #[doc = "Bit 27 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp27(&self) -> MPORTP27R {
let bits = {
const MASK: bool = true;
@@ -319577,8 +305875,7 @@ pub mod gpio_port {
};
MPORTP27R { bits }
}
- #[doc = "Bit 28 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp28(&self) -> MPORTP28R {
let bits = {
const MASK: bool = true;
@@ -319587,8 +305884,7 @@ pub mod gpio_port {
};
MPORTP28R { bits }
}
- #[doc = "Bit 29 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp29(&self) -> MPORTP29R {
let bits = {
const MASK: bool = true;
@@ -319597,8 +305893,7 @@ pub mod gpio_port {
};
MPORTP29R { bits }
}
- #[doc = "Bit 30 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp30(&self) -> MPORTP30R {
let bits = {
const MASK: bool = true;
@@ -319607,8 +305902,7 @@ pub mod gpio_port {
};
MPORTP30R { bits }
}
- #[doc = "Bit 31 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp31(&self) -> MPORTP31R {
let bits = {
const MASK: bool = true;
@@ -319630,163 +305924,131 @@ pub mod gpio_port {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp0(&mut self) -> _MPORTP0W {
_MPORTP0W { w: self }
}
- #[doc = "Bit 1 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp1(&mut self) -> _MPORTP1W {
_MPORTP1W { w: self }
}
- #[doc = "Bit 2 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp2(&mut self) -> _MPORTP2W {
_MPORTP2W { w: self }
}
- #[doc = "Bit 3 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp3(&mut self) -> _MPORTP3W {
_MPORTP3W { w: self }
}
- #[doc = "Bit 4 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp4(&mut self) -> _MPORTP4W {
_MPORTP4W { w: self }
}
- #[doc = "Bit 5 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp5(&mut self) -> _MPORTP5W {
_MPORTP5W { w: self }
}
- #[doc = "Bit 6 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp6(&mut self) -> _MPORTP6W {
_MPORTP6W { w: self }
}
- #[doc = "Bit 7 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp7(&mut self) -> _MPORTP7W {
_MPORTP7W { w: self }
}
- #[doc = "Bit 8 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp8(&mut self) -> _MPORTP8W {
_MPORTP8W { w: self }
}
- #[doc = "Bit 9 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp9(&mut self) -> _MPORTP9W {
_MPORTP9W { w: self }
}
- #[doc = "Bit 10 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp10(&mut self) -> _MPORTP10W {
_MPORTP10W { w: self }
}
- #[doc = "Bit 11 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp11(&mut self) -> _MPORTP11W {
_MPORTP11W { w: self }
}
- #[doc = "Bit 12 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp12(&mut self) -> _MPORTP12W {
_MPORTP12W { w: self }
}
- #[doc = "Bit 13 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp13(&mut self) -> _MPORTP13W {
_MPORTP13W { w: self }
}
- #[doc = "Bit 14 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp14(&mut self) -> _MPORTP14W {
_MPORTP14W { w: self }
}
- #[doc = "Bit 15 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp15(&mut self) -> _MPORTP15W {
_MPORTP15W { w: self }
}
- #[doc = "Bit 16 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp16(&mut self) -> _MPORTP16W {
_MPORTP16W { w: self }
}
- #[doc = "Bit 17 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp17(&mut self) -> _MPORTP17W {
_MPORTP17W { w: self }
}
- #[doc = "Bit 18 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp18(&mut self) -> _MPORTP18W {
_MPORTP18W { w: self }
}
- #[doc = "Bit 19 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp19(&mut self) -> _MPORTP19W {
_MPORTP19W { w: self }
}
- #[doc = "Bit 20 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp20(&mut self) -> _MPORTP20W {
_MPORTP20W { w: self }
}
- #[doc = "Bit 21 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp21(&mut self) -> _MPORTP21W {
_MPORTP21W { w: self }
}
- #[doc = "Bit 22 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp22(&mut self) -> _MPORTP22W {
_MPORTP22W { w: self }
}
- #[doc = "Bit 23 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp23(&mut self) -> _MPORTP23W {
_MPORTP23W { w: self }
}
- #[doc = "Bit 24 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp24(&mut self) -> _MPORTP24W {
_MPORTP24W { w: self }
}
- #[doc = "Bit 25 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp25(&mut self) -> _MPORTP25W {
_MPORTP25W { w: self }
}
- #[doc = "Bit 26 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp26(&mut self) -> _MPORTP26W {
_MPORTP26W { w: self }
}
- #[doc = "Bit 27 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp27(&mut self) -> _MPORTP27W {
_MPORTP27W { w: self }
}
- #[doc = "Bit 28 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp28(&mut self) -> _MPORTP28W {
_MPORTP28W { w: self }
}
- #[doc = "Bit 29 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp29(&mut self) -> _MPORTP29W {
_MPORTP29W { w: self }
}
- #[doc = "Bit 30 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp30(&mut self) -> _MPORTP30W {
_MPORTP30W { w: self }
}
- #[doc = "Bit 31 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." ] # [ inline ( always ) ]
pub fn mportp31(&mut self) -> _MPORTP31W {
_MPORTP31W { w: self }
}
@@ -321256,8 +307518,7 @@ pub mod gpio_port {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp0(&self) -> SETP0R {
let bits = {
const MASK: bool = true;
@@ -321266,8 +307527,7 @@ pub mod gpio_port {
};
SETP0R { bits }
}
- #[doc = "Bit 1 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp1(&self) -> SETP1R {
let bits = {
const MASK: bool = true;
@@ -321276,8 +307536,7 @@ pub mod gpio_port {
};
SETP1R { bits }
}
- #[doc = "Bit 2 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp2(&self) -> SETP2R {
let bits = {
const MASK: bool = true;
@@ -321286,8 +307545,7 @@ pub mod gpio_port {
};
SETP2R { bits }
}
- #[doc = "Bit 3 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp3(&self) -> SETP3R {
let bits = {
const MASK: bool = true;
@@ -321296,8 +307554,7 @@ pub mod gpio_port {
};
SETP3R { bits }
}
- #[doc = "Bit 4 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp4(&self) -> SETP4R {
let bits = {
const MASK: bool = true;
@@ -321306,8 +307563,7 @@ pub mod gpio_port {
};
SETP4R { bits }
}
- #[doc = "Bit 5 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp5(&self) -> SETP5R {
let bits = {
const MASK: bool = true;
@@ -321316,8 +307572,7 @@ pub mod gpio_port {
};
SETP5R { bits }
}
- #[doc = "Bit 6 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp6(&self) -> SETP6R {
let bits = {
const MASK: bool = true;
@@ -321326,8 +307581,7 @@ pub mod gpio_port {
};
SETP6R { bits }
}
- #[doc = "Bit 7 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp7(&self) -> SETP7R {
let bits = {
const MASK: bool = true;
@@ -321336,8 +307590,7 @@ pub mod gpio_port {
};
SETP7R { bits }
}
- #[doc = "Bit 8 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp8(&self) -> SETP8R {
let bits = {
const MASK: bool = true;
@@ -321346,8 +307599,7 @@ pub mod gpio_port {
};
SETP8R { bits }
}
- #[doc = "Bit 9 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp9(&self) -> SETP9R {
let bits = {
const MASK: bool = true;
@@ -321356,8 +307608,7 @@ pub mod gpio_port {
};
SETP9R { bits }
}
- #[doc = "Bit 10 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp10(&self) -> SETP10R {
let bits = {
const MASK: bool = true;
@@ -321366,8 +307617,7 @@ pub mod gpio_port {
};
SETP10R { bits }
}
- #[doc = "Bit 11 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp11(&self) -> SETP11R {
let bits = {
const MASK: bool = true;
@@ -321376,8 +307626,7 @@ pub mod gpio_port {
};
SETP11R { bits }
}
- #[doc = "Bit 12 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp12(&self) -> SETP12R {
let bits = {
const MASK: bool = true;
@@ -321386,8 +307635,7 @@ pub mod gpio_port {
};
SETP12R { bits }
}
- #[doc = "Bit 13 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp13(&self) -> SETP13R {
let bits = {
const MASK: bool = true;
@@ -321396,8 +307644,7 @@ pub mod gpio_port {
};
SETP13R { bits }
}
- #[doc = "Bit 14 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp14(&self) -> SETP14R {
let bits = {
const MASK: bool = true;
@@ -321406,8 +307653,7 @@ pub mod gpio_port {
};
SETP14R { bits }
}
- #[doc = "Bit 15 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp15(&self) -> SETP15R {
let bits = {
const MASK: bool = true;
@@ -321416,8 +307662,7 @@ pub mod gpio_port {
};
SETP15R { bits }
}
- #[doc = "Bit 16 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp16(&self) -> SETP16R {
let bits = {
const MASK: bool = true;
@@ -321426,8 +307671,7 @@ pub mod gpio_port {
};
SETP16R { bits }
}
- #[doc = "Bit 17 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp17(&self) -> SETP17R {
let bits = {
const MASK: bool = true;
@@ -321436,8 +307680,7 @@ pub mod gpio_port {
};
SETP17R { bits }
}
- #[doc = "Bit 18 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp18(&self) -> SETP18R {
let bits = {
const MASK: bool = true;
@@ -321446,8 +307689,7 @@ pub mod gpio_port {
};
SETP18R { bits }
}
- #[doc = "Bit 19 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp19(&self) -> SETP19R {
let bits = {
const MASK: bool = true;
@@ -321456,8 +307698,7 @@ pub mod gpio_port {
};
SETP19R { bits }
}
- #[doc = "Bit 20 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp20(&self) -> SETP20R {
let bits = {
const MASK: bool = true;
@@ -321466,8 +307707,7 @@ pub mod gpio_port {
};
SETP20R { bits }
}
- #[doc = "Bit 21 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp21(&self) -> SETP21R {
let bits = {
const MASK: bool = true;
@@ -321476,8 +307716,7 @@ pub mod gpio_port {
};
SETP21R { bits }
}
- #[doc = "Bit 22 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp22(&self) -> SETP22R {
let bits = {
const MASK: bool = true;
@@ -321486,8 +307725,7 @@ pub mod gpio_port {
};
SETP22R { bits }
}
- #[doc = "Bit 23 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp23(&self) -> SETP23R {
let bits = {
const MASK: bool = true;
@@ -321496,8 +307734,7 @@ pub mod gpio_port {
};
SETP23R { bits }
}
- #[doc = "Bit 24 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp24(&self) -> SETP24R {
let bits = {
const MASK: bool = true;
@@ -321506,8 +307743,7 @@ pub mod gpio_port {
};
SETP24R { bits }
}
- #[doc = "Bit 25 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp25(&self) -> SETP25R {
let bits = {
const MASK: bool = true;
@@ -321516,8 +307752,7 @@ pub mod gpio_port {
};
SETP25R { bits }
}
- #[doc = "Bit 26 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp26(&self) -> SETP26R {
let bits = {
const MASK: bool = true;
@@ -321526,8 +307761,7 @@ pub mod gpio_port {
};
SETP26R { bits }
}
- #[doc = "Bit 27 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp27(&self) -> SETP27R {
let bits = {
const MASK: bool = true;
@@ -321536,8 +307770,7 @@ pub mod gpio_port {
};
SETP27R { bits }
}
- #[doc = "Bit 28 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp28(&self) -> SETP28R {
let bits = {
const MASK: bool = true;
@@ -321546,8 +307779,7 @@ pub mod gpio_port {
};
SETP28R { bits }
}
- #[doc = "Bit 29 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp29(&self) -> SETP29R {
let bits = {
const MASK: bool = true;
@@ -321556,8 +307788,7 @@ pub mod gpio_port {
};
SETP29R { bits }
}
- #[doc = "Bit 30 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp30(&self) -> SETP30R {
let bits = {
const MASK: bool = true;
@@ -321566,8 +307797,7 @@ pub mod gpio_port {
};
SETP30R { bits }
}
- #[doc = "Bit 31 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp31(&self) -> SETP31R {
let bits = {
const MASK: bool = true;
@@ -321589,163 +307819,131 @@ pub mod gpio_port {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp0(&mut self) -> _SETP0W {
_SETP0W { w: self }
}
- #[doc = "Bit 1 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 1 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp1(&mut self) -> _SETP1W {
_SETP1W { w: self }
}
- #[doc = "Bit 2 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp2(&mut self) -> _SETP2W {
_SETP2W { w: self }
}
- #[doc = "Bit 3 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp3(&mut self) -> _SETP3W {
_SETP3W { w: self }
}
- #[doc = "Bit 4 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp4(&mut self) -> _SETP4W {
_SETP4W { w: self }
}
- #[doc = "Bit 5 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp5(&mut self) -> _SETP5W {
_SETP5W { w: self }
}
- #[doc = "Bit 6 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp6(&mut self) -> _SETP6W {
_SETP6W { w: self }
}
- #[doc = "Bit 7 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 7 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp7(&mut self) -> _SETP7W {
_SETP7W { w: self }
}
- #[doc = "Bit 8 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 8 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp8(&mut self) -> _SETP8W {
_SETP8W { w: self }
}
- #[doc = "Bit 9 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 9 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp9(&mut self) -> _SETP9W {
_SETP9W { w: self }
}
- #[doc = "Bit 10 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 10 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp10(&mut self) -> _SETP10W {
_SETP10W { w: self }
}
- #[doc = "Bit 11 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 11 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp11(&mut self) -> _SETP11W {
_SETP11W { w: self }
}
- #[doc = "Bit 12 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 12 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp12(&mut self) -> _SETP12W {
_SETP12W { w: self }
}
- #[doc = "Bit 13 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 13 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp13(&mut self) -> _SETP13W {
_SETP13W { w: self }
}
- #[doc = "Bit 14 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 14 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp14(&mut self) -> _SETP14W {
_SETP14W { w: self }
}
- #[doc = "Bit 15 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 15 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp15(&mut self) -> _SETP15W {
_SETP15W { w: self }
}
- #[doc = "Bit 16 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 16 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp16(&mut self) -> _SETP16W {
_SETP16W { w: self }
}
- #[doc = "Bit 17 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 17 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp17(&mut self) -> _SETP17W {
_SETP17W { w: self }
}
- #[doc = "Bit 18 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 18 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp18(&mut self) -> _SETP18W {
_SETP18W { w: self }
}
- #[doc = "Bit 19 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 19 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp19(&mut self) -> _SETP19W {
_SETP19W { w: self }
}
- #[doc = "Bit 20 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 20 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp20(&mut self) -> _SETP20W {
_SETP20W { w: self }
}
- #[doc = "Bit 21 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 21 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp21(&mut self) -> _SETP21W {
_SETP21W { w: self }
}
- #[doc = "Bit 22 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 22 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp22(&mut self) -> _SETP22W {
_SETP22W { w: self }
}
- #[doc = "Bit 23 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 23 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp23(&mut self) -> _SETP23W {
_SETP23W { w: self }
}
- #[doc = "Bit 24 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 24 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp24(&mut self) -> _SETP24W {
_SETP24W { w: self }
}
- #[doc = "Bit 25 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 25 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp25(&mut self) -> _SETP25W {
_SETP25W { w: self }
}
- #[doc = "Bit 26 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 26 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp26(&mut self) -> _SETP26W {
_SETP26W { w: self }
}
- #[doc = "Bit 27 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 27 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp27(&mut self) -> _SETP27W {
_SETP27W { w: self }
}
- #[doc = "Bit 28 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 28 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp28(&mut self) -> _SETP28W {
_SETP28W { w: self }
}
- #[doc = "Bit 29 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 29 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp29(&mut self) -> _SETP29W {
_SETP29W { w: self }
}
- #[doc = "Bit 30 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 30 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp30(&mut self) -> _SETP30W {
_SETP30W { w: self }
}
- #[doc = "Bit 31 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."]
- #[inline(always)]
+ # [ doc = "Bit 31 - Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." ] # [ inline ( always ) ]
pub fn setp31(&mut self) -> _SETP31W {
_SETP31W { w: self }
}
@@ -323633,23 +309831,7 @@ pub mod spi {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - SPI Control Register. This register controls the operation of the SPI."]
- pub cr: CR,
- #[doc = "0x04 - SPI Status Register. This register shows the status of the SPI."]
- pub sr: SR,
- #[doc = "0x08 - SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register."]
- pub dr: DR,
- #[doc = "0x0c - SPI Clock Counter Register. This register controls the frequency of a master's SCK0."]
- pub ccr: CCR,
- #[doc = "0x10 - SPI Test Control register. For functional testing only."]
- pub tcr: TCR,
- #[doc = "0x14 - SPI Test Status register. For functional testing only."]
- pub tsr: TSR,
- _reserved0: [u8; 4usize],
- #[doc = "0x1c - SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface."]
- pub int: INT,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - SPI Control Register. This register controls the operation of the SPI." ] pub cr : CR , # [ doc = "0x04 - SPI Status Register. This register shows the status of the SPI." ] pub sr : SR , # [ doc = "0x08 - SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." ] pub dr : DR , # [ doc = "0x0c - SPI Clock Counter Register. This register controls the frequency of a master's SCK0." ] pub ccr : CCR , # [ doc = "0x10 - SPI Test Control register. For functional testing only." ] pub tcr : TCR , # [ doc = "0x14 - SPI Test Status register. For functional testing only." ] pub tsr : TSR , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x1c - SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." ] pub int : INT , }
#[doc = "SPI Control Register. This register controls the operation of the SPI."]
pub struct CR {
register: VolatileCell<u32>,
@@ -323702,11 +309884,7 @@ pub mod spi {
}
#[doc = "Possible values of the field `BITENABLE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum BITENABLER {
- #[doc = "The SPI controller sends and receives the number of bits selected by bits 11:8."]
- THE_SPI_CONTROLLER_S,
- #[doc = r" Reserved"] _Reserved(bool),
- }
+ pub enum BITENABLER {# [ doc = "The SPI controller sends and receives the number of bits selected by bits 11:8." ] THE_SPI_CONTROLLER_S , # [ doc = r" Reserved" ] _Reserved ( bool )}
impl BITENABLER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -323743,12 +309921,7 @@ pub mod spi {
}
#[doc = "Possible values of the field `CPHA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum CPHAR {
- #[doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal."]
- FIRST_EDGE,
- #[doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active."]
- SECOND_EDGE,
- }
+ pub enum CPHAR {# [ doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." ] FIRST_EDGE , # [ doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." ] SECOND_EDGE}
impl CPHAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -323925,11 +310098,7 @@ pub mod spi {
}
#[doc = "Possible values of the field `SPIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
- pub enum SPIER {
- #[doc = "SPI interrupts are inhibited."] INTBLOCK,
- #[doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated."]
- HWINT,
- }
+ pub enum SPIER {# [ doc = "SPI interrupts are inhibited." ] INTBLOCK , # [ doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated." ] HWINT}
impl SPIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline(always)]
@@ -324064,10 +310233,7 @@ pub mod spi {
}
}
#[doc = "Values that can be written to the field `BITENABLE`"]
- pub enum BITENABLEW {
- #[doc = "The SPI controller sends and receives the number of bits selected by bits 11:8."]
- THE_SPI_CONTROLLER_S,
- }
+ pub enum BITENABLEW {# [ doc = "The SPI controller sends and receives the number of bits selected by bits 11:8." ] THE_SPI_CONTROLLER_S}
impl BITENABLEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -324090,8 +310256,7 @@ pub mod spi {
self.bit(variant._bits())
}
}
- #[doc = "The SPI controller sends and receives the number of bits selected by bits 11:8."]
- #[inline(always)]
+ # [ doc = "The SPI controller sends and receives the number of bits selected by bits 11:8." ] # [ inline ( always ) ]
pub fn the_spi_controller_s(self) -> &'a mut W {
self.variant(BITENABLEW::THE_SPI_CONTROLLER_S)
}
@@ -324114,12 +310279,7 @@ pub mod spi {
}
}
#[doc = "Values that can be written to the field `CPHA`"]
- pub enum CPHAW {
- #[doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal."]
- FIRST_EDGE,
- #[doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active."]
- SECOND_EDGE,
- }
+ pub enum CPHAW {# [ doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." ] FIRST_EDGE , # [ doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." ] SECOND_EDGE}
impl CPHAW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -324143,13 +310303,11 @@ pub mod spi {
self.bit(variant._bits())
}
}
- #[doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal."]
- #[inline(always)]
+ # [ doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." ] # [ inline ( always ) ]
pub fn first_edge(self) -> &'a mut W {
self.variant(CPHAW::FIRST_EDGE)
}
- #[doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active."]
- #[inline(always)]
+ # [ doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." ] # [ inline ( always ) ]
pub fn second_edge(self) -> &'a mut W {
self.variant(CPHAW::SECOND_EDGE)
}
@@ -324340,11 +310498,7 @@ pub mod spi {
}
}
#[doc = "Values that can be written to the field `SPIE`"]
- pub enum SPIEW {
- #[doc = "SPI interrupts are inhibited."] INTBLOCK,
- #[doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated."]
- HWINT,
- }
+ pub enum SPIEW {# [ doc = "SPI interrupts are inhibited." ] INTBLOCK , # [ doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated." ] HWINT}
impl SPIEW {
#[allow(missing_docs)]
#[doc(hidden)]
@@ -324373,8 +310527,7 @@ pub mod spi {
pub fn intblock(self) -> &'a mut W {
self.variant(SPIEW::INTBLOCK)
}
- #[doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated."]
- #[inline(always)]
+ # [ doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated." ] # [ inline ( always ) ]
pub fn hwint(self) -> &'a mut W {
self.variant(SPIEW::HWINT)
}
@@ -324506,8 +310659,7 @@ pub mod spi {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 3 - Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending." ] # [ inline ( always ) ]
pub fn cpha(&self) -> CPHAR {
CPHAR::_from({
const MASK: bool = true;
@@ -324533,8 +310685,7 @@ pub mod spi {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 6 - LSB First controls which direction each byte is shifted when transferred."]
- #[inline(always)]
+ # [ doc = "Bit 6 - LSB First controls which direction each byte is shifted when transferred." ] # [ inline ( always ) ]
pub fn lsbf(&self) -> LSBFR {
LSBFR::_from({
const MASK: bool = true;
@@ -324551,8 +310702,7 @@ pub mod spi {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bits 8:11 - When bit 2 of this register is 1, this field controls the number of bits per transfer:"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - When bit 2 of this register is 1, this field controls the number of bits per transfer:" ] # [ inline ( always ) ]
pub fn bits_(&self) -> BITSR {
BITSR::_from({
const MASK: u8 = 15;
@@ -324578,8 +310728,7 @@ pub mod spi {
pub fn bitenable(&mut self) -> _BITENABLEW {
_BITENABLEW { w: self }
}
- #[doc = "Bit 3 - Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending." ] # [ inline ( always ) ]
pub fn cpha(&mut self) -> _CPHAW {
_CPHAW { w: self }
}
@@ -324593,8 +310742,7 @@ pub mod spi {
pub fn mstr(&mut self) -> _MSTRW {
_MSTRW { w: self }
}
- #[doc = "Bit 6 - LSB First controls which direction each byte is shifted when transferred."]
- #[inline(always)]
+ # [ doc = "Bit 6 - LSB First controls which direction each byte is shifted when transferred." ] # [ inline ( always ) ]
pub fn lsbf(&mut self) -> _LSBFW {
_LSBFW { w: self }
}
@@ -324603,8 +310751,7 @@ pub mod spi {
pub fn spie(&mut self) -> _SPIEW {
_SPIEW { w: self }
}
- #[doc = "Bits 8:11 - When bit 2 of this register is 1, this field controls the number of bits per transfer:"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - When bit 2 of this register is 1, this field controls the number of bits per transfer:" ] # [ inline ( always ) ]
pub fn bits_(&mut self) -> _BITSW {
_BITSW { w: self }
}
@@ -324740,8 +310887,7 @@ pub mod spi {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 3 - Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register."]
- #[inline(always)]
+ # [ doc = "Bit 3 - Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." ] # [ inline ( always ) ]
pub fn abrt(&self) -> ABRTR {
let bits = {
const MASK: bool = true;
@@ -324750,8 +310896,7 @@ pub mod spi {
};
ABRTR { bits }
}
- #[doc = "Bit 4 - Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register."]
- #[inline(always)]
+ # [ doc = "Bit 4 - Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." ] # [ inline ( always ) ]
pub fn modf(&self) -> MODFR {
let bits = {
const MASK: bool = true;
@@ -324760,8 +310905,7 @@ pub mod spi {
};
MODFR { bits }
}
- #[doc = "Bit 5 - Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." ] # [ inline ( always ) ]
pub fn rovr(&self) -> ROVRR {
let bits = {
const MASK: bool = true;
@@ -324770,8 +310914,7 @@ pub mod spi {
};
ROVRR { bits }
}
- #[doc = "Bit 6 - Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register."]
- #[inline(always)]
+ # [ doc = "Bit 6 - Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." ] # [ inline ( always ) ]
pub fn wcol(&self) -> WCOLR {
let bits = {
const MASK: bool = true;
@@ -324780,8 +310923,7 @@ pub mod spi {
};
WCOLR { bits }
}
- #[doc = "Bit 7 - SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register."]
- #[inline(always)]
+ # [ doc = "Bit 7 - SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." ] # [ inline ( always ) ]
pub fn spif(&self) -> SPIFR {
let bits = {
const MASK: bool = true;
@@ -324792,11 +310934,11 @@ pub mod spi {
}
}
}
- #[doc = "SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register."]
+ # [ doc = "SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." ]
pub struct DR {
register: VolatileCell<u32>,
}
- #[doc = "SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register."]
+ # [ doc = "SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." ]
pub mod dr {
#[doc = r" Value read from the register"]
pub struct R {
@@ -324910,8 +311052,7 @@ pub mod spi {
};
DATALOWR { bits }
}
- #[doc = "Bits 8:15 - If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." ] # [ inline ( always ) ]
pub fn datahigh(&self) -> DATAHIGHR {
let bits = {
const MASK: u8 = 255;
@@ -324938,8 +311079,7 @@ pub mod spi {
pub fn datalow(&mut self) -> _DATALOWW {
_DATALOWW { w: self }
}
- #[doc = "Bits 8:15 - If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes."]
- #[inline(always)]
+ # [ doc = "Bits 8:15 - If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." ] # [ inline ( always ) ]
pub fn datahigh(&mut self) -> _DATAHIGHW {
_DATAHIGHW { w: self }
}
@@ -325139,8 +311279,7 @@ pub mod spi {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 1:7 - SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting."]
- #[inline(always)]
+ # [ doc = "Bits 1:7 - SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting." ] # [ inline ( always ) ]
pub fn test(&self) -> TESTR {
let bits = {
const MASK: u8 = 127;
@@ -325162,8 +311301,7 @@ pub mod spi {
self.bits = bits;
self
}
- #[doc = "Bits 1:7 - SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting."]
- #[inline(always)]
+ # [ doc = "Bits 1:7 - SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting." ] # [ inline ( always ) ]
pub fn test(&mut self) -> _TESTW {
_TESTW { w: self }
}
@@ -325635,8 +311773,7 @@ pub mod spi {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software."]
- #[inline(always)]
+ # [ doc = "Bit 0 - SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." ] # [ inline ( always ) ]
pub fn spif(&self) -> SPIFR {
let bits = {
const MASK: bool = true;
@@ -325658,8 +311795,7 @@ pub mod spi {
self.bits = bits;
self
}
- #[doc = "Bit 0 - SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software."]
- #[inline(always)]
+ # [ doc = "Bit 0 - SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." ] # [ inline ( always ) ]
pub fn spif(&mut self) -> _SPIFW {
_SPIFW { w: self }
}
@@ -326350,10 +312486,8 @@ pub mod sgpio {
pub enum QUALIFIER_MODER {
#[doc = "Enable"] ENABLE,
#[doc = "Disable"] DISABLE,
- #[doc = "Slice (see bits QUALIFIER_SLICE_MODE in this register)"]
- SLICE_SEE_BITS_QUAL,
- #[doc = "External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)"]
- EXTERNAL_SGPIO_PIN,
+ #[doc = "Slice (see bits QUALIFIER_SLICE_MODE in this register)"] SLICE_SEE_BITS_QUAL,
+ #[doc = "External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)"] EXTERNAL_SGPIO_PIN,
}
impl QUALIFIER_MODER {
#[doc = r" Value of the field as raw bits"]
@@ -326784,10 +312918,8 @@ pub mod sgpio {
pub enum QUALIFIER_MODEW {
#[doc = "Enable"] ENABLE,
#[doc = "Disable"] DISABLE,
- #[doc = "Slice (see bits QUALIFIER_SLICE_MODE in this register)"]
- SLICE_SEE_BITS_QUAL,
- #[doc = "External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)"]
- EXTERNAL_SGPIO_PIN,
+ #[doc = "Slice (see bits QUALIFIER_SLICE_MODE in this register)"] SLICE_SEE_BITS_QUAL,
+ #[doc = "External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)"] EXTERNAL_SGPIO_PIN,
}
impl QUALIFIER_MODEW {
#[allow(missing_docs)]
@@ -327110,8 +313242,7 @@ pub mod sgpio {
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
- #[doc = "Bits 3:4 - Select clock source slice. Note that slices D, H, O and P do not support this mode."]
- #[inline(always)]
+ # [ doc = "Bits 3:4 - Select clock source slice. Note that slices D, H, O and P do not support this mode." ] # [ inline ( always ) ]
pub fn clk_source_slice_mode(&self) -> CLK_SOURCE_SLICE_MODER {
CLK_SOURCE_SLICE_MODER::_from({
const MASK: u8 = 3;
@@ -327187,8 +313318,7 @@ pub mod sgpio {
pub fn clk_source_pin_mode(&mut self) -> _CLK_SOURCE_PIN_MODEW {
_CLK_SOURCE_PIN_MODEW { w: self }
}
- #[doc = "Bits 3:4 - Select clock source slice. Note that slices D, H, O and P do not support this mode."]
- #[inline(always)]
+ # [ doc = "Bits 3:4 - Select clock source slice. Note that slices D, H, O and P do not support this mode." ] # [ inline ( always ) ]
pub fn clk_source_slice_mode(&mut self) -> _CLK_SOURCE_SLICE_MODEW {
_CLK_SOURCE_SLICE_MODEW { w: self }
}
@@ -327362,10 +313492,8 @@ pub mod sgpio {
#[doc = "Possible values of the field `CLKGEN_MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKGEN_MODER {
- #[doc = "Use clock internally generated by COUNTER."]
- USE_CLOCK_INTERNALLY,
- #[doc = "Use external clock from a pin or other slice."]
- USE_EXTERNAL_CLOCK_F,
+ #[doc = "Use clock internally generated by COUNTER."] USE_CLOCK_INTERNALLY,
+ #[doc = "Use external clock from a pin or other slice."] USE_EXTERNAL_CLOCK_F,
}
impl CLKGEN_MODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -327714,10 +313842,8 @@ pub mod sgpio {
}
#[doc = "Values that can be written to the field `CLKGEN_MODE`"]
pub enum CLKGEN_MODEW {
- #[doc = "Use clock internally generated by COUNTER."]
- USE_CLOCK_INTERNALLY,
- #[doc = "Use external clock from a pin or other slice."]
- USE_EXTERNAL_CLOCK_F,
+ #[doc = "Use clock internally generated by COUNTER."] USE_CLOCK_INTERNALLY,
+ #[doc = "Use external clock from a pin or other slice."] USE_EXTERNAL_CLOCK_F,
}
impl CLKGEN_MODEW {
#[allow(missing_docs)]
@@ -328012,8 +314138,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Match mode. Selects whether the match filter is active or whether data is captured."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Match mode. Selects whether the match filter is active or whether data is captured." ] # [ inline ( always ) ]
pub fn match_mode(&self) -> MATCH_MODER {
MATCH_MODER::_from({
const MASK: bool = true;
@@ -328030,8 +314155,7 @@ pub mod sgpio {
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
- #[doc = "Bit 2 - Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock." ] # [ inline ( always ) ]
pub fn clkgen_mode(&self) -> CLKGEN_MODER {
CLKGEN_MODER::_from({
const MASK: bool = true;
@@ -328088,8 +314212,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Match mode. Selects whether the match filter is active or whether data is captured."]
- #[inline(always)]
+ # [ doc = "Bit 0 - Match mode. Selects whether the match filter is active or whether data is captured." ] # [ inline ( always ) ]
pub fn match_mode(&mut self) -> _MATCH_MODEW {
_MATCH_MODEW { w: self }
}
@@ -328098,8 +314221,7 @@ pub mod sgpio {
pub fn clk_capture_mode(&mut self) -> _CLK_CAPTURE_MODEW {
_CLK_CAPTURE_MODEW { w: self }
}
- #[doc = "Bit 2 - Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock." ] # [ inline ( always ) ]
pub fn clkgen_mode(&mut self) -> _CLKGEN_MODEW {
_CLKGEN_MODEW { w: self }
}
@@ -328125,11 +314247,11 @@ pub mod sgpio {
}
}
}
- #[doc = "Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)"]
+ # [ doc = "Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" ]
pub struct REG {
register: VolatileCell<u32>,
}
- #[doc = "Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)"]
+ # [ doc = "Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" ]
pub mod reg {
#[doc = r" Value read from the register"]
pub struct R {
@@ -328207,8 +314329,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." ] # [ inline ( always ) ]
pub fn reg(&self) -> REGR {
let bits = {
const MASK: u32 = 4294967295;
@@ -328230,18 +314351,17 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0)." ] # [ inline ( always ) ]
pub fn reg(&mut self) -> _REGW {
_REGW { w: self }
}
}
}
- #[doc = "Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG"]
+ # [ doc = "Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" ]
pub struct REG_SS {
register: VolatileCell<u32>,
}
- #[doc = "Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG"]
+ # [ doc = "Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" ]
pub mod reg_ss {
#[doc = r" Value read from the register"]
pub struct R {
@@ -328319,8 +314439,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." ] # [ inline ( always ) ]
pub fn reg_ss(&self) -> REG_SSR {
let bits = {
const MASK: u32 = 4294967295;
@@ -328342,8 +314461,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG." ] # [ inline ( always ) ]
pub fn reg_ss(&mut self) -> _REG_SSW {
_REG_SSW { w: self }
}
@@ -328543,8 +314661,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:11 - Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." ] # [ inline ( always ) ]
pub fn count(&self) -> COUNTR {
let bits = {
const MASK: u16 = 4095;
@@ -328566,8 +314683,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:11 - Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET."]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET." ] # [ inline ( always ) ]
pub fn count(&mut self) -> _COUNTW {
_COUNTW { w: self }
}
@@ -328808,8 +314924,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice A 0 = No effect. 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice A 0 = No effect. 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_a(&self) -> MASK_AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -328831,8 +314946,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice A 0 = No effect. 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice A 0 = No effect. 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_a(&mut self) -> _MASK_AW {
_MASK_AW { w: self }
}
@@ -328920,8 +315034,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice H 0 = No effect. 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice H 0 = No effect. 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_h(&self) -> MASK_HR {
let bits = {
const MASK: u32 = 4294967295;
@@ -328943,8 +315056,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice H 0 = No effect. 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice H 0 = No effect. 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_h(&mut self) -> _MASK_HW {
_MASK_HW { w: self }
}
@@ -329032,8 +315144,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice I 0 = No effect . 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice I 0 = No effect . 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_i(&self) -> MASK_IR {
let bits = {
const MASK: u32 = 4294967295;
@@ -329055,8 +315166,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice I 0 = No effect . 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice I 0 = No effect . 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_i(&mut self) -> _MASK_IW {
_MASK_IW { w: self }
}
@@ -329144,8 +315254,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice P 0 = No effect. 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice P 0 = No effect. 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_p(&self) -> MASK_PR {
let bits = {
const MASK: u32 = 4294967295;
@@ -329167,8 +315276,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Mask for pattern match function of slice P 0 = No effect. 1 = Mask this bit."]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Mask for pattern match function of slice P 0 = No effect. 1 = Mask this bit." ] # [ inline ( always ) ]
pub fn mask_p(&mut self) -> _MASK_PW {
_MASK_PW { w: self }
}
@@ -329304,8 +315412,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH"]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH" ] # [ inline ( always ) ]
pub fn gpio_out(&self) -> GPIO_OUTR {
let bits = {
const MASK: u16 = 65535;
@@ -329327,8 +315434,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH"]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH" ] # [ inline ( always ) ]
pub fn gpio_out(&mut self) -> _GPIO_OUTW {
_GPIO_OUTW { w: self }
}
@@ -329416,8 +315522,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active." ] # [ inline ( always ) ]
pub fn gpio_oe(&self) -> GPIO_OER {
let bits = {
const MASK: u16 = 65535;
@@ -329439,8 +315544,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active." ] # [ inline ( always ) ]
pub fn gpio_oe(&mut self) -> _GPIO_OEW {
_GPIO_OEW { w: self }
}
@@ -329528,8 +315632,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock." ] # [ inline ( always ) ]
pub fn ctrl_en(&self) -> CTRL_ENR {
let bits = {
const MASK: u16 = 65535;
@@ -329551,8 +315654,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock." ] # [ inline ( always ) ]
pub fn ctrl_en(&mut self) -> _CTRL_ENW {
_CTRL_ENW { w: self }
}
@@ -329640,8 +315742,7 @@ pub mod sgpio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:15 - Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n." ] # [ inline ( always ) ]
pub fn ctrl_dis(&self) -> CTRL_DISR {
let bits = {
const MASK: u16 = 65535;
@@ -329663,8 +315764,7 @@ pub mod sgpio {
self.bits = bits;
self
}
- #[doc = "Bits 0:15 - Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n."]
- #[inline(always)]
+ # [ doc = "Bits 0:15 - Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n." ] # [ inline ( always ) ]
pub fn ctrl_dis(&mut self) -> _CTRL_DISW {
_CTRL_DISW { w: self }
}