diff --git a/LPC43xx_43Sxx.svd b/LPC43xx_43Sxx.svd
index 411b9a1ce94e47cd5e7bbeed45c93879735360d9..aeaabd7af863fa75109b47c4d512c9e0d1f526d7 100644
--- a/LPC43xx_43Sxx.svd
+++ b/LPC43xx_43Sxx.svd
@@ -4371,42 +4371,42 @@
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
+ <name>Timer_0_match_0_UART0_transmit</name>
<description>Destination = Timer 0 match 0/UART0 transmit</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
+ <name>Timer_0_match_1_UART0_receive</name>
<description>Destination = Timer 0 match 1/UART0 receive</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
+ <name>Timer_1_match_0_UART1_transmit</name>
<description>Destination = Timer 1 match 0/UART1 transmit</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
- <description>Destination = Timer 1 match 1/UART 1 receive</description>
+ <name>Timer_1_match_1_UART1_receive</name>
+ <description>Destination = Timer 1 match 1/UART1 receive</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
- <description>Destination = Timer 2 match 0/UART 2 transmit</description>
+ <name>Timer_2_match_0_UART2_transmit</name>
+ <description>Destination = Timer 2 match 0/UART2 transmit</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
- <description>Destination = Timer 2 match 1/UART 2 receive</description>
+ <name>Timer_2_match_1_UART2_receive</name>
+ <description>Destination = Timer 2 match 1/UART2 receive</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
+ <name>Timer_3_match_0_UART3_transmit_SCT_DMA_request_0</name>
<description>Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
- <name>DESTINATION_EQ_TIMER_</name>
+ <name>Timer_3_match_1_UART3_receive_SCT_DMA_request_1</name>
<description>Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1</description>
<value>0x8</value>
</enumeratedValue>
@@ -8772,12 +8772,12 @@
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
- <name>DISABLED</name>
+ <name>DISABLED0</name>
<description>The periodic schedule status is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
- <name>DISABLED</name>
+ <name>DISABLED1</name>
<description>The periodic schedule status is enabled.</description>
<value>1</value>
</enumeratedValue>
@@ -8790,12 +8790,12 @@
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
- <name>DISABLED</name>
+ <name>DISABLED0</name>
<description>Asynchronous schedule status is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
- <name>DISABLED</name>
+ <name>DISABLED1</name>
<description>Asynchronous schedule status is enabled.</description>
<value>1</value>
</enumeratedValue>
@@ -17715,7 +17715,7 @@
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
- <name>INPUT_TO_EVENT_ROUTE</name>
+ <name>INPUT_TO_EVENT_ROUTE_0</name>
<description>Input to event router.</description>
<value>0x0</value>
</enumeratedValue>
@@ -17730,7 +17730,7 @@
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
- <name>INPUT_TO_EVENT_ROUTE</name>
+ <name>INPUT_TO_EVENT_ROUTE_3</name>
<description>Input to event router.</description>
<value>0x3</value>
</enumeratedValue>
@@ -37582,12 +37582,12 @@
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
- <name>BREAK_INTERRUPT_STAT</name>
+ <name>inactive</name>
<description>Break interrupt status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
- <name>BREAK_INTERRUPT_STAT</name>
+ <name>active</name>
<description>Break interrupt status is active.</description>
<value>1</value>
</enumeratedValue>
diff --git a/src/lib.rs b/src/lib.rs
index c7c163d3cc7b8aed6280dce83593143ce1c71c2b..37f9868f8632e8f0f00347bf1b5c2775c193633a 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -30770,21 +30770,21 @@ pub mod gpdma {
pub enum DESTPERIPHERALR {
#[doc = "Destination = SPIFI"] DESTINATION_EQ_SPIFI,
#[doc = "Destination = Timer 0 match 0/UART0 transmit"]
- DESTINATION_EQ_TIMER_,
+ TIMER_0_MATCH_0_UART0_TRANSMIT,
#[doc = "Destination = Timer 0 match 1/UART0 receive"]
- DESTINATION_EQ_TIMER_,
+ TIMER_0_MATCH_1_UART0_RECEIVE,
#[doc = "Destination = Timer 1 match 0/UART1 transmit"]
- DESTINATION_EQ_TIMER_,
- #[doc = "Destination = Timer 1 match 1/UART 1 receive"]
- DESTINATION_EQ_TIMER_,
- #[doc = "Destination = Timer 2 match 0/UART 2 transmit"]
- DESTINATION_EQ_TIMER_,
- #[doc = "Destination = Timer 2 match 1/UART 2 receive"]
- DESTINATION_EQ_TIMER_,
+ TIMER_1_MATCH_0_UART1_TRANSMIT,
+ #[doc = "Destination = Timer 1 match 1/UART1 receive"]
+ TIMER_1_MATCH_1_UART1_RECEIVE,
+ #[doc = "Destination = Timer 2 match 0/UART2 transmit"]
+ TIMER_2_MATCH_0_UART2_TRANSMIT,
+ #[doc = "Destination = Timer 2 match 1/UART2 receive"]
+ TIMER_2_MATCH_1_UART2_RECEIVE,
#[doc = "Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
- DESTINATION_EQ_TIMER_,
+ TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0,
#[doc = "Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
- DESTINATION_EQ_TIMER_,
+ TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1,
#[doc = "Destination = SSP0 receive/I2S channel 0"]
DESTINATION_EQ_SSP0_R,
#[doc = "Destination = SSP0 transmit/I2S channel 1"]
@@ -30800,94 +30800,62 @@ pub mod gpdma {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
- match *self {
- DESTPERIPHERALR::DESTINATION_EQ_SPIFI => 0,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 1,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 2,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 3,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 4,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 5,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 6,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 7,
- DESTPERIPHERALR::DESTINATION_EQ_TIMER_ => 8,
- DESTPERIPHERALR::DESTINATION_EQ_SSP0_R => 9,
- DESTPERIPHERALR::DESTINATION_EQ_SSP0_T => 10,
- DESTPERIPHERALR::DESTINATION_EQ_SSP1_R => 11,
- DESTPERIPHERALR::DESTINATION_EQ_SSP1_T => 12,
- DESTPERIPHERALR::DESTINATION_EQ_ADC0 => 13,
- DESTPERIPHERALR::DESTINATION_EQ_ADC1 => 14,
- DESTPERIPHERALR::DESTINATION_EQ_DAC => 15,
- DESTPERIPHERALR::_Reserved(bits) => bits,
- }
+ match * self { DESTPERIPHERALR :: DESTINATION_EQ_SPIFI => 0 , DESTPERIPHERALR :: TIMER_0_MATCH_0_UART0_TRANSMIT => 1 , DESTPERIPHERALR :: TIMER_0_MATCH_1_UART0_RECEIVE => 2 , DESTPERIPHERALR :: TIMER_1_MATCH_0_UART1_TRANSMIT => 3 , DESTPERIPHERALR :: TIMER_1_MATCH_1_UART1_RECEIVE => 4 , DESTPERIPHERALR :: TIMER_2_MATCH_0_UART2_TRANSMIT => 5 , DESTPERIPHERALR :: TIMER_2_MATCH_1_UART2_RECEIVE => 6 , DESTPERIPHERALR :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 => 7 , DESTPERIPHERALR :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 => 8 , DESTPERIPHERALR :: DESTINATION_EQ_SSP0_R => 9 , DESTPERIPHERALR :: DESTINATION_EQ_SSP0_T => 10 , DESTPERIPHERALR :: DESTINATION_EQ_SSP1_R => 11 , DESTPERIPHERALR :: DESTINATION_EQ_SSP1_T => 12 , DESTPERIPHERALR :: DESTINATION_EQ_ADC0 => 13 , DESTPERIPHERALR :: DESTINATION_EQ_ADC1 => 14 , DESTPERIPHERALR :: DESTINATION_EQ_DAC => 15 , DESTPERIPHERALR :: _Reserved ( bits ) => bits }
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> DESTPERIPHERALR {
- match value {
- 0 => DESTPERIPHERALR::DESTINATION_EQ_SPIFI,
- 1 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 2 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 3 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 4 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 5 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 6 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 7 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 8 => DESTPERIPHERALR::DESTINATION_EQ_TIMER_,
- 9 => DESTPERIPHERALR::DESTINATION_EQ_SSP0_R,
- 10 => DESTPERIPHERALR::DESTINATION_EQ_SSP0_T,
- 11 => DESTPERIPHERALR::DESTINATION_EQ_SSP1_R,
- 12 => DESTPERIPHERALR::DESTINATION_EQ_SSP1_T,
- 13 => DESTPERIPHERALR::DESTINATION_EQ_ADC0,
- 14 => DESTPERIPHERALR::DESTINATION_EQ_ADC1,
- 15 => DESTPERIPHERALR::DESTINATION_EQ_DAC,
- i => DESTPERIPHERALR::_Reserved(i),
- }
+ match value { 0 => DESTPERIPHERALR :: DESTINATION_EQ_SPIFI , 1 => DESTPERIPHERALR :: TIMER_0_MATCH_0_UART0_TRANSMIT , 2 => DESTPERIPHERALR :: TIMER_0_MATCH_1_UART0_RECEIVE , 3 => DESTPERIPHERALR :: TIMER_1_MATCH_0_UART1_TRANSMIT , 4 => DESTPERIPHERALR :: TIMER_1_MATCH_1_UART1_RECEIVE , 5 => DESTPERIPHERALR :: TIMER_2_MATCH_0_UART2_TRANSMIT , 6 => DESTPERIPHERALR :: TIMER_2_MATCH_1_UART2_RECEIVE , 7 => DESTPERIPHERALR :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 , 8 => DESTPERIPHERALR :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 , 9 => DESTPERIPHERALR :: DESTINATION_EQ_SSP0_R , 10 => DESTPERIPHERALR :: DESTINATION_EQ_SSP0_T , 11 => DESTPERIPHERALR :: DESTINATION_EQ_SSP1_R , 12 => DESTPERIPHERALR :: DESTINATION_EQ_SSP1_T , 13 => DESTPERIPHERALR :: DESTINATION_EQ_ADC0 , 14 => DESTPERIPHERALR :: DESTINATION_EQ_ADC1 , 15 => DESTPERIPHERALR :: DESTINATION_EQ_DAC , i => DESTPERIPHERALR :: _Reserved ( i ) , }
}
#[doc = "Checks if the value of the field is `DESTINATION_EQ_SPIFI`"]
#[inline(always)]
pub fn is_destination_eq_spifi(&self) -> bool {
*self == DESTPERIPHERALR::DESTINATION_EQ_SPIFI
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_0_MATCH_0_UART0_TRANSMIT`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_0_match_0_uart0_transmit(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_0_MATCH_0_UART0_TRANSMIT
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_0_MATCH_1_UART0_RECEIVE`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_0_match_1_uart0_receive(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_0_MATCH_1_UART0_RECEIVE
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_1_MATCH_0_UART1_TRANSMIT`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_1_match_0_uart1_transmit(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_1_MATCH_0_UART1_TRANSMIT
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_1_MATCH_1_UART1_RECEIVE`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_1_match_1_uart1_receive(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_1_MATCH_1_UART1_RECEIVE
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_2_MATCH_0_UART2_TRANSMIT`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_2_match_0_uart2_transmit(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_2_MATCH_0_UART2_TRANSMIT
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_2_MATCH_1_UART2_RECEIVE`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_2_match_1_uart2_receive(&self) -> bool {
+ *self == DESTPERIPHERALR::TIMER_2_MATCH_1_UART2_RECEIVE
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_3_match_0_uart3_transmit_sct_dma_request_0(
+ &self,
+ ) -> bool {
+ * self == DESTPERIPHERALR :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0
}
- #[doc = "Checks if the value of the field is `DESTINATION_EQ_TIMER_`"]
+ #[doc = "Checks if the value of the field is `TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1`"]
#[inline(always)]
- pub fn is_destination_eq_timer_(&self) -> bool {
- *self == DESTPERIPHERALR::DESTINATION_EQ_TIMER_
+ pub fn is_timer_3_match_1_uart3_receive_sct_dma_request_1(
+ &self,
+ ) -> bool {
+ * self == DESTPERIPHERALR :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1
}
#[doc = "Checks if the value of the field is `DESTINATION_EQ_SSP0_R`"]
#[inline(always)]
@@ -31359,21 +31327,21 @@ pub mod gpdma {
pub enum DESTPERIPHERALW {
#[doc = "Destination = SPIFI"] DESTINATION_EQ_SPIFI,
#[doc = "Destination = Timer 0 match 0/UART0 transmit"]
- DESTINATION_EQ_TIMER_,
+ TIMER_0_MATCH_0_UART0_TRANSMIT,
#[doc = "Destination = Timer 0 match 1/UART0 receive"]
- DESTINATION_EQ_TIMER_,
+ TIMER_0_MATCH_1_UART0_RECEIVE,
#[doc = "Destination = Timer 1 match 0/UART1 transmit"]
- DESTINATION_EQ_TIMER_,
- #[doc = "Destination = Timer 1 match 1/UART 1 receive"]
- DESTINATION_EQ_TIMER_,
- #[doc = "Destination = Timer 2 match 0/UART 2 transmit"]
- DESTINATION_EQ_TIMER_,
- #[doc = "Destination = Timer 2 match 1/UART 2 receive"]
- DESTINATION_EQ_TIMER_,
+ TIMER_1_MATCH_0_UART1_TRANSMIT,
+ #[doc = "Destination = Timer 1 match 1/UART1 receive"]
+ TIMER_1_MATCH_1_UART1_RECEIVE,
+ #[doc = "Destination = Timer 2 match 0/UART2 transmit"]
+ TIMER_2_MATCH_0_UART2_TRANSMIT,
+ #[doc = "Destination = Timer 2 match 1/UART2 receive"]
+ TIMER_2_MATCH_1_UART2_RECEIVE,
#[doc = "Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
- DESTINATION_EQ_TIMER_,
+ TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0,
#[doc = "Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
- DESTINATION_EQ_TIMER_,
+ TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1,
#[doc = "Destination = SSP0 receive/I2S channel 0"]
DESTINATION_EQ_SSP0_R,
#[doc = "Destination = SSP0 transmit/I2S channel 1"]
@@ -31389,24 +31357,7 @@ pub mod gpdma {
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
- match *self {
- DESTPERIPHERALW::DESTINATION_EQ_SPIFI => 0,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 1,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 2,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 3,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 4,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 5,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 6,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 7,
- DESTPERIPHERALW::DESTINATION_EQ_TIMER_ => 8,
- DESTPERIPHERALW::DESTINATION_EQ_SSP0_R => 9,
- DESTPERIPHERALW::DESTINATION_EQ_SSP0_T => 10,
- DESTPERIPHERALW::DESTINATION_EQ_SSP1_R => 11,
- DESTPERIPHERALW::DESTINATION_EQ_SSP1_T => 12,
- DESTPERIPHERALW::DESTINATION_EQ_ADC0 => 13,
- DESTPERIPHERALW::DESTINATION_EQ_ADC1 => 14,
- DESTPERIPHERALW::DESTINATION_EQ_DAC => 15,
- }
+ match * self { DESTPERIPHERALW :: DESTINATION_EQ_SPIFI => 0 , DESTPERIPHERALW :: TIMER_0_MATCH_0_UART0_TRANSMIT => 1 , DESTPERIPHERALW :: TIMER_0_MATCH_1_UART0_RECEIVE => 2 , DESTPERIPHERALW :: TIMER_1_MATCH_0_UART1_TRANSMIT => 3 , DESTPERIPHERALW :: TIMER_1_MATCH_1_UART1_RECEIVE => 4 , DESTPERIPHERALW :: TIMER_2_MATCH_0_UART2_TRANSMIT => 5 , DESTPERIPHERALW :: TIMER_2_MATCH_1_UART2_RECEIVE => 6 , DESTPERIPHERALW :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 => 7 , DESTPERIPHERALW :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 => 8 , DESTPERIPHERALW :: DESTINATION_EQ_SSP0_R => 9 , DESTPERIPHERALW :: DESTINATION_EQ_SSP0_T => 10 , DESTPERIPHERALW :: DESTINATION_EQ_SSP1_R => 11 , DESTPERIPHERALW :: DESTINATION_EQ_SSP1_T => 12 , DESTPERIPHERALW :: DESTINATION_EQ_ADC0 => 13 , DESTPERIPHERALW :: DESTINATION_EQ_ADC1 => 14 , DESTPERIPHERALW :: DESTINATION_EQ_DAC => 15 }
}
}
#[doc = r" Proxy"]
@@ -31426,43 +31377,47 @@ pub mod gpdma {
}
#[doc = "Destination = Timer 0 match 0/UART0 transmit"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_0_match_0_uart0_transmit(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_0_MATCH_0_UART0_TRANSMIT)
}
#[doc = "Destination = Timer 0 match 1/UART0 receive"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_0_match_1_uart0_receive(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_0_MATCH_1_UART0_RECEIVE)
}
#[doc = "Destination = Timer 1 match 0/UART1 transmit"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_1_match_0_uart1_transmit(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_1_MATCH_0_UART1_TRANSMIT)
}
- #[doc = "Destination = Timer 1 match 1/UART 1 receive"]
+ #[doc = "Destination = Timer 1 match 1/UART1 receive"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_1_match_1_uart1_receive(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_1_MATCH_1_UART1_RECEIVE)
}
- #[doc = "Destination = Timer 2 match 0/UART 2 transmit"]
+ #[doc = "Destination = Timer 2 match 0/UART2 transmit"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_2_match_0_uart2_transmit(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_2_MATCH_0_UART2_TRANSMIT)
}
- #[doc = "Destination = Timer 2 match 1/UART 2 receive"]
+ #[doc = "Destination = Timer 2 match 1/UART2 receive"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_2_match_1_uart2_receive(self) -> &'a mut W {
+ self.variant(DESTPERIPHERALW::TIMER_2_MATCH_1_UART2_RECEIVE)
}
#[doc = "Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_3_match_0_uart3_transmit_sct_dma_request_0(
+ self,
+ ) -> &'a mut W {
+ self . variant ( DESTPERIPHERALW :: TIMER_3_MATCH_0_UART3_TRANSMIT_SCT_DMA_REQUEST_0 )
}
#[doc = "Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1"]
#[inline(always)]
- pub fn destination_eq_timer_(self) -> &'a mut W {
- self.variant(DESTPERIPHERALW::DESTINATION_EQ_TIMER_)
+ pub fn timer_3_match_1_uart3_receive_sct_dma_request_1(
+ self,
+ ) -> &'a mut W {
+ self . variant ( DESTPERIPHERALW :: TIMER_3_MATCH_1_UART3_RECEIVE_SCT_DMA_REQUEST_1 )
}
#[doc = "Destination = SSP0 receive/I2S channel 0"]
#[inline(always)]
@@ -54736,8 +54691,8 @@ pub mod usb0 {
#[doc = "Possible values of the field `PS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PSR {
- #[doc = "The periodic schedule status is disabled."] DISABLED,
- #[doc = "The periodic schedule status is enabled."] DISABLED,
+ #[doc = "The periodic schedule status is disabled."] DISABLED0,
+ #[doc = "The periodic schedule status is enabled."] DISABLED1,
}
impl PSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -54754,8 +54709,8 @@ pub mod usb0 {
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
- PSR::DISABLED => false,
- PSR::DISABLED => true,
+ PSR::DISABLED0 => false,
+ PSR::DISABLED1 => true,
}
}
#[allow(missing_docs)]
@@ -54763,26 +54718,26 @@ pub mod usb0 {
#[inline(always)]
pub fn _from(value: bool) -> PSR {
match value {
- false => PSR::DISABLED,
- true => PSR::DISABLED,
+ false => PSR::DISABLED0,
+ true => PSR::DISABLED1,
}
}
- #[doc = "Checks if the value of the field is `DISABLED`"]
+ #[doc = "Checks if the value of the field is `DISABLED0`"]
#[inline(always)]
- pub fn is_disabled(&self) -> bool {
- *self == PSR::DISABLED
+ pub fn is_disabled0(&self) -> bool {
+ *self == PSR::DISABLED0
}
- #[doc = "Checks if the value of the field is `DISABLED`"]
+ #[doc = "Checks if the value of the field is `DISABLED1`"]
#[inline(always)]
- pub fn is_disabled(&self) -> bool {
- *self == PSR::DISABLED
+ pub fn is_disabled1(&self) -> bool {
+ *self == PSR::DISABLED1
}
}
#[doc = "Possible values of the field `AS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ASR {
- #[doc = "Asynchronous schedule status is disabled."] DISABLED,
- #[doc = "Asynchronous schedule status is enabled."] DISABLED,
+ #[doc = "Asynchronous schedule status is disabled."] DISABLED0,
+ #[doc = "Asynchronous schedule status is enabled."] DISABLED1,
}
impl ASR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -54799,8 +54754,8 @@ pub mod usb0 {
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
- ASR::DISABLED => false,
- ASR::DISABLED => true,
+ ASR::DISABLED0 => false,
+ ASR::DISABLED1 => true,
}
}
#[allow(missing_docs)]
@@ -54808,19 +54763,19 @@ pub mod usb0 {
#[inline(always)]
pub fn _from(value: bool) -> ASR {
match value {
- false => ASR::DISABLED,
- true => ASR::DISABLED,
+ false => ASR::DISABLED0,
+ true => ASR::DISABLED1,
}
}
- #[doc = "Checks if the value of the field is `DISABLED`"]
+ #[doc = "Checks if the value of the field is `DISABLED0`"]
#[inline(always)]
- pub fn is_disabled(&self) -> bool {
- *self == ASR::DISABLED
+ pub fn is_disabled0(&self) -> bool {
+ *self == ASR::DISABLED0
}
- #[doc = "Checks if the value of the field is `DISABLED`"]
+ #[doc = "Checks if the value of the field is `DISABLED1`"]
#[inline(always)]
- pub fn is_disabled(&self) -> bool {
- *self == ASR::DISABLED
+ pub fn is_disabled1(&self) -> bool {
+ *self == ASR::DISABLED1
}
}
#[doc = "Possible values of the field `UAI`"]
@@ -55375,8 +55330,8 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `PS`"]
pub enum PSW {
- #[doc = "The periodic schedule status is disabled."] DISABLED,
- #[doc = "The periodic schedule status is enabled."] DISABLED,
+ #[doc = "The periodic schedule status is disabled."] DISABLED0,
+ #[doc = "The periodic schedule status is enabled."] DISABLED1,
}
impl PSW {
#[allow(missing_docs)]
@@ -55384,8 +55339,8 @@ pub mod usb0 {
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
- PSW::DISABLED => false,
- PSW::DISABLED => true,
+ PSW::DISABLED0 => false,
+ PSW::DISABLED1 => true,
}
}
}
@@ -55403,13 +55358,13 @@ pub mod usb0 {
}
#[doc = "The periodic schedule status is disabled."]
#[inline(always)]
- pub fn disabled(self) -> &'a mut W {
- self.variant(PSW::DISABLED)
+ pub fn disabled0(self) -> &'a mut W {
+ self.variant(PSW::DISABLED0)
}
#[doc = "The periodic schedule status is enabled."]
#[inline(always)]
- pub fn disabled(self) -> &'a mut W {
- self.variant(PSW::DISABLED)
+ pub fn disabled1(self) -> &'a mut W {
+ self.variant(PSW::DISABLED1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
@@ -55431,8 +55386,8 @@ pub mod usb0 {
}
#[doc = "Values that can be written to the field `AS`"]
pub enum ASW {
- #[doc = "Asynchronous schedule status is disabled."] DISABLED,
- #[doc = "Asynchronous schedule status is enabled."] DISABLED,
+ #[doc = "Asynchronous schedule status is disabled."] DISABLED0,
+ #[doc = "Asynchronous schedule status is enabled."] DISABLED1,
}
impl ASW {
#[allow(missing_docs)]
@@ -55440,8 +55395,8 @@ pub mod usb0 {
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
- ASW::DISABLED => false,
- ASW::DISABLED => true,
+ ASW::DISABLED0 => false,
+ ASW::DISABLED1 => true,
}
}
}
@@ -55459,13 +55414,13 @@ pub mod usb0 {
}
#[doc = "Asynchronous schedule status is disabled."]
#[inline(always)]
- pub fn disabled(self) -> &'a mut W {
- self.variant(ASW::DISABLED)
+ pub fn disabled0(self) -> &'a mut W {
+ self.variant(ASW::DISABLED0)
}
#[doc = "Asynchronous schedule status is enabled."]
#[inline(always)]
- pub fn disabled(self) -> &'a mut W {
- self.variant(ASW::DISABLED)
+ pub fn disabled1(self) -> &'a mut W {
+ self.variant(ASW::DISABLED1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
@@ -108727,18 +108682,18 @@ pub mod creg {
#[doc = "Possible values of the field `WAKEUP1CTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WAKEUP1CTRLR {
- #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE,
+ #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE_0,
#[doc = "Output from the event router."] OUTPUT_FROM_THE_EVEN,
- #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE,
+ #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE_3,
}
impl WAKEUP1CTRLR {
#[doc = r" Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
- WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE => 0,
+ WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE_0 => 0,
WAKEUP1CTRLR::OUTPUT_FROM_THE_EVEN => 1,
- WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE => 3,
+ WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE_3 => 3,
}
}
#[allow(missing_docs)]
@@ -108746,26 +108701,26 @@ pub mod creg {
#[inline(always)]
pub fn _from(value: u8) -> WAKEUP1CTRLR {
match value {
- 0 => WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE,
+ 0 => WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE_0,
1 => WAKEUP1CTRLR::OUTPUT_FROM_THE_EVEN,
- 3 => WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE,
+ 3 => WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE_3,
_ => unreachable!(),
}
}
- #[doc = "Checks if the value of the field is `INPUT_TO_EVENT_ROUTE`"]
+ #[doc = "Checks if the value of the field is `INPUT_TO_EVENT_ROUTE_0`"]
#[inline(always)]
- pub fn is_input_to_event_route(&self) -> bool {
- *self == WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE
+ pub fn is_input_to_event_route_0(&self) -> bool {
+ *self == WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE_0
}
#[doc = "Checks if the value of the field is `OUTPUT_FROM_THE_EVEN`"]
#[inline(always)]
pub fn is_output_from_the_even(&self) -> bool {
*self == WAKEUP1CTRLR::OUTPUT_FROM_THE_EVEN
}
- #[doc = "Checks if the value of the field is `INPUT_TO_EVENT_ROUTE`"]
+ #[doc = "Checks if the value of the field is `INPUT_TO_EVENT_ROUTE_3`"]
#[inline(always)]
- pub fn is_input_to_event_route(&self) -> bool {
- *self == WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE
+ pub fn is_input_to_event_route_3(&self) -> bool {
+ *self == WAKEUP1CTRLR::INPUT_TO_EVENT_ROUTE_3
}
}
#[doc = "Values that can be written to the field `EN1KHZ`"]
@@ -109327,9 +109282,9 @@ pub mod creg {
}
#[doc = "Values that can be written to the field `WAKEUP1CTRL`"]
pub enum WAKEUP1CTRLW {
- #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE,
+ #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE_0,
#[doc = "Output from the event router."] OUTPUT_FROM_THE_EVEN,
- #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE,
+ #[doc = "Input to event router."] INPUT_TO_EVENT_ROUTE_3,
}
impl WAKEUP1CTRLW {
#[allow(missing_docs)]
@@ -109337,9 +109292,9 @@ pub mod creg {
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
- WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE => 0,
+ WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE_0 => 0,
WAKEUP1CTRLW::OUTPUT_FROM_THE_EVEN => 1,
- WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE => 3,
+ WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE_3 => 3,
}
}
}
@@ -109355,8 +109310,8 @@ pub mod creg {
}
#[doc = "Input to event router."]
#[inline(always)]
- pub fn input_to_event_route(self) -> &'a mut W {
- self.variant(WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE)
+ pub fn input_to_event_route_0(self) -> &'a mut W {
+ self.variant(WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE_0)
}
#[doc = "Output from the event router."]
#[inline(always)]
@@ -109365,8 +109320,8 @@ pub mod creg {
}
#[doc = "Input to event router."]
#[inline(always)]
- pub fn input_to_event_route(self) -> &'a mut W {
- self.variant(WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE)
+ pub fn input_to_event_route_3(self) -> &'a mut W {
+ self.variant(WAKEUP1CTRLW::INPUT_TO_EVENT_ROUTE_3)
}
#[doc = r" Writes raw bits to the field"]
#[inline(always)]
@@ -206172,8 +206127,8 @@ pub mod uart1 {
#[doc = "Possible values of the field `BI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIR {
- #[doc = "Break interrupt status is inactive."] BREAK_INTERRUPT_STAT,
- #[doc = "Break interrupt status is active."] BREAK_INTERRUPT_STAT,
+ #[doc = "Break interrupt status is inactive."] INACTIVE,
+ #[doc = "Break interrupt status is active."] ACTIVE,
}
impl BIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@@ -206190,8 +206145,8 @@ pub mod uart1 {
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
- BIR::BREAK_INTERRUPT_STAT => false,
- BIR::BREAK_INTERRUPT_STAT => true,
+ BIR::INACTIVE => false,
+ BIR::ACTIVE => true,
}
}
#[allow(missing_docs)]
@@ -206199,19 +206154,19 @@ pub mod uart1 {
#[inline(always)]
pub fn _from(value: bool) -> BIR {
match value {
- false => BIR::BREAK_INTERRUPT_STAT,
- true => BIR::BREAK_INTERRUPT_STAT,
+ false => BIR::INACTIVE,
+ true => BIR::ACTIVE,
}
}
- #[doc = "Checks if the value of the field is `BREAK_INTERRUPT_STAT`"]
+ #[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline(always)]
- pub fn is_break_interrupt_stat(&self) -> bool {
- *self == BIR::BREAK_INTERRUPT_STAT
+ pub fn is_inactive(&self) -> bool {
+ *self == BIR::INACTIVE
}
- #[doc = "Checks if the value of the field is `BREAK_INTERRUPT_STAT`"]
+ #[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline(always)]
- pub fn is_break_interrupt_stat(&self) -> bool {
- *self == BIR::BREAK_INTERRUPT_STAT
+ pub fn is_active(&self) -> bool {
+ *self == BIR::ACTIVE
}
}
#[doc = "Possible values of the field `THRE`"]