diff --git a/src/dma.rs b/src/dma.rs
index 2a5bdc8a31d1ee3c4610904a1d9d42a4c0235d6d..24d436da98cfcb665736e9c42f4ee0f3b8626562 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -113,6 +113,8 @@ pub struct W;
 pub struct Output<MODE> {
     _mode: PhantomData<MODE>,
 }
+// === Usart1TxPin
+pub unsafe trait Usart1TxStream<USART> {}
 
 pub mod dma1 {
     use core::marker::PhantomData;
@@ -160,10 +162,7 @@ pub mod dma1 {
         }
     }
 
-    // === Usart1TxPin
-    pub unsafe trait Usart1TxStream<USART> {}
-
-    unsafe impl Usart1TxStream<USART2> for S5<C4> {}
+    unsafe impl super::Usart1TxStream<USART2> for S5<C4> {}
 
     pub struct Streams(pub S4<C0>, pub S5<C0>);
 
@@ -183,7 +182,8 @@ pub mod dma1 {
     // lifcr 	low interrupt flag clear register
     // lisr 	low interrupt status register
 
-    impl<CHANNEL> S5<CHANNEL> {
+    //    impl<CHANNEL> S5<CHANNEL> {
+    impl S5<C4> {
         // sXcr 	stream x configuration register
         pub(crate) fn cr(&mut self) -> &dma2::S5CR {
             unsafe { &(*DMA1::ptr()).s5cr }
@@ -209,7 +209,7 @@ pub mod dma1 {
             unsafe { &(*DMA1::ptr()).s5ndtr }
         }
 
-        // s0par 	stream x peripheral address register
+        // sXpar 	stream x peripheral address register
         pub(crate) fn par(&mut self) -> &dma2::S5PAR {
             unsafe { &(*DMA1::ptr()).s5par }
         }
diff --git a/src/serial.rs b/src/serial.rs
index c1ce8d8fb65401f6814758393928f855d7dfab44..e03a8d64a779dc368ab39e271c00cac5ef67568a 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -8,11 +8,12 @@
 use core::sync::atomic::{self, Ordering};
 use core::ptr;
 use core::marker::{PhantomData, Unsize};
+use cast::u16;
 
 use hal::serial;
 use nb;
 use stm32f4x::{USART1, USART2, USART6};
-use dma::{Static, Transfer, R};
+use dma::{Static, Transfer, Usart1TxStream, R};
 
 // usart2
 use gpio::gpioa::{PA2, PA3};
@@ -241,50 +242,45 @@ macro_rules! hal {
                 }
             }
             impl Tx<$USARTX> {
-                pub fn write_all<A, B, C>(
+                pub fn write_all<A, B, S>(
                     self,
-                    mut chan: C,
+                    mut stream: S,
                     buffer: B,
-                ) -> Transfer<R, B, C, Self>
+                ) -> Transfer<R, B, S, Self>
                 where
                     A: Unsize<[u8]>,
                     B: Static<A>,
-                    C:
+                    S: Usart1TxStream<$USARTX>
                 {
                     //              // write!(dma1, "hi {}", 1);
                     // let usart2 = self.0;
 
-        // if dma1.s6cr.read().en().bit_is_set() {
-        //     return Err(dma::Error::InUse);
-        // }
-
-        // let buffer: &[u8] = buffer.lock();
-
-        // dma1.s6ndtr
-        //     .write(|w| unsafe { w.ndt().bits(u16(buffer.len()).unwrap()) });
-        // dma1.s6par
-        //     .write(|w| unsafe { w.bits(&usart2.dr as *const _ as u32) });
-        // dma1.s6m0ar
-        //     .write(|w| unsafe { w.bits(buffer.as_ptr() as u32) });
-        // dma1.s6cr.modify(|_, w| w.en().set_bit());
-
-
-
-                        //let buffer: &[u8] = buffer.borrow();
-                        // chan.cmar().write(|w| unsafe {
-                        //     w.ma().bits(buffer.as_ptr() as usize as u32)
-                        // });
-                        // chan.cndtr().write(|w| unsafe{
-                        //     w.ndt().bits(u16(buffer.len()).unwrap())
-                        // });
-                        // chan.cpar().write(|w| unsafe {
-                        //     w.pa().bits(&(*$USARTX::ptr()).dr as *const _ as usize as u32)
-                        // });
-
-                        // TODO can we weaken this compiler barrier?
-                        // NOTE(compiler_fence) operations on `buffer` should not be reordered after
-                        // the next statement, which starts the DMA transfer
-                        atomic::compiler_fence(Ordering::SeqCst);
+                    // let buffer: &[u8] = buffer.borrow();
+                    // stream.ndtr()
+                    //      .write(|w| unsafe { w.ndt().bits(u16(buffer.len()).unwrap()) });
+                    // dma1.s6par
+                    //     .write(|w| unsafe { w.bits(&usart2.dr as *const _ as u32) });
+                    // dma1.s6m0ar
+                    //     .write(|w| unsafe { w.bits(buffer.as_ptr() as u32) });
+                    // dma1.s6cr.modify(|_, w| w.en().set_bit());
+
+
+
+                    //let buffer: &[u8] = buffer.borrow();
+                    // chan.cmar().write(|w| unsafe {
+                    //     w.ma().bits(buffer.as_ptr() as usize as u32)
+                    // });
+                    // chan.cndtr().write(|w| unsafe{
+                    //     w.ndt().bits(u16(buffer.len()).unwrap())
+                    // });
+                    // chan.cpar().write(|w| unsafe {
+                    //     w.pa().bits(&(*$USARTX::ptr()).dr as *const _ as usize as u32)
+                    // });
+
+                    // TODO can we weaken this compiler barrier?
+                    // NOTE(compiler_fence) operations on `buffer` should not be reordered after
+                    // the next statement, which starts the DMA transfer
+                    // atomic::compiler_fence(Ordering::SeqCst);
 
                     //     chan.ccr().modify(|_, w| {
                     //         w.mem2mem()
@@ -297,7 +293,7 @@ macro_rules! hal {
                     //             .bit8()
                     //             .minc()
                     //             .set_bit()
-                    //             .pinc()
+                    //             .pinc()chan
                     //             .clear_bit()
                     //             .circ()
                     //             .clear_bit()
@@ -308,7 +304,7 @@ macro_rules! hal {
                     //     });
 
 
-                    Transfer::r(buffer, chan, self)
+                    Transfer::r(buffer, stream, self)
                 }
             }