diff --git a/.cargo/config b/.cargo/config
index 5d4b78a7cab49ca9c8bbe8d076af420fee86624f..ce50de7af963010d79e49fd9ac759b3e4e9bfcd9 100644
--- a/.cargo/config
+++ b/.cargo/config
@@ -5,10 +5,10 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment ONE of these three option to make `cargo run` start a GDB session
# which option to pick depends on your system
-# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+runner = "arm-none-eabi-gdb -q -x openocd.gdb"
# runner = "gdb-multiarch -q -x openocd.gdb"
# runner = "gdb -q -x openocd.gdb"
-runner = "probe-run --chip STM32F411RETx"
+# runner = "probe-run --chip STM32F411RETx"
rustflags = [
# This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
diff --git a/.vscode/CORTEX_DEBUG.md b/.vscode/CORTEX_DEBUG.md
new file mode 100644
index 0000000000000000000000000000000000000000..9e2bfcdb7b35893f9a8c84a32dfbb0c463a5b60c
--- /dev/null
+++ b/.vscode/CORTEX_DEBUG.md
@@ -0,0 +1,39 @@
+# Some notes on Debugging usin Cortex Debug
+
+In the `launch.json` three profiles are added.
+
+- `Cortex Debug`, running a debug build.
+- `Cortex Release`, running a release (optimized) build.
+- `Cortex Nightly`, running a release build with inlined assembly (optimized).
+
+All profiles apply to the currently active editor. (So if you e.g., try to debug this file you will get an error.)
+
+## Short cuts
+
+- Shift-Control-D, to get the list of launch profiles and select the one to use,
+- F5, to run the last one selected, or
+- F5, continue if already started,
+- Shift-F5, to abort debug session,
+- F10, to step over funciton (run function till it returns),
+- F11, to step into function,
+- Shift-F11, to step out of function (run function till it returns),
+- Ctrl-Shift-Y, focus debug console.
+
+In the console you can give `gdb` commands directly. Error handling and "tabbing" is sub-par compared to the terminal gdb, but at least it allows you to give `gdb` commands.
+
+It implements a history over sessions, which is neat. (Arrow up/down).
+
+## Console
+
+Examples of useful `gdb` console commands:
+
+> disassemble
+> continue
+> break *0x8000242
+> x 0xe0001004
+
+## Peripherals
+
+The profiles link to `STM32F401.svd`. This file is patched with to include the `DWT` unit where you find the `CYCCNT` register. You can `Right-Click` on the register to choose display format.
+
+This can be used in the lab to observe the content of `CYCCNT` (instead of `x 0xe0001004` in the console).
diff --git a/.vscode/STM32F401.svd b/.vscode/STM32F401.svd
index 4ed46659f64f696cd303761706a5e3e24c811234..c8890eb5dbe05e1452991204ef86868f0420fab6 100644
--- a/.vscode/STM32F401.svd
+++ b/.vscode/STM32F401.svd
@@ -4,16 +4,16 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32F401</name>
<version>1.1</version>
- <description>STM32F401</description>
- <!-- details about the cpu embedded in the device -->
- <cpu>
- <name>CM4</name>
- <revision>r1p0</revision>
- <endian>little</endian>
- <mpuPresent>false</mpuPresent>
- <fpuPresent>false</fpuPresent>
- <nvicPrioBits>3</nvicPrioBits>
- <vendorSystickConfig>false</vendorSystickConfig>
+ <description>STM32F401</description>
+ <!-- details about the cpu embedded in the device -->
+ <cpu>
+ <name>CM4</name>
+ <revision>r1p0</revision>
+ <endian>little</endian>
+ <mpuPresent>false</mpuPresent>
+ <fpuPresent>false</fpuPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<!--Bus Interface Properties-->
<!--Cortex-M4 is byte addressable-->
@@ -25,6 +25,302 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
+ <peripheral>
+ <name>DWT</name>
+ <version>1.0</version>
+ <description>Data Watchpoint Trace</description>
+ <baseAddress>0xE0001000</baseAddress>
+ <access>read-write</access>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x5C</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>CTRL</name>
+ <description>Control Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <fields>
+ <field>
+ <name>NUMCOMP</name>
+ <description>Number of comparators</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NOTRCPKT</name>
+ <description>No trace sampling and exception tracing</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NOEXTTRIG</name>
+ <description>No external match signals</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NOCYCCNT</name>
+ <description>No cycle counter</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>NOPRFCNT</name>
+ <description>No profiling counters</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>Reserved_23</name>
+ <description>Reserved bit 23</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>CYCEVTENA</name>
+ <description>enable Cycle count event</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FOLDEVTENA</name>
+ <description>enable Folded instruction count event</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>LSUEVTENA</name>
+ <description>enable Load Store Unit (LSU) count event</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SLEEPEVTENA</name>
+ <description>enable Sleep count event</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EXCEVTENA</name>
+ <description>enable interrupt overhead event</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CPIEVTENA</name>
+ <description>enable CPI count event</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EXCTRCENA</name>
+ <description>enable interrupt event tracing</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>Reserved_13_15</name>
+ <description>Reserved bits 13..15</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PCSAMPLENA</name>
+ <description>enable POSTCNT as timer for PC sample packets</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SYNCTAP</name>
+ <description>???</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CYCTAP</name>
+ <description>???</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>POSTINIT</name>
+ <description>???</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>POSTPRESET</name>
+ <description>???</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>4</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CYCCNTENA</name>
+ <description>enable cycle counter</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CYCCNT</name>
+ <description>Cycle Count Register</description>
+ <addressOffset>4</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>CPICNT</name>
+ <description>CPI Count Register</description>
+ <addressOffset>8</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>EXCCNT</name>
+ <description>Exception Overhead Count Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>SLEEPCNT</name>
+ <description>Sleep Count Register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>LSUCNT</name>
+ <description>LSU Count Register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>FOLDCNT</name>
+ <description>Folded-instruction Count Register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>PCSR</name>
+ <description>Program Counter Sample Register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>COMP0</name>
+ <description>Comparator Register 0</description>
+ <addressOffset>0x20</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>MASK0</name>
+ <description>Mask Register 0</description>
+ <addressOffset>0x24</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>FUNCTION0</name>
+ <description>Function Register 0</description>
+ <addressOffset>0x28</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>RESERVED0</name>
+ <description>Reserved 0</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>COMP1</name>
+ <description>Comparator Register 1</description>
+ <addressOffset>0x30</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>MASK1</name>
+ <description>Mask Register 1</description>
+ <addressOffset>0x34</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>FUNCTION1</name>
+ <description>Function Register 1</description>
+ <addressOffset>0x38</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>RESERVED1</name>
+ <description>Reserved 1</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>COMP2</name>
+ <description>Comparator Register 2</description>
+ <addressOffset>0x40</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>MASK2</name>
+ <description>Mask Register 2</description>
+ <addressOffset>0x44</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>FUNCTION2</name>
+ <description>Function Register 2</description>
+ <addressOffset>0x48</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>RESERVED2</name>
+ <description>Reserved 2</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>COMP3</name>
+ <description>Comparator Register 3</description>
+ <addressOffset>0x50</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>MASK3</name>
+ <description>Mask Register 3</description>
+ <addressOffset>0x54</addressOffset>
+ <size>32</size>
+ </register>
+ <register>
+ <name>FUNCTION3</name>
+ <description>Function Register 3</description>
+ <addressOffset>0x58</addressOffset>
+ <size>32</size>
+ </register>
+ </registers>
+ </peripheral>
<peripheral>
<name>ADC_Common</name>
<description>ADC common registers</description>
diff --git a/.vscode/launch.json b/.vscode/launch.json
index 83d5a308dc0f23bbcca9f8081b8bb965be3d8dc3..e353e7c06038970651569f87d501eebf68f0cf74 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -4,49 +4,58 @@
* https://marketplace.visualstudio.com/items?itemName=rust-lang.rust
* https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug
*/
+ // Use IntelliSense to learn about possible attributes.
+ // Hover to view descriptions of existing attributes.
+ // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
"version": "0.2.0",
"configurations": [
{
"type": "cortex-debug",
"request": "launch",
- "name": "Debug (QEMU)",
- "servertype": "qemu",
+ "name": "Cortex Debug",
+ "servertype": "openocd",
"cwd": "${workspaceRoot}",
- "preLaunchTask": "Cargo Build (debug)",
+ "preLaunchTask": "cargo build --examples",
"runToMain": true,
- "executable": "./target/thumbv7m-none-eabi/debug/app",
- /* Run `cargo build --example hello` and uncomment this line to run semi-hosting example */
- //"executable": "./target/thumbv7m-none-eabi/debug/examples/hello",
- "cpu": "cortex-m3",
- "machine": "lm3s6965evb",
+ "svdFile": "${workspaceRoot}/.vscode/STM32F401.svd",
+ "configFiles": [
+ "interface/stlink-v2-1.cfg",
+ "target/stm32f4x.cfg"
+ ],
+ "executable": "./target/thumbv7m-none-eabi/debug/examples/${fileBasenameNoExtension}",
+ "cpu": "cortex-m4",
},
{
- /* Configuration for the STM32F303 Discovery board */
"type": "cortex-debug",
"request": "launch",
- "name": "Debug (OpenOCD)",
+ "name": "Cortex Release",
"servertype": "openocd",
"cwd": "${workspaceRoot}",
- "preLaunchTask": "Cargo Build (debug)",
+ "preLaunchTask": "cargo build --examples --release",
"runToMain": true,
- "executable": "./target/thumbv7em-none-eabihf/debug/app",
- /* Run `cargo build --example itm` and uncomment this line to run itm example */
- // "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
- "device": "STM32F303VCT6",
+ "svdFile": "${workspaceRoot}/.vscode/STM32F401.svd",
+ "configFiles": [
+ "interface/stlink-v2-1.cfg",
+ "target/stm32f4x.cfg"
+ ],
+ "executable": "./target/thumbv7m-none-eabi/release/examples/${fileBasenameNoExtension}",
+ "cpu": "cortex-m4",
+ },
+ {
+ "type": "cortex-debug",
+ "request": "launch",
+ "name": "Cortex Nightly",
+ "servertype": "openocd",
+ "cwd": "${workspaceRoot}",
+ "preLaunchTask": "cargo build --examples --release --nightly",
+ // "runToMain": true,
+ "svdFile": "${workspaceRoot}/.vscode/STM32F401.svd",
"configFiles": [
"interface/stlink-v2-1.cfg",
- "target/stm32f3x.cfg"
+ "target/stm32f4x.cfg"
],
- "svdFile": "${workspaceRoot}/.vscode/STM32F303.svd",
- "swoConfig": {
- "enabled": true,
- "cpuFrequency": 8000000,
- "swoFrequency": 2000000,
- "source": "probe",
- "decoders": [
- { "type": "console", "label": "ITM", "port": 0 }
- ]
- }
- }
+ "executable": "./target/thumbv7m-none-eabi/release/examples/${fileBasenameNoExtension}",
+ "cpu": "cortex-m4",
+ },
]
}
\ No newline at end of file
diff --git a/.vscode/tasks.json b/.vscode/tasks.json
index 7f57a2787ddd3b859055135b2d69c23d43b3b87c..2f6aa72bafabd20ae7819d196f688b0818aca034 100644
--- a/.vscode/tasks.json
+++ b/.vscode/tasks.json
@@ -4,60 +4,31 @@
"version": "2.0.0",
"tasks": [
{
- /*
- * This is the default cargo build task,
- * but we need to provide a label for it,
- * so we can invoke it from the debug launcher.
- */
- "label": "Cargo Build (debug)",
- "type": "process",
- "command": "cargo",
- "args": ["build"],
+ "type": "cargo",
+ "command": "build --example ${fileBasenameNoExtension} --target thumbv7m-none-eabi",
"problemMatcher": [
"$rustc"
],
- "group": {
- "kind": "build",
- "isDefault": true
- }
+ "group": "build",
+ "label": "cargo build --examples"
},
{
- "label": "Cargo Build (release)",
- "type": "process",
- "command": "cargo",
- "args": ["build", "--release"],
+ "type": "cargo",
+ "command": "build --example ${fileBasenameNoExtension} --release --target thumbv7m-none-eabi",
"problemMatcher": [
"$rustc"
],
- "group": "build"
+ "group": "build",
+ "label": "cargo build --examples --release"
},
{
- "label": "Cargo Build Examples (debug)",
- "type": "process",
- "command": "cargo",
- "args": ["build","--examples"],
+ "type": "cargo",
+ "command": "build --example ${fileBasenameNoExtension} --release --features nightly --target thumbv7m-none-eabi",
"problemMatcher": [
"$rustc"
],
- "group": "build"
- },
- {
- "label": "Cargo Build Examples (release)",
- "type": "process",
- "command": "cargo",
- "args": ["build","--examples", "--release"],
- "problemMatcher": [
- "$rustc"
- ],
- "group": "build"
- },
- {
- "label": "Cargo Clean",
- "type": "process",
- "command": "cargo",
- "args": ["clean"],
- "problemMatcher": [],
- "group": "build"
- },
+ "group": "build",
+ "label": "cargo build --examples --release --nightly"
+ }
]
-}
+}
\ No newline at end of file