diff --git a/examples/timing_exam.rs b/examples/timing_exam.rs
index f332239b39bf722e95d2a806f49244c5d732a8f0..f8203a63bd5b34378d44101ef0d9e3f59721906e 100644
--- a/examples/timing_exam.rs
+++ b/examples/timing_exam.rs
@@ -40,6 +40,7 @@ const APP: () = {
     #[inline(never)]
     #[task(schedule = [t1], priority = 1)]
     fn t1(cx: t1::Context) {
+        let start = Instant::now();
         asm::bkpt();
         cx.schedule.t1(cx.scheduled + 100_000.cycles()).unwrap();
         asm::bkpt();
@@ -50,12 +51,24 @@ const APP: () = {
 
         // 2) your code here to update T1_MAX_RP and
         // break if deadline missed
+        let resp: u32= start.elapsed().as_cycles();
+        if  resp > 100_000 {
+            panic!();
+        } else {
+            unsafe {
+                if resp > T1_MAX_RP {
+                    T1_MAX_RP = resp;
+                }
+            }
+        }
     }
 
     // Deadline 200, Inter-arrival 200
     #[inline(never)]
     #[task(schedule = [t2], resources = [R1, R2], priority = 2)]
-    fn t2(cx: t2::Context) {
+    fn t2(mut cx: t2::Context) {
+        let start = Instant::now();
+
         asm::bkpt();
         cx.schedule.t2(cx.scheduled + 200_000.cycles()).unwrap();
         asm::bkpt();
@@ -63,14 +76,45 @@ const APP: () = {
         // 1) your code here to emulate timing behavior of t2
         asm::bkpt();
 
+        // == Begin trace ==
+        asm::delay(10_000);
+        //  R1 : claim
+        asm::delay(2_000);
+        // R2 : claim
+        cx.resources.R2.lock(|r2| {
+            asm::delay(4_000);
+        });
+        // R2 : release
+        asm::delay(4_000);
+        // R1 : release
+        asm::delay(2_000);
+        // R1 : claim
+        asm::delay(6_000);
+        // R1 : release
+        asm::delay(2_000);
+        // == End trace ==
+
+        asm::bkpt();
+
         // 2) your code here to update T2_MAX_RP and
         // break if deadline missed
+        let resp: u32= start.elapsed().as_cycles();
+        if  resp > 200_000 {
+            panic!();
+        } else {
+            unsafe {
+                if resp > T2_MAX_RP {
+                    T2_MAX_RP = resp;
+                }
+            }
+        }
     }
 
     // Deadline 50, Inter-arrival 50
     #[inline(never)]
     #[task(schedule = [t3], resources = [R2], priority = 3)]
     fn t3(cx: t3::Context) {
+        let start = Instant::now();
         asm::bkpt();
         cx.schedule.t3(cx.scheduled + 50_000.cycles()).unwrap();
         asm::bkpt();
@@ -78,8 +122,26 @@ const APP: () = {
         // 1) your code here to emulate timing behavior of t3
         asm::bkpt();
 
+        // == Begin trace ==
+        asm::delay(10_000);
+        // R2 : claim
+        asm::delay(10_000);
+        // R2 : release
+        asm::delay(10_000);
+        // == End trace ==
+
         // 2) your code here to update T3_MAX_RP and
         // break if deadline missed
+        let resp: u32= start.elapsed().as_cycles();
+        if  resp > 50_000 {
+            panic!();
+        } else {
+            unsafe {
+                if resp > T3_MAX_RP {
+                    T3_MAX_RP = resp;
+                }
+            }
+        }
     }
 
     // RTIC requires that unused interrupts are declared in an extern block when