diff --git a/examples/timing_exam.rs b/examples/timing_exam.rs index 892ef69f1aabe7e22c9e0beb311eb675901990cb..535e44125a7b2cca52668f28e474cdb1a94f8118 100644 --- a/examples/timing_exam.rs +++ b/examples/timing_exam.rs @@ -41,18 +41,18 @@ const APP: () = { #[task(schedule = [t1], priority = 1)] fn t1(cx: t1::Context) { //let start = Instant::now(); - asm::bkpt(); + asm::bkpt(); //=> 100171 t1,t2 running: 100_199 cx.schedule.t1(cx.scheduled + 100_000.cycles()).unwrap(); - asm::bkpt(); + asm::bkpt(); //=> 100350 // emulates timing behavior of t1 - cortex_m::asm::delay(10_000); + cortex_m::asm::delay(9_631); // 10_000 - 171 (context switch) - 179 (re-schedule) - 19 (rest of task code) - asm::bkpt(); + asm::bkpt(); //=> 110353 // 2) your code here to update T1_MAX_RP and // break if deadline missed let resp: u32= cx.scheduled.elapsed().as_cycles(); - asm::bkpt(); + asm::bkpt(); //=> 110362 if resp > 100_000 { //panic!(); asm::bkpt(); @@ -62,7 +62,7 @@ const APP: () = { T1_MAX_RP = resp; } } - asm::bkpt(); + asm::bkpt(); //=> 110369 } // Deadline 200, Inter-arrival 200 @@ -71,22 +71,24 @@ const APP: () = { fn t2(mut cx: t2::Context) { //let start = Instant::now(); - asm::bkpt(); + asm::bkpt(); //=> 200_183 t1,t2 rinning: 200_219 cx.schedule.t2(cx.scheduled + 200_000.cycles()).unwrap(); - asm::bkpt(); + asm::bkpt(); //=> 200_368 // 1) your code here to emulate timing behavior of t2 // == Begin trace == - asm::delay(10_000); + asm::delay(9_550); // 10_000 - 183 (context switch) - 75 (preemtion time, calc from t3) - 185 (re-schedual) - 7 (other) // R1 : claim asm::delay(2_000); // R2 : claim + asm::bkpt(); //=> 212_375 cx.resources.R2.lock(|r2| { *r2 = 1338; - asm::delay(4_000); + asm::delay(3_972); //=> 4_000 critical section - 29 (lock semantics + ) *r2 = 1668; }); + asm::bkpt(); //=> 216_406 // R2 : release asm::delay(4_000); // R1 : release @@ -94,7 +96,7 @@ const APP: () = { // R1 : claim asm::delay(6_000); // R1 : release - asm::delay(2_000); + asm::delay(1_968); //=> last 2_000 - 32 (rest of the task code) // == End trace == asm::bkpt(); @@ -110,7 +112,7 @@ const APP: () = { T2_MAX_RP = resp; } } - asm::bkpt(); + asm::bkpt(); //=> 230_438 ----> 230_001 } // Deadline 50, Inter-arrival 50 @@ -118,9 +120,9 @@ const APP: () = { #[task(schedule = [t3], resources = [R2], priority = 3)] fn t3(cx: t3::Context) { //let start = Instant::now(); - asm::bkpt(); + asm::bkpt(); // 50_174 all running: 50249 cx.schedule.t3(cx.scheduled + 50_000.cycles()).unwrap(); - asm::bkpt(); + asm::bkpt(); // 50_272 // 1) your code here to emulate timing behavior of t3 @@ -130,10 +132,10 @@ const APP: () = { *cx.resources.R2 = 1337; asm::delay(10_000); // R2 : release - asm::delay(10_000); + asm::delay(9_617); // 10_000 - 98 (re-scheduling) - 174 (context switching, one task) - 75 (preemption check, all tasks) - 36 (rest of the task code) // == End trace == - asm::bkpt(); + asm::bkpt(); // => 80290 // 2) your code here to update T3_MAX_RP and // break if deadline missed let resp: u32= cx.scheduled.elapsed().as_cycles(); @@ -146,7 +148,7 @@ const APP: () = { T3_MAX_RP = resp; } } - asm::bkpt(); + asm::bkpt(); // => 80_308 ----> 79_999 } // RTIC requires that unused interrupts are declared in an extern block when