From 9d9df6aa3be02eb20987bf4cee438889c15e66e3 Mon Sep 17 00:00:00 2001
From: Blinningjr <nicke.l@telia.com>
Date: Fri, 4 Dec 2020 13:53:34 +0100
Subject: [PATCH] Corrected my answers in timing_task
---
examples/timing_task.rs | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/examples/timing_task.rs b/examples/timing_task.rs
index ce72552..a4dbe5a 100644
--- a/examples/timing_task.rs
+++ b/examples/timing_task.rs
@@ -82,7 +82,7 @@ const APP: () = {
// (gdb) x 0xe0001004
//
// [Your answer here]
-// 0xe0001004: 0x0000000b
+// 0xe0001004: 0x0000000b = 11 cycles
//
// (gdb) disassemble
//
@@ -104,14 +104,14 @@ const APP: () = {
// What was the software latency observed to enter the task?
//
// [Your answer here]
-// 12 - 0 = 12 cycles
+// 11 - 0 = 11 cycles
//
// Does RTIC infer any overhead for launching the task?
//
// [Your answer here]
-// No, it dosen't. In the document
+// No, it doesn't. In the document
// https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/beginner-guide-on-interrupt-latency-and-interrupt-latency-of-the-arm-cortex-m-processors
-// it says that the interupt latency for Cortex-M4 is 12.
+// it says that the interrupt latency for Cortex-M4 is 12.
//
// Now we can continue to measure the round trip time.
//
@@ -122,7 +122,7 @@ const APP: () = {
// (gdb) x 0xe0001004
//
// [Your answer here]
-// 0xe0001004: 0x00000017
+// 0xe0001004: 0x00000017 = 16 + 7 = 23 cycles
//
//
// Looking at the EXTI0 (exti0) code, we see two additional
--
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