From ea4d250eb48a07e223107ea759923b47bc3ebcc4 Mon Sep 17 00:00:00 2001
From: grammers <samkar-4@student.ltu.se>
Date: Wed, 14 Feb 2018 20:07:52 +0000
Subject: [PATCH] bare5: task 2
---
examples/.bare5.rs.swp | Bin 20480 -> 24576 bytes
examples/bare5.rs | 46 +++++++++++++++++++++++++++++++----------
2 files changed, 35 insertions(+), 11 deletions(-)
diff --git a/examples/.bare5.rs.swp b/examples/.bare5.rs.swp
index 5f9c56a8961c6eeb8293d8357fd0d60aae8d53b0..3a33262254f9e0e8a262228114e94f049cdb9e18 100644
GIT binary patch
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diff --git a/examples/bare5.rs b/examples/bare5.rs
index eaf19e2..8123f65 100644
--- a/examples/bare5.rs
+++ b/examples/bare5.rs
@@ -9,6 +9,7 @@ extern crate cortex_m;
extern crate cortex_m_rt;
// C like API...
+/*
mod stm32f40x {
use core::{cell, ptr};
@@ -107,12 +108,19 @@ mod stm32f40x {
}
}
}
-use stm32f40x::*;
+*/
+//use stm32f40x::*;
// see the Reference Manual RM0368 (www.st.com/resource/en/reference_manual/dm00096844.pdf)
// rcc, chapter 6
// gpio, chapter 8
-
+mod address {
+ pub const PERIPH_BASE: u32 = 0x40000000;
+ pub const AHB1PERIPH_BASE: u32 = PERIPH_BASE + 0x00020000;
+ pub const RCC_BASE: u32 = AHB1PERIPH_BASE + 0x3800;
+ pub const GPIOA_BASE: u32 = AHB1PERIPH_BASE + 0x0000;
+ }
+
fn wait(i: u32) {
for _ in 0..i {
cortex_m::asm::nop(); // no operation (cannot be optimized out)
@@ -121,22 +129,25 @@ fn wait(i: u32) {
// system startup, can be hidden from the user
fn main() {
- let rcc = unsafe { &mut *RCC::get() }; // get the reference to RCC in memory
- let gpioa = unsafe { &mut *GPIOA::get() }; // get the reference to GPIOA in memory
- idle(rcc, gpioa);
+ //let rcc = unsafe { &mut *RCC::get() }; // get the reference to RCC in memory
+ //let gpioa = unsafe { &mut *GPIOA::get() }; // get the reference to GPIOA in memory
+ idle();
}
// user application
-fn idle(rcc: &mut RCC, gpioa: &mut GPIOA) {
- let rcc_copy = &rcc;
+fn idle() {
+ //let Rcc = RCC{};
+ //let rcc_copy = &rcc;
// power on GPIOA
- let r = rcc.AHB1ENR.read(); // read
- rcc.AHB1ENR.write(r | 1 << (0)); // set enable
+ // `let r = rcc.AHB1ENR.read(); // read
+ //rcc.AHB1ENR.write(r | 1 << (0)); // set enable
+ mod_u32((address::RCC_BASE + 0x30),0,1,1);
// configure PA5 as output
- let r = gpioa.MODER.read() & !(0b11 << (5 * 2)); // read and mask
- gpioa.MODER.write(r | 0b01 << (5 * 2)); // set output mode
+ //let r = gpioa.MODER.read() & !(0b11 << (5 * 2)); // read and mask
+ //gpioa.MODER.write(r | 0b01 << (5 * 2)); // set output mode
+ mod_u32(address::GPIOA_BASE, 10, 2, 0b01);
// and alter the data output through the BSRR register
// this is more efficient as the read register is not needed.
@@ -168,6 +179,19 @@ fn read_u32(addr: u32) -> u32{
core::ptr::read_volatile(addr as *const _)
}
}
+fn mod_u32(addr: u32, offset: u32, with: u32, mut value: u32){
+ let old: u32 = read_u32(addr);
+ let msc: u32 = old & !(mas_with(with) << offset);
+ value = msc | (value << offset);
+ write_u32(addr, value);
+}
+fn mas_with(with: u32) -> u32{
+ let mut r: u32 = 0;
+ for i in 1..with {
+ r = (r << 1) + 0b1;
+ }
+ return r;
+}
//ike API
// In C the .h files are used for defining interfaces, like function signatures (prototypes),
--
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