diff --git a/examples/rtt-pwm-dma.rs b/examples/rtt-pwm-dma.rs
index ab05fb1d1a27a22a63d040d0172054f959d82f3d..ad756ea17a48c5dd15ac7c0b05c85fcd33bdb06f 100644
--- a/examples/rtt-pwm-dma.rs
+++ b/examples/rtt-pwm-dma.rs
@@ -115,13 +115,23 @@ const APP: () = {
         tim1.ccr1.write(|w| unsafe { w.ccr().bits(128) });
         tim1.ccr2.write(|w| unsafe { w.ccr().bits(128) });
 
-        // loop {
-        //     for i in 0..255 {
-        //         tim1.ccr1.write(|w| unsafe { w.ccr().bits(i) });
-        //         tim1.ccr2.write(|w| unsafe { w.ccr().bits(i) });
-        //         while tim1.sr.read().tif().is_no_trigger() {}
-        //     }
-        // }
+        // Set preload for the CCx
+        tim1.cr2.write(|w| w.ccpc().set_bit());
+
+        tim1.dier.write(|w| w.uie().enabled());
+
+        loop {
+            for i in 0..255 {
+                tim1.ccr1.write(|w| unsafe { w.ccr().bits(i) });
+                tim1.ccr2.write(|w| unsafe { w.ccr().bits(i) });
+                // rprintln!("-");
+                //while tim1.sr.read().uif().is_clear() {
+                while !tim1.sr.read().uif().is_clear() {
+                    rprintln!("-");
+                }
+                // rprintln!("!");
+            }
+        }
     }
 
     #[idle]