From ae566846ce7a3f2c959be103fbf69f7c356584c2 Mon Sep 17 00:00:00 2001
From: anttib-5 <anttib-5@student.ltu.se>
Date: Tue, 12 Mar 2019 13:28:03 +0100
Subject: [PATCH] bare8_1
---
examples/bare8.rs | 2 +-
openocd.gdb | 2 +-
test | 11 +++++++++++
3 files changed, 13 insertions(+), 2 deletions(-)
create mode 100644 test
diff --git a/examples/bare8.rs b/examples/bare8.rs
index b889d6c..2f53850 100644
--- a/examples/bare8.rs
+++ b/examples/bare8.rs
@@ -114,7 +114,7 @@ const APP: () = {
//
// 1. Our CPU now runs slower, did it effect the behavior?
//
-// ** your answer here **
+// Yes
//
// Commit your answer (bare8_1)
//
diff --git a/openocd.gdb b/openocd.gdb
index 46b34b9..5bd8199 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -16,7 +16,7 @@ monitor arm semihosting enable
# send captured ITM to the file (fifo) /tmp/itm.log
# (the microcontroller SWO pin must be connected to the programmer SWO pin)
# 16000000 must match the core clock frequency
-monitor tpiu config internal /tmp/itm.log uart off 16000000
+monitor tpiu config internal test uart off 16000000
# OR: make the microcontroller SWO pin output compatible with UART (8N1)
# 8000000 must match the core clock frequency
diff --git a/test b/test
new file mode 100644
index 0000000..76df794
--- /dev/null
+++ b/test
@@ -0,0 +1,11 @@
+Ok 97
+Ok 98
+Ok 99
+Ok 100
+Ok 13
+Ok 13
+Ok 13
+Ok 13
+Ok 13
+Ok 13
+Ok 13
--
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