diff --git a/examples/bare8.rs b/examples/bare8.rs
index b889d6c41671797308d5359078bf4141eb1d7230..2f5385098732a4e5a2c197ea93c324504f6153e2 100644
--- a/examples/bare8.rs
+++ b/examples/bare8.rs
@@ -114,7 +114,7 @@ const APP: () = {
 //
 // 1. Our CPU now runs slower, did it effect the behavior?
 //
-//    ** your answer here **
+//    Yes
 //
 //    Commit your answer (bare8_1)
 //
diff --git a/openocd.gdb b/openocd.gdb
index 46b34b908e55412d05de8e077e8fe1ac55fe4712..5bd81992d0c7513c4629ba71358490e4b1cdbd05 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -16,7 +16,7 @@ monitor arm semihosting enable
 # send captured ITM to the file (fifo) /tmp/itm.log
 # (the microcontroller SWO pin must be connected to the programmer SWO pin)
 # 16000000 must match the core clock frequency
-monitor tpiu config internal /tmp/itm.log uart off 16000000
+monitor tpiu config internal test uart off 16000000
 
 # OR: make the microcontroller SWO pin output compatible with UART (8N1)
 # 8000000 must match the core clock frequency
diff --git a/test b/test
new file mode 100644
index 0000000000000000000000000000000000000000..76df794436c519ba00d148864d3f80de7b6e7ba5
--- /dev/null
+++ b/test
@@ -0,0 +1,11 @@
+Ok
 97

+Ok
 98

+Ok
 99

+Ok
 
100

+Ok
 13

+Ok
 13

+Ok
 13

+Ok
 13

+Ok
 13

+Ok
 13

+Ok
 13