From 8e495dd82be3351eaa3e39a52cd9641f1e7509e0 Mon Sep 17 00:00:00 2001
From: Ridgep <ridpet-5@student.ltu.se>
Date: Fri, 8 Mar 2019 15:16:13 +0100
Subject: [PATCH] bare4_3
---
examples/bare4.rs | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/examples/bare4.rs b/examples/bare4.rs
index ea70453..7ccfa77 100644
--- a/examples/bare4.rs
+++ b/examples/bare4.rs
@@ -36,8 +36,8 @@ use address::*;
#[inline(always)]
fn read_u32(addr: u32) -> u32 {
- // unsafe { core::ptr::read_volatile(addr as *const _) }
- core::ptr::read_volatile(addr as *const _)
+ unsafe { core::ptr::read_volatile(addr as *const _) }
+ // core::ptr::read_volatile(addr as *const _)
}
#[inline(always)]
@@ -55,13 +55,15 @@ fn wait(i: u32) {
#[entry]
fn main() -> ! {
+ // configure PA5 as output
+ let r = read_u32(GPIOA_MODER) & !(0b11 << (5 * 2)); // read and mask
+ write_u32(GPIOA_MODER, r | 0b01 << (5 * 2)); // set output mode
+
// power on GPIOA
let r = read_u32(RCC_AHB1ENR); // read
write_u32(RCC_AHB1ENR, r | 1); // set enable
- // configure PA5 as output
- let r = read_u32(GPIOA_MODER) & !(0b11 << (5 * 2)); // read and mask
- write_u32(GPIOA_MODER, r | 0b01 << (5 * 2)); // set output mode
+
// and alter the data output through the BSRR register
// this is more efficient as the read register is not needed.
--
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