From 0ee1312d2d71c68f685e70560a44d2fccbc7770b Mon Sep 17 00:00:00 2001
From: Ridgep <ridpet-5@student.ltu.se>
Date: Sun, 10 Mar 2019 13:38:21 +0100
Subject: [PATCH] bare7_1
---
examples/bare7.rs | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/examples/bare7.rs b/examples/bare7.rs
index ecf0fbb..d451c85 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -125,11 +125,12 @@ fn main() -> ! {
//
// rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// Max frequency for pclk1 is 42 MHz, and hclk must be specified to the same value as
+// sysclk / 1 which it is not right now so it's being defaulted to 16 MHz.
//
// rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// Only wrong in this configuration is that hclk will not be set to sysclk / 1 as it should be.
//
// Commit your answers (bare7_1)
//
--
GitLab