Commit aae6a171 authored by Per Lindgren's avatar Per Lindgren

bare3

parent 91c83a75
......@@ -30,6 +30,41 @@ fn main() {
}
}
// 1. build and run the application (debug build)
// start ITM tracing to console *version 0.1.1*
// > itmdump /tmp/itm.log
// or alternatively *version 0.2.0*
// > mkfifo /tmp/itm.log
// > itmdump -f /tmp/itm.log -F
//
// start openocd (in my case...)
// > openocd -f interface/stlink.cfg -f target/stm32f4x.cfg
//
// what is the output in the ITM console
// ** your answer here **
//
// estimate the frequency of the output, give freq in hz
// ** your answer here **
//
// commit your answers (bare2_1)
//
// 2. rebuild and run in release mode
// estimate the frequency of the output, give freq in hz
// ** your answer here **
//
// estimate the ratio between debug/release optimized code
// (speedup)
// ** your answer here **
//
// commit your answers (bare2_2)
//
// 3. optional
// inspect the generated binaries, and try stepping through the code
// for both debug and release binaries. How do they differ
// ** your answer here **
//
// commit your answers (bare2_3)
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
......
......@@ -7,22 +7,86 @@
extern crate cortex_m;
extern crate cortex_m_rt;
use core::str;
#[macro_use]
extern crate cortex_m_debug;
fn main() {
let s = "ABCD";
ipln!("s = {:?}", s);
let bs = s.as_bytes();
ipln!("s = {}", s);
ipln!("bs = {:?}", bs);
// iterate over the byte repr. of s
for c in s.as_bytes() {
ipln!("iterate over slice");
for c in bs {
ip!("{},", c)
}
let mut a = [65u8; 4];
//let mut a = [0u8; 4];
ipln!();
ipln!("iterate iterate uning (raw) indexing");
for i in 0..s.len() {
ip!("{},", bs[i]);
}
ipln!();
ipln!("a = {}", str::from_utf8(&a).unwrap());
loop {}
}
// 1. build and run the application (debug build)
// start ITM tracing to console *version 0.1.1*
// > itmdump /tmp/itm.log
// or alternatively *version 0.2.0*
// > mkfifo /tmp/itm.log
// > itmdump -f /tmp/itm.log -F
//
// start openocd (in my case...)
// > openocd -f interface/stlink.cfg -f target/stm32f4x.cfg
//
// what is the output in the ITM console
// ** your answer here **
//
// what is the type of `s`
// ** your answer here **
//
// what is the type of `bs`
// ** your answer here **
//
// what is the type of `c`
// ** your answer here **
//
// what is the type of `a`
// ** your answer here **
//
// what is the type of `i`
// ** your answer here **
//
// commit your answers (bare3_1)
//
// 2. make types of `s`, `bs`, `c`, `a`, `i` explicit
//
// commit your answers (bare3_2)
//
// 3. uncomment line 28 (let mut a = [0u8; 4];)
// what happens and why
// ** your answer here **
//
// commit your answers (bare3_3)
//
// 4. alter the program so that the data from `bs` is copied byte by byte into `a`
// implement your solution
//
// commit your answers (bare3_4)
//
// 5. look for a way to make this copy done without a loop
// implement your solution
//
// commit your answers (bare3_5)
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
......
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