Commit 5c792b31 authored by DevDoggo's avatar DevDoggo

bare0 - done

parents
[target.thumbv6m-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=true",
"-Z", "linker-flavor=ld",
]
[target.thumbv7m-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
]
[target.thumbv7em-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
]
[target.thumbv7em-none-eabihf]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
]
[build]
target = "thumbv7em-none-eabihf"
\ No newline at end of file
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[Dolphin]
Timestamp=2017,12,27,22,4,55
Version=4
ViewMode=1
[Settings]
HiddenFilesShown=true
target remote :3333
monitor reset init
monitor arm semihosting enable
monitor tpiu config internal /tmp/itm.log uart off 84000000
monitor itm port 0 on
load
monitor reset init
**/*.rs.bk
*.org
.gdb_history
Cargo.lock
target/
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>rtfm-app</name>
<comment></comment>
<projects>
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<buildSpec>
<buildCommand>
<name>com.github.rustdt.ide.core.Builder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
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<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
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<triggers>full,incremental,</triggers>
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<nature>com.github.rustdt.ide.core.nature</nature>
</natures>
</projectDescription>
BOARD=NUCLEO-F401RE
CODE_LOCATION=FLASH
ENDIAN=Little-endian
MCU=STM32F401RE
MCU_VENDOR=STMicroelectronics
MODEL=Pro
PROJECT_FORMAT_VERSION=2
TARGET=ARM\u00AE
VERSION=8.1.0
eclipse.preferences.version=1
eclipse.preferences.version=1
svd_custom_file_path=
svd_file_path=/opt/truestudio/ide/plugins/com.atollic.truestudio.tsp.stm32_1.0.0.20171023-2304/tsp/sfr/STM32F401.svd
build_targets=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\n<build_targets xmlns\="com.github.rustdt.ide.core">\n<target auto_enabled\="false" config\="build" n_enabled\="false" version2\="true">\n<command_invocation append_env\="true" command_arguments\=" xargo build --example bare0&\#10;">\n<env_vars/>\n</command_invocation>\n</target>\n<target auto_enabled\="false" config\="check" n_enabled\="false" version2\="true">\n<command_invocation append_env\="true" command_arguments\="xargo build --example bare0&\#10;">\n<env_vars/>\n</command_invocation>\n</target>\n<target auto_enabled\="false" config\="clean" n_enabled\="false" version2\="true"/>\n</build_targets>\n
eclipse.preferences.version=1
format_onSave=true
racer_path=/home/pln/.cargo/bin/racer
rainicorn_path=/home/pln/.cargo/RustDT/bin/parse_describe
rustfmt_path=/home/pln/.cargo/bin/rustfmt
sdk_path=/home/pln/.cargo/
sdk_src_path=/home/pln/.rustup/toolchains/nightly-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/src/
toolchain_prefs.use_project_settings=false
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</project>
This diff is collapsed.
{
// See https://go.microsoft.com/fwlink/?LinkId=733558
// for the documentation about the tasks.json format
"version": "2.0.0",
"tasks": [
{
"type": "shell",
"label": "xargo build --examples",
"command": "xargo build --examples",
"problemMatcher": [
"$rustc"
],
"group": {
"kind": "build",
"isDefault": true
}
},
{
"type": "shell",
"label": "xargo build --examples --release",
"command": "xargo build --examples --release",
"problemMatcher": [
"$rustc"
],
"group": {
"kind": "build",
"isDefault": true
}
},
]
}
\ No newline at end of file
[package]
authors = [
"Per Lindgren <per.lindgren@ltu.se>",
]
categories = ["concurrency", "embedded", "no-std"]
description = "Real Time For the Masses (RTFM) framework for ARM Cortex-M microcontrollers"
documentation = "https://docs.rs/cortex-m-rtfm"
keywords = ["arm", "cortex-m"]
license = "MIT OR Apache-2.0"
name = "app"
repository = "https://github.com/japaric/cortex-m-rtfm"
version = "0.1.0"
[dependencies]
cortex-m-rtfm = "0.2.2"
cortex-m = "0.3.1"
rtfm-core = "0.1.0"
cortex-m-semihosting = "0.2.0"
heapless = "0.2.0"
[dependencies.cortex-m-debug]
version = "0.1.0"
git = "https://gitlab.henriktjader.com/pln/cortex-m-debug.git"
[dependencies.cortex-m-rt]
features = ["abort-on-panic"]
version = "0.3.3"
[dependencies.stm32f40x]
git = "https://gitlab.henriktjader.com/pln/STM32F40x.git"
features = ["rt"]
version = "0.2.0"
[dependencies.f4]
git = "https://github.com/jsjolund/f4"
version = "0.1.0"
#[dev-dependencies.nb]
#features = ["unstable"]
#version = "0.1.1"
[dependencies.nb]
git = "https://github.com/japaric/nb"
[profile.release]
lto = true
debug = true
[profile.dev]
codegen-units = 1
incremental = false
\ No newline at end of file
TARGETS = bare0 bare1 bare2 bare3 bare4 bare5 bare6
DEV = target/thumbv7em-none-eabihf/debug/examples/
REL = target/thumbv7em-none-eabihf/release/examples/
ELFS = $(addprefix $(DEV), $(TARGETS))
EELFS = $(addsuffix .elf, $(ELFS))
ELFSR = $(addprefix $(REL), $(TARGETS))
EELFSR = $(addsuffix .elf, $(ELFSR))
.PHONY: all
all: xargo $(EELFS) $(EELFSR)
xargo:
xargo build --examples
xargo build --release --examples
%.elf : %
cp $< $@
This diff is collapsed.
[dependencies.core]
stage = 0
[dependencies.compiler_builtins]
features = ["mem"]
stage = 1
\ No newline at end of file
#!/bin/bash
#cargo build --target thumbv7em-none-eabihf --release
cargo build --target thumbv7em-none-eabihf --example bare0
#cargo build --target thumbv7em-none-eabihf --example bare1
//! bare0.rs
//! Simple bare metal application
// feature to ensure symbols to be linked
#![feature(used)]
// build without the Rust standard library
#![no_std]
// Minimal runtime / startup for Cortex-M microcontrollers
extern crate cortex_m_rt;
extern crate cortex_m;
extern crate cortex_m_semihosting;
use cortex_m::asm;
use core::u32;
//use cortex_m_semihosting::hio;
//use core::fmt::Write;
const X_INIT: u32 = <u32>::max_value();
static mut X: u32 = X_INIT;
static mut Y: u32 = 0;
#[inline(never)]
fn main() {
asm::bkpt();
let mut x = unsafe { X };
loop {
x = x.wrapping_add(1);
// write_x(read_x().wrapping_add(1));
// write_y(read_x());
// write_u32(&X, &(X.wrapping_add(1)));
// write_u32(&Y, &X);
unsafe {
read_u32(&X);
write_u32(&mut X, &(X.wrapping_add(1)));
write_u32(&mut Y, &X);
}
// with nop this works
// asm::nop();
// assert!(x == X && X == Y );
// assert!(x == X && X == Y + 1);
}
}
fn read_u32(val: &u32) -> u32 {
unsafe { *val }
}
fn write_u32(x: &mut u32, y: &u32){
unsafe { *x = *y; }
}
/////////
// fn read_x() -> u32{
// unsafe { X }
// }
//
// fn read_y() -> u32 {
// unsafe { Y }
// }
//
// fn write_x(val: u32) {
// unsafe {
// X = val;
// }
// }
//
// fn write_y(val: u32) {
// unsafe {
// Y = val;
// }
// }
// 1. run the program in the debugger,
// let the program run for a while and then press pause
// look in the (Local -vscode) Variables view what do you find
// ** your answer here **
//
// in the Expressions (WATCH -vscode) view add X and Y
// what do you find
//
// ** your answer here **
// step through one complete iteration of the loop
// and see how the (Local) Variables are updated
// can you foresee what will eventually happen?
// ** place your answer here **
//
// commit your answers (bare0_1)
//
// 2. alter the constant X_INIT so that line 22 directly causes the x to wrap
// what happens when x wraps
// ** your answer here **
//
// commit your answers (bare0_2)
//
// >>Causing it to break immediately will cause the program to break and go immediately to the
// loop{} given by the default_handler for interrupts
//
// 3. change += opertions to wrapping_add
// place a breakpoint at line 22
// load and run the progam, what happens
// ** your answer here **
//
// now continue exectution, what happens
// ** your answer here **
//
// >> X wraps around properly and starts over at 0.
//
// commit your answers (bare0_3)
//
// (if the program did not succed back to the breakpoint
// you have some fault in the program and go back to 3)
//
// 4. change the asserion to assert!(x == X && X == Y + 1), what happens
// ** place your answer here **
//
// >> The assert! goes through!
// >> My guess is that Y hasn't been +1:ed before the assert! takes place.
// >> Inserting NOPs should make the X == Y assert! work!
//
//
// commit your answers (bare0_4)
//
// 5. remove the assertion and
//
// make "safe" functions for reading and writing X and Y
// e.g. read_x, read_y, write_x, write_y
//
// rewrite the program to use ONLY "safe" code besides the
// read/write functions (which are internally "unsafe")
//
// commit your solution (bare0_5)
//
// 6*. optional
// implement a read_u32/write_u32, taking a reference to a
// "static" variable
//
// rewrite the program to use this abstraction instead of "read_x", etc.
//
// commit your solution (bare0_6)
//
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
extern "C" fn default_handler() {
loop {}
}
//! bare1.rs
//! Simple bare metal tracing
// feature to ensure symbols to be linked
#![feature(used)]
// build without the Rust standard library
#![no_std]
// API to the ARM Cortex M Peripherals
extern crate cortex_m;
// Minimal runtime / startup for Cortex-M microcontrollers
extern crate cortex_m_rt;
// Convenient tracing over semihosting and ITM
#[macro_use]
extern crate cortex_m_debug;
#[inline(never)]
fn main() {
// ITM trace (fast)
// start `itmdump` before `openocd`
ipln!("ITM: Hello World");
// semihosting trace (slow)
sprintln!("SEMIHOSTING: Hello World");
// to prevent returning
loop {
// cortex_m::asm::nop();
// cortex_m::asm::bkpt();
}
}
// 1. build and run the application
// start ITM tracing to console
// > itmdump /tmp/itm.log
// start openocd (in my case...)
// > openocd -f interface/stlink.cfg -f target/stm32f4x.cfg
//
// when debugging the application it should get stuck in the
// loop, (press pause/suspend to verify this).
// what is the output in the ITM console
// ** your answer here **
//
// what is the output in the semihosting (openocd) console
// ** your answer here **
//
// commit your answers (bare1_1)
//
// 2. inspecting the assembly
// what is shown in the Dissasmbly view, what instruction is executing
// (if you are NOT under eclipse, then give the command in gdb console
// (gdb) disassemble
// ** your answer here **
//
// commit your answers (bare1_2)
//
// 3. now remove the comment line 30.
// rebuild and debug, pause the program.
// what is shown in the Dissasmbly view, what instruction is executing
// ** your answer here **
//
// commit your answers (bare1_3)
//
// 4. now remeve the comment line 31
// what is shown in the Dissasmbly view, what instruction is executing
// ** your answer here **
//
// commit your answers (bare1_4)
//
// 5. release mode (optimized builds)
// rebuild bare1 in release (optimized mode)
// compare the generated assembly for the loop
// between the dev (unoptimized) and release (optimized) build
// in Atollic/eclipse the easiest way is to build the target using
// > xargo build --release --examples
// in gdb console
// > file target/thumbv7em-none-eabihf/release/examples/bare1
// so l
// (which sources/executes the gbd script l, which loads the file)
// c
// (to continue executing)
// ** your answer here **
//
// commit your answers (bare1_5)
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
extern "C" fn default_handler() {
// cortex_m::asm::bkpt();
}
//! bare2.rs
//! Simple bare metal application
#![feature(used)]
#![no_std]
extern crate cortex_m;
extern crate cortex_m_rt;
#[macro_use]
extern crate cortex_m_debug;
// burns CPU cycles by just looping `i` times
fn wait(i: u32) {
for _ in 0..i {
// no operation (ensured not optimized out)
cortex_m::asm::nop();
}
}
fn main() {
ipln!("Start");
// a "mutable" (changeable) variable
let mut s = 0;
loop {
ipln!("s = {}", s);
s += 1;
wait(100_000);
}
}
// 1. build and run the application (debug build)
// start ITM tracing to console *version 0.1.1*
// > itmdump /tmp/itm.log
// or alternatively *version 0.2.0*
// > mkfifo /tmp/itm.log
// > itmdump -f /tmp/itm.log -F
//
// start openocd (in my case...)
// > openocd -f interface/stlink.cfg -f target/stm32f4x.cfg
//
// what is the output in the ITM console
// ** your answer here **
//
// estimate the frequency of the output, give freq in hz
// ** your answer here **
//
// commit your answers (bare2_1)
//
// 2. rebuild and run in release mode
// estimate the frequency of the output, give freq in hz
// ** your answer here **
//
// estimate the ratio between debug/release optimized code
// (speedup)
// ** your answer here **
//
// commit your answers (bare2_2)
//
// 3. optional
// inspect the generated binaries, and try stepping through the code
// for both debug and release binaries. How do they differ
// ** your answer here **
//
// commit your answers (bare2_3)
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
extern "C" fn default_handler() {
cortex_m::asm::bkpt();
}
//! bare3.rs
//! Simple bare metal application
//!
#![feature(used)]
#![no_std]
extern crate cortex_m;
extern crate cortex_m_rt;
use core::str;
#[macro_use]
extern crate cortex_m_debug;
fn main() {
let s = "ABCD";
let bs = s.as_bytes();
ipln!("s = {}", s);
ipln!("bs = {:?}", bs);
ipln!("iterate over slice");
for c in bs {
ip!("{},", c)
}
let mut a = [65u8; 4];
//let mut a = [0u8; 4];
ipln!();
ipln!("iterate iterate using (raw) indexing");
for i in 0..s.len() {
ip!("{},", bs[i]);
}
ipln!();
ipln!("a = {}", str::from_utf8(&a).unwrap());
loop {}
}
// 1. build and run the application (debug build)
// start ITM tracing to console *version 0.1.1*
// > itmdump /tmp/itm.log
// or alternatively *version 0.2.0*
// > mkfifo /tmp/itm.log
// > itmdump -f /tmp/itm.log -F
//
// start openocd (in my case...)
// > openocd -f interface/stlink.cfg -f target/stm32f4x.cfg
//
// what is the output in the ITM console
// ** your answer here **
//
// what is the type of `s`
// ** your answer here **
//
// what is the type of `bs`
// ** your answer here **
//
// what is the type of `c`
// ** your answer here **
//
// what is the type of `a`
// ** your answer here **
//
// what is the type of `i`
// ** your answer here **
//
// commit your answers (bare3_1)
//
// 2. make types of `s`, `bs`, `c`, `a`, `i` explicit
//
// commit your answers (bare3_2)
//
// 3. uncomment line 28 (let mut a = [0u8; 4];)
// what happens and why
// ** your answer here **
//
// commit your answers (bare3_3)
//
// 4. alter the program so that the data from `bs` is copied byte by byte into `a`
// implement your solution
//
// commit your answers (bare3_4)
//
// 5. look for a way to make this copy done without a loop
// implement your solution
//
// commit your answers (bare3_5)
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
extern "C" fn default_handler() {
cortex_m::asm::bkpt();
}
//! bare4.rs
//! Simple bare metal application
//!
#![feature(used)]
#![feature(custom_attribute)] // needed for #[rustfmt_skip]
#![no_std]
extern crate cortex_m;
extern crate cortex_m_rt;
// Peripheral addresses as constants
#[rustfmt_skip]
mod address {
pub const PERIPH_BASE: u32 = 0x40000000;
pub const AHB1PERIPH_BASE: u32 = PERIPH_BASE + 0x00020000;
pub const RCC_BASE: u32 = AHB1PERIPH_BASE + 0x3800;
pub const RCC_AHB1ENR: u32 = RCC_BASE + 0x30;
pub const GBPIA_BASE: u32 = AHB1PERIPH_BASE + 0x0000;
pub const GPIOA_MODER: u32 = GBPIA_BASE + 0x00;
pub const GPIOA_BSRR: u32 = GBPIA_BASE + 0x18;
}
use address::*;