diff --git a/examples/rtic_bare5.rs b/examples/rtic_bare5.rs index 5686e1b7a24c32db2f45dd120b87c33605af10ee..6c88f9a7df348343c64f74617dc9dacacfc25ab6 100644 --- a/examples/rtic_bare5.rs +++ b/examples/rtic_bare5.rs @@ -11,6 +11,7 @@ extern crate cortex_m; extern crate panic_semihosting; +//use bitvec::prelude::*; <-- Might wont to look in to this. // C like API... mod stm32f40x { @@ -58,7 +59,9 @@ mod stm32f40x { impl VolatileCell<u32> { #[inline(always)] pub fn modify(&self, offset: u8, width: u8, value: u32) { - // your code here + let mut value_mut = value << 32-width; + value_mut = value_mut >> 32-width; + self.write(value_mut << offset); } } @@ -179,22 +182,25 @@ const APP: () = { // test_modify(); + test_modify(); + + loop { // set PA5 high - gpioa.BSRRH.write(1 << 5); // set bit, output hight (turn on led) + //gpioa.BSRRH.write(1 << 5); // set bit, output hight (turn on led) // alternatively to set the bit high we can // read the value, or with PA5 (bit 5) and write back - // gpioa.ODR.write(gpioa.ODR.read() | (1 << 5)); + gpioa.ODR.write(gpioa.ODR.read() | (1 << 5)); wait(10_000); // set PA5 low - gpioa.BSRRL.write(1 << 5); // clear bit, output low (turn off led) + //gpioa.BSRRL.write(1 << 5); // clear bit, output low (turn off led) // alternatively to clear the bit we can // read the value, mask out PA5 (bit 5) and write back - // gpioa.ODR.write(gpioa.ODR.read() & !(1 << 5)); + gpioa.ODR.write(gpioa.ODR.read() & !(1 << 5)); wait(10_000); } } @@ -241,6 +247,6 @@ const APP: () = { // What if we could automatically generate that from Vendors specifications (SVD files)? // Wouldn't that be great? // -// ** your answer here ** +// I got the first assert to work. But I don't understand the second. What are we supposed to do? // // Commit your answers (bare5_2)