diff --git a/examples/bare4.rs b/examples/bare4.rs
index 07ce483f31f97174ac046b5a43a6548af79a212d..1a381a517b2ce92fcae68f32cb0fae1ccbd8f460 100644
--- a/examples/bare4.rs
+++ b/examples/bare4.rs
@@ -19,12 +19,12 @@ use cortex_m_rt::entry;
 // Peripheral addresses as constants
 #[rustfmt::skip]
 mod address {
-    pub const PERIPH_BASE: u32      = 0x40000000;
+    pub const PERIPH_BASE: u32      = 0x40000000; 
     pub const AHB1PERIPH_BASE: u32  = PERIPH_BASE + 0x00020000;
     pub const RCC_BASE: u32         = AHB1PERIPH_BASE + 0x3800;
     pub const RCC_AHB1ENR: u32      = RCC_BASE + 0x30;
     pub const GBPIA_BASE: u32       = AHB1PERIPH_BASE + 0x0000;
-    pub const GPIOA_MODER: u32      = GBPIA_BASE + 0x00;
+    pub const GPIOA_MODER: u32      = GBPIA_BASE + 0x00; 
     pub const GPIOA_BSRR: u32       = GBPIA_BASE + 0x18;
 }
 
@@ -56,10 +56,12 @@ fn wait(i: u32) {
 #[entry]
 fn main() -> ! {
     // power on GPIOA
+    //6.3.9
     let r = read_u32(RCC_AHB1ENR); // read
     write_u32(RCC_AHB1ENR, r | 1); // set enable
 
     // configure PA5 as output
+    //8.4.1
     let r = read_u32(GPIOA_MODER) & !(0b11 << (5 * 2)); // read and mask
     write_u32(GPIOA_MODER, r | 0b01 << (5 * 2)); // set output mode
 
@@ -68,6 +70,7 @@ fn main() -> ! {
 
     loop {
         // set PA5 high
+        //8.4.7
         write_u32(GPIOA_BSRR, 1 << 5); // set bit, output hight (turn on led)
         wait(10_000);
 
@@ -85,6 +88,7 @@ fn main() -> ! {
 // 1.  Did you enjoy the blinking?
 //
 //    ** your answer here **
+//      yes
 //
 //    Now lookup the data-sheets, and read each section referred,
 //    6.3.11, 8.4.1, 8.4.7