diff --git a/examples/rtic_bare6.rs b/examples/rtic_bare6.rs
index 255ff36543eba6a24d3004793164498294fc1643..5458a9157fa4f3449f8960d5698233a010152072 100644
--- a/examples/rtic_bare6.rs
+++ b/examples/rtic_bare6.rs
@@ -202,7 +202,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //
 //    `rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze()`;
 //
-//    ** your answer here **
+//    PCLK1 needs to have a clock frequency of <= 42 MHz
 //
 //    `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
 //
@@ -237,15 +237,15 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //
 //    What is the (default) MCU (SYSCLK) frequency?
 //
-//    ** your answer here **
+//    8 Mhz
 //
 //    What is the (default) DWT CYCCNT frequency?
 //
-//    ** your answer here **
+//    Same as SYSCLK? 
 //
 //    What is the frequency of blinking?
 //
-//    ** your answer here **
+//    1 hz
 //
 //    Commit your answers (bare6_1)
 //