From eb956b5c441d7410156792ba22d9485eb14813e8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Daniel=20Bj=C3=B6rk?= <ddbjork@gmail.com>
Date: Thu, 22 Dec 2016 17:46:45 +0100
Subject: [PATCH] USART and IMU DMA info added
---
components/usart.tex | 7 +++----
implementation/imu.tex | 3 +++
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/components/usart.tex b/components/usart.tex
index 359ef22..67613e9 100644
--- a/components/usart.tex
+++ b/components/usart.tex
@@ -1,6 +1,5 @@
\subsection{USART - Universal Synchronous/Asynchronous \\Receiver/Transmitter}
-The built in USART in the \href{http://www.st.com/en/evaluation-tools/nucleo-f767zi.html}{STM32F7-NUCLEO}
-supports several communication standards for data transmission. Among these are RS-232 which requires two
-extra lines for communication. A Ready To Send (RTS) and a Clear To Send (CTS), which adds a layer of
-hardware flow control.
+The built in USART in the \href{http://www.st.com/en/evaluation-tools/nucleo-f767zi.html}{STM32F7-NUCLEO} supports several communication standards for data transmission. Among these are RS-232 which requires two extra lines for communication. A Ready To Send (RTS) and a Clear To Send (CTS), which adds a layer of hardware flow control.
+
+The processor also support Direct Memory Access(DMA). This automates the buffering of transmitted bytes, which relieves the processor of executing code to fetch each byte and store it in a buffer. This can be done both while transmitting and receiving data.
diff --git a/implementation/imu.tex b/implementation/imu.tex
index 188f41b..124d29b 100644
--- a/implementation/imu.tex
+++ b/implementation/imu.tex
@@ -13,6 +13,9 @@
The data received \texttt{8bits} at a time. Each data point transmitted contains \texttt{32bits}, formatted as a standard \texttt{IEEE 754 float}. The data is shifted into a temporary \texttt{32bit unsigned int} and then a \texttt{memcpy()} is executed from the \texttt{int} to a \texttt{float}. The data points are then sent over to \texttt{MSP} and stored.
+ Due to the high transmission rate of the MTi, DMA buffering has been implemented to relieve
+ the processor of constant code execution of receiving each byte. However transmission to the MTi is interrupt driven, due to the small amount of data that has to be sent. Something which is only executed upon launch, to configure the MTi.
+
\begin{table}[H]
\begin{center}
\begin{tabular}{ l l }
--
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