diff --git a/examples/rtic_bare6.rs b/examples/rtic_bare6.rs index df5f9deb53f89109ea89e205e599e836886342b5..8527c984706dff4fc4be71c6d0cff36c211fdc5e 100644 --- a/examples/rtic_bare6.rs +++ b/examples/rtic_bare6.rs @@ -55,21 +55,21 @@ const APP: () = { let rcc = device.RCC.constrain(); - let _clocks = rcc.cfgr.freeze(); + //let _clocks = rcc.cfgr.freeze(); - // Set up the system clock. 48 MHz? + //Set up the system clock. 48 MHz? // let _clocks = rcc // .cfgr // .sysclk(48.mhz()) // .pclk1(24.mhz()) // .freeze(); - // let _clocks = rcc - // .cfgr - // .sysclk(64.mhz()) - // .pclk1(64.mhz()) - // .pclk2(64.mhz()) - // .freeze(); + let _clocks = rcc + .cfgr + .sysclk(64.mhz()) + .pclk1(64.mhz()) + .pclk2(64.mhz()) + .freeze(); // // let _clocks = rcc // .cfgr @@ -208,6 +208,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) { // `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();` // // ** your answer here ** +// It works? // // Start `stm32cubemx` and select or create a project targeting stm32f401. // Go to the graphical clock configuration view. @@ -219,6 +220,8 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) { // What happens? // // ** your answer here ** +// panicked at 'assertion failed: pclk1 <= pclk1_max', /home/carlosterberg/.cargo/registry/src/github.com-1ecc6299db9ec823/stm32f4xx-hal-0.8.3/src/rcc.rs:321:9 +// In other words it crashes. // // Try to setup the clock according to: // @@ -227,6 +230,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) { // `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();` // // ** your answer here ** +// It works, very fast blinking // // Commit your answers (bare6_0) // diff --git a/examples/rtic_bare8.rs b/examples/rtic_bare8.rs index b4b18ee4a72d728359e36c70467f4de9ba8643a0..241530d1a1ed614fd0b22617ea7831326e9d3580 100644 --- a/examples/rtic_bare8.rs +++ b/examples/rtic_bare8.rs @@ -11,7 +11,7 @@ use panic_rtt_target as _; -use nb::block; +use stm32f4xx_hal::nb::block; use stm32f4xx_hal::{ gpio::{gpioa::PA, Output, PushPull},