diff --git a/examples/rtic_bare6.rs b/examples/rtic_bare6.rs
index 862c49bc4f9409703b6f53cb92f78154b3752629..869e7dc8009115a9ae1f548aa9ec6ce4fe89e9dd 100644
--- a/examples/rtic_bare6.rs
+++ b/examples/rtic_bare6.rs
@@ -18,7 +18,8 @@ use stm32f4xx_hal::{
     stm32::{self, GPIOC, RCC},
 };
 
-const OFFSET: u32 = 8_000_000;
+//const OFFSET: u32 = 8_000_000;
+const OFFSET: u32 = 24_000_000;
 
 #[rtic::app(device = stm32f4xx_hal::stm32, monotonic = rtic::cyccnt::CYCCNT, peripherals = true)]
 const APP: () = {
@@ -55,15 +56,14 @@ const APP: () = {
 
         let rcc = device.RCC.constrain();
 
-        let _clocks = rcc.cfgr.freeze();
-        //rprintln!("mhz: {:?}", _clocks.sysclk());
+        //let _clocks = rcc.cfgr.freeze();
 
         //Set up the system clock. 48 MHz?
-        // let _clocks = rcc
-        //     .cfgr
-        //     .sysclk(48.mhz())
-        //     .pclk1(24.mhz())
-        //     .freeze();
+        let _clocks = rcc
+            .cfgr
+            .sysclk(48.mhz())
+            .pclk1(24.mhz())
+            .freeze();
 
         // let _clocks = rcc
         //     .cfgr
@@ -123,22 +123,22 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
     // mco2 	: SYSCLK = 0b00
     // mcopre 	: divide by 4 = 0b110
     rcc.cfgr
-        .modify(|_, w| unsafe { w.mco2().bits(0b00).mco2pre().bits(0b110) });
+        .modify(|_, w| unsafe { w.mco2().sysclk().mco2pre().div4() });
 
     // power on GPIOC, RM0368 6.3.11
-    rcc.ahb1enr.modify(|_, w| w.gpiocen().set_bit());
+    rcc.ahb1enr.modify(|_, w| w.gpiocen().enabled());
 
     // MCO_2 alternate function AF0, STM32F401xD STM32F401xE data sheet
     // table 9
     // AF0, gpioc reset value = AF0
 
     // configure PC9 as alternate function 0b10, RM0368 6.2.10
-    gpioc.moder.modify(|_, w| w.moder9().bits(0b10));
+    gpioc.moder.modify(|_, w| w.moder9().alternate());
 
     // otyper reset state push/pull, in reset state (don't need to change)
 
     // ospeedr 0b11 = very high speed
-    gpioc.ospeedr.modify(|_, w| w.ospeedr9().bits(0b11));
+    gpioc.ospeedr.modify(|_, w| w.ospeedr9().high_speed());
 }
 
 // 0. Background reading:
@@ -264,10 +264,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //    Compute the value of SYSCLK based on the oscilloscope reading
 //
 //    ** your answer here **
+//    (1 /  250*10^(-9))*4 = 16 MHz
 //
 //    What is the peak to peak (voltage) reading of the signal?
 //
 //    ** your answer here **
+//    8V
 //
 //    Make a folder called "pictures" in your git project.
 //    Make a screen dump or photo of the oscilloscope output.
@@ -281,10 +283,13 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //    What is the frequency of blinking?
 //
 //    ** your answer here **
+//    3 blinks per second
 //
 //    Now change the constant `OFFSET` so you get the same blinking frequency as in 1.
 //    Test and validate that you got the desired behavior.
 //
+//    Multiply OFFSET by a factor 3 and you will get the same results as before.
+//
 //    Commit your answers (bare6_3)
 //
 // 4. Repeat experiment 2
@@ -292,14 +297,17 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //    What is the frequency of MCO2 read by the oscilloscope?
 //
 //    ** your answer here **
+//    12MHz
 //
 //    Compute the value of SYSCLK based on the oscilloscope reading.
 //
 //    ** your answer here **
+//    48MHz
 //
 //    What is the peak to peak reading of the signal?
 //
 //    ** your answer here **
+//    7.75V
 //
 //    Make a screen dump or photo of the oscilloscope output.
 //    Save the the picture as "bare_6_48mhz_high_speed".
diff --git a/pictures/oscilloscope b/pictures/bare_6_16mhz_high_speed
similarity index 100%
rename from pictures/oscilloscope
rename to pictures/bare_6_16mhz_high_speed
diff --git a/pictures/bare_6_48mhz_high_speed b/pictures/bare_6_48mhz_high_speed
new file mode 100644
index 0000000000000000000000000000000000000000..9a2bf7ffa45b85911e98705d9ad800d0849aa804
Binary files /dev/null and b/pictures/bare_6_48mhz_high_speed differ